Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
110:165afa46840b 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_pwr_ex.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
emilmont 77:869cf507173a 7 * @brief Header file of PWR HAL Extension module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_PWR_EX_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_PWR_EX_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup PWREx
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 59 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
Kojto 110:165afa46840b 62 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 63 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 90:cb3d968589d8 64
Kojto 99:dbbf35b96557 65 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
Kojto 90:cb3d968589d8 66 * @{
Kojto 90:cb3d968589d8 67 */
Kojto 90:cb3d968589d8 68 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
Kojto 90:cb3d968589d8 69 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
Kojto 90:cb3d968589d8 70 /**
Kojto 90:cb3d968589d8 71 * @}
Kojto 90:cb3d968589d8 72 */
Kojto 90:cb3d968589d8 73
Kojto 99:dbbf35b96557 74 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
emilmont 77:869cf507173a 75 * @{
emilmont 77:869cf507173a 76 */
emilmont 77:869cf507173a 77 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
emilmont 77:869cf507173a 78 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
emilmont 77:869cf507173a 79 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
emilmont 77:869cf507173a 80 /**
emilmont 77:869cf507173a 81 * @}
emilmont 77:869cf507173a 82 */
Kojto 110:165afa46840b 83 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 84
Kojto 110:165afa46840b 85 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
Kojto 99:dbbf35b96557 86 * @{
Kojto 99:dbbf35b96557 87 */
Kojto 106:ba1f97679dad 88 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 89 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
Kojto 99:dbbf35b96557 90 #define PWR_REGULATOR_VOLTAGE_SCALE2 ((uint32_t)0x00000000) /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
Kojto 99:dbbf35b96557 91 #else
Kojto 99:dbbf35b96557 92 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
Kojto 99:dbbf35b96557 93 180 MHz by activating the over-drive mode. */
Kojto 99:dbbf35b96557 94 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
Kojto 99:dbbf35b96557 95 168 MHz by activating the over-drive mode. */
Kojto 99:dbbf35b96557 96 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
Kojto 99:dbbf35b96557 97 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 99:dbbf35b96557 98 /**
Kojto 99:dbbf35b96557 99 * @}
Kojto 99:dbbf35b96557 100 */
Kojto 110:165afa46840b 101 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx)
Kojto 110:165afa46840b 102 /** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
Kojto 110:165afa46840b 103 * @{
Kojto 110:165afa46840b 104 */
Kojto 110:165afa46840b 105 #define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080)
Kojto 110:165afa46840b 106 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
Kojto 110:165afa46840b 107 #define PWR_WAKEUP_PIN3 ((uint32_t)0x00000040)
Kojto 110:165afa46840b 108 #endif /* STM32F410xx */
Kojto 110:165afa46840b 109 /**
Kojto 110:165afa46840b 110 * @}
Kojto 110:165afa46840b 111 */
Kojto 110:165afa46840b 112 #endif /* STM32F410xx || STM32F446xx */
Kojto 110:165afa46840b 113
emilmont 77:869cf507173a 114 /**
emilmont 77:869cf507173a 115 * @}
emilmont 77:869cf507173a 116 */
emilmont 77:869cf507173a 117
emilmont 77:869cf507173a 118 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 119 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
Kojto 99:dbbf35b96557 120 * @{
Kojto 99:dbbf35b96557 121 */
Kojto 110:165afa46840b 122
Kojto 110:165afa46840b 123 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 110:165afa46840b 124 /** @brief macros configure the main internal regulator output voltage.
Kojto 110:165afa46840b 125 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 110:165afa46840b 126 * a tradeoff between performance and power consumption when the device does
Kojto 110:165afa46840b 127 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 110:165afa46840b 128 * This parameter can be one of the following values:
Kojto 110:165afa46840b 129 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 110:165afa46840b 130 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 110:165afa46840b 131 * @retval None
Kojto 110:165afa46840b 132 */
Kojto 110:165afa46840b 133 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 110:165afa46840b 134 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 135 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 110:165afa46840b 136 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 137 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 110:165afa46840b 138 UNUSED(tmpreg); \
Kojto 110:165afa46840b 139 } while(0)
Kojto 110:165afa46840b 140 #else
Kojto 110:165afa46840b 141 /** @brief macros configure the main internal regulator output voltage.
Kojto 110:165afa46840b 142 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 110:165afa46840b 143 * a tradeoff between performance and power consumption when the device does
Kojto 110:165afa46840b 144 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 110:165afa46840b 145 * This parameter can be one of the following values:
Kojto 110:165afa46840b 146 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 110:165afa46840b 147 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 110:165afa46840b 148 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
Kojto 110:165afa46840b 149 * @retval None
Kojto 110:165afa46840b 150 */
Kojto 110:165afa46840b 151 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 110:165afa46840b 152 __IO uint32_t tmpreg; \
Kojto 110:165afa46840b 153 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 110:165afa46840b 154 /* Delay after an RCC peripheral clock enabling */ \
Kojto 110:165afa46840b 155 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 110:165afa46840b 156 UNUSED(tmpreg); \
Kojto 110:165afa46840b 157 } while(0)
Kojto 110:165afa46840b 158 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 110:165afa46840b 159
Kojto 110:165afa46840b 160 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 161 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
emilmont 77:869cf507173a 162 /** @brief Macros to enable or disable the Over drive mode.
emilmont 77:869cf507173a 163 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 164 */
emilmont 77:869cf507173a 165 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
emilmont 77:869cf507173a 166 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
emilmont 77:869cf507173a 167
emilmont 77:869cf507173a 168 /** @brief Macros to enable or disable the Over drive switching.
emilmont 77:869cf507173a 169 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 170 */
emilmont 77:869cf507173a 171 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
emilmont 77:869cf507173a 172 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 /** @brief Macros to enable or disable the Under drive mode.
emilmont 77:869cf507173a 175 * @note This mode is enabled only with STOP low power mode.
emilmont 77:869cf507173a 176 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
emilmont 77:869cf507173a 177 * mode is only available when the main regulator or the low power regulator
emilmont 77:869cf507173a 178 * is in low voltage mode.
emilmont 77:869cf507173a 179 * @note If the Under-drive mode was enabled, it is automatically disabled after
emilmont 77:869cf507173a 180 * exiting Stop mode.
emilmont 77:869cf507173a 181 * When the voltage regulator operates in Under-drive mode, an additional
emilmont 77:869cf507173a 182 * startup delay is induced when waking up from Stop mode.
emilmont 77:869cf507173a 183 */
emilmont 77:869cf507173a 184 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
emilmont 77:869cf507173a 185 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
emilmont 77:869cf507173a 186
emilmont 77:869cf507173a 187 /** @brief Check PWR flag is set or not.
emilmont 77:869cf507173a 188 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 189 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 190 * This parameter can be one of the following values:
emilmont 77:869cf507173a 191 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
emilmont 77:869cf507173a 192 * is ready
emilmont 77:869cf507173a 193 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
emilmont 77:869cf507173a 194 * switching is ready
emilmont 77:869cf507173a 195 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
emilmont 77:869cf507173a 196 * is enabled in Stop mode
emilmont 77:869cf507173a 197 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 198 */
emilmont 77:869cf507173a 199 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
emilmont 77:869cf507173a 200
emilmont 77:869cf507173a 201 /** @brief Clear the Under-Drive Ready flag.
emilmont 77:869cf507173a 202 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 203 */
emilmont 77:869cf507173a 204 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
emilmont 77:869cf507173a 205
Kojto 110:165afa46840b 206 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 207 /**
Kojto 99:dbbf35b96557 208 * @}
Kojto 99:dbbf35b96557 209 */
emilmont 77:869cf507173a 210
emilmont 77:869cf507173a 211 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 212 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
Kojto 99:dbbf35b96557 213 * @{
Kojto 99:dbbf35b96557 214 */
Kojto 99:dbbf35b96557 215
Kojto 99:dbbf35b96557 216 /** @addtogroup PWREx_Exported_Functions_Group1
Kojto 99:dbbf35b96557 217 * @{
Kojto 99:dbbf35b96557 218 */
Kojto 99:dbbf35b96557 219 void HAL_PWREx_EnableFlashPowerDown(void);
Kojto 99:dbbf35b96557 220 void HAL_PWREx_DisableFlashPowerDown(void);
emilmont 77:869cf507173a 221 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
emilmont 77:869cf507173a 222 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
Kojto 99:dbbf35b96557 223 uint32_t HAL_PWREx_GetVoltageRange(void);
Kojto 99:dbbf35b96557 224 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
emilmont 77:869cf507173a 225
Kojto 110:165afa46840b 226 #if defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 227 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void);
Kojto 110:165afa46840b 228 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void);
Kojto 110:165afa46840b 229 #endif /* STM32F469xx || STM32F479xx */
Kojto 110:165afa46840b 230
Kojto 110:165afa46840b 231 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
Kojto 110:165afa46840b 232 defined(STM32F401xE) || defined(STM32F411xE)
Kojto 90:cb3d968589d8 233 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 234 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 235 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 236 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
Kojto 110:165afa46840b 237 #endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 90:cb3d968589d8 238
Kojto 110:165afa46840b 239 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
Kojto 110:165afa46840b 240 defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 241 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
Kojto 99:dbbf35b96557 242 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
Kojto 90:cb3d968589d8 243 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
Kojto 110:165afa46840b 244 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 245
Kojto 99:dbbf35b96557 246 /**
Kojto 99:dbbf35b96557 247 * @}
Kojto 99:dbbf35b96557 248 */
Kojto 99:dbbf35b96557 249
Kojto 99:dbbf35b96557 250 /**
Kojto 99:dbbf35b96557 251 * @}
Kojto 99:dbbf35b96557 252 */
Kojto 99:dbbf35b96557 253 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 254 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 255 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 256 /** @defgroup PWREx_Private_Constants PWREx Private Constants
Kojto 99:dbbf35b96557 257 * @{
Kojto 99:dbbf35b96557 258 */
Kojto 99:dbbf35b96557 259
Kojto 99:dbbf35b96557 260 /** @defgroup PWREx_register_alias_address PWREx Register alias address
Kojto 99:dbbf35b96557 261 * @{
Kojto 99:dbbf35b96557 262 */
Kojto 99:dbbf35b96557 263 /* ------------- PWR registers bit address in the alias region ---------------*/
Kojto 99:dbbf35b96557 264 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 265 /* Alias word address of FPDS bit */
Kojto 99:dbbf35b96557 266 #define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
Kojto 99:dbbf35b96557 267 #define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FPDS_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 268
Kojto 99:dbbf35b96557 269 /* Alias word address of ODEN bit */
Kojto 99:dbbf35b96557 270 #define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
Kojto 99:dbbf35b96557 271 #define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODEN_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 272
Kojto 99:dbbf35b96557 273 /* Alias word address of ODSWEN bit */
Kojto 99:dbbf35b96557 274 #define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
Kojto 99:dbbf35b96557 275 #define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ODSWEN_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 276
Kojto 99:dbbf35b96557 277 /* Alias word address of MRLVDS bit */
Kojto 99:dbbf35b96557 278 #define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
Kojto 99:dbbf35b96557 279 #define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (MRLVDS_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 280
Kojto 99:dbbf35b96557 281 /* Alias word address of LPLVDS bit */
Kojto 99:dbbf35b96557 282 #define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
Kojto 99:dbbf35b96557 283 #define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPLVDS_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 284
Kojto 99:dbbf35b96557 285 /**
Kojto 99:dbbf35b96557 286 * @}
Kojto 99:dbbf35b96557 287 */
Kojto 99:dbbf35b96557 288
Kojto 99:dbbf35b96557 289 /** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
Kojto 99:dbbf35b96557 290 * @{
Kojto 99:dbbf35b96557 291 */
Kojto 99:dbbf35b96557 292 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 293 /* Alias word address of BRE bit */
Kojto 99:dbbf35b96557 294 #define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
Kojto 110:165afa46840b 295 #define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (BRE_BIT_NUMBER * 4))
Kojto 110:165afa46840b 296
Kojto 110:165afa46840b 297 #if defined(STM32F469xx) || defined(STM32F479xx)
Kojto 110:165afa46840b 298 /* Alias word address of WUPP bit */
Kojto 110:165afa46840b 299 #define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP)
Kojto 110:165afa46840b 300 #define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (WUPP_BIT_NUMBER * 4))
Kojto 110:165afa46840b 301 #endif /* STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 302 /**
Kojto 99:dbbf35b96557 303 * @}
Kojto 99:dbbf35b96557 304 */
Kojto 99:dbbf35b96557 305
Kojto 99:dbbf35b96557 306 /**
Kojto 99:dbbf35b96557 307 * @}
Kojto 99:dbbf35b96557 308 */
Kojto 99:dbbf35b96557 309
Kojto 99:dbbf35b96557 310 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 311 /** @defgroup PWREx_Private_Macros PWREx Private Macros
Kojto 99:dbbf35b96557 312 * @{
Kojto 99:dbbf35b96557 313 */
Kojto 99:dbbf35b96557 314
Kojto 99:dbbf35b96557 315 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
Kojto 99:dbbf35b96557 316 * @{
Kojto 99:dbbf35b96557 317 */
Kojto 110:165afa46840b 318 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 319 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 99:dbbf35b96557 320 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
Kojto 99:dbbf35b96557 321 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
Kojto 110:165afa46840b 322 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 323
Kojto 106:ba1f97679dad 324 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 99:dbbf35b96557 325 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 99:dbbf35b96557 326 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
Kojto 99:dbbf35b96557 327 #else
Kojto 99:dbbf35b96557 328 #define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 99:dbbf35b96557 329 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
Kojto 99:dbbf35b96557 330 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
Kojto 99:dbbf35b96557 331 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 99:dbbf35b96557 332
Kojto 110:165afa46840b 333 #if defined(STM32F446xx)
Kojto 110:165afa46840b 334 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
Kojto 110:165afa46840b 335 #elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
Kojto 110:165afa46840b 336 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
Kojto 110:165afa46840b 337 ((PIN) == PWR_WAKEUP_PIN3))
Kojto 110:165afa46840b 338 #else
Kojto 110:165afa46840b 339 #define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
Kojto 110:165afa46840b 340 #endif /* STM32F446xx */
Kojto 99:dbbf35b96557 341 /**
Kojto 99:dbbf35b96557 342 * @}
Kojto 99:dbbf35b96557 343 */
Kojto 99:dbbf35b96557 344
Kojto 99:dbbf35b96557 345 /**
Kojto 99:dbbf35b96557 346 * @}
Kojto 99:dbbf35b96557 347 */
emilmont 77:869cf507173a 348
emilmont 77:869cf507173a 349 /**
emilmont 77:869cf507173a 350 * @}
emilmont 77:869cf507173a 351 */
emilmont 77:869cf507173a 352
emilmont 77:869cf507173a 353 /**
emilmont 77:869cf507173a 354 * @}
emilmont 77:869cf507173a 355 */
emilmont 77:869cf507173a 356
emilmont 77:869cf507173a 357 #ifdef __cplusplus
emilmont 77:869cf507173a 358 }
emilmont 77:869cf507173a 359 #endif
emilmont 77:869cf507173a 360
emilmont 77:869cf507173a 361
emilmont 77:869cf507173a 362 #endif /* __STM32F4xx_HAL_PWR_EX_H */
emilmont 77:869cf507173a 363
emilmont 77:869cf507173a 364 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/