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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 108:34e6b704fe68

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_rcc_ex.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
Kojto	108:34e6b704fe68	5	* @version V1.3.0
Kojto	108:34e6b704fe68	6	* @date 26-June-2015
bogdanm	85:024bf7f99721	7	* @brief Header file of RCC HAL Extension module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
Kojto	108:34e6b704fe68	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
Kojto	108:34e6b704fe68	40	#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
Kojto	108:34e6b704fe68	53	/** @addtogroup RCC
Kojto	108:34e6b704fe68	54	* @{
Kojto	108:34e6b704fe68	55	*/
Kojto	108:34e6b704fe68	56
Kojto	108:34e6b704fe68	57	/** @addtogroup RCC_Private_Macros
Kojto	108:34e6b704fe68	58	* @{
Kojto	108:34e6b704fe68	59	*/
Kojto	108:34e6b704fe68	60	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	61	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	62	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	63	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	108:34e6b704fe68	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	108:34e6b704fe68	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	108:34e6b704fe68	66	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	108:34e6b704fe68	67	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	108:34e6b704fe68	68	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
Kojto	108:34e6b704fe68	69	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
Kojto	108:34e6b704fe68	70	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	71	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	72	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
Kojto	108:34e6b704fe68	73	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
Kojto	108:34e6b704fe68	74
Kojto	108:34e6b704fe68	75	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	108:34e6b704fe68	76	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	108:34e6b704fe68	77	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
Kojto	108:34e6b704fe68	78	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
Kojto	108:34e6b704fe68	79	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	80	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
Kojto	108:34e6b704fe68	81	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	108:34e6b704fe68	82	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
Kojto	108:34e6b704fe68	83	#else
Kojto	108:34e6b704fe68	84	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	108:34e6b704fe68	85	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	108:34e6b704fe68	86	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	108:34e6b704fe68	87	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	108:34e6b704fe68	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	108:34e6b704fe68	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
Kojto	108:34e6b704fe68	90	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	91	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	92	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	108:34e6b704fe68	93
Kojto	108:34e6b704fe68	94	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
Kojto	108:34e6b704fe68	95	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
Kojto	108:34e6b704fe68	96	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto	108:34e6b704fe68	97	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	98	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	108:34e6b704fe68	99
Kojto	108:34e6b704fe68	100	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	101	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	102	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	103
Kojto	108:34e6b704fe68	104	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	105	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	106
Kojto	108:34e6b704fe68	107	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	108:34e6b704fe68	108	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	108:34e6b704fe68	109	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	110	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	111	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	112	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	113	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
Kojto	108:34e6b704fe68	114	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	115	((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto	108:34e6b704fe68	116
Kojto	108:34e6b704fe68	117	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
Kojto	108:34e6b704fe68	118
Kojto	108:34e6b704fe68	119	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	108:34e6b704fe68	120
Kojto	108:34e6b704fe68	121	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	108:34e6b704fe68	122	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	108:34e6b704fe68	123	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	124	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	125	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	126	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	127	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	128	((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto	108:34e6b704fe68	129
Kojto	108:34e6b704fe68	130	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	108:34e6b704fe68	131
Kojto	108:34e6b704fe68	132	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	133	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	134	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	135
Kojto	108:34e6b704fe68	136	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	108:34e6b704fe68	137	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	108:34e6b704fe68	138	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	139	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	140	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	141	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	142	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
Kojto	108:34e6b704fe68	143	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	144	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
Kojto	108:34e6b704fe68	145	((SOURCE) == RCC_MCOSOURCE_HSI48))
Kojto	108:34e6b704fe68	146
Kojto	108:34e6b704fe68	147	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	148	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	149	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	150
Kojto	108:34e6b704fe68	151	/**
Kojto	108:34e6b704fe68	152	* @}
Kojto	108:34e6b704fe68	153	*/
Kojto	108:34e6b704fe68	154
Kojto	108:34e6b704fe68	155	/** @addtogroup RCC_Exported_Constants
Kojto	108:34e6b704fe68	156	* @{
Kojto	108:34e6b704fe68	157	*/
Kojto	108:34e6b704fe68	158	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	159	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	160	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	161
Kojto	108:34e6b704fe68	162	/** @addtogroup RCC_PLL_Clock_Source
Kojto	108:34e6b704fe68	163	* @{
Kojto	108:34e6b704fe68	164	*/
Kojto	108:34e6b704fe68	165	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	108:34e6b704fe68	166	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
Kojto	108:34e6b704fe68	167
Kojto	108:34e6b704fe68	168	/**
Kojto	108:34e6b704fe68	169	* @}
Kojto	108:34e6b704fe68	170	*/
Kojto	108:34e6b704fe68	171
Kojto	108:34e6b704fe68	172	/** @addtogroup RCC_Oscillator_Type
Kojto	108:34e6b704fe68	173	* @{
Kojto	108:34e6b704fe68	174	*/
Kojto	108:34e6b704fe68	175	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto	108:34e6b704fe68	176	/**
Kojto	108:34e6b704fe68	177	* @}
Kojto	108:34e6b704fe68	178	*/
Kojto	108:34e6b704fe68	179
Kojto	108:34e6b704fe68	180	/** @addtogroup RCC_Interrupt
Kojto	108:34e6b704fe68	181	* @{
Kojto	108:34e6b704fe68	182	*/
Kojto	108:34e6b704fe68	183	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
Kojto	108:34e6b704fe68	184	/**
Kojto	108:34e6b704fe68	185	* @}
Kojto	108:34e6b704fe68	186	*/
Kojto	108:34e6b704fe68	187
Kojto	108:34e6b704fe68	188	/** @addtogroup RCC_Flag
Kojto	108:34e6b704fe68	189	* @{
Kojto	108:34e6b704fe68	190	*/
Kojto	108:34e6b704fe68	191	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
Kojto	108:34e6b704fe68	192	/**
Kojto	108:34e6b704fe68	193	* @}
Kojto	108:34e6b704fe68	194	*/
Kojto	108:34e6b704fe68	195
Kojto	108:34e6b704fe68	196	/** @addtogroup RCC_System_Clock_Source
Kojto	108:34e6b704fe68	197	* @{
Kojto	108:34e6b704fe68	198	*/
Kojto	108:34e6b704fe68	199	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
Kojto	108:34e6b704fe68	200	/**
Kojto	108:34e6b704fe68	201	* @}
Kojto	108:34e6b704fe68	202	*/
Kojto	108:34e6b704fe68	203
Kojto	108:34e6b704fe68	204	/** @addtogroup RCC_System_Clock_Source_Status
Kojto	108:34e6b704fe68	205	* @{
Kojto	108:34e6b704fe68	206	*/
Kojto	108:34e6b704fe68	207	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
Kojto	108:34e6b704fe68	208	/**
Kojto	108:34e6b704fe68	209	* @}
Kojto	108:34e6b704fe68	210	*/
Kojto	108:34e6b704fe68	211
Kojto	108:34e6b704fe68	212	#else
Kojto	108:34e6b704fe68	213	/** @addtogroup RCC_PLL_Clock_Source
Kojto	108:34e6b704fe68	214	* @{
Kojto	108:34e6b704fe68	215	*/
Kojto	108:34e6b704fe68	216
Kojto	108:34e6b704fe68	217	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	218	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	108:34e6b704fe68	219	#else
Kojto	108:34e6b704fe68	220	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	108:34e6b704fe68	221	#endif
Kojto	108:34e6b704fe68	222
Kojto	108:34e6b704fe68	223	/**
Kojto	108:34e6b704fe68	224	* @}
Kojto	108:34e6b704fe68	225	*/
Kojto	108:34e6b704fe68	226
Kojto	108:34e6b704fe68	227	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	228	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	229	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	230
Kojto	108:34e6b704fe68	231	/** @addtogroup RCC_MCO_Clock_Source
Kojto	108:34e6b704fe68	232	* @{
Kojto	108:34e6b704fe68	233	*/
Kojto	108:34e6b704fe68	234
Kojto	108:34e6b704fe68	235	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	236	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	237
Kojto	108:34e6b704fe68	238	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	108:34e6b704fe68	239
Kojto	108:34e6b704fe68	240	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
Kojto	108:34e6b704fe68	241
Kojto	108:34e6b704fe68	242	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	243	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	244	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	245
Kojto	108:34e6b704fe68	246	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto	108:34e6b704fe68	247	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
Kojto	108:34e6b704fe68	248
Kojto	108:34e6b704fe68	249	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	250	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	251	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	252	/**
Kojto	108:34e6b704fe68	253	* @}
Kojto	108:34e6b704fe68	254	*/
Kojto	108:34e6b704fe68	255
Kojto	108:34e6b704fe68	256	/**
Kojto	108:34e6b704fe68	257	* @}
Kojto	108:34e6b704fe68	258	*/
Kojto	108:34e6b704fe68	259
Kojto	108:34e6b704fe68	260	/**
Kojto	108:34e6b704fe68	261	* @}
Kojto	108:34e6b704fe68	262	*/
Kojto	108:34e6b704fe68	263
bogdanm	85:024bf7f99721	264	/** @addtogroup RCCEx
bogdanm	85:024bf7f99721	265	* @{
bogdanm	85:024bf7f99721	266	*/
bogdanm	85:024bf7f99721	267
Kojto	108:34e6b704fe68	268	/* Private macro -------------------------------------------------------------*/
Kojto	108:34e6b704fe68	269	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	108:34e6b704fe68	270	* @{
Kojto	108:34e6b704fe68	271	*/
Kojto	108:34e6b704fe68	272	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	273	\|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	274
Kojto	108:34e6b704fe68	275	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	276	RCC_PERIPHCLK_RTC))
Kojto	108:34e6b704fe68	277	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	108:34e6b704fe68	278	STM32F030xC */
Kojto	108:34e6b704fe68	279
Kojto	108:34e6b704fe68	280	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	108:34e6b704fe68	281
Kojto	108:34e6b704fe68	282	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	283	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	108:34e6b704fe68	284	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	108:34e6b704fe68	285
Kojto	108:34e6b704fe68	286	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
Kojto	108:34e6b704fe68	287
Kojto	108:34e6b704fe68	288	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	289	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
Kojto	108:34e6b704fe68	290	RCC_PERIPHCLK_USB))
Kojto	108:34e6b704fe68	291	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	108:34e6b704fe68	292
Kojto	108:34e6b704fe68	293	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	108:34e6b704fe68	294
Kojto	108:34e6b704fe68	295	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	108:34e6b704fe68	296	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
Kojto	108:34e6b704fe68	297	#endif /* STM32F051x8 \|\| STM32F058xx */
Kojto	108:34e6b704fe68	298
Kojto	108:34e6b704fe68	299	#if defined(STM32F071xB)
Kojto	108:34e6b704fe68	300
Kojto	108:34e6b704fe68	301	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	108:34e6b704fe68	302	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	108:34e6b704fe68	303	RCC_PERIPHCLK_RTC))
Kojto	108:34e6b704fe68	304	#endif /* STM32F071xB */
Kojto	108:34e6b704fe68	305
Kojto	108:34e6b704fe68	306	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	108:34e6b704fe68	307
Kojto	108:34e6b704fe68	308	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	108:34e6b704fe68	309	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	108:34e6b704fe68	310	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	108:34e6b704fe68	311	#endif /* STM32F072xB \|\| STM32F078xx */
Kojto	108:34e6b704fe68	312
Kojto	108:34e6b704fe68	313	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	314
Kojto	108:34e6b704fe68	315	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
Kojto	108:34e6b704fe68	316	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
Kojto	108:34e6b704fe68	317	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
Kojto	108:34e6b704fe68	318	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	319
Kojto	108:34e6b704fe68	320	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
Kojto	108:34e6b704fe68	321
Kojto	108:34e6b704fe68	322	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
Kojto	108:34e6b704fe68	323	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto	108:34e6b704fe68	324
Kojto	108:34e6b704fe68	325	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
Kojto	108:34e6b704fe68	326
Kojto	108:34e6b704fe68	327	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	108:34e6b704fe68	328
Kojto	108:34e6b704fe68	329	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto	108:34e6b704fe68	330
Kojto	108:34e6b704fe68	331	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	108:34e6b704fe68	332
Kojto	108:34e6b704fe68	333	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	334	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	335
Kojto	108:34e6b704fe68	336	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	108:34e6b704fe68	337	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	338	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	339	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto	108:34e6b704fe68	340
Kojto	108:34e6b704fe68	341	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	342	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	343
Kojto	108:34e6b704fe68	344	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	345
Kojto	108:34e6b704fe68	346	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	108:34e6b704fe68	347	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	108:34e6b704fe68	348	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	349	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto	108:34e6b704fe68	350	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	351
Kojto	108:34e6b704fe68	352
Kojto	108:34e6b704fe68	353	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	354	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	355	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	356	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	357
Kojto	108:34e6b704fe68	358	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	359	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	108:34e6b704fe68	360	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	361	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	362	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	363	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	364
Kojto	108:34e6b704fe68	365	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
Kojto	108:34e6b704fe68	366
Kojto	108:34e6b704fe68	367	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
Kojto	108:34e6b704fe68	368
Kojto	108:34e6b704fe68	369	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
Kojto	108:34e6b704fe68	370
Kojto	108:34e6b704fe68	371	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	372	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	373	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	374	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	375
Kojto	108:34e6b704fe68	376	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
Kojto	108:34e6b704fe68	377	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
Kojto	108:34e6b704fe68	378	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
Kojto	108:34e6b704fe68	379	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
Kojto	108:34e6b704fe68	380
Kojto	108:34e6b704fe68	381	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	382	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
Kojto	108:34e6b704fe68	383	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	384
Kojto	108:34e6b704fe68	385	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	386	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	387	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	388
Kojto	108:34e6b704fe68	389	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
Kojto	108:34e6b704fe68	390	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	391	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Kojto	108:34e6b704fe68	392	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
Kojto	108:34e6b704fe68	393	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
Kojto	108:34e6b704fe68	394	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
Kojto	108:34e6b704fe68	395	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
Kojto	108:34e6b704fe68	396	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
Kojto	108:34e6b704fe68	397	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto	108:34e6b704fe68	398	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
Kojto	108:34e6b704fe68	399	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
Kojto	108:34e6b704fe68	400	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
Kojto	108:34e6b704fe68	401	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
Kojto	108:34e6b704fe68	402	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto	108:34e6b704fe68	403	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	404	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	405	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	406	/**
Kojto	108:34e6b704fe68	407	* @}
Kojto	108:34e6b704fe68	408	*/
Kojto	108:34e6b704fe68	409
bogdanm	85:024bf7f99721	410	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	411
bogdanm	92:4fc01daae5a5	412	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm	92:4fc01daae5a5	413	* @{
bogdanm	92:4fc01daae5a5	414	*/
bogdanm	92:4fc01daae5a5	415
bogdanm	85:024bf7f99721	416	/**
bogdanm	85:024bf7f99721	417	* @brief RCC extended clocks structure definition
bogdanm	85:024bf7f99721	418	*/
Kojto	108:34e6b704fe68	419	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	420	\|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	421	typedef struct
bogdanm	85:024bf7f99721	422	{
bogdanm	85:024bf7f99721	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	425
bogdanm	85:024bf7f99721	426	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	427	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	428
bogdanm	85:024bf7f99721	429	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	430	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	431
bogdanm	85:024bf7f99721	432	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	433	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	434
bogdanm	85:024bf7f99721	435	}RCC_PeriphCLKInitTypeDef;
Kojto	93:e188a91d3eaa	436	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	93:e188a91d3eaa	437	STM32F030xC */
Kojto	93:e188a91d3eaa	438
Kojto	93:e188a91d3eaa	439	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	440	typedef struct
Kojto	93:e188a91d3eaa	441	{
Kojto	93:e188a91d3eaa	442	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	93:e188a91d3eaa	443	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	93:e188a91d3eaa	444
Kojto	93:e188a91d3eaa	445	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	93:e188a91d3eaa	446	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	93:e188a91d3eaa	447
Kojto	93:e188a91d3eaa	448	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	93:e188a91d3eaa	449	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	93:e188a91d3eaa	450
Kojto	93:e188a91d3eaa	451	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	93:e188a91d3eaa	452	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	93:e188a91d3eaa	453
Kojto	93:e188a91d3eaa	454	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	93:e188a91d3eaa	455	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	93:e188a91d3eaa	456
Kojto	93:e188a91d3eaa	457	}RCC_PeriphCLKInitTypeDef;
Kojto	93:e188a91d3eaa	458	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	85:024bf7f99721	459
bogdanm	85:024bf7f99721	460	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	85:024bf7f99721	461	typedef struct
bogdanm	85:024bf7f99721	462	{
bogdanm	85:024bf7f99721	463	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	464	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	465
bogdanm	85:024bf7f99721	466	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	467	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	468
bogdanm	85:024bf7f99721	469	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	470	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	471
bogdanm	85:024bf7f99721	472	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	473	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	474
bogdanm	85:024bf7f99721	475	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	476	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	477
bogdanm	85:024bf7f99721	478	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	479	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	480
bogdanm	85:024bf7f99721	481	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	482	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	483
bogdanm	85:024bf7f99721	484	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	485	typedef struct
bogdanm	85:024bf7f99721	486	{
bogdanm	85:024bf7f99721	487	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	488	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	489
bogdanm	85:024bf7f99721	490	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	491	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	492
bogdanm	85:024bf7f99721	493	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	494	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	495
bogdanm	85:024bf7f99721	496	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	497	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	498
bogdanm	85:024bf7f99721	499	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	500	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	501
bogdanm	85:024bf7f99721	502	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	503	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	504
bogdanm	85:024bf7f99721	505	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	506	typedef struct
bogdanm	85:024bf7f99721	507	{
bogdanm	85:024bf7f99721	508	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	509	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	510
bogdanm	85:024bf7f99721	511	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	512	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	513
bogdanm	85:024bf7f99721	514	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	515	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	516
bogdanm	85:024bf7f99721	517	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	518	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	519
bogdanm	85:024bf7f99721	520	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	521	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	522
bogdanm	85:024bf7f99721	523	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	524	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	525
bogdanm	85:024bf7f99721	526	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	527	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	528
bogdanm	92:4fc01daae5a5	529	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	530	typedef struct
bogdanm	85:024bf7f99721	531	{
bogdanm	85:024bf7f99721	532	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	533	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	534
bogdanm	85:024bf7f99721	535	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	536	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	537
bogdanm	85:024bf7f99721	538	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	539	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	540
bogdanm	85:024bf7f99721	541	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	542	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	543
bogdanm	85:024bf7f99721	544	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	545	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	546
bogdanm	85:024bf7f99721	547	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	548	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	549
bogdanm	85:024bf7f99721	550	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	551	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	552
bogdanm	85:024bf7f99721	553	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	554	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	555
bogdanm	92:4fc01daae5a5	556
bogdanm	92:4fc01daae5a5	557	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	558	typedef struct
bogdanm	85:024bf7f99721	559	{
bogdanm	85:024bf7f99721	560	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	561	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	562
bogdanm	85:024bf7f99721	563	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	564	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	565
bogdanm	85:024bf7f99721	566	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	567	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	568
bogdanm	85:024bf7f99721	569	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	570	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	571
bogdanm	92:4fc01daae5a5	572	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	92:4fc01daae5a5	573	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
bogdanm	92:4fc01daae5a5	574
bogdanm	85:024bf7f99721	575	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	576	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	577
bogdanm	85:024bf7f99721	578	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	579	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	580
bogdanm	85:024bf7f99721	581	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	582	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	583
Kojto	108:34e6b704fe68	584	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	585	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	586	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	587
bogdanm	85:024bf7f99721	588	/**
bogdanm	85:024bf7f99721	589	* @brief RCC_CRS Init structure definition
bogdanm	85:024bf7f99721	590	*/
bogdanm	85:024bf7f99721	591	typedef struct
bogdanm	85:024bf7f99721	592	{
bogdanm	85:024bf7f99721	593	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	85:024bf7f99721	594	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	85:024bf7f99721	595
bogdanm	85:024bf7f99721	596	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	85:024bf7f99721	597	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	85:024bf7f99721	598
bogdanm	85:024bf7f99721	599	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	85:024bf7f99721	600	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	85:024bf7f99721	601
bogdanm	85:024bf7f99721	602	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	85:024bf7f99721	603	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	85:024bf7f99721	604	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	85:024bf7f99721	605
bogdanm	85:024bf7f99721	606	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	85:024bf7f99721	607	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	85:024bf7f99721	608
bogdanm	85:024bf7f99721	609	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	85:024bf7f99721	610	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	85:024bf7f99721	611
bogdanm	85:024bf7f99721	612	}RCC_CRSInitTypeDef;
bogdanm	85:024bf7f99721	613
bogdanm	85:024bf7f99721	614	/**
bogdanm	85:024bf7f99721	615	* @brief RCC_CRS Synchronization structure definition
bogdanm	85:024bf7f99721	616	*/
bogdanm	85:024bf7f99721	617	typedef struct
bogdanm	85:024bf7f99721	618	{
bogdanm	85:024bf7f99721	619	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	85:024bf7f99721	620	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	85:024bf7f99721	621
bogdanm	85:024bf7f99721	622	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	85:024bf7f99721	623	This parameter must be a number between 0 and 0x3F */
bogdanm	85:024bf7f99721	624
bogdanm	85:024bf7f99721	625	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	85:024bf7f99721	626	value latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	627	This parameter must be a number between 0 and 0xFFFF */
bogdanm	85:024bf7f99721	628
bogdanm	85:024bf7f99721	629	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	85:024bf7f99721	630	frequency error counter latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	631	It shows whether the actual frequency is below or above the target.
bogdanm	85:024bf7f99721	632	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	85:024bf7f99721	633
bogdanm	85:024bf7f99721	634	}RCC_CRSSynchroInfoTypeDef;
bogdanm	85:024bf7f99721	635
Kojto	93:e188a91d3eaa	636	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	92:4fc01daae5a5	637	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	638	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	639
bogdanm	92:4fc01daae5a5	640	/**
bogdanm	92:4fc01daae5a5	641	* @}
bogdanm	92:4fc01daae5a5	642	*/
bogdanm	85:024bf7f99721	643
bogdanm	85:024bf7f99721	644	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	645
bogdanm	92:4fc01daae5a5	646	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	85:024bf7f99721	647	* @{
bogdanm	85:024bf7f99721	648	*/
bogdanm	85:024bf7f99721	649
Kojto	108:34e6b704fe68	650	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	651	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	652	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	653	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto	108:34e6b704fe68	654	* @{
Kojto	108:34e6b704fe68	655	*/
Kojto	108:34e6b704fe68	656	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	108:34e6b704fe68	657	#define RCC_HSI48_ON ((uint8_t)0x01)
Kojto	108:34e6b704fe68	658
Kojto	108:34e6b704fe68	659	/**
Kojto	108:34e6b704fe68	660	* @}
Kojto	108:34e6b704fe68	661	*/
Kojto	108:34e6b704fe68	662
Kojto	93:e188a91d3eaa	663	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto	93:e188a91d3eaa	664	* @{
Kojto	93:e188a91d3eaa	665	*/
Kojto	93:e188a91d3eaa	666	#define RCC_CRS_NONE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	667	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	668	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
Kojto	93:e188a91d3eaa	669	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
Kojto	93:e188a91d3eaa	670	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
Kojto	93:e188a91d3eaa	671	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
Kojto	93:e188a91d3eaa	672	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
Kojto	93:e188a91d3eaa	673
Kojto	93:e188a91d3eaa	674	/**
Kojto	93:e188a91d3eaa	675	* @}
Kojto	93:e188a91d3eaa	676	*/
Kojto	93:e188a91d3eaa	677
Kojto	108:34e6b704fe68	678	#else
Kojto	108:34e6b704fe68	679
Kojto	108:34e6b704fe68	680	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto	108:34e6b704fe68	681	* @{
Kojto	108:34e6b704fe68	682	*/
Kojto	108:34e6b704fe68	683	#define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto	108:34e6b704fe68	684	/**
Kojto	108:34e6b704fe68	685	* @}
Kojto	108:34e6b704fe68	686	*/
Kojto	108:34e6b704fe68	687
Kojto	108:34e6b704fe68	688	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	108:34e6b704fe68	689	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	690	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	691
bogdanm	92:4fc01daae5a5	692	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
bogdanm	85:024bf7f99721	693	* @{
bogdanm	85:024bf7f99721	694	*/
Kojto	108:34e6b704fe68	695	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	696	\|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	697	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	698	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	699	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	700
Kojto	93:e188a91d3eaa	701	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	93:e188a91d3eaa	702	STM32F030xC */
Kojto	93:e188a91d3eaa	703
Kojto	93:e188a91d3eaa	704	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	705	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	706	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	93:e188a91d3eaa	707	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	93:e188a91d3eaa	708	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	93:e188a91d3eaa	709
Kojto	93:e188a91d3eaa	710	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	92:4fc01daae5a5	711
bogdanm	92:4fc01daae5a5	712	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	92:4fc01daae5a5	713	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	714	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	715	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	92:4fc01daae5a5	716	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	717	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	718
bogdanm	92:4fc01daae5a5	719	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	720
bogdanm	85:024bf7f99721	721	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	722	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	723	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	724	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	725	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	726
bogdanm	85:024bf7f99721	727	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	728
bogdanm	85:024bf7f99721	729	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	730	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	731	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	732	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	733	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	734	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	735
bogdanm	85:024bf7f99721	736	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	737
bogdanm	92:4fc01daae5a5	738	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	739	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	740	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	741	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	742	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	743	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	744	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	745
bogdanm	92:4fc01daae5a5	746	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	747
bogdanm	92:4fc01daae5a5	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	749	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	750	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	751	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	752	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	753	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	754	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	755
bogdanm	92:4fc01daae5a5	756	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	757
bogdanm	85:024bf7f99721	758	/**
bogdanm	85:024bf7f99721	759	* @}
bogdanm	85:024bf7f99721	760	*/
bogdanm	85:024bf7f99721	761
bogdanm	92:4fc01daae5a5	762	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	763
bogdanm	92:4fc01daae5a5	764	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
bogdanm	85:024bf7f99721	765	* @{
bogdanm	85:024bf7f99721	766	*/
bogdanm	85:024bf7f99721	767	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
bogdanm	85:024bf7f99721	768	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
bogdanm	85:024bf7f99721	769
bogdanm	85:024bf7f99721	770	/**
bogdanm	85:024bf7f99721	771	* @}
bogdanm	85:024bf7f99721	772	*/
bogdanm	85:024bf7f99721	773
bogdanm	92:4fc01daae5a5	774	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	775
Kojto	93:e188a91d3eaa	776	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	777
Kojto	93:e188a91d3eaa	778	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto	93:e188a91d3eaa	779	* @{
Kojto	93:e188a91d3eaa	780	*/
Kojto	93:e188a91d3eaa	781	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto	93:e188a91d3eaa	782
Kojto	93:e188a91d3eaa	783	/**
Kojto	93:e188a91d3eaa	784	* @}
Kojto	93:e188a91d3eaa	785	*/
Kojto	93:e188a91d3eaa	786
Kojto	93:e188a91d3eaa	787	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	93:e188a91d3eaa	788
Kojto	108:34e6b704fe68	789	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	790	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	791
bogdanm	92:4fc01daae5a5	792	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
bogdanm	85:024bf7f99721	793	* @{
bogdanm	85:024bf7f99721	794	*/
bogdanm	85:024bf7f99721	795	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	85:024bf7f99721	796	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	85:024bf7f99721	797	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	85:024bf7f99721	798	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	85:024bf7f99721	799
bogdanm	85:024bf7f99721	800	/**
bogdanm	85:024bf7f99721	801	* @}
bogdanm	85:024bf7f99721	802	*/
bogdanm	85:024bf7f99721	803
bogdanm	92:4fc01daae5a5	804	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	805	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	806
bogdanm	92:4fc01daae5a5	807	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	808
bogdanm	92:4fc01daae5a5	809	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
bogdanm	92:4fc01daae5a5	810	* @{
bogdanm	92:4fc01daae5a5	811	*/
bogdanm	92:4fc01daae5a5	812	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm	92:4fc01daae5a5	813	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm	92:4fc01daae5a5	814	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm	92:4fc01daae5a5	815	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm	92:4fc01daae5a5	816
bogdanm	92:4fc01daae5a5	817	/**
bogdanm	92:4fc01daae5a5	818	* @}
bogdanm	92:4fc01daae5a5	819	*/
bogdanm	92:4fc01daae5a5	820
bogdanm	92:4fc01daae5a5	821	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	822
bogdanm	85:024bf7f99721	823
Kojto	108:34e6b704fe68	824	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	825	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	826	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	827	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	828
bogdanm	92:4fc01daae5a5	829	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
bogdanm	85:024bf7f99721	830	* @{
bogdanm	85:024bf7f99721	831	*/
bogdanm	85:024bf7f99721	832	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm	85:024bf7f99721	833	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm	85:024bf7f99721	834
bogdanm	85:024bf7f99721	835	/**
bogdanm	85:024bf7f99721	836	* @}
bogdanm	85:024bf7f99721	837	*/
bogdanm	85:024bf7f99721	838
bogdanm	92:4fc01daae5a5	839	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	840	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	841	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	842	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	843
bogdanm	92:4fc01daae5a5	844	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
bogdanm	92:4fc01daae5a5	845	* @{
bogdanm	92:4fc01daae5a5	846	*/
bogdanm	92:4fc01daae5a5	847
bogdanm	85:024bf7f99721	848	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	849
Kojto	108:34e6b704fe68	850	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	851
bogdanm	85:024bf7f99721	852	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	853
Kojto	108:34e6b704fe68	854	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	855	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	856	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	857	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	858
bogdanm	85:024bf7f99721	859	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	860	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	861	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	862	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	863	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	864	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm	85:024bf7f99721	865	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm	85:024bf7f99721	866	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm	85:024bf7f99721	867
bogdanm	92:4fc01daae5a5	868	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	869	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
Kojto	93:e188a91d3eaa	870	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	871
bogdanm	85:024bf7f99721	872	/**
bogdanm	85:024bf7f99721	873	* @}
bogdanm	85:024bf7f99721	874	*/
bogdanm	85:024bf7f99721	875
Kojto	108:34e6b704fe68	876	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	877	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	878	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	879
bogdanm	92:4fc01daae5a5	880	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
bogdanm	85:024bf7f99721	881	* @{
bogdanm	85:024bf7f99721	882	*/
bogdanm	85:024bf7f99721	883	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
bogdanm	85:024bf7f99721	884	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	85:024bf7f99721	885	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	85:024bf7f99721	886
bogdanm	85:024bf7f99721	887	/**
bogdanm	85:024bf7f99721	888	* @}
bogdanm	85:024bf7f99721	889	*/
bogdanm	85:024bf7f99721	890
bogdanm	92:4fc01daae5a5	891	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
bogdanm	85:024bf7f99721	892	* @{
bogdanm	85:024bf7f99721	893	*/
bogdanm	85:024bf7f99721	894	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	85:024bf7f99721	895	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	85:024bf7f99721	896	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	85:024bf7f99721	897	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	85:024bf7f99721	898	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	85:024bf7f99721	899	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	85:024bf7f99721	900	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	85:024bf7f99721	901	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	85:024bf7f99721	902
bogdanm	85:024bf7f99721	903	/**
bogdanm	85:024bf7f99721	904	* @}
bogdanm	85:024bf7f99721	905	*/
bogdanm	85:024bf7f99721	906
bogdanm	92:4fc01daae5a5	907	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
bogdanm	85:024bf7f99721	908	* @{
bogdanm	85:024bf7f99721	909	*/
bogdanm	85:024bf7f99721	910	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	85:024bf7f99721	911	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	85:024bf7f99721	912
bogdanm	85:024bf7f99721	913	/**
bogdanm	85:024bf7f99721	914	* @}
bogdanm	85:024bf7f99721	915	*/
bogdanm	85:024bf7f99721	916
bogdanm	92:4fc01daae5a5	917	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
bogdanm	85:024bf7f99721	918	* @{
bogdanm	85:024bf7f99721	919	*/
bogdanm	85:024bf7f99721	920	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	92:4fc01daae5a5	921	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	92:4fc01daae5a5	922
bogdanm	85:024bf7f99721	923	/**
bogdanm	85:024bf7f99721	924	* @}
bogdanm	85:024bf7f99721	925	*/
bogdanm	85:024bf7f99721	926
bogdanm	92:4fc01daae5a5	927	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
bogdanm	85:024bf7f99721	928	* @{
bogdanm	85:024bf7f99721	929	*/
bogdanm	85:024bf7f99721	930	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	85:024bf7f99721	931
bogdanm	85:024bf7f99721	932	/**
bogdanm	85:024bf7f99721	933	* @}
bogdanm	85:024bf7f99721	934	*/
bogdanm	85:024bf7f99721	935
bogdanm	92:4fc01daae5a5	936	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
bogdanm	85:024bf7f99721	937	* @{
bogdanm	85:024bf7f99721	938	*/
bogdanm	92:4fc01daae5a5	939	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	92:4fc01daae5a5	940	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	92:4fc01daae5a5	941	corresponds to a higher output frequency */
bogdanm	85:024bf7f99721	942
bogdanm	85:024bf7f99721	943	/**
bogdanm	85:024bf7f99721	944	* @}
bogdanm	85:024bf7f99721	945	*/
bogdanm	85:024bf7f99721	946
bogdanm	92:4fc01daae5a5	947	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
bogdanm	85:024bf7f99721	948	* @{
bogdanm	85:024bf7f99721	949	*/
bogdanm	85:024bf7f99721	950	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	85:024bf7f99721	951	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	85:024bf7f99721	952
bogdanm	85:024bf7f99721	953	/**
bogdanm	85:024bf7f99721	954	* @}
bogdanm	85:024bf7f99721	955	*/
bogdanm	85:024bf7f99721	956
bogdanm	92:4fc01daae5a5	957	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
bogdanm	85:024bf7f99721	958	* @{
bogdanm	85:024bf7f99721	959	*/
bogdanm	85:024bf7f99721	960	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	85:024bf7f99721	961	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	85:024bf7f99721	962	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	85:024bf7f99721	963	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	85:024bf7f99721	964	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	965	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	85:024bf7f99721	966	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	85:024bf7f99721	967
bogdanm	85:024bf7f99721	968	/**
bogdanm	85:024bf7f99721	969	* @}
bogdanm	85:024bf7f99721	970	*/
bogdanm	85:024bf7f99721	971
bogdanm	92:4fc01daae5a5	972	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
bogdanm	85:024bf7f99721	973	* @{
bogdanm	85:024bf7f99721	974	*/
bogdanm	85:024bf7f99721	975	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	85:024bf7f99721	976	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	85:024bf7f99721	977	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	85:024bf7f99721	978	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	85:024bf7f99721	979	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	980	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	85:024bf7f99721	981	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	85:024bf7f99721	982
bogdanm	85:024bf7f99721	983	/**
bogdanm	85:024bf7f99721	984	* @}
bogdanm	85:024bf7f99721	985	*/
bogdanm	85:024bf7f99721	986
Kojto	93:e188a91d3eaa	987	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	988	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	989	/* STM32F091xC \|\| STM32F098xx */
Kojto	93:e188a91d3eaa	990
bogdanm	85:024bf7f99721	991	/**
bogdanm	85:024bf7f99721	992	* @}
bogdanm	85:024bf7f99721	993	*/
bogdanm	85:024bf7f99721	994
bogdanm	92:4fc01daae5a5	995	/* Exported macros ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	996	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	85:024bf7f99721	997	* @{
bogdanm	85:024bf7f99721	998	*/
bogdanm	85:024bf7f99721	999
bogdanm	92:4fc01daae5a5	1000	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
bogdanm	92:4fc01daae5a5	1001	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	85:024bf7f99721	1002	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	1003	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	1004	* using it.
bogdanm	92:4fc01daae5a5	1005	* @{
bogdanm	85:024bf7f99721	1006	*/
Kojto	108:34e6b704fe68	1007	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1008	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1009	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1010	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1011
Kojto	108:34e6b704fe68	1012	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1013	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1014	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	108:34e6b704fe68	1015	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1016	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
Kojto	108:34e6b704fe68	1017	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1018	} while(0)
bogdanm	85:024bf7f99721	1019
Kojto	108:34e6b704fe68	1020	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm	85:024bf7f99721	1021
Kojto	93:e188a91d3eaa	1022	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	93:e188a91d3eaa	1023	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1024	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	1025	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1026
Kojto	108:34e6b704fe68	1027	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1028	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1029
Kojto	108:34e6b704fe68	1030	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1031	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1032	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto	108:34e6b704fe68	1033	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1034	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
Kojto	108:34e6b704fe68	1035	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1036	} while(0)
bogdanm	85:024bf7f99721	1037
Kojto	108:34e6b704fe68	1038	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	85:024bf7f99721	1039
Kojto	93:e188a91d3eaa	1040	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1041	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1042
Kojto	108:34e6b704fe68	1043	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1044	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1045	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1046	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1047
Kojto	108:34e6b704fe68	1048	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1049	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1050	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	108:34e6b704fe68	1051	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1052	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
Kojto	108:34e6b704fe68	1053	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1054	} while(0)
bogdanm	85:024bf7f99721	1055
Kojto	108:34e6b704fe68	1056	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	85:024bf7f99721	1057
bogdanm	92:4fc01daae5a5	1058	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1059	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1060	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1061	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1062
bogdanm	92:4fc01daae5a5	1063	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1064
Kojto	108:34e6b704fe68	1065	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1066	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1067	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto	108:34e6b704fe68	1068	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1069	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
Kojto	108:34e6b704fe68	1070	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1071	} while(0)
bogdanm	92:4fc01daae5a5	1072
Kojto	108:34e6b704fe68	1073	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm	92:4fc01daae5a5	1074
bogdanm	92:4fc01daae5a5	1075	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1076
bogdanm	85:024bf7f99721	1077	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	85:024bf7f99721	1078	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	1079	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	1080	* using it.
bogdanm	85:024bf7f99721	1081	*/
Kojto	108:34e6b704fe68	1082	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1083	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1084	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1085	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1086	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1087
Kojto	108:34e6b704fe68	1088	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1089	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1090	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	108:34e6b704fe68	1091	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1092	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	108:34e6b704fe68	1093	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1094	} while(0)
Kojto	108:34e6b704fe68	1095
Kojto	108:34e6b704fe68	1096	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	85:024bf7f99721	1097
Kojto	108:34e6b704fe68	1098	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1099	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1100	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1101	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1102
Kojto	108:34e6b704fe68	1103	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1104	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1105	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1106	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1107	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1108
Kojto	108:34e6b704fe68	1109	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1110	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1111	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	108:34e6b704fe68	1112	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1113	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	108:34e6b704fe68	1114	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1115	} while(0)
Kojto	108:34e6b704fe68	1116
Kojto	108:34e6b704fe68	1117	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	85:024bf7f99721	1118
bogdanm	92:4fc01daae5a5	1119	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1120	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1121	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1122	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1123
Kojto	108:34e6b704fe68	1124	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1125	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1126	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1127	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1128	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1129
Kojto	108:34e6b704fe68	1130	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1131	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1132	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	108:34e6b704fe68	1133	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1134	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	108:34e6b704fe68	1135	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1136	} while(0)
bogdanm	85:024bf7f99721	1137
Kojto	108:34e6b704fe68	1138	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	85:024bf7f99721	1139
bogdanm	92:4fc01daae5a5	1140	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	92:4fc01daae5a5	1141	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1142	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1143	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1144	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1145
Kojto	108:34e6b704fe68	1146	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1147	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1148	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1149	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1150
Kojto	108:34e6b704fe68	1151	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1152	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	108:34e6b704fe68	1154	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	108:34e6b704fe68	1156	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1157	} while(0)
Kojto	108:34e6b704fe68	1158	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1159	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	108:34e6b704fe68	1161	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	108:34e6b704fe68	1163	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1164	} while(0)
bogdanm	85:024bf7f99721	1165
Kojto	108:34e6b704fe68	1166	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	108:34e6b704fe68	1167	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	85:024bf7f99721	1168
bogdanm	85:024bf7f99721	1169	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1170	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1171	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1172	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1173
Kojto	108:34e6b704fe68	1174	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1177
Kojto	108:34e6b704fe68	1178	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1179	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1180	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	108:34e6b704fe68	1181	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1182	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	108:34e6b704fe68	1183	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1184	} while(0)
bogdanm	85:024bf7f99721	1185
Kojto	108:34e6b704fe68	1186	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	85:024bf7f99721	1187
bogdanm	85:024bf7f99721	1188	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1189	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1190	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1191
Kojto	108:34e6b704fe68	1192	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1193	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1194	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1195	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1196
Kojto	108:34e6b704fe68	1197	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1198	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1199	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	108:34e6b704fe68	1200	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1201	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	108:34e6b704fe68	1202	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1203	} while(0)
bogdanm	85:024bf7f99721	1204
Kojto	108:34e6b704fe68	1205	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	85:024bf7f99721	1206
bogdanm	92:4fc01daae5a5	1207	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1208	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1209	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1210	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1211
Kojto	108:34e6b704fe68	1212	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1213	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1214
Kojto	108:34e6b704fe68	1215	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1216	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	108:34e6b704fe68	1218	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	108:34e6b704fe68	1220	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1221	} while(0)
Kojto	108:34e6b704fe68	1222	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1223	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	108:34e6b704fe68	1225	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	108:34e6b704fe68	1227	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1228	} while(0)
Kojto	108:34e6b704fe68	1229	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1230	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
Kojto	108:34e6b704fe68	1232	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
Kojto	108:34e6b704fe68	1234	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1235	} while(0)
bogdanm	85:024bf7f99721	1236
Kojto	108:34e6b704fe68	1237	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	108:34e6b704fe68	1238	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	108:34e6b704fe68	1239	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
bogdanm	85:024bf7f99721	1240
Kojto	93:e188a91d3eaa	1241	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1242	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1243
Kojto	108:34e6b704fe68	1244	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1245	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1246
Kojto	108:34e6b704fe68	1247	#define __HAL_RCC_USB_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1248	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1249	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto	108:34e6b704fe68	1250	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1251	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
Kojto	108:34e6b704fe68	1252	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1253	} while(0)
bogdanm	85:024bf7f99721	1254
Kojto	108:34e6b704fe68	1255	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm	85:024bf7f99721	1256
Kojto	93:e188a91d3eaa	1257	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1258	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1259
Kojto	108:34e6b704fe68	1260	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	108:34e6b704fe68	1261	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1262
Kojto	108:34e6b704fe68	1263	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1264	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto	108:34e6b704fe68	1266	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
Kojto	108:34e6b704fe68	1268	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1269	} while(0)
Kojto	108:34e6b704fe68	1270	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm	85:024bf7f99721	1271
bogdanm	92:4fc01daae5a5	1272	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	92:4fc01daae5a5	1273	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1274
Kojto	108:34e6b704fe68	1275	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1276	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1277	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1278
Kojto	108:34e6b704fe68	1279	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1280	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1281	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
Kojto	108:34e6b704fe68	1282	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1283	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
Kojto	108:34e6b704fe68	1284	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1285	} while(0)
bogdanm	85:024bf7f99721	1286
Kojto	108:34e6b704fe68	1287	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	85:024bf7f99721	1288
bogdanm	92:4fc01daae5a5	1289	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1290	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1291	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1292
Kojto	93:e188a91d3eaa	1293	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	92:4fc01daae5a5	1294
Kojto	108:34e6b704fe68	1295	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1296	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
Kojto	108:34e6b704fe68	1298	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
Kojto	108:34e6b704fe68	1300	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1301	} while(0)
bogdanm	92:4fc01daae5a5	1302
Kojto	108:34e6b704fe68	1303	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
bogdanm	92:4fc01daae5a5	1304
Kojto	93:e188a91d3eaa	1305	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1306
bogdanm	85:024bf7f99721	1307	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	85:024bf7f99721	1308	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	1309	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	1310	* using it.
bogdanm	85:024bf7f99721	1311	*/
Kojto	108:34e6b704fe68	1312	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1313	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1314	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1315	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1316
Kojto	108:34e6b704fe68	1317	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1318	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1319	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	108:34e6b704fe68	1320	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1321	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
Kojto	108:34e6b704fe68	1322	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1323	} while(0)
bogdanm	85:024bf7f99721	1324
Kojto	108:34e6b704fe68	1325	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm	85:024bf7f99721	1326
Kojto	93:e188a91d3eaa	1327	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1328	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1329	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1330	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1331
Kojto	93:e188a91d3eaa	1332	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	1333
Kojto	108:34e6b704fe68	1334	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1335	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1336	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	108:34e6b704fe68	1337	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1338	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	108:34e6b704fe68	1339	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1340	} while(0)
Kojto	93:e188a91d3eaa	1341
Kojto	108:34e6b704fe68	1342	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	93:e188a91d3eaa	1343
Kojto	93:e188a91d3eaa	1344	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	1345
bogdanm	92:4fc01daae5a5	1346	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1347
Kojto	108:34e6b704fe68	1348	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1349	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
Kojto	108:34e6b704fe68	1351	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
Kojto	108:34e6b704fe68	1353	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1354	} while(0)
Kojto	108:34e6b704fe68	1355	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	1356	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
Kojto	108:34e6b704fe68	1358	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
Kojto	108:34e6b704fe68	1360	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	1361	} while(0)
bogdanm	92:4fc01daae5a5	1362
Kojto	108:34e6b704fe68	1363	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
Kojto	108:34e6b704fe68	1364	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
bogdanm	92:4fc01daae5a5	1365
bogdanm	92:4fc01daae5a5	1366	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1367
bogdanm	92:4fc01daae5a5	1368	/**
bogdanm	92:4fc01daae5a5	1369	* @}
bogdanm	92:4fc01daae5a5	1370	*/
bogdanm	92:4fc01daae5a5	1371
bogdanm	92:4fc01daae5a5	1372
bogdanm	92:4fc01daae5a5	1373	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
bogdanm	92:4fc01daae5a5	1374	* @brief Forces or releases peripheral reset.
bogdanm	92:4fc01daae5a5	1375	* @{
bogdanm	92:4fc01daae5a5	1376	*/
bogdanm	85:024bf7f99721	1377
bogdanm	85:024bf7f99721	1378	/** @brief Force or release AHB peripheral reset.
bogdanm	85:024bf7f99721	1379	*/
Kojto	108:34e6b704fe68	1380	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1381	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1382	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1383	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1384
Kojto	108:34e6b704fe68	1385	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	1386
Kojto	108:34e6b704fe68	1387	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	1388
bogdanm	85:024bf7f99721	1389	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1390	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1391	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1392	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1393
Kojto	108:34e6b704fe68	1394	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1395	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1396
Kojto	108:34e6b704fe68	1397	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	1398
Kojto	108:34e6b704fe68	1399	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	1400
Kojto	93:e188a91d3eaa	1401	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1402	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1403
Kojto	108:34e6b704fe68	1404	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1405	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1406	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1407	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1408
Kojto	108:34e6b704fe68	1409	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	1410
Kojto	108:34e6b704fe68	1411	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	1412
bogdanm	92:4fc01daae5a5	1413	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1414	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1415	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1416	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1417
bogdanm	85:024bf7f99721	1418	/** @brief Force or release APB1 peripheral reset.
bogdanm	85:024bf7f99721	1419	*/
Kojto	108:34e6b704fe68	1420	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1421	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1422	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1423	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1424	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1425
Kojto	108:34e6b704fe68	1426	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	108:34e6b704fe68	1427	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	1428
Kojto	108:34e6b704fe68	1429	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	108:34e6b704fe68	1430	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	1431
Kojto	93:e188a91d3eaa	1432	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1433	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1434	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1435	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1436
Kojto	108:34e6b704fe68	1437	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1438	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1439	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1440	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1441	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1442
Kojto	108:34e6b704fe68	1443	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	1444
Kojto	108:34e6b704fe68	1445	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	1446
bogdanm	92:4fc01daae5a5	1447	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	92:4fc01daae5a5	1448	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1449	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1450	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1451	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1452
Kojto	108:34e6b704fe68	1453	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1454	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1455	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1456	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1457
Kojto	108:34e6b704fe68	1458	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	108:34e6b704fe68	1459	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	1460
Kojto	108:34e6b704fe68	1461	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	108:34e6b704fe68	1462	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	1463
bogdanm	85:024bf7f99721	1464	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1465	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1467	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1468
Kojto	108:34e6b704fe68	1469	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1470	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1471	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1472
Kojto	108:34e6b704fe68	1473	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1474
Kojto	108:34e6b704fe68	1475	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1476
bogdanm	85:024bf7f99721	1477	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1478	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1479	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1480
Kojto	108:34e6b704fe68	1481	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1482	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1483	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1484	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1485
Kojto	108:34e6b704fe68	1486	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1487
Kojto	108:34e6b704fe68	1488	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1489
bogdanm	92:4fc01daae5a5	1490	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1491	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1492	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1493	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1494
Kojto	108:34e6b704fe68	1495	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1496	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1497
Kojto	108:34e6b704fe68	1498	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	108:34e6b704fe68	1499	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	108:34e6b704fe68	1500	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1501
Kojto	108:34e6b704fe68	1502	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	108:34e6b704fe68	1503	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	108:34e6b704fe68	1504	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1505
Kojto	93:e188a91d3eaa	1506	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1507	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1508
Kojto	108:34e6b704fe68	1509	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1510	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1511
Kojto	108:34e6b704fe68	1512	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1513
Kojto	108:34e6b704fe68	1514	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1515
Kojto	93:e188a91d3eaa	1516	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1517	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1518
Kojto	108:34e6b704fe68	1519	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	108:34e6b704fe68	1520	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1521
Kojto	108:34e6b704fe68	1522	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1523
Kojto	108:34e6b704fe68	1524	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1525
bogdanm	92:4fc01daae5a5	1526	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	92:4fc01daae5a5	1527	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1528
Kojto	108:34e6b704fe68	1529	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1530	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1531	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1532
Kojto	108:34e6b704fe68	1533	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1534
Kojto	108:34e6b704fe68	1535	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1536
bogdanm	92:4fc01daae5a5	1537	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1538	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1539	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1540
Kojto	93:e188a91d3eaa	1541	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	92:4fc01daae5a5	1542
Kojto	108:34e6b704fe68	1543	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
bogdanm	92:4fc01daae5a5	1544
Kojto	108:34e6b704fe68	1545	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
bogdanm	92:4fc01daae5a5	1546
Kojto	93:e188a91d3eaa	1547	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1548
bogdanm	85:024bf7f99721	1549
bogdanm	85:024bf7f99721	1550	/** @brief Force or release APB2 peripheral reset.
bogdanm	85:024bf7f99721	1551	*/
Kojto	108:34e6b704fe68	1552	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1553	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1554	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1555	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1556
Kojto	108:34e6b704fe68	1557	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1558
Kojto	108:34e6b704fe68	1559	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1560
Kojto	93:e188a91d3eaa	1561	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1562	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1563	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1564	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1565
Kojto	93:e188a91d3eaa	1566	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	1567
Kojto	108:34e6b704fe68	1568	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	93:e188a91d3eaa	1569
Kojto	108:34e6b704fe68	1570	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	93:e188a91d3eaa	1571
Kojto	93:e188a91d3eaa	1572	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	1573
bogdanm	92:4fc01daae5a5	1574	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1575
Kojto	108:34e6b704fe68	1576	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
Kojto	108:34e6b704fe68	1577	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
bogdanm	85:024bf7f99721	1578
Kojto	108:34e6b704fe68	1579	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
Kojto	108:34e6b704fe68	1580	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
bogdanm	92:4fc01daae5a5	1581
bogdanm	92:4fc01daae5a5	1582	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1583
bogdanm	92:4fc01daae5a5	1584	/**
bogdanm	92:4fc01daae5a5	1585	* @}
bogdanm	92:4fc01daae5a5	1586	*/
Kojto	108:34e6b704fe68	1587
Kojto	108:34e6b704fe68	1588	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1589	* @brief Get the enable or disable status of peripheral clock.
Kojto	108:34e6b704fe68	1590	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	1591	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	1592	* using it.
Kojto	108:34e6b704fe68	1593	* @{
Kojto	108:34e6b704fe68	1594	*/
Kojto	108:34e6b704fe68	1595	/** @brief AHB Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1596	*/
Kojto	108:34e6b704fe68	1597	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1598	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1599	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1600	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1601
Kojto	108:34e6b704fe68	1602	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
Kojto	108:34e6b704fe68	1603	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
Kojto	108:34e6b704fe68	1604
Kojto	108:34e6b704fe68	1605	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	108:34e6b704fe68	1606	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1607	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1608	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1609
Kojto	108:34e6b704fe68	1610	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1611	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1612
Kojto	108:34e6b704fe68	1613	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
Kojto	108:34e6b704fe68	1614	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
Kojto	108:34e6b704fe68	1615
Kojto	108:34e6b704fe68	1616	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1617	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1618
Kojto	108:34e6b704fe68	1619	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1620	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1621	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1622	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1623
Kojto	108:34e6b704fe68	1624	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
Kojto	108:34e6b704fe68	1625	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
Kojto	108:34e6b704fe68	1626
Kojto	108:34e6b704fe68	1627	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1628	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1629	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1630	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1631
Kojto	108:34e6b704fe68	1632	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1633
Kojto	108:34e6b704fe68	1634	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
Kojto	108:34e6b704fe68	1635	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
Kojto	108:34e6b704fe68	1636
Kojto	108:34e6b704fe68	1637	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1638
Kojto	108:34e6b704fe68	1639	/** @brief APB1 Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1640	*/
Kojto	108:34e6b704fe68	1641	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1642	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1643	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1644	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1645	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1646
Kojto	108:34e6b704fe68	1647	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto	108:34e6b704fe68	1648	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto	108:34e6b704fe68	1649
Kojto	108:34e6b704fe68	1650	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1651	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1652	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1653	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1654
Kojto	108:34e6b704fe68	1655	#if defined(STM32F030x8)\
Kojto	108:34e6b704fe68	1656	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1657	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1658	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1659	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1660
Kojto	108:34e6b704fe68	1661	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto	108:34e6b704fe68	1662	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto	108:34e6b704fe68	1663
Kojto	108:34e6b704fe68	1664	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1665	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1666	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1667	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1668
Kojto	108:34e6b704fe68	1669	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1670	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1671	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1672	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1673	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1674
Kojto	108:34e6b704fe68	1675	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	108:34e6b704fe68	1676	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	108:34e6b704fe68	1677
Kojto	108:34e6b704fe68	1678	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
Kojto	108:34e6b704fe68	1679	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1680	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1681	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1682	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1683
Kojto	108:34e6b704fe68	1684	#if defined(STM32F030x8) \
Kojto	108:34e6b704fe68	1685	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1686	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1687	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1688
Kojto	108:34e6b704fe68	1689	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	108:34e6b704fe68	1690	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto	108:34e6b704fe68	1691	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	108:34e6b704fe68	1692	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto	108:34e6b704fe68	1693
Kojto	108:34e6b704fe68	1694	#endif /* STM32F030x8 \|\| */
Kojto	108:34e6b704fe68	1695	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1696	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1697	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1698
Kojto	108:34e6b704fe68	1699	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1700	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1701	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1702
Kojto	108:34e6b704fe68	1703	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
Kojto	108:34e6b704fe68	1704	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
Kojto	108:34e6b704fe68	1705
Kojto	108:34e6b704fe68	1706	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1707	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1708	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1709
Kojto	108:34e6b704fe68	1710	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1711	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1712	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1713	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1714
Kojto	108:34e6b704fe68	1715	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto	108:34e6b704fe68	1716	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto	108:34e6b704fe68	1717
Kojto	108:34e6b704fe68	1718	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1719	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1720	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1721	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1722
Kojto	108:34e6b704fe68	1723	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1724	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1725
Kojto	108:34e6b704fe68	1726	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	108:34e6b704fe68	1727	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	108:34e6b704fe68	1728	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
Kojto	108:34e6b704fe68	1729	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	108:34e6b704fe68	1730	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	108:34e6b704fe68	1731	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
Kojto	108:34e6b704fe68	1732
Kojto	108:34e6b704fe68	1733	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1734	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1735
Kojto	108:34e6b704fe68	1736	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1737	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
Kojto	108:34e6b704fe68	1738
Kojto	108:34e6b704fe68	1739	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
Kojto	108:34e6b704fe68	1740	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
Kojto	108:34e6b704fe68	1741
Kojto	108:34e6b704fe68	1742	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1743	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
Kojto	108:34e6b704fe68	1744
Kojto	108:34e6b704fe68	1745	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
Kojto	108:34e6b704fe68	1746	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1747
Kojto	108:34e6b704fe68	1748	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	108:34e6b704fe68	1749	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	108:34e6b704fe68	1750
Kojto	108:34e6b704fe68	1751	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
Kojto	108:34e6b704fe68	1752	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1753
Kojto	108:34e6b704fe68	1754	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1755	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1756	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1757
Kojto	108:34e6b704fe68	1758	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
Kojto	108:34e6b704fe68	1759	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
Kojto	108:34e6b704fe68	1760
Kojto	108:34e6b704fe68	1761	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	108:34e6b704fe68	1762	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	108:34e6b704fe68	1763	/* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1764
Kojto	108:34e6b704fe68	1765	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1766
Kojto	108:34e6b704fe68	1767	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
Kojto	108:34e6b704fe68	1768	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
Kojto	108:34e6b704fe68	1769
Kojto	108:34e6b704fe68	1770	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1771
Kojto	108:34e6b704fe68	1772	/** @brief APB1 Peripheral Clock Enable Disable Status
Kojto	108:34e6b704fe68	1773	*/
Kojto	108:34e6b704fe68	1774	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1775	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1776	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1777	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1778
Kojto	108:34e6b704fe68	1779	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
Kojto	108:34e6b704fe68	1780	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
Kojto	108:34e6b704fe68	1781
Kojto	108:34e6b704fe68	1782	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	108:34e6b704fe68	1783	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	108:34e6b704fe68	1784	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	108:34e6b704fe68	1785	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1786
Kojto	108:34e6b704fe68	1787	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	108:34e6b704fe68	1788
Kojto	108:34e6b704fe68	1789	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto	108:34e6b704fe68	1790	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto	108:34e6b704fe68	1791
Kojto	108:34e6b704fe68	1792	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	108:34e6b704fe68	1793
Kojto	108:34e6b704fe68	1794	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	108:34e6b704fe68	1795
Kojto	108:34e6b704fe68	1796	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
Kojto	108:34e6b704fe68	1797	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
Kojto	108:34e6b704fe68	1798	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
Kojto	108:34e6b704fe68	1799	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
Kojto	108:34e6b704fe68	1800
Kojto	108:34e6b704fe68	1801	#endif /* STM32F091xC \|\| STM32F098xx */
Kojto	108:34e6b704fe68	1802	/**
Kojto	108:34e6b704fe68	1803	* @}
Kojto	108:34e6b704fe68	1804	*/
Kojto	108:34e6b704fe68	1805
bogdanm	92:4fc01daae5a5	1806
bogdanm	92:4fc01daae5a5	1807	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
bogdanm	92:4fc01daae5a5	1808	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
bogdanm	85:024bf7f99721	1809	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1810	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	1811	* you have to select another source of the system clock then stop the HSI14.
bogdanm	85:024bf7f99721	1812	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
bogdanm	85:024bf7f99721	1813	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
bogdanm	85:024bf7f99721	1814	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	85:024bf7f99721	1815	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
bogdanm	85:024bf7f99721	1816	* clock cycles.
bogdanm	92:4fc01daae5a5	1817	* @{
bogdanm	85:024bf7f99721	1818	*/
Kojto	108:34e6b704fe68	1819	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1820	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1821	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1822
bogdanm	85:024bf7f99721	1823	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1824	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1825
bogdanm	85:024bf7f99721	1826	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1827	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1828	* @arg RCC_HSI48_ON: HSI48 enabled
bogdanm	85:024bf7f99721	1829	* @arg RCC_HSI48_OFF: HSI48 disabled
bogdanm	85:024bf7f99721	1830	*/
bogdanm	85:024bf7f99721	1831	#define __HAL_RCC_GET_HSI48_STATE() \
bogdanm	85:024bf7f99721	1832	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
bogdanm	85:024bf7f99721	1833
bogdanm	85:024bf7f99721	1834	#else
bogdanm	85:024bf7f99721	1835
bogdanm	85:024bf7f99721	1836	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1837	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1838	* @arg RCC_HSI_OFF: HSI48 disabled
bogdanm	85:024bf7f99721	1839	*/
bogdanm	85:024bf7f99721	1840	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
bogdanm	85:024bf7f99721	1841
bogdanm	92:4fc01daae5a5	1842	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1843	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1844	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1845
bogdanm	92:4fc01daae5a5	1846	/**
bogdanm	92:4fc01daae5a5	1847	* @}
bogdanm	92:4fc01daae5a5	1848	*/
bogdanm	92:4fc01daae5a5	1849
bogdanm	92:4fc01daae5a5	1850	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
bogdanm	92:4fc01daae5a5	1851	* @{
bogdanm	92:4fc01daae5a5	1852	*/
Kojto	108:34e6b704fe68	1853	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1854	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1855	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1856
bogdanm	85:024bf7f99721	1857	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	85:024bf7f99721	1858	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	85:024bf7f99721	1859	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1860	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
bogdanm	85:024bf7f99721	1861	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1862	*/
bogdanm	85:024bf7f99721	1863	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	85:024bf7f99721	1864	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
bogdanm	85:024bf7f99721	1865
bogdanm	85:024bf7f99721	1866	/** @brief Macro to get the USB clock source.
bogdanm	85:024bf7f99721	1867	* @retval The clock source can be one of the following values:
Kojto	108:34e6b704fe68	1868	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	85:024bf7f99721	1869	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1870	*/
bogdanm	85:024bf7f99721	1871	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
bogdanm	85:024bf7f99721	1872
bogdanm	92:4fc01daae5a5	1873	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	1874	/* STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	1875	/* STM32F070x6 \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1876
Kojto	108:34e6b704fe68	1877	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	1878	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
Kojto	108:34e6b704fe68	1879	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1880	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1881
bogdanm	85:024bf7f99721	1882	/** @brief Macro to configure the CEC clock.
bogdanm	85:024bf7f99721	1883	* @param __CECCLKSource__: specifies the CEC clock source.
bogdanm	85:024bf7f99721	1884	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1885	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	85:024bf7f99721	1886	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	85:024bf7f99721	1887	*/
bogdanm	85:024bf7f99721	1888	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm	85:024bf7f99721	1889	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm	85:024bf7f99721	1890
bogdanm	85:024bf7f99721	1891	/** @brief Macro to get the HDMI CEC clock source.
bogdanm	85:024bf7f99721	1892	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1893	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	85:024bf7f99721	1894	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	85:024bf7f99721	1895	*/
bogdanm	85:024bf7f99721	1896	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm	85:024bf7f99721	1897
bogdanm	92:4fc01daae5a5	1898	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1899	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1900	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1901	/* STM32F091xC \|\| defined(STM32F098xx) */
bogdanm	85:024bf7f99721	1902
Kojto	108:34e6b704fe68	1903	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
Kojto	108:34e6b704fe68	1904	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
Kojto	108:34e6b704fe68	1905	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
Kojto	108:34e6b704fe68	1906	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1907
bogdanm	85:024bf7f99721	1908	/** @brief Macro to configure the MCO clock.
bogdanm	85:024bf7f99721	1909	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	85:024bf7f99721	1910	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1911	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	85:024bf7f99721	1912	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	85:024bf7f99721	1913	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	85:024bf7f99721	1914	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	85:024bf7f99721	1915	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
bogdanm	85:024bf7f99721	1916	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	85:024bf7f99721	1917	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	85:024bf7f99721	1918	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	85:024bf7f99721	1919	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	85:024bf7f99721	1920	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	85:024bf7f99721	1921	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1922	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
bogdanm	85:024bf7f99721	1923	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
bogdanm	85:024bf7f99721	1924	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
bogdanm	85:024bf7f99721	1925	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
bogdanm	85:024bf7f99721	1926	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
bogdanm	85:024bf7f99721	1927	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
bogdanm	85:024bf7f99721	1928	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
bogdanm	85:024bf7f99721	1929	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
bogdanm	85:024bf7f99721	1930	*/
bogdanm	85:024bf7f99721	1931	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	85:024bf7f99721	1932	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
bogdanm	85:024bf7f99721	1933	#else
bogdanm	85:024bf7f99721	1934
bogdanm	85:024bf7f99721	1935	/** @brief Macro to configure the MCO clock.
bogdanm	85:024bf7f99721	1936	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	85:024bf7f99721	1937	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1938	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	85:024bf7f99721	1939	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	85:024bf7f99721	1940	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	85:024bf7f99721	1941	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	85:024bf7f99721	1942	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	85:024bf7f99721	1943	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	85:024bf7f99721	1944	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	85:024bf7f99721	1945	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	85:024bf7f99721	1946	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	85:024bf7f99721	1947	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1948	* @arg RCC_MCODIV_1: No division applied on MCO clock source
bogdanm	85:024bf7f99721	1949	*/
bogdanm	85:024bf7f99721	1950	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	85:024bf7f99721	1951	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
bogdanm	85:024bf7f99721	1952
Kojto	93:e188a91d3eaa	1953	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1954	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	1955	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1956	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1957
Kojto	108:34e6b704fe68	1958	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	1959	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	93:e188a91d3eaa	1960	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	93:e188a91d3eaa	1961	* @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto	93:e188a91d3eaa	1962	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1963	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	93:e188a91d3eaa	1964	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	93:e188a91d3eaa	1965	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	93:e188a91d3eaa	1966	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	93:e188a91d3eaa	1967	*/
Kojto	93:e188a91d3eaa	1968	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto	93:e188a91d3eaa	1969	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto	93:e188a91d3eaa	1970
Kojto	93:e188a91d3eaa	1971	/** @brief Macro to get the USART2 clock source.
Kojto	93:e188a91d3eaa	1972	* @retval The clock source can be one of the following values:
Kojto	93:e188a91d3eaa	1973	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	93:e188a91d3eaa	1974	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	93:e188a91d3eaa	1975	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	93:e188a91d3eaa	1976	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	93:e188a91d3eaa	1977	*/
Kojto	93:e188a91d3eaa	1978	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto	93:e188a91d3eaa	1979	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
bogdanm	92:4fc01daae5a5	1980
bogdanm	92:4fc01daae5a5	1981	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1982	/** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm	92:4fc01daae5a5	1983	* @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm	92:4fc01daae5a5	1984	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1985	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	92:4fc01daae5a5	1986	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	92:4fc01daae5a5	1987	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	92:4fc01daae5a5	1988	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	92:4fc01daae5a5	1989	*/
bogdanm	92:4fc01daae5a5	1990	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm	92:4fc01daae5a5	1991	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm	85:024bf7f99721	1992
bogdanm	92:4fc01daae5a5	1993	/** @brief Macro to get the USART3 clock source.
bogdanm	92:4fc01daae5a5	1994	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	1995	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	92:4fc01daae5a5	1996	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	92:4fc01daae5a5	1997	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	92:4fc01daae5a5	1998	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	92:4fc01daae5a5	1999	*/
bogdanm	92:4fc01daae5a5	2000	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm	92:4fc01daae5a5	2001
Kojto	93:e188a91d3eaa	2002	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	2003	/**
bogdanm	92:4fc01daae5a5	2004	* @}
bogdanm	92:4fc01daae5a5	2005	*/
bogdanm	92:4fc01daae5a5	2006
Kojto	108:34e6b704fe68	2007	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	2008	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	2009	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	2010
bogdanm	92:4fc01daae5a5	2011	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
bogdanm	92:4fc01daae5a5	2012	* @{
bogdanm	92:4fc01daae5a5	2013	*/
bogdanm	85:024bf7f99721	2014	/* Interrupt & Flag management */
bogdanm	85:024bf7f99721	2015
bogdanm	85:024bf7f99721	2016	/**
bogdanm	85:024bf7f99721	2017	* @brief Enables the specified CRS interrupts.
bogdanm	85:024bf7f99721	2018	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	85:024bf7f99721	2019	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	2020	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	2021	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	2022	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	2023	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	2024	* @retval None
bogdanm	85:024bf7f99721	2025	*/
bogdanm	85:024bf7f99721	2026	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	2027
bogdanm	85:024bf7f99721	2028	/**
bogdanm	85:024bf7f99721	2029	* @brief Disables the specified CRS interrupts.
bogdanm	85:024bf7f99721	2030	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	85:024bf7f99721	2031	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	2032	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	2033	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	2034	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	2035	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	2036	* @retval None
bogdanm	85:024bf7f99721	2037	*/
bogdanm	85:024bf7f99721	2038	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	2039
bogdanm	85:024bf7f99721	2040	/** @brief Check the CRS's interrupt has occurred or not.
bogdanm	85:024bf7f99721	2041	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	85:024bf7f99721	2042	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	2043	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	2044	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	2045	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	2046	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	2047	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	85:024bf7f99721	2048	*/
bogdanm	85:024bf7f99721	2049	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	85:024bf7f99721	2050
bogdanm	85:024bf7f99721	2051	/** @brief Clear the CRS's interrupt pending bits
bogdanm	85:024bf7f99721	2052	* bits to clear the selected interrupt pending bits.
bogdanm	85:024bf7f99721	2053	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	85:024bf7f99721	2054	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	2055	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	2056	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	2057	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	2058	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	2059	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	85:024bf7f99721	2060	* @arg RCC_CRS_IT_SYNCERR
bogdanm	85:024bf7f99721	2061	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	85:024bf7f99721	2062	*/
bogdanm	85:024bf7f99721	2063	/* CRS IT Error Mask */
bogdanm	85:024bf7f99721	2064	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	85:024bf7f99721	2065
bogdanm	92:4fc01daae5a5	2066	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	92:4fc01daae5a5	2067	(CRS->ICR \|= (__INTERRUPT__)))
bogdanm	85:024bf7f99721	2068
bogdanm	85:024bf7f99721	2069	/**
bogdanm	85:024bf7f99721	2070	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	85:024bf7f99721	2071	* @param _FLAG_: specifies the flag to check.
bogdanm	85:024bf7f99721	2072	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	2073	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	85:024bf7f99721	2074	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	85:024bf7f99721	2075	* @arg RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	2076	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	85:024bf7f99721	2077	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	85:024bf7f99721	2078	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	85:024bf7f99721	2079	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	85:024bf7f99721	2080	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	85:024bf7f99721	2081	*/
bogdanm	85:024bf7f99721	2082	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
bogdanm	85:024bf7f99721	2083
bogdanm	85:024bf7f99721	2084	/**
bogdanm	85:024bf7f99721	2085	* @brief Clears the CRS specified FLAG.
bogdanm	85:024bf7f99721	2086	* @param _FLAG_: specifies the flag to clear.
bogdanm	85:024bf7f99721	2087	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	2088	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	85:024bf7f99721	2089	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	85:024bf7f99721	2090	* @arg RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	2091	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	85:024bf7f99721	2092	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	85:024bf7f99721	2093	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	85:024bf7f99721	2094	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	85:024bf7f99721	2095	* @retval None
bogdanm	85:024bf7f99721	2096	*/
bogdanm	85:024bf7f99721	2097
bogdanm	85:024bf7f99721	2098	/* CRS Flag Error Mask */
bogdanm	85:024bf7f99721	2099	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	85:024bf7f99721	2100
bogdanm	85:024bf7f99721	2101	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	92:4fc01daae5a5	2102	(CRS->ICR \|= (__FLAG__)))
bogdanm	85:024bf7f99721	2103
bogdanm	92:4fc01daae5a5	2104	/**
bogdanm	92:4fc01daae5a5	2105	* @}
bogdanm	92:4fc01daae5a5	2106	*/
bogdanm	85:024bf7f99721	2107
bogdanm	92:4fc01daae5a5	2108	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
bogdanm	92:4fc01daae5a5	2109	* @{
bogdanm	92:4fc01daae5a5	2110	*/
bogdanm	85:024bf7f99721	2111	/**
bogdanm	85:024bf7f99721	2112	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	2113	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	2114	* @retval None
bogdanm	85:024bf7f99721	2115	*/
bogdanm	85:024bf7f99721	2116	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	85:024bf7f99721	2117
bogdanm	85:024bf7f99721	2118	/**
bogdanm	85:024bf7f99721	2119	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	2120	* @retval None
bogdanm	85:024bf7f99721	2121	*/
bogdanm	85:024bf7f99721	2122	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	85:024bf7f99721	2123
bogdanm	85:024bf7f99721	2124	/**
bogdanm	85:024bf7f99721	2125	* @brief Enables the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	2126	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	2127	* @retval None
bogdanm	85:024bf7f99721	2128	*/
bogdanm	85:024bf7f99721	2129	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	2130
bogdanm	85:024bf7f99721	2131	/**
bogdanm	85:024bf7f99721	2132	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	2133	* @retval None
bogdanm	85:024bf7f99721	2134	*/
bogdanm	85:024bf7f99721	2135	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	2136
bogdanm	85:024bf7f99721	2137	/**
bogdanm	85:024bf7f99721	2138	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	85:024bf7f99721	2139	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	85:024bf7f99721	2140	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	85:024bf7f99721	2141	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	85:024bf7f99721	2142	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	85:024bf7f99721	2143	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	85:024bf7f99721	2144	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	85:024bf7f99721	2145	* @retval None
bogdanm	85:024bf7f99721	2146	*/
bogdanm	85:024bf7f99721	2147	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
bogdanm	85:024bf7f99721	2148
bogdanm	92:4fc01daae5a5	2149	/**
bogdanm	92:4fc01daae5a5	2150	* @}
bogdanm	92:4fc01daae5a5	2151	*/
bogdanm	92:4fc01daae5a5	2152
bogdanm	92:4fc01daae5a5	2153	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	2154	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	2155	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	2156
bogdanm	85:024bf7f99721	2157	/**
bogdanm	85:024bf7f99721	2158	* @}
bogdanm	85:024bf7f99721	2159	*/
bogdanm	85:024bf7f99721	2160
bogdanm	85:024bf7f99721	2161	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	2162	/** @addtogroup RCCEx_Exported_Functions
bogdanm	92:4fc01daae5a5	2163	* @{
bogdanm	92:4fc01daae5a5	2164	*/
bogdanm	92:4fc01daae5a5	2165
bogdanm	92:4fc01daae5a5	2166	/** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	2167	* @{
bogdanm	92:4fc01daae5a5	2168	*/
bogdanm	92:4fc01daae5a5	2169
bogdanm	85:024bf7f99721	2170	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	85:024bf7f99721	2171	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	108:34e6b704fe68	2172	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
bogdanm	85:024bf7f99721	2173
Kojto	108:34e6b704fe68	2174	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
Kojto	108:34e6b704fe68	2175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
Kojto	108:34e6b704fe68	2176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	2177	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	85:024bf7f99721	2178	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	85:024bf7f99721	2179	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto	93:e188a91d3eaa	2180	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	92:4fc01daae5a5	2181	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	2182	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	2183	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	2184
bogdanm	85:024bf7f99721	2185
bogdanm	85:024bf7f99721	2186	/**
bogdanm	85:024bf7f99721	2187	* @}
bogdanm	85:024bf7f99721	2188	*/
bogdanm	85:024bf7f99721	2189
bogdanm	85:024bf7f99721	2190	/**
bogdanm	85:024bf7f99721	2191	* @}
bogdanm	85:024bf7f99721	2192	*/
bogdanm	92:4fc01daae5a5	2193
bogdanm	92:4fc01daae5a5	2194	/**
bogdanm	92:4fc01daae5a5	2195	* @}
bogdanm	92:4fc01daae5a5	2196	*/
bogdanm	92:4fc01daae5a5	2197
bogdanm	92:4fc01daae5a5	2198	/**
bogdanm	92:4fc01daae5a5	2199	* @}
bogdanm	92:4fc01daae5a5	2200	*/
bogdanm	85:024bf7f99721	2201
bogdanm	85:024bf7f99721	2202	#ifdef __cplusplus
bogdanm	85:024bf7f99721	2203	}
bogdanm	85:024bf7f99721	2204	#endif
bogdanm	85:024bf7f99721	2205
bogdanm	85:024bf7f99721	2206	#endif /* __STM32F0xx_HAL_RCC_EX_H */
bogdanm	85:024bf7f99721	2207
bogdanm	85:024bf7f99721	2208	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

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