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Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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TARGET_NRF51822/nrf51.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 97:433970e64889

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	97:433970e64889	1
Kojto	97:433970e64889	2	/**************************************************************************************************//
Kojto	97:433970e64889	3	* @file nRF51.h
Kojto	97:433970e64889	4	*
Kojto	97:433970e64889	5	* @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
Kojto	97:433970e64889	6	* nRF51 from Nordic Semiconductor.
Kojto	97:433970e64889	7	*
Kojto	97:433970e64889	8	* @version V522
Kojto	97:433970e64889	9	* @date 31. October 2014
emilmont	80:8e73be2a2ac1	10	*
Kojto	97:433970e64889	11	* @note Generated with SVDConv V2.81d
Kojto	97:433970e64889	12	* from CMSIS SVD File 'nRF51.xml' Version 522,
Kojto	97:433970e64889	13	*
Kojto	97:433970e64889	14	* @par Copyright (c) 2013, Nordic Semiconductor ASA
Kojto	97:433970e64889	15	* All rights reserved.
Kojto	97:433970e64889	16	*
Kojto	97:433970e64889	17	* Redistribution and use in source and binary forms, with or without
Kojto	97:433970e64889	18	* modification, are permitted provided that the following conditions are met:
Kojto	97:433970e64889	19	*
Kojto	97:433970e64889	20	* * Redistributions of source code must retain the above copyright notice, this
Kojto	97:433970e64889	21	* list of conditions and the following disclaimer.
emilmont	80:8e73be2a2ac1	22	*
Kojto	97:433970e64889	23	* * Redistributions in binary form must reproduce the above copyright notice,
Kojto	97:433970e64889	24	* this list of conditions and the following disclaimer in the documentation
Kojto	97:433970e64889	25	* and/or other materials provided with the distribution.
Kojto	97:433970e64889	26	*
Kojto	97:433970e64889	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto	97:433970e64889	28	* contributors may be used to endorse or promote products derived from
Kojto	97:433970e64889	29	* this software without specific prior written permission.
emilmont	80:8e73be2a2ac1	30	*
Kojto	97:433970e64889	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	97:433970e64889	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	97:433970e64889	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	97:433970e64889	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	97:433970e64889	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	97:433970e64889	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	97:433970e64889	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	97:433970e64889	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	97:433970e64889	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	97:433970e64889	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	97:433970e64889	41	*
Kojto	97:433970e64889	42	*
Kojto	97:433970e64889	43	*******************************************************************************************************/
emilmont	80:8e73be2a2ac1	44
emilmont	80:8e73be2a2ac1	45
emilmont	80:8e73be2a2ac1	46
emilmont	80:8e73be2a2ac1	47	/** @addtogroup Nordic Semiconductor
emilmont	80:8e73be2a2ac1	48	* @{
emilmont	80:8e73be2a2ac1	49	*/
emilmont	80:8e73be2a2ac1	50
emilmont	80:8e73be2a2ac1	51	/** @addtogroup nRF51
emilmont	80:8e73be2a2ac1	52	* @{
emilmont	80:8e73be2a2ac1	53	*/
emilmont	80:8e73be2a2ac1	54
emilmont	80:8e73be2a2ac1	55	#ifndef NRF51_H
emilmont	80:8e73be2a2ac1	56	#define NRF51_H
emilmont	80:8e73be2a2ac1	57
emilmont	80:8e73be2a2ac1	58	#ifdef __cplusplus
emilmont	80:8e73be2a2ac1	59	extern "C" {
emilmont	80:8e73be2a2ac1	60	#endif
emilmont	80:8e73be2a2ac1	61
emilmont	80:8e73be2a2ac1	62
emilmont	80:8e73be2a2ac1	63	/* ------------------------- Interrupt Number Definition ------------------------ */
emilmont	80:8e73be2a2ac1	64
emilmont	80:8e73be2a2ac1	65	typedef enum {
emilmont	80:8e73be2a2ac1	66	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
emilmont	80:8e73be2a2ac1	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
emilmont	80:8e73be2a2ac1	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
emilmont	80:8e73be2a2ac1	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
emilmont	80:8e73be2a2ac1	70	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
emilmont	80:8e73be2a2ac1	71	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
emilmont	80:8e73be2a2ac1	72	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
emilmont	80:8e73be2a2ac1	73	SysTick_IRQn = -1, /!< 15 System Tick Timer /
emilmont	80:8e73be2a2ac1	74	/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
emilmont	80:8e73be2a2ac1	75	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
emilmont	80:8e73be2a2ac1	76	RADIO_IRQn = 1, /!< 1 RADIO /
emilmont	80:8e73be2a2ac1	77	UART0_IRQn = 2, /!< 2 UART0 /
emilmont	80:8e73be2a2ac1	78	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
emilmont	80:8e73be2a2ac1	79	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
emilmont	80:8e73be2a2ac1	80	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
emilmont	80:8e73be2a2ac1	81	ADC_IRQn = 7, /!< 7 ADC /
emilmont	80:8e73be2a2ac1	82	TIMER0_IRQn = 8, /!< 8 TIMER0 /
emilmont	80:8e73be2a2ac1	83	TIMER1_IRQn = 9, /!< 9 TIMER1 /
emilmont	80:8e73be2a2ac1	84	TIMER2_IRQn = 10, /!< 10 TIMER2 /
emilmont	80:8e73be2a2ac1	85	RTC0_IRQn = 11, /!< 11 RTC0 /
emilmont	80:8e73be2a2ac1	86	TEMP_IRQn = 12, /!< 12 TEMP /
emilmont	80:8e73be2a2ac1	87	RNG_IRQn = 13, /!< 13 RNG /
emilmont	80:8e73be2a2ac1	88	ECB_IRQn = 14, /!< 14 ECB /
emilmont	80:8e73be2a2ac1	89	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
emilmont	80:8e73be2a2ac1	90	WDT_IRQn = 16, /!< 16 WDT /
emilmont	80:8e73be2a2ac1	91	RTC1_IRQn = 17, /!< 17 RTC1 /
emilmont	80:8e73be2a2ac1	92	QDEC_IRQn = 18, /!< 18 QDEC /
Kojto	97:433970e64889	93	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
emilmont	80:8e73be2a2ac1	94	SWI0_IRQn = 20, /!< 20 SWI0 /
emilmont	80:8e73be2a2ac1	95	SWI1_IRQn = 21, /!< 21 SWI1 /
emilmont	80:8e73be2a2ac1	96	SWI2_IRQn = 22, /!< 22 SWI2 /
emilmont	80:8e73be2a2ac1	97	SWI3_IRQn = 23, /!< 23 SWI3 /
emilmont	80:8e73be2a2ac1	98	SWI4_IRQn = 24, /!< 24 SWI4 /
emilmont	80:8e73be2a2ac1	99	SWI5_IRQn = 25 /!< 25 SWI5 /
emilmont	80:8e73be2a2ac1	100	} IRQn_Type;
emilmont	80:8e73be2a2ac1	101
emilmont	80:8e73be2a2ac1	102
emilmont	80:8e73be2a2ac1	103	/** @addtogroup Configuration_of_CMSIS
emilmont	80:8e73be2a2ac1	104	* @{
emilmont	80:8e73be2a2ac1	105	*/
emilmont	80:8e73be2a2ac1	106
emilmont	80:8e73be2a2ac1	107
emilmont	80:8e73be2a2ac1	108	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	109	/* ================ Processor and Core Peripheral Section ================ */
emilmont	80:8e73be2a2ac1	110	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	111
Kojto	97:433970e64889	112	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
emilmont	80:8e73be2a2ac1	113	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
emilmont	80:8e73be2a2ac1	114	#define __MPU_PRESENT 0 /!< MPU present or not /
emilmont	80:8e73be2a2ac1	115	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
emilmont	80:8e73be2a2ac1	116	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
emilmont	80:8e73be2a2ac1	117	/** @} / / End of group Configuration_of_CMSIS */
emilmont	80:8e73be2a2ac1	118
Kojto	97:433970e64889	119	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
Kojto	97:433970e64889	120	#include "system_nrf51.h" /!< nRF51 System /
emilmont	80:8e73be2a2ac1	121
emilmont	80:8e73be2a2ac1	122	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	123	/* ================ Device Specific Peripheral Section ================ */
emilmont	80:8e73be2a2ac1	124	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	125
emilmont	80:8e73be2a2ac1	126
emilmont	80:8e73be2a2ac1	127	/** @addtogroup Device_Peripheral_Registers
emilmont	80:8e73be2a2ac1	128	* @{
emilmont	80:8e73be2a2ac1	129	*/
emilmont	80:8e73be2a2ac1	130
emilmont	80:8e73be2a2ac1	131
emilmont	80:8e73be2a2ac1	132	/* ------------------- Start of section using anonymous unions ------------------ */
emilmont	80:8e73be2a2ac1	133	#if defined(__CC_ARM)
emilmont	80:8e73be2a2ac1	134	#pragma push
emilmont	80:8e73be2a2ac1	135	#pragma anon_unions
emilmont	80:8e73be2a2ac1	136	#elif defined(__ICCARM__)
emilmont	80:8e73be2a2ac1	137	#pragma language=extended
emilmont	80:8e73be2a2ac1	138	#elif defined(__GNUC__)
emilmont	80:8e73be2a2ac1	139	/* anonymous unions are enabled by default */
emilmont	80:8e73be2a2ac1	140	#elif defined(__TMS470__)
emilmont	80:8e73be2a2ac1	141	/* anonymous unions are enabled by default */
emilmont	80:8e73be2a2ac1	142	#elif defined(__TASKING__)
emilmont	80:8e73be2a2ac1	143	#pragma warning 586
emilmont	80:8e73be2a2ac1	144	#else
emilmont	80:8e73be2a2ac1	145	#warning Not supported compiler type
emilmont	80:8e73be2a2ac1	146	#endif
emilmont	80:8e73be2a2ac1	147
emilmont	80:8e73be2a2ac1	148
emilmont	80:8e73be2a2ac1	149	typedef struct {
emilmont	80:8e73be2a2ac1	150	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
emilmont	80:8e73be2a2ac1	151	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
emilmont	80:8e73be2a2ac1	152	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
emilmont	80:8e73be2a2ac1	153	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
emilmont	80:8e73be2a2ac1	154	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
emilmont	80:8e73be2a2ac1	155	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
emilmont	80:8e73be2a2ac1	156	} AMLI_RAMPRI_Type;
emilmont	80:8e73be2a2ac1	157
emilmont	80:8e73be2a2ac1	158	typedef struct {
Kojto	97:433970e64889	159	__IO uint32_t SCK; /!< Pin select for SCK. /
Kojto	97:433970e64889	160	__IO uint32_t MOSI; /!< Pin select for MOSI. /
Kojto	97:433970e64889	161	__IO uint32_t MISO; /!< Pin select for MISO. /
Kojto	97:433970e64889	162	} SPIM_PSEL_Type;
Kojto	97:433970e64889	163
Kojto	97:433970e64889	164	typedef struct {
Kojto	97:433970e64889	165	__IO uint32_t PTR; /!< Data pointer. /
Kojto	97:433970e64889	166	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
Kojto	97:433970e64889	167	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
Kojto	97:433970e64889	168	} SPIM_RXD_Type;
Kojto	97:433970e64889	169
Kojto	97:433970e64889	170	typedef struct {
Kojto	97:433970e64889	171	__IO uint32_t PTR; /!< Data pointer. /
Kojto	97:433970e64889	172	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
Kojto	97:433970e64889	173	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
Kojto	97:433970e64889	174	} SPIM_TXD_Type;
Kojto	97:433970e64889	175
Kojto	97:433970e64889	176	typedef struct {
emilmont	80:8e73be2a2ac1	177	__O uint32_t EN; /!< Enable channel group. /
emilmont	80:8e73be2a2ac1	178	__O uint32_t DIS; /!< Disable channel group. /
emilmont	80:8e73be2a2ac1	179	} PPI_TASKS_CHG_Type;
emilmont	80:8e73be2a2ac1	180
emilmont	80:8e73be2a2ac1	181	typedef struct {
emilmont	80:8e73be2a2ac1	182	__IO uint32_t EEP; /!< Channel event end-point. /
emilmont	80:8e73be2a2ac1	183	__IO uint32_t TEP; /!< Channel task end-point. /
emilmont	80:8e73be2a2ac1	184	} PPI_CH_Type;
emilmont	80:8e73be2a2ac1	185
Kojto	97:433970e64889	186	typedef struct {
Kojto	97:433970e64889	187	__I uint32_t PART; /!< Part code /
Kojto	97:433970e64889	188	__I uint32_t VARIANT; /!< Part variant /
Kojto	97:433970e64889	189	__I uint32_t PACKAGE; /!< Package option /
Kojto	97:433970e64889	190	__I uint32_t RAM; /!< RAM variant /
Kojto	97:433970e64889	191	__I uint32_t FLASH; /!< Flash variant /
Kojto	97:433970e64889	192	__I uint32_t RESERVED[3]; /!< Reserved /
Kojto	97:433970e64889	193	} FICR_INFO_Type;
Kojto	97:433970e64889	194
emilmont	80:8e73be2a2ac1	195
emilmont	80:8e73be2a2ac1	196	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	197	/* ================ POWER ================ */
emilmont	80:8e73be2a2ac1	198	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	199
emilmont	80:8e73be2a2ac1	200
emilmont	80:8e73be2a2ac1	201	/**
emilmont	80:8e73be2a2ac1	202	* @brief Power Control. (POWER)
emilmont	80:8e73be2a2ac1	203	*/
emilmont	80:8e73be2a2ac1	204
emilmont	80:8e73be2a2ac1	205	typedef struct { /!< POWER Structure /
emilmont	80:8e73be2a2ac1	206	__I uint32_t RESERVED0[30];
emilmont	80:8e73be2a2ac1	207	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
emilmont	80:8e73be2a2ac1	208	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
emilmont	80:8e73be2a2ac1	209	__I uint32_t RESERVED1[34];
emilmont	80:8e73be2a2ac1	210	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
emilmont	80:8e73be2a2ac1	211	__I uint32_t RESERVED2[126];
emilmont	80:8e73be2a2ac1	212	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	213	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	214	__I uint32_t RESERVED3[61];
emilmont	80:8e73be2a2ac1	215	__IO uint32_t RESETREAS; /!< Reset reason. /
Kojto	97:433970e64889	216	__I uint32_t RESERVED4[9];
Kojto	97:433970e64889	217	__I uint32_t RAMSTATUS; /!< Ram status register. /
Kojto	97:433970e64889	218	__I uint32_t RESERVED5[53];
emilmont	80:8e73be2a2ac1	219	__O uint32_t SYSTEMOFF; /!< System off register. /
Kojto	97:433970e64889	220	__I uint32_t RESERVED6[3];
emilmont	80:8e73be2a2ac1	221	__IO uint32_t POFCON; /!< Power failure configuration. /
Kojto	97:433970e64889	222	__I uint32_t RESERVED7[2];
emilmont	80:8e73be2a2ac1	223	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
emilmont	80:8e73be2a2ac1	224	register. */
Kojto	97:433970e64889	225	__I uint32_t RESERVED8;
emilmont	80:8e73be2a2ac1	226	__IO uint32_t RAMON; /!< Ram on/off. /
Kojto	97:433970e64889	227	__I uint32_t RESERVED9[7];
emilmont	80:8e73be2a2ac1	228	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
emilmont	80:8e73be2a2ac1	229	is a retained register. */
Kojto	97:433970e64889	230	__I uint32_t RESERVED10[3];
Kojto	97:433970e64889	231	__IO uint32_t RAMONB; /!< Ram on/off. /
Kojto	97:433970e64889	232	__I uint32_t RESERVED11[8];
emilmont	80:8e73be2a2ac1	233	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
Kojto	97:433970e64889	234	__I uint32_t RESERVED12[291];
Kojto	97:433970e64889	235	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
emilmont	80:8e73be2a2ac1	236	} NRF_POWER_Type;
emilmont	80:8e73be2a2ac1	237
emilmont	80:8e73be2a2ac1	238
emilmont	80:8e73be2a2ac1	239	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	240	/* ================ CLOCK ================ */
emilmont	80:8e73be2a2ac1	241	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	242
emilmont	80:8e73be2a2ac1	243
emilmont	80:8e73be2a2ac1	244	/**
emilmont	80:8e73be2a2ac1	245	* @brief Clock control. (CLOCK)
emilmont	80:8e73be2a2ac1	246	*/
emilmont	80:8e73be2a2ac1	247
emilmont	80:8e73be2a2ac1	248	typedef struct { /!< CLOCK Structure /
emilmont	80:8e73be2a2ac1	249	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
emilmont	80:8e73be2a2ac1	250	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
emilmont	80:8e73be2a2ac1	251	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
emilmont	80:8e73be2a2ac1	252	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
emilmont	80:8e73be2a2ac1	253	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
emilmont	80:8e73be2a2ac1	254	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
emilmont	80:8e73be2a2ac1	255	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
emilmont	80:8e73be2a2ac1	256	__I uint32_t RESERVED0[57];
emilmont	80:8e73be2a2ac1	257	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
emilmont	80:8e73be2a2ac1	258	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
emilmont	80:8e73be2a2ac1	259	__I uint32_t RESERVED1;
Kojto	97:433970e64889	260	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
Kojto	97:433970e64889	261	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
emilmont	80:8e73be2a2ac1	262	__I uint32_t RESERVED2[124];
emilmont	80:8e73be2a2ac1	263	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	264	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	97:433970e64889	265	__I uint32_t RESERVED3[63];
Kojto	97:433970e64889	266	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
emilmont	80:8e73be2a2ac1	267	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
Kojto	97:433970e64889	268	__I uint32_t RESERVED4;
Kojto	97:433970e64889	269	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
emilmont	80:8e73be2a2ac1	270	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
Kojto	97:433970e64889	271	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto	97:433970e64889	272	triggered. */
Kojto	97:433970e64889	273	__I uint32_t RESERVED5[62];
emilmont	80:8e73be2a2ac1	274	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
emilmont	80:8e73be2a2ac1	275	__I uint32_t RESERVED6[7];
emilmont	80:8e73be2a2ac1	276	__IO uint32_t CTIV; /!< Calibration timer interval. /
emilmont	80:8e73be2a2ac1	277	__I uint32_t RESERVED7[5];
emilmont	80:8e73be2a2ac1	278	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
emilmont	80:8e73be2a2ac1	279	} NRF_CLOCK_Type;
emilmont	80:8e73be2a2ac1	280
emilmont	80:8e73be2a2ac1	281
emilmont	80:8e73be2a2ac1	282	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	283	/* ================ MPU ================ */
emilmont	80:8e73be2a2ac1	284	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	285
emilmont	80:8e73be2a2ac1	286
emilmont	80:8e73be2a2ac1	287	/**
emilmont	80:8e73be2a2ac1	288	* @brief Memory Protection Unit. (MPU)
emilmont	80:8e73be2a2ac1	289	*/
emilmont	80:8e73be2a2ac1	290
emilmont	80:8e73be2a2ac1	291	typedef struct { /!< MPU Structure /
emilmont	80:8e73be2a2ac1	292	__I uint32_t RESERVED0[330];
emilmont	80:8e73be2a2ac1	293	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
emilmont	80:8e73be2a2ac1	294	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
emilmont	80:8e73be2a2ac1	295	__I uint32_t RESERVED1[52];
Kojto	97:433970e64889	296	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
Kojto	97:433970e64889	297	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
Kojto	97:433970e64889	298	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
Kojto	97:433970e64889	299	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
emilmont	80:8e73be2a2ac1	300	} NRF_MPU_Type;
emilmont	80:8e73be2a2ac1	301
emilmont	80:8e73be2a2ac1	302
emilmont	80:8e73be2a2ac1	303	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	304	/* ================ PU ================ */
emilmont	80:8e73be2a2ac1	305	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	306
emilmont	80:8e73be2a2ac1	307
emilmont	80:8e73be2a2ac1	308	/**
emilmont	80:8e73be2a2ac1	309	* @brief Patch unit. (PU)
emilmont	80:8e73be2a2ac1	310	*/
emilmont	80:8e73be2a2ac1	311
emilmont	80:8e73be2a2ac1	312	typedef struct { /!< PU Structure /
emilmont	80:8e73be2a2ac1	313	__I uint32_t RESERVED0[448];
emilmont	80:8e73be2a2ac1	314	__IO uint32_t REPLACEADDR[8]; /!< Address of first instruction to replace. /
emilmont	80:8e73be2a2ac1	315	__I uint32_t RESERVED1[24];
emilmont	80:8e73be2a2ac1	316	__IO uint32_t PATCHADDR[8]; /!< Relative address of patch instructions. /
emilmont	80:8e73be2a2ac1	317	__I uint32_t RESERVED2[24];
emilmont	80:8e73be2a2ac1	318	__IO uint32_t PATCHEN; /!< Patch enable register. /
emilmont	80:8e73be2a2ac1	319	__IO uint32_t PATCHENSET; /!< Patch enable register. /
emilmont	80:8e73be2a2ac1	320	__IO uint32_t PATCHENCLR; /!< Patch disable register. /
emilmont	80:8e73be2a2ac1	321	} NRF_PU_Type;
emilmont	80:8e73be2a2ac1	322
emilmont	80:8e73be2a2ac1	323
emilmont	80:8e73be2a2ac1	324	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	325	/* ================ AMLI ================ */
emilmont	80:8e73be2a2ac1	326	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	327
emilmont	80:8e73be2a2ac1	328
emilmont	80:8e73be2a2ac1	329	/**
emilmont	80:8e73be2a2ac1	330	* @brief AHB Multi-Layer Interface. (AMLI)
emilmont	80:8e73be2a2ac1	331	*/
emilmont	80:8e73be2a2ac1	332
emilmont	80:8e73be2a2ac1	333	typedef struct { /!< AMLI Structure /
emilmont	80:8e73be2a2ac1	334	__I uint32_t RESERVED0[896];
emilmont	80:8e73be2a2ac1	335	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
emilmont	80:8e73be2a2ac1	336	} NRF_AMLI_Type;
emilmont	80:8e73be2a2ac1	337
emilmont	80:8e73be2a2ac1	338
emilmont	80:8e73be2a2ac1	339	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	340	/* ================ RADIO ================ */
emilmont	80:8e73be2a2ac1	341	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	342
emilmont	80:8e73be2a2ac1	343
emilmont	80:8e73be2a2ac1	344	/**
emilmont	80:8e73be2a2ac1	345	* @brief The radio. (RADIO)
emilmont	80:8e73be2a2ac1	346	*/
emilmont	80:8e73be2a2ac1	347
emilmont	80:8e73be2a2ac1	348	typedef struct { /!< RADIO Structure /
emilmont	80:8e73be2a2ac1	349	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
emilmont	80:8e73be2a2ac1	350	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
emilmont	80:8e73be2a2ac1	351	__O uint32_t TASKS_START; /!< Start radio. /
emilmont	80:8e73be2a2ac1	352	__O uint32_t TASKS_STOP; /!< Stop radio. /
emilmont	80:8e73be2a2ac1	353	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
emilmont	80:8e73be2a2ac1	354	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
emilmont	80:8e73be2a2ac1	355	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
emilmont	80:8e73be2a2ac1	356	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
emilmont	80:8e73be2a2ac1	357	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
emilmont	80:8e73be2a2ac1	358	__I uint32_t RESERVED0[55];
emilmont	80:8e73be2a2ac1	359	__IO uint32_t EVENTS_READY; /!< Ready event. /
emilmont	80:8e73be2a2ac1	360	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
emilmont	80:8e73be2a2ac1	361	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
emilmont	80:8e73be2a2ac1	362	__IO uint32_t EVENTS_END; /!< End event. /
emilmont	80:8e73be2a2ac1	363	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
emilmont	80:8e73be2a2ac1	364	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
emilmont	80:8e73be2a2ac1	365	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
emilmont	80:8e73be2a2ac1	366	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
emilmont	80:8e73be2a2ac1	367	sample is ready for readout at the RSSISAMPLE register. */
emilmont	80:8e73be2a2ac1	368	__I uint32_t RESERVED1[2];
emilmont	80:8e73be2a2ac1	369	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BC register. /
emilmont	80:8e73be2a2ac1	370	__I uint32_t RESERVED2[53];
Kojto	97:433970e64889	371	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
emilmont	80:8e73be2a2ac1	372	__I uint32_t RESERVED3[64];
emilmont	80:8e73be2a2ac1	373	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	374	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	375	__I uint32_t RESERVED4[61];
emilmont	80:8e73be2a2ac1	376	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
Kojto	97:433970e64889	377	__I uint32_t CD; /!< Carrier detect. /
emilmont	80:8e73be2a2ac1	378	__I uint32_t RXMATCH; /!< Received address. /
emilmont	80:8e73be2a2ac1	379	__I uint32_t RXCRC; /!< Received CRC. /
Kojto	97:433970e64889	380	__I uint32_t DAI; /!< Device address match index. /
Kojto	97:433970e64889	381	__I uint32_t RESERVED5[60];
emilmont	80:8e73be2a2ac1	382	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
emilmont	80:8e73be2a2ac1	383	__IO uint32_t FREQUENCY; /!< Frequency. /
emilmont	80:8e73be2a2ac1	384	__IO uint32_t TXPOWER; /!< Output power. /
emilmont	80:8e73be2a2ac1	385	__IO uint32_t MODE; /!< Data rate and modulation. /
emilmont	80:8e73be2a2ac1	386	__IO uint32_t PCNF0; /!< Packet configuration 0. /
emilmont	80:8e73be2a2ac1	387	__IO uint32_t PCNF1; /!< Packet configuration 1. /
emilmont	80:8e73be2a2ac1	388	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
emilmont	80:8e73be2a2ac1	389	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
emilmont	80:8e73be2a2ac1	390	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
emilmont	80:8e73be2a2ac1	391	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
emilmont	80:8e73be2a2ac1	392	__IO uint32_t TXADDRESS; /!< Transmit address select. /
emilmont	80:8e73be2a2ac1	393	__IO uint32_t RXADDRESSES; /!< Receive address select. /
emilmont	80:8e73be2a2ac1	394	__IO uint32_t CRCCNF; /!< CRC configuration. /
emilmont	80:8e73be2a2ac1	395	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
emilmont	80:8e73be2a2ac1	396	__IO uint32_t CRCINIT; /!< CRC initial value. /
emilmont	80:8e73be2a2ac1	397	__IO uint32_t TEST; /!< Test features enable register. /
emilmont	80:8e73be2a2ac1	398	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
Kojto	97:433970e64889	399	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
Kojto	97:433970e64889	400	__I uint32_t RESERVED6;
emilmont	80:8e73be2a2ac1	401	__I uint32_t STATE; /!< Current radio state. /
emilmont	80:8e73be2a2ac1	402	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
Kojto	97:433970e64889	403	__I uint32_t RESERVED7[2];
emilmont	80:8e73be2a2ac1	404	__IO uint32_t BCC; /!< Bit counter compare. /
Kojto	97:433970e64889	405	__I uint32_t RESERVED8[39];
emilmont	80:8e73be2a2ac1	406	__IO uint32_t DAB[8]; /!< Device address base segment. /
emilmont	80:8e73be2a2ac1	407	__IO uint32_t DAP[8]; /!< Device address prefix. /
emilmont	80:8e73be2a2ac1	408	__IO uint32_t DACNF; /!< Device address match configuration. /
Kojto	97:433970e64889	409	__I uint32_t RESERVED9[56];
emilmont	80:8e73be2a2ac1	410	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
emilmont	80:8e73be2a2ac1	411	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
emilmont	80:8e73be2a2ac1	412	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
emilmont	80:8e73be2a2ac1	413	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
emilmont	80:8e73be2a2ac1	414	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
Kojto	97:433970e64889	415	__I uint32_t RESERVED10[561];
emilmont	80:8e73be2a2ac1	416	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	417	} NRF_RADIO_Type;
emilmont	80:8e73be2a2ac1	418
emilmont	80:8e73be2a2ac1	419
emilmont	80:8e73be2a2ac1	420	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	421	/* ================ UART ================ */
emilmont	80:8e73be2a2ac1	422	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	423
emilmont	80:8e73be2a2ac1	424
emilmont	80:8e73be2a2ac1	425	/**
emilmont	80:8e73be2a2ac1	426	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
emilmont	80:8e73be2a2ac1	427	*/
emilmont	80:8e73be2a2ac1	428
emilmont	80:8e73be2a2ac1	429	typedef struct { /!< UART Structure /
emilmont	80:8e73be2a2ac1	430	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
emilmont	80:8e73be2a2ac1	431	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
emilmont	80:8e73be2a2ac1	432	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
emilmont	80:8e73be2a2ac1	433	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
emilmont	80:8e73be2a2ac1	434	__I uint32_t RESERVED0[3];
emilmont	80:8e73be2a2ac1	435	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
emilmont	80:8e73be2a2ac1	436	__I uint32_t RESERVED1[56];
emilmont	80:8e73be2a2ac1	437	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
emilmont	80:8e73be2a2ac1	438	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
emilmont	80:8e73be2a2ac1	439	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
emilmont	80:8e73be2a2ac1	440	__I uint32_t RESERVED2[4];
emilmont	80:8e73be2a2ac1	441	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
emilmont	80:8e73be2a2ac1	442	__I uint32_t RESERVED3;
emilmont	80:8e73be2a2ac1	443	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
emilmont	80:8e73be2a2ac1	444	__I uint32_t RESERVED4[7];
emilmont	80:8e73be2a2ac1	445	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
emilmont	80:8e73be2a2ac1	446	__I uint32_t RESERVED5[46];
Kojto	97:433970e64889	447	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
Kojto	97:433970e64889	448	__I uint32_t RESERVED6[64];
emilmont	80:8e73be2a2ac1	449	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	450	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	451	__I uint32_t RESERVED7[93];
emilmont	80:8e73be2a2ac1	452	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
emilmont	80:8e73be2a2ac1	453	__I uint32_t RESERVED8[31];
emilmont	80:8e73be2a2ac1	454	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
emilmont	80:8e73be2a2ac1	455	__I uint32_t RESERVED9;
emilmont	80:8e73be2a2ac1	456	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
emilmont	80:8e73be2a2ac1	457	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
emilmont	80:8e73be2a2ac1	458	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
emilmont	80:8e73be2a2ac1	459	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
emilmont	80:8e73be2a2ac1	460	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto	97:433970e64889	461	Once read the character is consumed. If read when no character
emilmont	80:8e73be2a2ac1	462	available, the UART will stop working. */
emilmont	80:8e73be2a2ac1	463	__O uint32_t TXD; /!< TXD register. /
emilmont	80:8e73be2a2ac1	464	__I uint32_t RESERVED10;
emilmont	80:8e73be2a2ac1	465	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
emilmont	80:8e73be2a2ac1	466	__I uint32_t RESERVED11[17];
emilmont	80:8e73be2a2ac1	467	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
emilmont	80:8e73be2a2ac1	468	__I uint32_t RESERVED12[675];
emilmont	80:8e73be2a2ac1	469	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	470	} NRF_UART_Type;
emilmont	80:8e73be2a2ac1	471
emilmont	80:8e73be2a2ac1	472
emilmont	80:8e73be2a2ac1	473	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	474	/* ================ SPI ================ */
emilmont	80:8e73be2a2ac1	475	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	476
emilmont	80:8e73be2a2ac1	477
emilmont	80:8e73be2a2ac1	478	/**
emilmont	80:8e73be2a2ac1	479	* @brief SPI master 0. (SPI)
emilmont	80:8e73be2a2ac1	480	*/
emilmont	80:8e73be2a2ac1	481
emilmont	80:8e73be2a2ac1	482	typedef struct { /!< SPI Structure /
emilmont	80:8e73be2a2ac1	483	__I uint32_t RESERVED0[66];
emilmont	80:8e73be2a2ac1	484	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
emilmont	80:8e73be2a2ac1	485	__I uint32_t RESERVED1[126];
emilmont	80:8e73be2a2ac1	486	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	487	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	488	__I uint32_t RESERVED2[125];
emilmont	80:8e73be2a2ac1	489	__IO uint32_t ENABLE; /!< Enable SPI. /
emilmont	80:8e73be2a2ac1	490	__I uint32_t RESERVED3;
emilmont	80:8e73be2a2ac1	491	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
emilmont	80:8e73be2a2ac1	492	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
emilmont	80:8e73be2a2ac1	493	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
emilmont	80:8e73be2a2ac1	494	__I uint32_t RESERVED4;
Kojto	97:433970e64889	495	__I uint32_t RXD; /!< RX data. /
emilmont	80:8e73be2a2ac1	496	__IO uint32_t TXD; /!< TX data. /
emilmont	80:8e73be2a2ac1	497	__I uint32_t RESERVED5;
emilmont	80:8e73be2a2ac1	498	__IO uint32_t FREQUENCY; /!< SPI frequency /
emilmont	80:8e73be2a2ac1	499	__I uint32_t RESERVED6[11];
emilmont	80:8e73be2a2ac1	500	__IO uint32_t CONFIG; /!< Configuration register. /
emilmont	80:8e73be2a2ac1	501	__I uint32_t RESERVED7[681];
emilmont	80:8e73be2a2ac1	502	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	503	} NRF_SPI_Type;
emilmont	80:8e73be2a2ac1	504
emilmont	80:8e73be2a2ac1	505
emilmont	80:8e73be2a2ac1	506	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	507	/* ================ TWI ================ */
emilmont	80:8e73be2a2ac1	508	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	509
emilmont	80:8e73be2a2ac1	510
emilmont	80:8e73be2a2ac1	511	/**
emilmont	80:8e73be2a2ac1	512	* @brief Two-wire interface master 0. (TWI)
emilmont	80:8e73be2a2ac1	513	*/
emilmont	80:8e73be2a2ac1	514
emilmont	80:8e73be2a2ac1	515	typedef struct { /!< TWI Structure /
emilmont	80:8e73be2a2ac1	516	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
emilmont	80:8e73be2a2ac1	517	__I uint32_t RESERVED0;
emilmont	80:8e73be2a2ac1	518	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
emilmont	80:8e73be2a2ac1	519	__I uint32_t RESERVED1[2];
emilmont	80:8e73be2a2ac1	520	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
emilmont	80:8e73be2a2ac1	521	__I uint32_t RESERVED2;
emilmont	80:8e73be2a2ac1	522	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
emilmont	80:8e73be2a2ac1	523	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
emilmont	80:8e73be2a2ac1	524	__I uint32_t RESERVED3[56];
emilmont	80:8e73be2a2ac1	525	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
emilmont	80:8e73be2a2ac1	526	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
emilmont	80:8e73be2a2ac1	527	__I uint32_t RESERVED4[4];
emilmont	80:8e73be2a2ac1	528	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
emilmont	80:8e73be2a2ac1	529	__I uint32_t RESERVED5;
emilmont	80:8e73be2a2ac1	530	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
emilmont	80:8e73be2a2ac1	531	__I uint32_t RESERVED6[4];
emilmont	80:8e73be2a2ac1	532	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
Kojto	97:433970e64889	533	__I uint32_t RESERVED7[3];
Kojto	97:433970e64889	534	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
Kojto	97:433970e64889	535	__I uint32_t RESERVED8[45];
emilmont	80:8e73be2a2ac1	536	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
Kojto	97:433970e64889	537	__I uint32_t RESERVED9[64];
emilmont	80:8e73be2a2ac1	538	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	539	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	97:433970e64889	540	__I uint32_t RESERVED10[110];
emilmont	80:8e73be2a2ac1	541	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
Kojto	97:433970e64889	542	__I uint32_t RESERVED11[14];
emilmont	80:8e73be2a2ac1	543	__IO uint32_t ENABLE; /!< Enable two-wire master. /
Kojto	97:433970e64889	544	__I uint32_t RESERVED12;
emilmont	80:8e73be2a2ac1	545	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
emilmont	80:8e73be2a2ac1	546	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
Kojto	97:433970e64889	547	__I uint32_t RESERVED13[2];
Kojto	97:433970e64889	548	__I uint32_t RXD; /!< RX data register. /
emilmont	80:8e73be2a2ac1	549	__IO uint32_t TXD; /!< TX data register. /
Kojto	97:433970e64889	550	__I uint32_t RESERVED14;
emilmont	80:8e73be2a2ac1	551	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
Kojto	97:433970e64889	552	__I uint32_t RESERVED15[24];
emilmont	80:8e73be2a2ac1	553	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
Kojto	97:433970e64889	554	__I uint32_t RESERVED16[668];
emilmont	80:8e73be2a2ac1	555	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	556	} NRF_TWI_Type;
emilmont	80:8e73be2a2ac1	557
emilmont	80:8e73be2a2ac1	558
emilmont	80:8e73be2a2ac1	559	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	560	/* ================ SPIS ================ */
emilmont	80:8e73be2a2ac1	561	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	562
emilmont	80:8e73be2a2ac1	563
emilmont	80:8e73be2a2ac1	564	/**
emilmont	80:8e73be2a2ac1	565	* @brief SPI slave 1. (SPIS)
emilmont	80:8e73be2a2ac1	566	*/
emilmont	80:8e73be2a2ac1	567
emilmont	80:8e73be2a2ac1	568	typedef struct { /!< SPIS Structure /
emilmont	80:8e73be2a2ac1	569	__I uint32_t RESERVED0[9];
emilmont	80:8e73be2a2ac1	570	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
emilmont	80:8e73be2a2ac1	571	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
emilmont	80:8e73be2a2ac1	572	__I uint32_t RESERVED1[54];
emilmont	80:8e73be2a2ac1	573	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
emilmont	80:8e73be2a2ac1	574	__I uint32_t RESERVED2[8];
emilmont	80:8e73be2a2ac1	575	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
emilmont	80:8e73be2a2ac1	576	__I uint32_t RESERVED3[53];
emilmont	80:8e73be2a2ac1	577	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
emilmont	80:8e73be2a2ac1	578	__I uint32_t RESERVED4[64];
emilmont	80:8e73be2a2ac1	579	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	580	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	581	__I uint32_t RESERVED5[61];
emilmont	80:8e73be2a2ac1	582	__I uint32_t SEMSTAT; /!< Semaphore status. /
emilmont	80:8e73be2a2ac1	583	__I uint32_t RESERVED6[15];
emilmont	80:8e73be2a2ac1	584	__IO uint32_t STATUS; /!< Status from last transaction. /
emilmont	80:8e73be2a2ac1	585	__I uint32_t RESERVED7[47];
emilmont	80:8e73be2a2ac1	586	__IO uint32_t ENABLE; /!< Enable SPIS. /
emilmont	80:8e73be2a2ac1	587	__I uint32_t RESERVED8;
emilmont	80:8e73be2a2ac1	588	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
emilmont	80:8e73be2a2ac1	589	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
emilmont	80:8e73be2a2ac1	590	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
emilmont	80:8e73be2a2ac1	591	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
emilmont	80:8e73be2a2ac1	592	__I uint32_t RESERVED9[7];
emilmont	80:8e73be2a2ac1	593	__IO uint32_t RXDPTR; /!< RX data pointer. /
emilmont	80:8e73be2a2ac1	594	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
Kojto	97:433970e64889	595	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
emilmont	80:8e73be2a2ac1	596	__I uint32_t RESERVED10;
emilmont	80:8e73be2a2ac1	597	__IO uint32_t TXDPTR; /!< TX data pointer. /
emilmont	80:8e73be2a2ac1	598	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
Kojto	97:433970e64889	599	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
emilmont	80:8e73be2a2ac1	600	__I uint32_t RESERVED11;
emilmont	80:8e73be2a2ac1	601	__IO uint32_t CONFIG; /!< Configuration register. /
emilmont	80:8e73be2a2ac1	602	__I uint32_t RESERVED12;
emilmont	80:8e73be2a2ac1	603	__IO uint32_t DEF; /!< Default character. /
emilmont	80:8e73be2a2ac1	604	__I uint32_t RESERVED13[24];
emilmont	80:8e73be2a2ac1	605	__IO uint32_t ORC; /!< Over-read character. /
emilmont	80:8e73be2a2ac1	606	__I uint32_t RESERVED14[654];
emilmont	80:8e73be2a2ac1	607	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	608	} NRF_SPIS_Type;
emilmont	80:8e73be2a2ac1	609
emilmont	80:8e73be2a2ac1	610
emilmont	80:8e73be2a2ac1	611	/* ================================================================================ */
Kojto	97:433970e64889	612	/* ================ SPIM ================ */
Kojto	97:433970e64889	613	/* ================================================================================ */
Kojto	97:433970e64889	614
Kojto	97:433970e64889	615
Kojto	97:433970e64889	616	/**
Kojto	97:433970e64889	617	* @brief SPI master with easyDMA 1. (SPIM)
Kojto	97:433970e64889	618	*/
Kojto	97:433970e64889	619
Kojto	97:433970e64889	620	typedef struct { /!< SPIM Structure /
Kojto	97:433970e64889	621	__I uint32_t RESERVED0[4];
Kojto	97:433970e64889	622	__O uint32_t TASKS_START; /!< Start SPI transaction. /
Kojto	97:433970e64889	623	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
Kojto	97:433970e64889	624	__I uint32_t RESERVED1;
Kojto	97:433970e64889	625	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
Kojto	97:433970e64889	626	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
Kojto	97:433970e64889	627	__I uint32_t RESERVED2[56];
Kojto	97:433970e64889	628	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
Kojto	97:433970e64889	629	__I uint32_t RESERVED3[2];
Kojto	97:433970e64889	630	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
Kojto	97:433970e64889	631	__I uint32_t RESERVED4;
Kojto	97:433970e64889	632	__IO uint32_t EVENTS_END; /!< End of RXD buffer and TXD buffer reached. /
Kojto	97:433970e64889	633	__I uint32_t RESERVED5;
Kojto	97:433970e64889	634	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
Kojto	97:433970e64889	635	__I uint32_t RESERVED6[10];
Kojto	97:433970e64889	636	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
Kojto	97:433970e64889	637	__I uint32_t RESERVED7[44];
Kojto	97:433970e64889	638	__IO uint32_t SHORTS; /!< Shortcuts for SPIM. /
Kojto	97:433970e64889	639	__I uint32_t RESERVED8[64];
Kojto	97:433970e64889	640	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Kojto	97:433970e64889	641	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Kojto	97:433970e64889	642	__I uint32_t RESERVED9[125];
Kojto	97:433970e64889	643	__IO uint32_t ENABLE; /!< Enable SPIM. /
Kojto	97:433970e64889	644	__I uint32_t RESERVED10;
Kojto	97:433970e64889	645	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
Kojto	97:433970e64889	646	__I uint32_t RESERVED11;
Kojto	97:433970e64889	647	__I uint32_t RXDDATA; /!< RXD register. /
Kojto	97:433970e64889	648	__IO uint32_t TXDDATA; /!< TXD register. /
Kojto	97:433970e64889	649	__I uint32_t RESERVED12;
Kojto	97:433970e64889	650	__IO uint32_t FREQUENCY; /!< SPI frequency. /
Kojto	97:433970e64889	651	__I uint32_t RESERVED13[3];
Kojto	97:433970e64889	652	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
Kojto	97:433970e64889	653	__I uint32_t RESERVED14;
Kojto	97:433970e64889	654	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
Kojto	97:433970e64889	655	__I uint32_t RESERVED15;
Kojto	97:433970e64889	656	__IO uint32_t CONFIG; /!< Configuration register. /
Kojto	97:433970e64889	657	__I uint32_t RESERVED16[26];
Kojto	97:433970e64889	658	__IO uint32_t ORC; /!< Over-read character. /
Kojto	97:433970e64889	659	__I uint32_t RESERVED17[654];
Kojto	97:433970e64889	660	__IO uint32_t POWER; /!< Peripheral power control. /
Kojto	97:433970e64889	661	} NRF_SPIM_Type;
Kojto	97:433970e64889	662
Kojto	97:433970e64889	663
Kojto	97:433970e64889	664	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	665	/* ================ GPIOTE ================ */
emilmont	80:8e73be2a2ac1	666	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	667
emilmont	80:8e73be2a2ac1	668
emilmont	80:8e73be2a2ac1	669	/**
emilmont	80:8e73be2a2ac1	670	* @brief GPIO tasks and events. (GPIOTE)
emilmont	80:8e73be2a2ac1	671	*/
emilmont	80:8e73be2a2ac1	672
emilmont	80:8e73be2a2ac1	673	typedef struct { /!< GPIOTE Structure /
emilmont	80:8e73be2a2ac1	674	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
emilmont	80:8e73be2a2ac1	675	__I uint32_t RESERVED0[60];
emilmont	80:8e73be2a2ac1	676	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
emilmont	80:8e73be2a2ac1	677	__I uint32_t RESERVED1[27];
emilmont	80:8e73be2a2ac1	678	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
emilmont	80:8e73be2a2ac1	679	__I uint32_t RESERVED2[97];
emilmont	80:8e73be2a2ac1	680	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	681	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	682	__I uint32_t RESERVED3[129];
emilmont	80:8e73be2a2ac1	683	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
emilmont	80:8e73be2a2ac1	684	__I uint32_t RESERVED4[695];
emilmont	80:8e73be2a2ac1	685	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	686	} NRF_GPIOTE_Type;
emilmont	80:8e73be2a2ac1	687
emilmont	80:8e73be2a2ac1	688
emilmont	80:8e73be2a2ac1	689	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	690	/* ================ ADC ================ */
emilmont	80:8e73be2a2ac1	691	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	692
emilmont	80:8e73be2a2ac1	693
emilmont	80:8e73be2a2ac1	694	/**
emilmont	80:8e73be2a2ac1	695	* @brief Analog to digital converter. (ADC)
emilmont	80:8e73be2a2ac1	696	*/
emilmont	80:8e73be2a2ac1	697
emilmont	80:8e73be2a2ac1	698	typedef struct { /!< ADC Structure /
emilmont	80:8e73be2a2ac1	699	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
emilmont	80:8e73be2a2ac1	700	__O uint32_t TASKS_STOP; /!< Stop ADC. /
emilmont	80:8e73be2a2ac1	701	__I uint32_t RESERVED0[62];
emilmont	80:8e73be2a2ac1	702	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
emilmont	80:8e73be2a2ac1	703	__I uint32_t RESERVED1[128];
emilmont	80:8e73be2a2ac1	704	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	705	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	706	__I uint32_t RESERVED2[61];
emilmont	80:8e73be2a2ac1	707	__I uint32_t BUSY; /!< ADC busy register. /
emilmont	80:8e73be2a2ac1	708	__I uint32_t RESERVED3[63];
emilmont	80:8e73be2a2ac1	709	__IO uint32_t ENABLE; /!< ADC enable. /
emilmont	80:8e73be2a2ac1	710	__IO uint32_t CONFIG; /!< ADC configuration register. /
emilmont	80:8e73be2a2ac1	711	__I uint32_t RESULT; /!< Result of ADC conversion. /
emilmont	80:8e73be2a2ac1	712	__I uint32_t RESERVED4[700];
emilmont	80:8e73be2a2ac1	713	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	714	} NRF_ADC_Type;
emilmont	80:8e73be2a2ac1	715
emilmont	80:8e73be2a2ac1	716
emilmont	80:8e73be2a2ac1	717	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	718	/* ================ TIMER ================ */
emilmont	80:8e73be2a2ac1	719	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	720
emilmont	80:8e73be2a2ac1	721
emilmont	80:8e73be2a2ac1	722	/**
emilmont	80:8e73be2a2ac1	723	* @brief Timer 0. (TIMER)
emilmont	80:8e73be2a2ac1	724	*/
emilmont	80:8e73be2a2ac1	725
emilmont	80:8e73be2a2ac1	726	typedef struct { /!< TIMER Structure /
emilmont	80:8e73be2a2ac1	727	__O uint32_t TASKS_START; /!< Start Timer. /
emilmont	80:8e73be2a2ac1	728	__O uint32_t TASKS_STOP; /!< Stop Timer. /
emilmont	80:8e73be2a2ac1	729	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
emilmont	80:8e73be2a2ac1	730	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
Kojto	97:433970e64889	731	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
Kojto	97:433970e64889	732	__I uint32_t RESERVED0[11];
emilmont	80:8e73be2a2ac1	733	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
emilmont	80:8e73be2a2ac1	734	__I uint32_t RESERVED1[60];
emilmont	80:8e73be2a2ac1	735	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
emilmont	80:8e73be2a2ac1	736	__I uint32_t RESERVED2[44];
emilmont	80:8e73be2a2ac1	737	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
emilmont	80:8e73be2a2ac1	738	__I uint32_t RESERVED3[64];
emilmont	80:8e73be2a2ac1	739	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	740	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	741	__I uint32_t RESERVED4[126];
emilmont	80:8e73be2a2ac1	742	__IO uint32_t MODE; /!< Timer Mode selection. /
emilmont	80:8e73be2a2ac1	743	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
emilmont	80:8e73be2a2ac1	744	__I uint32_t RESERVED5;
emilmont	80:8e73be2a2ac1	745	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
emilmont	80:8e73be2a2ac1	746	clock frequency is divided by 2^SCALE. */
emilmont	80:8e73be2a2ac1	747	__I uint32_t RESERVED6[11];
emilmont	80:8e73be2a2ac1	748	__IO uint32_t CC[4]; /!< Capture/compare registers. /
emilmont	80:8e73be2a2ac1	749	__I uint32_t RESERVED7[683];
emilmont	80:8e73be2a2ac1	750	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	751	} NRF_TIMER_Type;
emilmont	80:8e73be2a2ac1	752
emilmont	80:8e73be2a2ac1	753
emilmont	80:8e73be2a2ac1	754	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	755	/* ================ RTC ================ */
emilmont	80:8e73be2a2ac1	756	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	757
emilmont	80:8e73be2a2ac1	758
emilmont	80:8e73be2a2ac1	759	/**
emilmont	80:8e73be2a2ac1	760	* @brief Real time counter 0. (RTC)
emilmont	80:8e73be2a2ac1	761	*/
emilmont	80:8e73be2a2ac1	762
emilmont	80:8e73be2a2ac1	763	typedef struct { /!< RTC Structure /
emilmont	80:8e73be2a2ac1	764	__O uint32_t TASKS_START; /!< Start RTC Counter. /
emilmont	80:8e73be2a2ac1	765	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
emilmont	80:8e73be2a2ac1	766	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
emilmont	80:8e73be2a2ac1	767	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
emilmont	80:8e73be2a2ac1	768	__I uint32_t RESERVED0[60];
emilmont	80:8e73be2a2ac1	769	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
emilmont	80:8e73be2a2ac1	770	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
emilmont	80:8e73be2a2ac1	771	__I uint32_t RESERVED1[14];
emilmont	80:8e73be2a2ac1	772	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
emilmont	80:8e73be2a2ac1	773	__I uint32_t RESERVED2[109];
emilmont	80:8e73be2a2ac1	774	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	775	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	776	__I uint32_t RESERVED3[13];
emilmont	80:8e73be2a2ac1	777	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
emilmont	80:8e73be2a2ac1	778	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
emilmont	80:8e73be2a2ac1	779	the value of EVTEN. */
emilmont	80:8e73be2a2ac1	780	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
emilmont	80:8e73be2a2ac1	781	gives the value of EVTEN. */
emilmont	80:8e73be2a2ac1	782	__I uint32_t RESERVED4[110];
Kojto	97:433970e64889	783	__I uint32_t COUNTER; /!< Current COUNTER value. /
emilmont	80:8e73be2a2ac1	784	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
emilmont	80:8e73be2a2ac1	785	Must be written when RTC is STOPed. */
emilmont	80:8e73be2a2ac1	786	__I uint32_t RESERVED5[13];
emilmont	80:8e73be2a2ac1	787	__IO uint32_t CC[4]; /!< Capture/compare registers. /
emilmont	80:8e73be2a2ac1	788	__I uint32_t RESERVED6[683];
emilmont	80:8e73be2a2ac1	789	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	790	} NRF_RTC_Type;
emilmont	80:8e73be2a2ac1	791
emilmont	80:8e73be2a2ac1	792
emilmont	80:8e73be2a2ac1	793	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	794	/* ================ TEMP ================ */
emilmont	80:8e73be2a2ac1	795	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	796
emilmont	80:8e73be2a2ac1	797
emilmont	80:8e73be2a2ac1	798	/**
emilmont	80:8e73be2a2ac1	799	* @brief Temperature Sensor. (TEMP)
emilmont	80:8e73be2a2ac1	800	*/
emilmont	80:8e73be2a2ac1	801
emilmont	80:8e73be2a2ac1	802	typedef struct { /!< TEMP Structure /
emilmont	80:8e73be2a2ac1	803	__O uint32_t TASKS_START; /!< Start temperature measurement. /
emilmont	80:8e73be2a2ac1	804	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
emilmont	80:8e73be2a2ac1	805	__I uint32_t RESERVED0[62];
emilmont	80:8e73be2a2ac1	806	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
emilmont	80:8e73be2a2ac1	807	__I uint32_t RESERVED1[128];
emilmont	80:8e73be2a2ac1	808	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	809	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	810	__I uint32_t RESERVED2[127];
emilmont	80:8e73be2a2ac1	811	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
emilmont	80:8e73be2a2ac1	812	__I uint32_t RESERVED3[700];
emilmont	80:8e73be2a2ac1	813	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	814	} NRF_TEMP_Type;
emilmont	80:8e73be2a2ac1	815
emilmont	80:8e73be2a2ac1	816
emilmont	80:8e73be2a2ac1	817	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	818	/* ================ RNG ================ */
emilmont	80:8e73be2a2ac1	819	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	820
emilmont	80:8e73be2a2ac1	821
emilmont	80:8e73be2a2ac1	822	/**
emilmont	80:8e73be2a2ac1	823	* @brief Random Number Generator. (RNG)
emilmont	80:8e73be2a2ac1	824	*/
emilmont	80:8e73be2a2ac1	825
emilmont	80:8e73be2a2ac1	826	typedef struct { /!< RNG Structure /
emilmont	80:8e73be2a2ac1	827	__O uint32_t TASKS_START; /!< Start the random number generator. /
emilmont	80:8e73be2a2ac1	828	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
emilmont	80:8e73be2a2ac1	829	__I uint32_t RESERVED0[62];
emilmont	80:8e73be2a2ac1	830	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
emilmont	80:8e73be2a2ac1	831	__I uint32_t RESERVED1[63];
Kojto	97:433970e64889	832	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
emilmont	80:8e73be2a2ac1	833	__I uint32_t RESERVED2[64];
emilmont	80:8e73be2a2ac1	834	__IO uint32_t INTENSET; /!< Interrupt enable set register /
emilmont	80:8e73be2a2ac1	835	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
emilmont	80:8e73be2a2ac1	836	__I uint32_t RESERVED3[126];
emilmont	80:8e73be2a2ac1	837	__IO uint32_t CONFIG; /!< Configuration register. /
emilmont	80:8e73be2a2ac1	838	__I uint32_t VALUE; /!< RNG random number. /
emilmont	80:8e73be2a2ac1	839	__I uint32_t RESERVED4[700];
emilmont	80:8e73be2a2ac1	840	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	841	} NRF_RNG_Type;
emilmont	80:8e73be2a2ac1	842
emilmont	80:8e73be2a2ac1	843
emilmont	80:8e73be2a2ac1	844	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	845	/* ================ ECB ================ */
emilmont	80:8e73be2a2ac1	846	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	847
emilmont	80:8e73be2a2ac1	848
emilmont	80:8e73be2a2ac1	849	/**
emilmont	80:8e73be2a2ac1	850	* @brief AES ECB Mode Encryption. (ECB)
emilmont	80:8e73be2a2ac1	851	*/
emilmont	80:8e73be2a2ac1	852
emilmont	80:8e73be2a2ac1	853	typedef struct { /!< ECB Structure /
emilmont	80:8e73be2a2ac1	854	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
emilmont	80:8e73be2a2ac1	855	will not initiate a new encryption and the ERRORECB event will
emilmont	80:8e73be2a2ac1	856	be triggered. */
emilmont	80:8e73be2a2ac1	857	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
emilmont	80:8e73be2a2ac1	858	this will will trigger the ERRORECB event. */
emilmont	80:8e73be2a2ac1	859	__I uint32_t RESERVED0[62];
emilmont	80:8e73be2a2ac1	860	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
emilmont	80:8e73be2a2ac1	861	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
emilmont	80:8e73be2a2ac1	862	error. */
emilmont	80:8e73be2a2ac1	863	__I uint32_t RESERVED1[127];
emilmont	80:8e73be2a2ac1	864	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	865	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	866	__I uint32_t RESERVED2[126];
emilmont	80:8e73be2a2ac1	867	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
emilmont	80:8e73be2a2ac1	868	__I uint32_t RESERVED3[701];
emilmont	80:8e73be2a2ac1	869	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	870	} NRF_ECB_Type;
emilmont	80:8e73be2a2ac1	871
emilmont	80:8e73be2a2ac1	872
emilmont	80:8e73be2a2ac1	873	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	874	/* ================ AAR ================ */
emilmont	80:8e73be2a2ac1	875	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	876
emilmont	80:8e73be2a2ac1	877
emilmont	80:8e73be2a2ac1	878	/**
emilmont	80:8e73be2a2ac1	879	* @brief Accelerated Address Resolver. (AAR)
emilmont	80:8e73be2a2ac1	880	*/
emilmont	80:8e73be2a2ac1	881
emilmont	80:8e73be2a2ac1	882	typedef struct { /!< AAR Structure /
emilmont	80:8e73be2a2ac1	883	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
emilmont	80:8e73be2a2ac1	884	data structure. */
emilmont	80:8e73be2a2ac1	885	__I uint32_t RESERVED0;
emilmont	80:8e73be2a2ac1	886	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
emilmont	80:8e73be2a2ac1	887	__I uint32_t RESERVED1[61];
emilmont	80:8e73be2a2ac1	888	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
emilmont	80:8e73be2a2ac1	889	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
emilmont	80:8e73be2a2ac1	890	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
emilmont	80:8e73be2a2ac1	891	__I uint32_t RESERVED2[126];
emilmont	80:8e73be2a2ac1	892	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	893	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	894	__I uint32_t RESERVED3[61];
emilmont	80:8e73be2a2ac1	895	__I uint32_t STATUS; /!< Resolution status. /
emilmont	80:8e73be2a2ac1	896	__I uint32_t RESERVED4[63];
emilmont	80:8e73be2a2ac1	897	__IO uint32_t ENABLE; /!< Enable AAR. /
emilmont	80:8e73be2a2ac1	898	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
emilmont	80:8e73be2a2ac1	899	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
emilmont	80:8e73be2a2ac1	900	__I uint32_t RESERVED5;
emilmont	80:8e73be2a2ac1	901	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
Kojto	97:433970e64889	902	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto	97:433970e64889	903	during resolution. A minimum of 3 bytes must be reserved. */
emilmont	80:8e73be2a2ac1	904	__I uint32_t RESERVED6[697];
emilmont	80:8e73be2a2ac1	905	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	906	} NRF_AAR_Type;
emilmont	80:8e73be2a2ac1	907
emilmont	80:8e73be2a2ac1	908
emilmont	80:8e73be2a2ac1	909	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	910	/* ================ CCM ================ */
emilmont	80:8e73be2a2ac1	911	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	912
emilmont	80:8e73be2a2ac1	913
emilmont	80:8e73be2a2ac1	914	/**
emilmont	80:8e73be2a2ac1	915	* @brief AES CCM Mode Encryption. (CCM)
emilmont	80:8e73be2a2ac1	916	*/
emilmont	80:8e73be2a2ac1	917
emilmont	80:8e73be2a2ac1	918	typedef struct { /!< CCM Structure /
emilmont	80:8e73be2a2ac1	919	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
emilmont	80:8e73be2a2ac1	920	itself when completed. */
emilmont	80:8e73be2a2ac1	921	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
emilmont	80:8e73be2a2ac1	922	completed. */
emilmont	80:8e73be2a2ac1	923	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
emilmont	80:8e73be2a2ac1	924	__I uint32_t RESERVED0[61];
emilmont	80:8e73be2a2ac1	925	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
emilmont	80:8e73be2a2ac1	926	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
emilmont	80:8e73be2a2ac1	927	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
emilmont	80:8e73be2a2ac1	928	__I uint32_t RESERVED1[61];
Kojto	97:433970e64889	929	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
emilmont	80:8e73be2a2ac1	930	__I uint32_t RESERVED2[64];
emilmont	80:8e73be2a2ac1	931	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	932	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	933	__I uint32_t RESERVED3[61];
emilmont	80:8e73be2a2ac1	934	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
emilmont	80:8e73be2a2ac1	935	__I uint32_t RESERVED4[63];
emilmont	80:8e73be2a2ac1	936	__IO uint32_t ENABLE; /!< CCM enable. /
emilmont	80:8e73be2a2ac1	937	__IO uint32_t MODE; /!< Operation mode. /
Kojto	97:433970e64889	938	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
Kojto	97:433970e64889	939	__IO uint32_t INPTR; /!< Pointer to the input packet. /
Kojto	97:433970e64889	940	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
Kojto	97:433970e64889	941	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto	97:433970e64889	942	during resolution. A minimum of 43 bytes must be reserved. */
emilmont	80:8e73be2a2ac1	943	__I uint32_t RESERVED5[697];
emilmont	80:8e73be2a2ac1	944	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	945	} NRF_CCM_Type;
emilmont	80:8e73be2a2ac1	946
emilmont	80:8e73be2a2ac1	947
emilmont	80:8e73be2a2ac1	948	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	949	/* ================ WDT ================ */
emilmont	80:8e73be2a2ac1	950	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	951
emilmont	80:8e73be2a2ac1	952
emilmont	80:8e73be2a2ac1	953	/**
emilmont	80:8e73be2a2ac1	954	* @brief Watchdog Timer. (WDT)
emilmont	80:8e73be2a2ac1	955	*/
emilmont	80:8e73be2a2ac1	956
emilmont	80:8e73be2a2ac1	957	typedef struct { /!< WDT Structure /
emilmont	80:8e73be2a2ac1	958	__O uint32_t TASKS_START; /!< Start the watchdog. /
emilmont	80:8e73be2a2ac1	959	__I uint32_t RESERVED0[63];
emilmont	80:8e73be2a2ac1	960	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
emilmont	80:8e73be2a2ac1	961	__I uint32_t RESERVED1[128];
emilmont	80:8e73be2a2ac1	962	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	963	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	964	__I uint32_t RESERVED2[61];
emilmont	80:8e73be2a2ac1	965	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
emilmont	80:8e73be2a2ac1	966	__I uint32_t REQSTATUS; /!< Request status. /
emilmont	80:8e73be2a2ac1	967	__I uint32_t RESERVED3[63];
emilmont	80:8e73be2a2ac1	968	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
emilmont	80:8e73be2a2ac1	969	__IO uint32_t RREN; /!< Reload request enable. /
emilmont	80:8e73be2a2ac1	970	__IO uint32_t CONFIG; /!< Configuration register. /
emilmont	80:8e73be2a2ac1	971	__I uint32_t RESERVED4[60];
emilmont	80:8e73be2a2ac1	972	__O uint32_t RR[8]; /!< Reload requests registers. /
emilmont	80:8e73be2a2ac1	973	__I uint32_t RESERVED5[631];
emilmont	80:8e73be2a2ac1	974	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	975	} NRF_WDT_Type;
emilmont	80:8e73be2a2ac1	976
emilmont	80:8e73be2a2ac1	977
emilmont	80:8e73be2a2ac1	978	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	979	/* ================ QDEC ================ */
emilmont	80:8e73be2a2ac1	980	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	981
emilmont	80:8e73be2a2ac1	982
emilmont	80:8e73be2a2ac1	983	/**
emilmont	80:8e73be2a2ac1	984	* @brief Rotary decoder. (QDEC)
emilmont	80:8e73be2a2ac1	985	*/
emilmont	80:8e73be2a2ac1	986
emilmont	80:8e73be2a2ac1	987	typedef struct { /!< QDEC Structure /
emilmont	80:8e73be2a2ac1	988	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
emilmont	80:8e73be2a2ac1	989	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
emilmont	80:8e73be2a2ac1	990	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
emilmont	80:8e73be2a2ac1	991	and clears the ACC registers. */
emilmont	80:8e73be2a2ac1	992	__I uint32_t RESERVED0[61];
emilmont	80:8e73be2a2ac1	993	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
emilmont	80:8e73be2a2ac1	994	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
emilmont	80:8e73be2a2ac1	995	ACC register different than zero. */
emilmont	80:8e73be2a2ac1	996	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
emilmont	80:8e73be2a2ac1	997	__I uint32_t RESERVED1[61];
Kojto	97:433970e64889	998	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
emilmont	80:8e73be2a2ac1	999	__I uint32_t RESERVED2[64];
emilmont	80:8e73be2a2ac1	1000	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	1001	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	1002	__I uint32_t RESERVED3[125];
emilmont	80:8e73be2a2ac1	1003	__IO uint32_t ENABLE; /!< Enable the QDEC. /
emilmont	80:8e73be2a2ac1	1004	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
emilmont	80:8e73be2a2ac1	1005	__IO uint32_t SAMPLEPER; /!< Sample period. /
emilmont	80:8e73be2a2ac1	1006	__I int32_t SAMPLE; /!< Motion sample value. /
emilmont	80:8e73be2a2ac1	1007	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
emilmont	80:8e73be2a2ac1	1008	__I int32_t ACC; /!< Accumulated valid transitions register. /
emilmont	80:8e73be2a2ac1	1009	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
emilmont	80:8e73be2a2ac1	1010	task. */
emilmont	80:8e73be2a2ac1	1011	__IO uint32_t PSELLED; /!< Pin select for LED output. /
emilmont	80:8e73be2a2ac1	1012	__IO uint32_t PSELA; /!< Pin select for phase A input. /
emilmont	80:8e73be2a2ac1	1013	__IO uint32_t PSELB; /!< Pin select for phase B input. /
emilmont	80:8e73be2a2ac1	1014	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
emilmont	80:8e73be2a2ac1	1015	__I uint32_t RESERVED4[5];
emilmont	80:8e73be2a2ac1	1016	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
emilmont	80:8e73be2a2ac1	1017	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
emilmont	80:8e73be2a2ac1	1018	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
emilmont	80:8e73be2a2ac1	1019	task. */
emilmont	80:8e73be2a2ac1	1020	__I uint32_t RESERVED5[684];
emilmont	80:8e73be2a2ac1	1021	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	1022	} NRF_QDEC_Type;
emilmont	80:8e73be2a2ac1	1023
emilmont	80:8e73be2a2ac1	1024
emilmont	80:8e73be2a2ac1	1025	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1026	/* ================ LPCOMP ================ */
emilmont	80:8e73be2a2ac1	1027	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1028
emilmont	80:8e73be2a2ac1	1029
emilmont	80:8e73be2a2ac1	1030	/**
Kojto	97:433970e64889	1031	* @brief Low power comparator. (LPCOMP)
emilmont	80:8e73be2a2ac1	1032	*/
emilmont	80:8e73be2a2ac1	1033
emilmont	80:8e73be2a2ac1	1034	typedef struct { /!< LPCOMP Structure /
emilmont	80:8e73be2a2ac1	1035	__O uint32_t TASKS_START; /!< Start the comparator. /
emilmont	80:8e73be2a2ac1	1036	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
emilmont	80:8e73be2a2ac1	1037	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
emilmont	80:8e73be2a2ac1	1038	__I uint32_t RESERVED0[61];
emilmont	80:8e73be2a2ac1	1039	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
emilmont	80:8e73be2a2ac1	1040	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
emilmont	80:8e73be2a2ac1	1041	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
emilmont	80:8e73be2a2ac1	1042	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
emilmont	80:8e73be2a2ac1	1043	__I uint32_t RESERVED1[60];
Kojto	97:433970e64889	1044	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
emilmont	80:8e73be2a2ac1	1045	__I uint32_t RESERVED2[64];
emilmont	80:8e73be2a2ac1	1046	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
emilmont	80:8e73be2a2ac1	1047	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
emilmont	80:8e73be2a2ac1	1048	__I uint32_t RESERVED3[61];
emilmont	80:8e73be2a2ac1	1049	__I uint32_t RESULT; /!< Result of last compare. /
emilmont	80:8e73be2a2ac1	1050	__I uint32_t RESERVED4[63];
emilmont	80:8e73be2a2ac1	1051	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
emilmont	80:8e73be2a2ac1	1052	__IO uint32_t PSEL; /!< Input pin select. /
emilmont	80:8e73be2a2ac1	1053	__IO uint32_t REFSEL; /!< Reference select. /
emilmont	80:8e73be2a2ac1	1054	__IO uint32_t EXTREFSEL; /!< External reference select. /
emilmont	80:8e73be2a2ac1	1055	__I uint32_t RESERVED5[4];
emilmont	80:8e73be2a2ac1	1056	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
emilmont	80:8e73be2a2ac1	1057	__I uint32_t RESERVED6[694];
emilmont	80:8e73be2a2ac1	1058	__IO uint32_t POWER; /!< Peripheral power control. /
emilmont	80:8e73be2a2ac1	1059	} NRF_LPCOMP_Type;
emilmont	80:8e73be2a2ac1	1060
emilmont	80:8e73be2a2ac1	1061
emilmont	80:8e73be2a2ac1	1062	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1063	/* ================ SWI ================ */
emilmont	80:8e73be2a2ac1	1064	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1065
emilmont	80:8e73be2a2ac1	1066
emilmont	80:8e73be2a2ac1	1067	/**
emilmont	80:8e73be2a2ac1	1068	* @brief SW Interrupts. (SWI)
emilmont	80:8e73be2a2ac1	1069	*/
emilmont	80:8e73be2a2ac1	1070
emilmont	80:8e73be2a2ac1	1071	typedef struct { /!< SWI Structure /
emilmont	80:8e73be2a2ac1	1072	__I uint32_t UNUSED; /!< Unused. /
emilmont	80:8e73be2a2ac1	1073	} NRF_SWI_Type;
emilmont	80:8e73be2a2ac1	1074
emilmont	80:8e73be2a2ac1	1075
emilmont	80:8e73be2a2ac1	1076	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1077	/* ================ NVMC ================ */
emilmont	80:8e73be2a2ac1	1078	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1079
emilmont	80:8e73be2a2ac1	1080
emilmont	80:8e73be2a2ac1	1081	/**
emilmont	80:8e73be2a2ac1	1082	* @brief Non Volatile Memory Controller. (NVMC)
emilmont	80:8e73be2a2ac1	1083	*/
emilmont	80:8e73be2a2ac1	1084
emilmont	80:8e73be2a2ac1	1085	typedef struct { /!< NVMC Structure /
emilmont	80:8e73be2a2ac1	1086	__I uint32_t RESERVED0[256];
emilmont	80:8e73be2a2ac1	1087	__I uint32_t READY; /!< Ready flag. /
emilmont	80:8e73be2a2ac1	1088	__I uint32_t RESERVED1[64];
emilmont	80:8e73be2a2ac1	1089	__IO uint32_t CONFIG; /!< Configuration register. /
emilmont	80:8e73be2a2ac1	1090	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
emilmont	80:8e73be2a2ac1	1091	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
emilmont	80:8e73be2a2ac1	1092	__IO uint32_t ERASEPROTECTEDPAGE; /!< Register for erasing a protected non-volatile memory page. /
emilmont	80:8e73be2a2ac1	1093	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
emilmont	80:8e73be2a2ac1	1094	} NRF_NVMC_Type;
emilmont	80:8e73be2a2ac1	1095
emilmont	80:8e73be2a2ac1	1096
emilmont	80:8e73be2a2ac1	1097	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1098	/* ================ PPI ================ */
emilmont	80:8e73be2a2ac1	1099	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1100
emilmont	80:8e73be2a2ac1	1101
emilmont	80:8e73be2a2ac1	1102	/**
emilmont	80:8e73be2a2ac1	1103	* @brief PPI controller. (PPI)
emilmont	80:8e73be2a2ac1	1104	*/
emilmont	80:8e73be2a2ac1	1105
emilmont	80:8e73be2a2ac1	1106	typedef struct { /!< PPI Structure /
emilmont	80:8e73be2a2ac1	1107	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
emilmont	80:8e73be2a2ac1	1108	__I uint32_t RESERVED0[312];
emilmont	80:8e73be2a2ac1	1109	__IO uint32_t CHEN; /!< Channel enable. /
emilmont	80:8e73be2a2ac1	1110	__IO uint32_t CHENSET; /!< Channel enable set. /
emilmont	80:8e73be2a2ac1	1111	__IO uint32_t CHENCLR; /!< Channel enable clear. /
emilmont	80:8e73be2a2ac1	1112	__I uint32_t RESERVED1;
emilmont	80:8e73be2a2ac1	1113	PPI_CH_Type CH[16]; /!< PPI Channel. /
emilmont	80:8e73be2a2ac1	1114	__I uint32_t RESERVED2[156];
emilmont	80:8e73be2a2ac1	1115	__IO uint32_t CHG[4]; /!< Channel group configuration. /
emilmont	80:8e73be2a2ac1	1116	} NRF_PPI_Type;
emilmont	80:8e73be2a2ac1	1117
emilmont	80:8e73be2a2ac1	1118
emilmont	80:8e73be2a2ac1	1119	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1120	/* ================ FICR ================ */
emilmont	80:8e73be2a2ac1	1121	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1122
emilmont	80:8e73be2a2ac1	1123
emilmont	80:8e73be2a2ac1	1124	/**
emilmont	80:8e73be2a2ac1	1125	* @brief Factory Information Configuration. (FICR)
emilmont	80:8e73be2a2ac1	1126	*/
emilmont	80:8e73be2a2ac1	1127
emilmont	80:8e73be2a2ac1	1128	typedef struct { /!< FICR Structure /
emilmont	80:8e73be2a2ac1	1129	__I uint32_t RESERVED0[4];
emilmont	80:8e73be2a2ac1	1130	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
emilmont	80:8e73be2a2ac1	1131	__I uint32_t CODESIZE; /!< Code memory size in pages. /
emilmont	80:8e73be2a2ac1	1132	__I uint32_t RESERVED1[4];
emilmont	80:8e73be2a2ac1	1133	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
emilmont	80:8e73be2a2ac1	1134	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
emilmont	80:8e73be2a2ac1	1135	__I uint32_t RESERVED2;
emilmont	80:8e73be2a2ac1	1136	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
Kojto	97:433970e64889	1137
Kojto	97:433970e64889	1138	union {
Kojto	97:433970e64889	1139	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto	97:433970e64889	1140	kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto	97:433970e64889	1141	instead. */
Kojto	97:433970e64889	1142	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
Kojto	97:433970e64889	1143	};
emilmont	80:8e73be2a2ac1	1144	__I uint32_t RESERVED3[5];
emilmont	80:8e73be2a2ac1	1145	__I uint32_t CONFIGID; /!< Configuration identifier. /
emilmont	80:8e73be2a2ac1	1146	__I uint32_t DEVICEID[2]; /!< Device identifier. /
emilmont	80:8e73be2a2ac1	1147	__I uint32_t RESERVED4[6];
emilmont	80:8e73be2a2ac1	1148	__I uint32_t ER[4]; /!< Encryption root. /
emilmont	80:8e73be2a2ac1	1149	__I uint32_t IR[4]; /!< Identity root. /
emilmont	80:8e73be2a2ac1	1150	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
emilmont	80:8e73be2a2ac1	1151	__I uint32_t DEVICEADDR[2]; /!< Device address. /
emilmont	80:8e73be2a2ac1	1152	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
Kojto	97:433970e64889	1153	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto	97:433970e64889	1154	mode. */
Kojto	97:433970e64889	1155	__I uint32_t RESERVED5[10];
emilmont	80:8e73be2a2ac1	1156	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
emilmont	80:8e73be2a2ac1	1157	mode. */
Kojto	97:433970e64889	1158	FICR_INFO_Type INFO; /!< Device info /
emilmont	80:8e73be2a2ac1	1159	} NRF_FICR_Type;
emilmont	80:8e73be2a2ac1	1160
emilmont	80:8e73be2a2ac1	1161
emilmont	80:8e73be2a2ac1	1162	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1163	/* ================ UICR ================ */
emilmont	80:8e73be2a2ac1	1164	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1165
emilmont	80:8e73be2a2ac1	1166
emilmont	80:8e73be2a2ac1	1167	/**
emilmont	80:8e73be2a2ac1	1168	* @brief User Information Configuration. (UICR)
emilmont	80:8e73be2a2ac1	1169	*/
emilmont	80:8e73be2a2ac1	1170
emilmont	80:8e73be2a2ac1	1171	typedef struct { /!< UICR Structure /
emilmont	80:8e73be2a2ac1	1172	__IO uint32_t CLENR0; /!< Length of code region 0. /
emilmont	80:8e73be2a2ac1	1173	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
emilmont	80:8e73be2a2ac1	1174	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
emilmont	80:8e73be2a2ac1	1175	__I uint32_t RESERVED0;
emilmont	80:8e73be2a2ac1	1176	__I uint32_t FWID; /!< Firmware ID. /
emilmont	80:8e73be2a2ac1	1177	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
emilmont	80:8e73be2a2ac1	1178	} NRF_UICR_Type;
emilmont	80:8e73be2a2ac1	1179
emilmont	80:8e73be2a2ac1	1180
emilmont	80:8e73be2a2ac1	1181	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1182	/* ================ GPIO ================ */
emilmont	80:8e73be2a2ac1	1183	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1184
emilmont	80:8e73be2a2ac1	1185
emilmont	80:8e73be2a2ac1	1186	/**
emilmont	80:8e73be2a2ac1	1187	* @brief General purpose input and output. (GPIO)
emilmont	80:8e73be2a2ac1	1188	*/
emilmont	80:8e73be2a2ac1	1189
emilmont	80:8e73be2a2ac1	1190	typedef struct { /!< GPIO Structure /
emilmont	80:8e73be2a2ac1	1191	__I uint32_t RESERVED0[321];
emilmont	80:8e73be2a2ac1	1192	__IO uint32_t OUT; /!< Write GPIO port. /
emilmont	80:8e73be2a2ac1	1193	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
emilmont	80:8e73be2a2ac1	1194	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
emilmont	80:8e73be2a2ac1	1195	__I uint32_t IN; /!< Read GPIO port. /
emilmont	80:8e73be2a2ac1	1196	__IO uint32_t DIR; /!< Direction of GPIO pins. /
emilmont	80:8e73be2a2ac1	1197	__IO uint32_t DIRSET; /!< DIR set register. /
emilmont	80:8e73be2a2ac1	1198	__IO uint32_t DIRCLR; /!< DIR clear register. /
emilmont	80:8e73be2a2ac1	1199	__I uint32_t RESERVED1[120];
emilmont	80:8e73be2a2ac1	1200	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
emilmont	80:8e73be2a2ac1	1201	} NRF_GPIO_Type;
emilmont	80:8e73be2a2ac1	1202
emilmont	80:8e73be2a2ac1	1203
emilmont	80:8e73be2a2ac1	1204	/* -------------------- End of section using anonymous unions ------------------- */
emilmont	80:8e73be2a2ac1	1205	#if defined(__CC_ARM)
emilmont	80:8e73be2a2ac1	1206	#pragma pop
emilmont	80:8e73be2a2ac1	1207	#elif defined(__ICCARM__)
emilmont	80:8e73be2a2ac1	1208	/* leave anonymous unions enabled */
emilmont	80:8e73be2a2ac1	1209	#elif defined(__GNUC__)
emilmont	80:8e73be2a2ac1	1210	/* anonymous unions are enabled by default */
emilmont	80:8e73be2a2ac1	1211	#elif defined(__TMS470__)
emilmont	80:8e73be2a2ac1	1212	/* anonymous unions are enabled by default */
emilmont	80:8e73be2a2ac1	1213	#elif defined(__TASKING__)
emilmont	80:8e73be2a2ac1	1214	#pragma warning restore
emilmont	80:8e73be2a2ac1	1215	#else
emilmont	80:8e73be2a2ac1	1216	#warning Not supported compiler type
emilmont	80:8e73be2a2ac1	1217	#endif
emilmont	80:8e73be2a2ac1	1218
emilmont	80:8e73be2a2ac1	1219
emilmont	80:8e73be2a2ac1	1220
emilmont	80:8e73be2a2ac1	1221
emilmont	80:8e73be2a2ac1	1222	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1223	/* ================ Peripheral memory map ================ */
emilmont	80:8e73be2a2ac1	1224	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1225
emilmont	80:8e73be2a2ac1	1226	#define NRF_POWER_BASE 0x40000000UL
emilmont	80:8e73be2a2ac1	1227	#define NRF_CLOCK_BASE 0x40000000UL
emilmont	80:8e73be2a2ac1	1228	#define NRF_MPU_BASE 0x40000000UL
emilmont	80:8e73be2a2ac1	1229	#define NRF_PU_BASE 0x40000000UL
emilmont	80:8e73be2a2ac1	1230	#define NRF_AMLI_BASE 0x40000000UL
emilmont	80:8e73be2a2ac1	1231	#define NRF_RADIO_BASE 0x40001000UL
emilmont	80:8e73be2a2ac1	1232	#define NRF_UART0_BASE 0x40002000UL
emilmont	80:8e73be2a2ac1	1233	#define NRF_SPI0_BASE 0x40003000UL
emilmont	80:8e73be2a2ac1	1234	#define NRF_TWI0_BASE 0x40003000UL
emilmont	80:8e73be2a2ac1	1235	#define NRF_SPI1_BASE 0x40004000UL
emilmont	80:8e73be2a2ac1	1236	#define NRF_TWI1_BASE 0x40004000UL
emilmont	80:8e73be2a2ac1	1237	#define NRF_SPIS1_BASE 0x40004000UL
Kojto	97:433970e64889	1238	#define NRF_SPIM1_BASE 0x40004000UL
emilmont	80:8e73be2a2ac1	1239	#define NRF_GPIOTE_BASE 0x40006000UL
emilmont	80:8e73be2a2ac1	1240	#define NRF_ADC_BASE 0x40007000UL
emilmont	80:8e73be2a2ac1	1241	#define NRF_TIMER0_BASE 0x40008000UL
emilmont	80:8e73be2a2ac1	1242	#define NRF_TIMER1_BASE 0x40009000UL
emilmont	80:8e73be2a2ac1	1243	#define NRF_TIMER2_BASE 0x4000A000UL
emilmont	80:8e73be2a2ac1	1244	#define NRF_RTC0_BASE 0x4000B000UL
emilmont	80:8e73be2a2ac1	1245	#define NRF_TEMP_BASE 0x4000C000UL
emilmont	80:8e73be2a2ac1	1246	#define NRF_RNG_BASE 0x4000D000UL
emilmont	80:8e73be2a2ac1	1247	#define NRF_ECB_BASE 0x4000E000UL
emilmont	80:8e73be2a2ac1	1248	#define NRF_AAR_BASE 0x4000F000UL
emilmont	80:8e73be2a2ac1	1249	#define NRF_CCM_BASE 0x4000F000UL
emilmont	80:8e73be2a2ac1	1250	#define NRF_WDT_BASE 0x40010000UL
emilmont	80:8e73be2a2ac1	1251	#define NRF_RTC1_BASE 0x40011000UL
emilmont	80:8e73be2a2ac1	1252	#define NRF_QDEC_BASE 0x40012000UL
emilmont	80:8e73be2a2ac1	1253	#define NRF_LPCOMP_BASE 0x40013000UL
emilmont	80:8e73be2a2ac1	1254	#define NRF_SWI_BASE 0x40014000UL
emilmont	80:8e73be2a2ac1	1255	#define NRF_NVMC_BASE 0x4001E000UL
emilmont	80:8e73be2a2ac1	1256	#define NRF_PPI_BASE 0x4001F000UL
emilmont	80:8e73be2a2ac1	1257	#define NRF_FICR_BASE 0x10000000UL
emilmont	80:8e73be2a2ac1	1258	#define NRF_UICR_BASE 0x10001000UL
emilmont	80:8e73be2a2ac1	1259	#define NRF_GPIO_BASE 0x50000000UL
emilmont	80:8e73be2a2ac1	1260
emilmont	80:8e73be2a2ac1	1261
emilmont	80:8e73be2a2ac1	1262	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1263	/* ================ Peripheral declaration ================ */
emilmont	80:8e73be2a2ac1	1264	/* ================================================================================ */
emilmont	80:8e73be2a2ac1	1265
emilmont	80:8e73be2a2ac1	1266	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
emilmont	80:8e73be2a2ac1	1267	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
emilmont	80:8e73be2a2ac1	1268	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
emilmont	80:8e73be2a2ac1	1269	#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
emilmont	80:8e73be2a2ac1	1270	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
emilmont	80:8e73be2a2ac1	1271	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
emilmont	80:8e73be2a2ac1	1272	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
emilmont	80:8e73be2a2ac1	1273	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
emilmont	80:8e73be2a2ac1	1274	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
emilmont	80:8e73be2a2ac1	1275	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
emilmont	80:8e73be2a2ac1	1276	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
emilmont	80:8e73be2a2ac1	1277	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto	97:433970e64889	1278	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
emilmont	80:8e73be2a2ac1	1279	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
emilmont	80:8e73be2a2ac1	1280	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
emilmont	80:8e73be2a2ac1	1281	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
emilmont	80:8e73be2a2ac1	1282	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
emilmont	80:8e73be2a2ac1	1283	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
emilmont	80:8e73be2a2ac1	1284	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
emilmont	80:8e73be2a2ac1	1285	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
emilmont	80:8e73be2a2ac1	1286	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
emilmont	80:8e73be2a2ac1	1287	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
emilmont	80:8e73be2a2ac1	1288	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
emilmont	80:8e73be2a2ac1	1289	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
emilmont	80:8e73be2a2ac1	1290	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
emilmont	80:8e73be2a2ac1	1291	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
emilmont	80:8e73be2a2ac1	1292	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
emilmont	80:8e73be2a2ac1	1293	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
emilmont	80:8e73be2a2ac1	1294	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
emilmont	80:8e73be2a2ac1	1295	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
emilmont	80:8e73be2a2ac1	1296	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
emilmont	80:8e73be2a2ac1	1297	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
emilmont	80:8e73be2a2ac1	1298	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
emilmont	80:8e73be2a2ac1	1299	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
emilmont	80:8e73be2a2ac1	1300
emilmont	80:8e73be2a2ac1	1301
emilmont	80:8e73be2a2ac1	1302	/** @} / / End of group Device_Peripheral_Registers */
emilmont	80:8e73be2a2ac1	1303	/** @} / / End of group nRF51 */
emilmont	80:8e73be2a2ac1	1304	/** @} / / End of group Nordic Semiconductor */
emilmont	80:8e73be2a2ac1	1305
emilmont	80:8e73be2a2ac1	1306	#ifdef __cplusplus
emilmont	80:8e73be2a2ac1	1307	}
emilmont	80:8e73be2a2ac1	1308	#endif
emilmont	80:8e73be2a2ac1	1309
emilmont	80:8e73be2a2ac1	1310
emilmont	80:8e73be2a2ac1	1311	#endif /* nRF51_H */
Kojto	97:433970e64889	1312

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NRF51822/nrf51.h@121:672067c3ada4, 2016-04-14 (annotated)

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