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TARGET_MOTE_L152RC/stm32l1xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 112:6f327212ef96

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	112:6f327212ef96	1	/**
Kojto	112:6f327212ef96	2	******************************************************************************
Kojto	112:6f327212ef96	3	* @file stm32l1xx_hal_rcc.h
Kojto	112:6f327212ef96	4	* @author MCD Application Team
Kojto	112:6f327212ef96	5	* @version V1.0.0
Kojto	112:6f327212ef96	6	* @date 5-September-2014
Kojto	112:6f327212ef96	7	* @brief Header file of RCC HAL module.
Kojto	112:6f327212ef96	8	******************************************************************************
Kojto	112:6f327212ef96	9	* @attention
Kojto	112:6f327212ef96	10	*
Kojto	112:6f327212ef96	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	112:6f327212ef96	12	*
Kojto	112:6f327212ef96	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	112:6f327212ef96	14	* are permitted provided that the following conditions are met:
Kojto	112:6f327212ef96	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	112:6f327212ef96	16	* this list of conditions and the following disclaimer.
Kojto	112:6f327212ef96	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	112:6f327212ef96	18	* this list of conditions and the following disclaimer in the documentation
Kojto	112:6f327212ef96	19	* and/or other materials provided with the distribution.
Kojto	112:6f327212ef96	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	112:6f327212ef96	21	* may be used to endorse or promote products derived from this software
Kojto	112:6f327212ef96	22	* without specific prior written permission.
Kojto	112:6f327212ef96	23	*
Kojto	112:6f327212ef96	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	112:6f327212ef96	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	112:6f327212ef96	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	112:6f327212ef96	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	112:6f327212ef96	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	112:6f327212ef96	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	112:6f327212ef96	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	112:6f327212ef96	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	112:6f327212ef96	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	112:6f327212ef96	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	112:6f327212ef96	34	*
Kojto	112:6f327212ef96	35	******************************************************************************
Kojto	112:6f327212ef96	36	*/
Kojto	112:6f327212ef96	37
Kojto	112:6f327212ef96	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	112:6f327212ef96	39	#ifndef __STM32L1xx_HAL_RCC_H
Kojto	112:6f327212ef96	40	#define __STM32L1xx_HAL_RCC_H
Kojto	112:6f327212ef96	41
Kojto	112:6f327212ef96	42	#ifdef __cplusplus
Kojto	112:6f327212ef96	43	extern "C" {
Kojto	112:6f327212ef96	44	#endif
Kojto	112:6f327212ef96	45
Kojto	112:6f327212ef96	46	/* Includes ------------------------------------------------------------------*/
Kojto	112:6f327212ef96	47	#include "stm32l1xx_hal_def.h"
Kojto	112:6f327212ef96	48
Kojto	112:6f327212ef96	49	/** @addtogroup STM32L1xx_HAL_Driver
Kojto	112:6f327212ef96	50	* @{
Kojto	112:6f327212ef96	51	*/
Kojto	112:6f327212ef96	52
Kojto	112:6f327212ef96	53	/** @addtogroup RCC
Kojto	112:6f327212ef96	54	* @{
Kojto	112:6f327212ef96	55	*/
Kojto	112:6f327212ef96	56
Kojto	112:6f327212ef96	57	/* Exported types ------------------------------------------------------------*/
Kojto	112:6f327212ef96	58
Kojto	112:6f327212ef96	59	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	112:6f327212ef96	60	* @{
Kojto	112:6f327212ef96	61	*/
Kojto	112:6f327212ef96	62
Kojto	112:6f327212ef96	63	/**
Kojto	112:6f327212ef96	64	* @brief RCC PLL configuration structure definition
Kojto	112:6f327212ef96	65	*/
Kojto	112:6f327212ef96	66	typedef struct
Kojto	112:6f327212ef96	67	{
Kojto	112:6f327212ef96	68	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	112:6f327212ef96	69	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	112:6f327212ef96	70
Kojto	112:6f327212ef96	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	112:6f327212ef96	72	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	112:6f327212ef96	73
Kojto	112:6f327212ef96	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	112:6f327212ef96	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	112:6f327212ef96	76
Kojto	112:6f327212ef96	77	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
Kojto	112:6f327212ef96	78	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
Kojto	112:6f327212ef96	79	} RCC_PLLInitTypeDef;
Kojto	112:6f327212ef96	80
Kojto	112:6f327212ef96	81	/**
Kojto	112:6f327212ef96	82	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	112:6f327212ef96	83	*/
Kojto	112:6f327212ef96	84	typedef struct
Kojto	112:6f327212ef96	85	{
Kojto	112:6f327212ef96	86	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	112:6f327212ef96	87	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	112:6f327212ef96	88
Kojto	112:6f327212ef96	89	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	112:6f327212ef96	90	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	112:6f327212ef96	91
Kojto	112:6f327212ef96	92	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	112:6f327212ef96	93	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	112:6f327212ef96	94
Kojto	112:6f327212ef96	95	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	112:6f327212ef96	96	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	112:6f327212ef96	97
Kojto	112:6f327212ef96	98	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	112:6f327212ef96	99	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	112:6f327212ef96	100
Kojto	112:6f327212ef96	101	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	112:6f327212ef96	102	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	112:6f327212ef96	103
Kojto	112:6f327212ef96	104	uint32_t MSIState; /*!< The new state of the MSI.
Kojto	112:6f327212ef96	105	This parameter can be a value of @ref RCC_MSI_Config */
Kojto	112:6f327212ef96	106
Kojto	112:6f327212ef96	107	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
Kojto	112:6f327212ef96	108	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto	112:6f327212ef96	109
Kojto	112:6f327212ef96	110	uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto	112:6f327212ef96	111	This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto	112:6f327212ef96	112
Kojto	112:6f327212ef96	113	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	112:6f327212ef96	114
Kojto	112:6f327212ef96	115	} RCC_OscInitTypeDef;
Kojto	112:6f327212ef96	116
Kojto	112:6f327212ef96	117	/**
Kojto	112:6f327212ef96	118	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	112:6f327212ef96	119	*/
Kojto	112:6f327212ef96	120	typedef struct
Kojto	112:6f327212ef96	121	{
Kojto	112:6f327212ef96	122	uint32_t ClockType; /*!< The clock to be configured.
Kojto	112:6f327212ef96	123	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	112:6f327212ef96	124
Kojto	112:6f327212ef96	125	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	112:6f327212ef96	126	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	112:6f327212ef96	127
Kojto	112:6f327212ef96	128	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	112:6f327212ef96	129	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	112:6f327212ef96	130
Kojto	112:6f327212ef96	131	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	112:6f327212ef96	132	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	112:6f327212ef96	133
Kojto	112:6f327212ef96	134	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	112:6f327212ef96	135	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	112:6f327212ef96	136
Kojto	112:6f327212ef96	137	} RCC_ClkInitTypeDef;
Kojto	112:6f327212ef96	138
Kojto	112:6f327212ef96	139	/**
Kojto	112:6f327212ef96	140	* @}
Kojto	112:6f327212ef96	141	*/
Kojto	112:6f327212ef96	142
Kojto	112:6f327212ef96	143	/* Exported constants --------------------------------------------------------*/
Kojto	112:6f327212ef96	144	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	112:6f327212ef96	145	* @{
Kojto	112:6f327212ef96	146	*/
Kojto	112:6f327212ef96	147	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	112:6f327212ef96	148	#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	112:6f327212ef96	149
Kojto	112:6f327212ef96	150	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	112:6f327212ef96	151	* @brief RCC registers bit address in the alias region
Kojto	112:6f327212ef96	152	* @{
Kojto	112:6f327212ef96	153	*/
Kojto	112:6f327212ef96	154	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	112:6f327212ef96	155	#define RCC_CR_OFFSET 0x00
Kojto	112:6f327212ef96	156	#define RCC_CFGR_OFFSET 0x08
Kojto	112:6f327212ef96	157	#define RCC_CIR_OFFSET 0x0C
Kojto	112:6f327212ef96	158	#define RCC_CSR_OFFSET 0x34
Kojto	112:6f327212ef96	159	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
Kojto	112:6f327212ef96	160	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
Kojto	112:6f327212ef96	161	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
Kojto	112:6f327212ef96	162	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
Kojto	112:6f327212ef96	163
Kojto	112:6f327212ef96	164	/* --- CR Register ---*/
Kojto	112:6f327212ef96	165	/* Alias word address of HSION bit */
Kojto	112:6f327212ef96	166	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
Kojto	112:6f327212ef96	167	#define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
Kojto	112:6f327212ef96	168	/* Alias word address of MSION bit */
Kojto	112:6f327212ef96	169	#define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION)
Kojto	112:6f327212ef96	170	#define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4)))
Kojto	112:6f327212ef96	171	/* Alias word address of HSEON bit */
Kojto	112:6f327212ef96	172	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
Kojto	112:6f327212ef96	173	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
Kojto	112:6f327212ef96	174	/* Alias word address of CSSON bit */
Kojto	112:6f327212ef96	175	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
Kojto	112:6f327212ef96	176	#define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
Kojto	112:6f327212ef96	177	/* Alias word address of PLLON bit */
Kojto	112:6f327212ef96	178	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
Kojto	112:6f327212ef96	179	#define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
Kojto	112:6f327212ef96	180
Kojto	112:6f327212ef96	181	/* --- CSR Register ---*/
Kojto	112:6f327212ef96	182	/* Alias word address of LSION bit */
Kojto	112:6f327212ef96	183	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
Kojto	112:6f327212ef96	184	#define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
Kojto	112:6f327212ef96	185
Kojto	112:6f327212ef96	186	/* Alias word address of LSEON bit */
Kojto	112:6f327212ef96	187	#define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON)
Kojto	112:6f327212ef96	188	#define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
Kojto	112:6f327212ef96	189
Kojto	112:6f327212ef96	190	/* Alias word address of LSEON bit */
Kojto	112:6f327212ef96	191	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP)
Kojto	112:6f327212ef96	192	#define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
Kojto	112:6f327212ef96	193
Kojto	112:6f327212ef96	194	/* Alias word address of RTCEN bit */
Kojto	112:6f327212ef96	195	#define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN)
Kojto	112:6f327212ef96	196	#define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
Kojto	112:6f327212ef96	197
Kojto	112:6f327212ef96	198	/* Alias word address of RTCRST bit */
Kojto	112:6f327212ef96	199	#define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST)
Kojto	112:6f327212ef96	200	#define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4)))
Kojto	112:6f327212ef96	201
Kojto	112:6f327212ef96	202	/* CR register byte 2 (Bits[23:16]) base address */
Kojto	112:6f327212ef96	203	#define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
Kojto	112:6f327212ef96	204
Kojto	112:6f327212ef96	205	/* CIR register byte 1 (Bits[15:8]) base address */
Kojto	112:6f327212ef96	206	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
Kojto	112:6f327212ef96	207
Kojto	112:6f327212ef96	208	/* CIR register byte 2 (Bits[23:16]) base address */
Kojto	112:6f327212ef96	209	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
Kojto	112:6f327212ef96	210
Kojto	112:6f327212ef96	211	/**
Kojto	112:6f327212ef96	212	* @}
Kojto	112:6f327212ef96	213	*/
Kojto	112:6f327212ef96	214
Kojto	112:6f327212ef96	215	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
Kojto	112:6f327212ef96	216	* @{
Kojto	112:6f327212ef96	217	*/
Kojto	112:6f327212ef96	218
Kojto	112:6f327212ef96	219	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
Kojto	112:6f327212ef96	220	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
Kojto	112:6f327212ef96	221
Kojto	112:6f327212ef96	222	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	112:6f327212ef96	223	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	112:6f327212ef96	224	/**
Kojto	112:6f327212ef96	225	* @}
Kojto	112:6f327212ef96	226	*/
Kojto	112:6f327212ef96	227
Kojto	112:6f327212ef96	228	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto	112:6f327212ef96	229	* @{
Kojto	112:6f327212ef96	230	*/
Kojto	112:6f327212ef96	231	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	232	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	233	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	234	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	235	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	236	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	237
Kojto	112:6f327212ef96	238	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	112:6f327212ef96	239	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	112:6f327212ef96	240	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	112:6f327212ef96	241	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	112:6f327212ef96	242	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	112:6f327212ef96	243	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
Kojto	112:6f327212ef96	244	/**
Kojto	112:6f327212ef96	245	* @}
Kojto	112:6f327212ef96	246	*/
Kojto	112:6f327212ef96	247
Kojto	112:6f327212ef96	248	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	112:6f327212ef96	249	* @{
Kojto	112:6f327212ef96	250	*/
Kojto	112:6f327212ef96	251	#define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	252	#define RCC_HSE_ON ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	253	#define RCC_HSE_BYPASS ((uint32_t)0x00000005)
Kojto	112:6f327212ef96	254
Kojto	112:6f327212ef96	255	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	112:6f327212ef96	256	((__HSE__) == RCC_HSE_BYPASS))
Kojto	112:6f327212ef96	257	/**
Kojto	112:6f327212ef96	258	* @}
Kojto	112:6f327212ef96	259	*/
Kojto	112:6f327212ef96	260
Kojto	112:6f327212ef96	261	/** @defgroup RCC_LSE_Config RCC LSE Config
Kojto	112:6f327212ef96	262	* @{
Kojto	112:6f327212ef96	263	*/
Kojto	112:6f327212ef96	264	#define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	265	#define RCC_LSE_ON ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	266	#define RCC_LSE_BYPASS ((uint32_t)0x00000005)
Kojto	112:6f327212ef96	267
Kojto	112:6f327212ef96	268	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	112:6f327212ef96	269	((__LSE__) == RCC_LSE_BYPASS))
Kojto	112:6f327212ef96	270	/**
Kojto	112:6f327212ef96	271	* @}
Kojto	112:6f327212ef96	272	*/
Kojto	112:6f327212ef96	273
Kojto	112:6f327212ef96	274	/** @defgroup RCC_HSI_Config RCC HSI Config
Kojto	112:6f327212ef96	275	* @{
Kojto	112:6f327212ef96	276	*/
Kojto	112:6f327212ef96	277	#define RCC_HSI_OFF ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	278	#define RCC_HSI_ON ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	279
Kojto	112:6f327212ef96	280	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
Kojto	112:6f327212ef96	281
Kojto	112:6f327212ef96	282	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	112:6f327212ef96	283
Kojto	112:6f327212ef96	284	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	112:6f327212ef96	285	/**
Kojto	112:6f327212ef96	286	* @}
Kojto	112:6f327212ef96	287	*/
Kojto	112:6f327212ef96	288
Kojto	112:6f327212ef96	289	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
Kojto	112:6f327212ef96	290	* @{
Kojto	112:6f327212ef96	291	*/
Kojto	112:6f327212ef96	292
Kojto	112:6f327212ef96	293	#define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /!< MSI = 65.536 KHz /
Kojto	112:6f327212ef96	294	#define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /!< MSI = 131.072 KHz /
Kojto	112:6f327212ef96	295	#define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /!< MSI = 262.144 KHz /
Kojto	112:6f327212ef96	296	#define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /!< MSI = 524.288 KHz /
Kojto	112:6f327212ef96	297	#define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /!< MSI = 1.048 MHz /
Kojto	112:6f327212ef96	298	#define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /!< MSI = 2.097 MHz /
Kojto	112:6f327212ef96	299	#define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /!< MSI = 4.194 MHz /
Kojto	112:6f327212ef96	300
Kojto	112:6f327212ef96	301	#define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
Kojto	112:6f327212ef96	302	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
Kojto	112:6f327212ef96	303	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
Kojto	112:6f327212ef96	304	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
Kojto	112:6f327212ef96	305	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Kojto	112:6f327212ef96	306	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Kojto	112:6f327212ef96	307	((__RANGE__) == RCC_MSIRANGE_6))
Kojto	112:6f327212ef96	308	/**
Kojto	112:6f327212ef96	309	* @}
Kojto	112:6f327212ef96	310	*/
Kojto	112:6f327212ef96	311
Kojto	112:6f327212ef96	312	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	112:6f327212ef96	313	* @{
Kojto	112:6f327212ef96	314	*/
Kojto	112:6f327212ef96	315	#define RCC_LSI_OFF ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	316	#define RCC_LSI_ON ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	317
Kojto	112:6f327212ef96	318	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	112:6f327212ef96	319	/**
Kojto	112:6f327212ef96	320	* @}
Kojto	112:6f327212ef96	321	*/
Kojto	112:6f327212ef96	322
Kojto	112:6f327212ef96	323
Kojto	112:6f327212ef96	324	/** @defgroup RCC_MSI_Config RCC MSI Config
Kojto	112:6f327212ef96	325	* @{
Kojto	112:6f327212ef96	326	*/
Kojto	112:6f327212ef96	327	#define RCC_MSI_OFF ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	328	#define RCC_MSI_ON ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	329
Kojto	112:6f327212ef96	330	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
Kojto	112:6f327212ef96	331
Kojto	112:6f327212ef96	332	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */
Kojto	112:6f327212ef96	333
Kojto	112:6f327212ef96	334	/**
Kojto	112:6f327212ef96	335	* @}
Kojto	112:6f327212ef96	336	*/
Kojto	112:6f327212ef96	337
Kojto	112:6f327212ef96	338	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	112:6f327212ef96	339	* @{
Kojto	112:6f327212ef96	340	*/
Kojto	112:6f327212ef96	341	#define RCC_PLL_NONE ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	342	#define RCC_PLL_OFF ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	343	#define RCC_PLL_ON ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	344
Kojto	112:6f327212ef96	345	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
Kojto	112:6f327212ef96	346	((__PLL__) == RCC_PLL_ON))
Kojto	112:6f327212ef96	347	/**
Kojto	112:6f327212ef96	348	* @}
Kojto	112:6f327212ef96	349	*/
Kojto	112:6f327212ef96	350
Kojto	112:6f327212ef96	351	/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor
Kojto	112:6f327212ef96	352	* @{
Kojto	112:6f327212ef96	353	*/
Kojto	112:6f327212ef96	354
Kojto	112:6f327212ef96	355	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
Kojto	112:6f327212ef96	356	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
Kojto	112:6f327212ef96	357	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
Kojto	112:6f327212ef96	358
Kojto	112:6f327212ef96	359	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
Kojto	112:6f327212ef96	360	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
Kojto	112:6f327212ef96	361
Kojto	112:6f327212ef96	362	/**
Kojto	112:6f327212ef96	363	* @}
Kojto	112:6f327212ef96	364	*/
Kojto	112:6f327212ef96	365
Kojto	112:6f327212ef96	366	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto	112:6f327212ef96	367	* @{
Kojto	112:6f327212ef96	368	*/
Kojto	112:6f327212ef96	369
Kojto	112:6f327212ef96	370	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto	112:6f327212ef96	371	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto	112:6f327212ef96	372	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto	112:6f327212ef96	373	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto	112:6f327212ef96	374	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto	112:6f327212ef96	375	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto	112:6f327212ef96	376	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
Kojto	112:6f327212ef96	377	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
Kojto	112:6f327212ef96	378	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
Kojto	112:6f327212ef96	379
Kojto	112:6f327212ef96	380	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
Kojto	112:6f327212ef96	381	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
Kojto	112:6f327212ef96	382	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
Kojto	112:6f327212ef96	383	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
Kojto	112:6f327212ef96	384	((__MUL__) == RCC_PLL_MUL48))
Kojto	112:6f327212ef96	385	/**
Kojto	112:6f327212ef96	386	* @}
Kojto	112:6f327212ef96	387	*/
Kojto	112:6f327212ef96	388
Kojto	112:6f327212ef96	389	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	112:6f327212ef96	390	* @{
Kojto	112:6f327212ef96	391	*/
Kojto	112:6f327212ef96	392	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	393	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	394	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	395	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	396
Kojto	112:6f327212ef96	397	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto	112:6f327212ef96	398	/**
Kojto	112:6f327212ef96	399	* @}
Kojto	112:6f327212ef96	400	*/
Kojto	112:6f327212ef96	401
Kojto	112:6f327212ef96	402	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	112:6f327212ef96	403	* @{
Kojto	112:6f327212ef96	404	*/
Kojto	112:6f327212ef96	405	#define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI)
Kojto	112:6f327212ef96	406	#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI)
Kojto	112:6f327212ef96	407	#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE)
Kojto	112:6f327212ef96	408	#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL)
Kojto	112:6f327212ef96	409
Kojto	112:6f327212ef96	410	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
Kojto	112:6f327212ef96	411	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	112:6f327212ef96	412	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	112:6f327212ef96	413	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	112:6f327212ef96	414	/**
Kojto	112:6f327212ef96	415	* @}
Kojto	112:6f327212ef96	416	*/
Kojto	112:6f327212ef96	417
Kojto	112:6f327212ef96	418	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto	112:6f327212ef96	419	* @{
Kojto	112:6f327212ef96	420	*/
Kojto	112:6f327212ef96	421	#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
Kojto	112:6f327212ef96	422	#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
Kojto	112:6f327212ef96	423	#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
Kojto	112:6f327212ef96	424	#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
Kojto	112:6f327212ef96	425	#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
Kojto	112:6f327212ef96	426	#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
Kojto	112:6f327212ef96	427	#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
Kojto	112:6f327212ef96	428	#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
Kojto	112:6f327212ef96	429	#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
Kojto	112:6f327212ef96	430
Kojto	112:6f327212ef96	431	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	112:6f327212ef96	432	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	112:6f327212ef96	433	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	112:6f327212ef96	434	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	112:6f327212ef96	435	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	112:6f327212ef96	436	/**
Kojto	112:6f327212ef96	437	* @}
Kojto	112:6f327212ef96	438	*/
Kojto	112:6f327212ef96	439
Kojto	112:6f327212ef96	440	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
Kojto	112:6f327212ef96	441	* @{
Kojto	112:6f327212ef96	442	*/
Kojto	112:6f327212ef96	443	#define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1)
Kojto	112:6f327212ef96	444	#define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2)
Kojto	112:6f327212ef96	445	#define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4)
Kojto	112:6f327212ef96	446	#define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8)
Kojto	112:6f327212ef96	447	#define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16)
Kojto	112:6f327212ef96	448
Kojto	112:6f327212ef96	449	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	112:6f327212ef96	450	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	112:6f327212ef96	451	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	112:6f327212ef96	452	/**
Kojto	112:6f327212ef96	453	* @}
Kojto	112:6f327212ef96	454	*/
Kojto	112:6f327212ef96	455
Kojto	112:6f327212ef96	456	/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source
Kojto	112:6f327212ef96	457	* @{
Kojto	112:6f327212ef96	458	*/
Kojto	112:6f327212ef96	459	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE)
Kojto	112:6f327212ef96	460	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI)
Kojto	112:6f327212ef96	461	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE)
Kojto	112:6f327212ef96	462	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 \| RCC_CSR_RTCSEL_HSE))
Kojto	112:6f327212ef96	463	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 \| RCC_CSR_RTCSEL_HSE))
Kojto	112:6f327212ef96	464	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE \| RCC_CSR_RTCSEL_HSE))
Kojto	112:6f327212ef96	465	/**
Kojto	112:6f327212ef96	466	* @}
Kojto	112:6f327212ef96	467	*/
Kojto	112:6f327212ef96	468
Kojto	112:6f327212ef96	469	/** @defgroup RCC_MCO_Index RCC MCO Index
Kojto	112:6f327212ef96	470	* @{
Kojto	112:6f327212ef96	471	*/
Kojto	112:6f327212ef96	472	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	473	#define RCC_MCO RCC_MCO1
Kojto	112:6f327212ef96	474
Kojto	112:6f327212ef96	475	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
Kojto	112:6f327212ef96	476	/**
Kojto	112:6f327212ef96	477	* @}
Kojto	112:6f327212ef96	478	*/
Kojto	112:6f327212ef96	479
Kojto	112:6f327212ef96	480	/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
Kojto	112:6f327212ef96	481	* @{
Kojto	112:6f327212ef96	482	*/
Kojto	112:6f327212ef96	483	#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
Kojto	112:6f327212ef96	484	#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
Kojto	112:6f327212ef96	485	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
Kojto	112:6f327212ef96	486	#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
Kojto	112:6f327212ef96	487	#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
Kojto	112:6f327212ef96	488
Kojto	112:6f327212ef96	489	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
Kojto	112:6f327212ef96	490	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
Kojto	112:6f327212ef96	491	((__DIV__) == RCC_MCODIV_16))
Kojto	112:6f327212ef96	492	/**
Kojto	112:6f327212ef96	493	* @}
Kojto	112:6f327212ef96	494	*/
Kojto	112:6f327212ef96	495
Kojto	112:6f327212ef96	496	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
Kojto	112:6f327212ef96	497	* @{
Kojto	112:6f327212ef96	498	*/
Kojto	112:6f327212ef96	499	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
Kojto	112:6f327212ef96	500	#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
Kojto	112:6f327212ef96	501	#define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI)
Kojto	112:6f327212ef96	502	#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
Kojto	112:6f327212ef96	503	#define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE)
Kojto	112:6f327212ef96	504	#define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI)
Kojto	112:6f327212ef96	505	#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
Kojto	112:6f327212ef96	506	#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL)
Kojto	112:6f327212ef96	507
Kojto	112:6f327212ef96	508	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
Kojto	112:6f327212ef96	509	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
Kojto	112:6f327212ef96	510	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
Kojto	112:6f327212ef96	511	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
Kojto	112:6f327212ef96	512	/**
Kojto	112:6f327212ef96	513	* @}
Kojto	112:6f327212ef96	514	*/
Kojto	112:6f327212ef96	515
Kojto	112:6f327212ef96	516	/** @defgroup RCC_Interrupt RCC Interrupt
Kojto	112:6f327212ef96	517	* @{
Kojto	112:6f327212ef96	518	*/
Kojto	112:6f327212ef96	519	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
Kojto	112:6f327212ef96	520	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
Kojto	112:6f327212ef96	521	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
Kojto	112:6f327212ef96	522	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
Kojto	112:6f327212ef96	523	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
Kojto	112:6f327212ef96	524	#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF)
Kojto	112:6f327212ef96	525	#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS)
Kojto	112:6f327212ef96	526	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
Kojto	112:6f327212ef96	527	/**
Kojto	112:6f327212ef96	528	* @}
Kojto	112:6f327212ef96	529	*/
Kojto	112:6f327212ef96	530
Kojto	112:6f327212ef96	531	/** @defgroup RCC_Flag RCC Flag
Kojto	112:6f327212ef96	532	* Elements values convention: 0XXYYYYYb
Kojto	112:6f327212ef96	533	* - YYYYY : Flag position in the register
Kojto	112:6f327212ef96	534	* - XX : Register index
Kojto	112:6f327212ef96	535	* - 01: CR register
Kojto	112:6f327212ef96	536	* - 11: CSR register
Kojto	112:6f327212ef96	537	* @{
Kojto	112:6f327212ef96	538	*/
Kojto	112:6f327212ef96	539	#define CR_REG_INDEX ((uint8_t)1)
Kojto	112:6f327212ef96	540	#define CSR_REG_INDEX ((uint8_t)3)
Kojto	112:6f327212ef96	541
Kojto	112:6f327212ef96	542	/* Flags in the CR register */
Kojto	112:6f327212ef96	543	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY)))
Kojto	112:6f327212ef96	544	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY)))
Kojto	112:6f327212ef96	545	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY)))
Kojto	112:6f327212ef96	546	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY)))
Kojto	112:6f327212ef96	547
Kojto	112:6f327212ef96	548	/* Flags in the CSR register */
Kojto	112:6f327212ef96	549	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY)))
Kojto	112:6f327212ef96	550	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSERDY)))
Kojto	112:6f327212ef96	551	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSECSSD)))
Kojto	112:6f327212ef96	552	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF)))
Kojto	112:6f327212ef96	553	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF)))
Kojto	112:6f327212ef96	554	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF)))
Kojto	112:6f327212ef96	555	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF)))
Kojto	112:6f327212ef96	556	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF)))
Kojto	112:6f327212ef96	557	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF)))
Kojto	112:6f327212ef96	558	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF)))
Kojto	112:6f327212ef96	559	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF)))
Kojto	112:6f327212ef96	560
Kojto	112:6f327212ef96	561	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	112:6f327212ef96	562
Kojto	112:6f327212ef96	563	/**
Kojto	112:6f327212ef96	564	* @}
Kojto	112:6f327212ef96	565	*/
Kojto	112:6f327212ef96	566
Kojto	112:6f327212ef96	567	/**
Kojto	112:6f327212ef96	568	* @}
Kojto	112:6f327212ef96	569	*/
Kojto	112:6f327212ef96	570
Kojto	112:6f327212ef96	571	/* Exported macro ------------------------------------------------------------*/
Kojto	112:6f327212ef96	572
Kojto	112:6f327212ef96	573	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	112:6f327212ef96	574	* @{
Kojto	112:6f327212ef96	575	*/
Kojto	112:6f327212ef96	576
Kojto	112:6f327212ef96	577	/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	578	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	112:6f327212ef96	579	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	580	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	581	* using it.
Kojto	112:6f327212ef96	582	* @{
Kojto	112:6f327212ef96	583	*/
Kojto	112:6f327212ef96	584	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
Kojto	112:6f327212ef96	585	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
Kojto	112:6f327212ef96	586	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
Kojto	112:6f327212ef96	587	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
Kojto	112:6f327212ef96	588	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
Kojto	112:6f327212ef96	589
Kojto	112:6f327212ef96	590	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
Kojto	112:6f327212ef96	591	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
Kojto	112:6f327212ef96	592	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
Kojto	112:6f327212ef96	593
Kojto	112:6f327212ef96	594	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto	112:6f327212ef96	595	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto	112:6f327212ef96	596	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto	112:6f327212ef96	597	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto	112:6f327212ef96	598	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
Kojto	112:6f327212ef96	599
Kojto	112:6f327212ef96	600	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	112:6f327212ef96	601	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto	112:6f327212ef96	602	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	112:6f327212ef96	603
Kojto	112:6f327212ef96	604	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	605	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	606	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	607	* using it.
Kojto	112:6f327212ef96	608	*/
Kojto	112:6f327212ef96	609	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	610	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	611	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	612	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
Kojto	112:6f327212ef96	613	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
Kojto	112:6f327212ef96	614	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
Kojto	112:6f327212ef96	615	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	112:6f327212ef96	616	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	112:6f327212ef96	617	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
Kojto	112:6f327212ef96	618	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	112:6f327212ef96	619	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	112:6f327212ef96	620	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
Kojto	112:6f327212ef96	621	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
Kojto	112:6f327212ef96	622	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
Kojto	112:6f327212ef96	623	#define __COMP_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_COMPEN))
Kojto	112:6f327212ef96	624
Kojto	112:6f327212ef96	625	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	626	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	627	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	628	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	112:6f327212ef96	629	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	112:6f327212ef96	630	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	112:6f327212ef96	631	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	112:6f327212ef96	632	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	112:6f327212ef96	633	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	112:6f327212ef96	634	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	112:6f327212ef96	635	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	112:6f327212ef96	636	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto	112:6f327212ef96	637	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	112:6f327212ef96	638	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	112:6f327212ef96	639	#define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
Kojto	112:6f327212ef96	640
Kojto	112:6f327212ef96	641	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	642	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	643	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	644	* using it.
Kojto	112:6f327212ef96	645	*/
Kojto	112:6f327212ef96	646	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
Kojto	112:6f327212ef96	647	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
Kojto	112:6f327212ef96	648	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	649	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
Kojto	112:6f327212ef96	650	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
Kojto	112:6f327212ef96	651	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	112:6f327212ef96	652	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
Kojto	112:6f327212ef96	653
Kojto	112:6f327212ef96	654	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	112:6f327212ef96	655	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto	112:6f327212ef96	656	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	657	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto	112:6f327212ef96	658	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	112:6f327212ef96	659	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	112:6f327212ef96	660	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	112:6f327212ef96	661
Kojto	112:6f327212ef96	662	/**
Kojto	112:6f327212ef96	663	* @}
Kojto	112:6f327212ef96	664	*/
Kojto	112:6f327212ef96	665
Kojto	112:6f327212ef96	666	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
Kojto	112:6f327212ef96	667	* @brief Force or release AHB peripheral reset.
Kojto	112:6f327212ef96	668	* @{
Kojto	112:6f327212ef96	669	*/
Kojto	112:6f327212ef96	670	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	671	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
Kojto	112:6f327212ef96	672	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
Kojto	112:6f327212ef96	673	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
Kojto	112:6f327212ef96	674	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
Kojto	112:6f327212ef96	675	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
Kojto	112:6f327212ef96	676
Kojto	112:6f327212ef96	677	#define __CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
Kojto	112:6f327212ef96	678	#define __FLITF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FLITFRST))
Kojto	112:6f327212ef96	679	#define __DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
Kojto	112:6f327212ef96	680
Kojto	112:6f327212ef96	681	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	112:6f327212ef96	682	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto	112:6f327212ef96	683	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto	112:6f327212ef96	684	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto	112:6f327212ef96	685	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto	112:6f327212ef96	686	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
Kojto	112:6f327212ef96	687
Kojto	112:6f327212ef96	688	#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
Kojto	112:6f327212ef96	689	#define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
Kojto	112:6f327212ef96	690	#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
Kojto	112:6f327212ef96	691
Kojto	112:6f327212ef96	692	/** @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	693	*/
Kojto	112:6f327212ef96	694	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	695	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	696	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	697	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	698	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	699	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	700	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	112:6f327212ef96	701	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	112:6f327212ef96	702	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	112:6f327212ef96	703	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	704	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	112:6f327212ef96	705	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	112:6f327212ef96	706	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	112:6f327212ef96	707	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	112:6f327212ef96	708	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	709	#define __COMP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_COMPRST))
Kojto	112:6f327212ef96	710
Kojto	112:6f327212ef96	711	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	112:6f327212ef96	712	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	713	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	714	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	715	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	716	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	717	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	112:6f327212ef96	718	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	112:6f327212ef96	719	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	112:6f327212ef96	720	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	721	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	112:6f327212ef96	722	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	112:6f327212ef96	723	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto	112:6f327212ef96	724	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	112:6f327212ef96	725	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	726	#define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
Kojto	112:6f327212ef96	727
Kojto	112:6f327212ef96	728	/** @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	729	*/
Kojto	112:6f327212ef96	730	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	731	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	112:6f327212ef96	732	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
Kojto	112:6f327212ef96	733	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	734	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
Kojto	112:6f327212ef96	735	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	112:6f327212ef96	736	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	112:6f327212ef96	737	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	112:6f327212ef96	738
Kojto	112:6f327212ef96	739	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	112:6f327212ef96	740	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	112:6f327212ef96	741	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto	112:6f327212ef96	742	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	743	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto	112:6f327212ef96	744	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	112:6f327212ef96	745	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	112:6f327212ef96	746	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	112:6f327212ef96	747
Kojto	112:6f327212ef96	748	/**
Kojto	112:6f327212ef96	749	* @}
Kojto	112:6f327212ef96	750	*/
Kojto	112:6f327212ef96	751
Kojto	112:6f327212ef96	752	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
Kojto	112:6f327212ef96	753	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	754	* power consumption.
Kojto	112:6f327212ef96	755	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	756	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	757	* @{
Kojto	112:6f327212ef96	758	*/
Kojto	112:6f327212ef96	759	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOALPEN))
Kojto	112:6f327212ef96	760	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOBLPEN))
Kojto	112:6f327212ef96	761	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOCLPEN))
Kojto	112:6f327212ef96	762	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIODLPEN))
Kojto	112:6f327212ef96	763	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOHLPEN))
Kojto	112:6f327212ef96	764
Kojto	112:6f327212ef96	765	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_CRCLPEN))
Kojto	112:6f327212ef96	766	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_FLITFLPEN))
Kojto	112:6f327212ef96	767	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_DMA1LPEN))
Kojto	112:6f327212ef96	768
Kojto	112:6f327212ef96	769	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
Kojto	112:6f327212ef96	770	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
Kojto	112:6f327212ef96	771	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
Kojto	112:6f327212ef96	772	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
Kojto	112:6f327212ef96	773	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
Kojto	112:6f327212ef96	774
Kojto	112:6f327212ef96	775	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
Kojto	112:6f327212ef96	776	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
Kojto	112:6f327212ef96	777	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
Kojto	112:6f327212ef96	778
Kojto	112:6f327212ef96	779	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	780	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	781	* power consumption.
Kojto	112:6f327212ef96	782	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	783	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	784	*/
Kojto	112:6f327212ef96	785	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	786	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	787	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	788	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	789	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	790	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
Kojto	112:6f327212ef96	791	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
Kojto	112:6f327212ef96	792	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
Kojto	112:6f327212ef96	793	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	794	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
Kojto	112:6f327212ef96	795	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
Kojto	112:6f327212ef96	796	#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USBLPEN))
Kojto	112:6f327212ef96	797	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
Kojto	112:6f327212ef96	798	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	799	#define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_COMPLPEN))
Kojto	112:6f327212ef96	800
Kojto	112:6f327212ef96	801	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	802	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	803	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	804	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	805	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	806	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto	112:6f327212ef96	807	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto	112:6f327212ef96	808	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto	112:6f327212ef96	809	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	810	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto	112:6f327212ef96	811	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto	112:6f327212ef96	812	#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
Kojto	112:6f327212ef96	813	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto	112:6f327212ef96	814	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	815	#define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
Kojto	112:6f327212ef96	816
Kojto	112:6f327212ef96	817	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	818	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	819	* power consumption.
Kojto	112:6f327212ef96	820	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	821	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	822	*/
Kojto	112:6f327212ef96	823	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto	112:6f327212ef96	824	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
Kojto	112:6f327212ef96	825	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	826	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
Kojto	112:6f327212ef96	827	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
Kojto	112:6f327212ef96	828	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
Kojto	112:6f327212ef96	829	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
Kojto	112:6f327212ef96	830
Kojto	112:6f327212ef96	831	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto	112:6f327212ef96	832	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto	112:6f327212ef96	833	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	834	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto	112:6f327212ef96	835	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto	112:6f327212ef96	836	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto	112:6f327212ef96	837	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto	112:6f327212ef96	838
Kojto	112:6f327212ef96	839	/**
Kojto	112:6f327212ef96	840	* @}
Kojto	112:6f327212ef96	841	*/
Kojto	112:6f327212ef96	842
Kojto	112:6f327212ef96	843	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	112:6f327212ef96	844	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	845	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	112:6f327212ef96	846	* you have to select another source of the system clock then stop the HSI.
Kojto	112:6f327212ef96	847	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	112:6f327212ef96	848	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	112:6f327212ef96	849	* system clock source.
Kojto	112:6f327212ef96	850	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	112:6f327212ef96	851	* clock cycles.
Kojto	112:6f327212ef96	852	*/
Kojto	112:6f327212ef96	853	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
Kojto	112:6f327212ef96	854	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
Kojto	112:6f327212ef96	855
Kojto	112:6f327212ef96	856	/** @brief Macros to enable or disable the External High Speed oscillator (HSE).
Kojto	112:6f327212ef96	857	* @param __HSE_STATE__: specifies the new state of the HSE.
Kojto	112:6f327212ef96	858	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	859	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	112:6f327212ef96	860	* 6 HSE oscillator clock cycles.
Kojto	112:6f327212ef96	861	* @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto	112:6f327212ef96	862	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto	112:6f327212ef96	863	*/
Kojto	112:6f327212ef96	864	#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__HSE_STATE__))
Kojto	112:6f327212ef96	865
Kojto	112:6f327212ef96	866	/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto	112:6f327212ef96	867	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	868	* It is used (enabled by hardware) as system clock source after startup
Kojto	112:6f327212ef96	869	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	112:6f327212ef96	870	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	112:6f327212ef96	871	* Security System CSS is enabled).
Kojto	112:6f327212ef96	872	* @note MSI can not be stopped if it is used as system clock source. In this case,
Kojto	112:6f327212ef96	873	* you have to select another source of the system clock then stop the MSI.
Kojto	112:6f327212ef96	874	* @note After enabling the MSI, the application software should wait on MSIRDY
Kojto	112:6f327212ef96	875	* flag to be set indicating that MSI clock is stable and can be used as
Kojto	112:6f327212ef96	876	* system clock source.
Kojto	112:6f327212ef96	877	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto	112:6f327212ef96	878	* clock cycles.
Kojto	112:6f327212ef96	879	*/
Kojto	112:6f327212ef96	880	#define __HAL_RCC_MSI_ENABLE() ((__IO uint32_t ) CR_MSION_BB = ENABLE)
Kojto	112:6f327212ef96	881	#define __HAL_RCC_MSI_DISABLE() ((__IO uint32_t ) CR_MSION_BB = DISABLE)
Kojto	112:6f327212ef96	882
Kojto	112:6f327212ef96	883	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	112:6f327212ef96	884	* @note The calibration is used to compensate for the variations in voltage
Kojto	112:6f327212ef96	885	* and temperature that influence the frequency of the internal HSI RC.
Kojto	112:6f327212ef96	886	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto	112:6f327212ef96	887	* (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	112:6f327212ef96	888	* This parameter must be a number between 0 and 0x1F.
Kojto	112:6f327212ef96	889	*/
Kojto	112:6f327212ef96	890	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto	112:6f327212ef96	891	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
Kojto	112:6f327212ef96	892
Kojto	112:6f327212ef96	893	/** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
Kojto	112:6f327212ef96	894	* @note The calibration is used to compensate for the variations in voltage
Kojto	112:6f327212ef96	895	* and temperature that influence the frequency of the internal MSI RC.
Kojto	112:6f327212ef96	896	* @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto	112:6f327212ef96	897	* (default is RCC_MSICALIBRATION_DEFAULT).
Kojto	112:6f327212ef96	898	* This parameter must be a number between 0 and 0x1F.
Kojto	112:6f327212ef96	899	*/
Kojto	112:6f327212ef96	900	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
Kojto	112:6f327212ef96	901	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
Kojto	112:6f327212ef96	902
Kojto	112:6f327212ef96	903	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
Kojto	112:6f327212ef96	904	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
Kojto	112:6f327212ef96	905	* around 2.097 MHz. The MSI clock does not change after wake-up from
Kojto	112:6f327212ef96	906	* STOP mode.
Kojto	112:6f327212ef96	907	* @note The MSI clock range can be modified on the fly.
Kojto	112:6f327212ef96	908	* @param _MSIRANGEVALUE_: specifies the MSI Clock range.
Kojto	112:6f327212ef96	909	* This parameter must be one of the following values:
Kojto	112:6f327212ef96	910	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
Kojto	112:6f327212ef96	911	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
Kojto	112:6f327212ef96	912	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
Kojto	112:6f327212ef96	913	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
Kojto	112:6f327212ef96	914	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
Kojto	112:6f327212ef96	915	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Kojto	112:6f327212ef96	916	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
Kojto	112:6f327212ef96	917	*/
Kojto	112:6f327212ef96	918	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
Kojto	112:6f327212ef96	919
Kojto	112:6f327212ef96	920
Kojto	112:6f327212ef96	921	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	112:6f327212ef96	922	* @note After enabling the LSI, the application software should wait on
Kojto	112:6f327212ef96	923	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	112:6f327212ef96	924	* be used to clock the IWDG and/or the RTC.
Kojto	112:6f327212ef96	925	* @note LSI can not be disabled if the IWDG is running.
Kojto	112:6f327212ef96	926	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	112:6f327212ef96	927	* clock cycles.
Kojto	112:6f327212ef96	928	*/
Kojto	112:6f327212ef96	929	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
Kojto	112:6f327212ef96	930	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
Kojto	112:6f327212ef96	931
Kojto	112:6f327212ef96	932	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
Kojto	112:6f327212ef96	933	*/
Kojto	112:6f327212ef96	934	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
Kojto	112:6f327212ef96	935	do{ \
Kojto	112:6f327212ef96	936	if ((__LSE_STATE__) == RCC_LSE_OFF) \
Kojto	112:6f327212ef96	937	{ \
Kojto	112:6f327212ef96	938	(__IO uint32_t ) CSR_LSEON_BB = DISABLE; \
Kojto	112:6f327212ef96	939	(__IO uint32_t ) CSR_LSEBYP_BB = DISABLE; \
Kojto	112:6f327212ef96	940	} \
Kojto	112:6f327212ef96	941	else if ((__LSE_STATE__) == RCC_LSE_ON) \
Kojto	112:6f327212ef96	942	{ \
Kojto	112:6f327212ef96	943	(__IO uint32_t ) CSR_LSEBYP_BB = DISABLE; \
Kojto	112:6f327212ef96	944	(__IO uint32_t ) CSR_LSEON_BB = ENABLE; \
Kojto	112:6f327212ef96	945	} \
Kojto	112:6f327212ef96	946	else \
Kojto	112:6f327212ef96	947	{ \
Kojto	112:6f327212ef96	948	(__IO uint32_t ) CSR_LSEON_BB = DISABLE; \
Kojto	112:6f327212ef96	949	(__IO uint32_t ) CSR_LSEBYP_BB = ENABLE; \
Kojto	112:6f327212ef96	950	} \
Kojto	112:6f327212ef96	951	}while(0)
Kojto	112:6f327212ef96	952
Kojto	112:6f327212ef96	953	/** @brief Macros to enable or disable the the RTC clock.
Kojto	112:6f327212ef96	954	* @note These macros must be used only after the RTC clock source was selected.
Kojto	112:6f327212ef96	955	*/
Kojto	112:6f327212ef96	956	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) CSR_RTCEN_BB = ENABLE)
Kojto	112:6f327212ef96	957	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) CSR_RTCEN_BB = DISABLE)
Kojto	112:6f327212ef96	958
Kojto	112:6f327212ef96	959	/** @brief Macros to force or release the Backup domain reset.
Kojto	112:6f327212ef96	960	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	112:6f327212ef96	961	* and the RTC clock source selection in RCC_CSR register.
Kojto	112:6f327212ef96	962	* @note The BKPSRAM is not affected by this reset.
Kojto	112:6f327212ef96	963	*/
Kojto	112:6f327212ef96	964	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) CSR_RTCRST_BB = ENABLE)
Kojto	112:6f327212ef96	965	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) CSR_RTCRST_BB = DISABLE)
Kojto	112:6f327212ef96	966
Kojto	112:6f327212ef96	967
Kojto	112:6f327212ef96	968	/** @brief Macro to configures the RTC clock (RTCCLK).
Kojto	112:6f327212ef96	969	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	112:6f327212ef96	970	* access is denied to this domain after reset, you have to enable write
Kojto	112:6f327212ef96	971	* access using the Power Backup Access macro before to configure
Kojto	112:6f327212ef96	972	* the RTC clock source (to be done once after reset).
Kojto	112:6f327212ef96	973	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	112:6f327212ef96	974	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto	112:6f327212ef96	975	* a Power On Reset (POR).
Kojto	112:6f327212ef96	976	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
Kojto	112:6f327212ef96	977	*
Kojto	112:6f327212ef96	978	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto	112:6f327212ef96	979	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	980	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	112:6f327212ef96	981	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	112:6f327212ef96	982	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
Kojto	112:6f327212ef96	983	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
Kojto	112:6f327212ef96	984	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
Kojto	112:6f327212ef96	985	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
Kojto	112:6f327212ef96	986	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	112:6f327212ef96	987	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	112:6f327212ef96	988	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	112:6f327212ef96	989	* cannot be used in STOP and STANDBY modes.
Kojto	112:6f327212ef96	990	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	112:6f327212ef96	991	* RTC clock source).
Kojto	112:6f327212ef96	992	*/
Kojto	112:6f327212ef96	993	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
Kojto	112:6f327212ef96	994	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
Kojto	112:6f327212ef96	995	{ \
Kojto	112:6f327212ef96	996	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
Kojto	112:6f327212ef96	997	} \
Kojto	112:6f327212ef96	998	} while (0)
Kojto	112:6f327212ef96	999
Kojto	112:6f327212ef96	1000	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
Kojto	112:6f327212ef96	1001	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
Kojto	112:6f327212ef96	1002	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
Kojto	112:6f327212ef96	1003	} while (0)
Kojto	112:6f327212ef96	1004
Kojto	112:6f327212ef96	1005	/** @brief macros to get the RTC clock source.
Kojto	112:6f327212ef96	1006	*/
Kojto	112:6f327212ef96	1007	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
Kojto	112:6f327212ef96	1008
Kojto	112:6f327212ef96	1009	/** @brief Macros to enable or disable the main PLL.
Kojto	112:6f327212ef96	1010	* @note After enabling the main PLL, the application software should wait on
Kojto	112:6f327212ef96	1011	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	112:6f327212ef96	1012	* be used as system clock source.
Kojto	112:6f327212ef96	1013	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	112:6f327212ef96	1014	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	1015	*/
Kojto	112:6f327212ef96	1016	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
Kojto	112:6f327212ef96	1017	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
Kojto	112:6f327212ef96	1018
Kojto	112:6f327212ef96	1019	/** @brief macros to configure the main PLL clock source, multiplication and division factors.
Kojto	112:6f327212ef96	1020	* @note This function must be used only when the main PLL is disabled.
Kojto	112:6f327212ef96	1021	*
Kojto	112:6f327212ef96	1022	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
Kojto	112:6f327212ef96	1023	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1024	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	1025	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	1026	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
Kojto	112:6f327212ef96	1027	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1028	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3
Kojto	112:6f327212ef96	1029	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
Kojto	112:6f327212ef96	1030	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
Kojto	112:6f327212ef96	1031	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
Kojto	112:6f327212ef96	1032	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12
Kojto	112:6f327212ef96	1033	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16
Kojto	112:6f327212ef96	1034	* @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24
Kojto	112:6f327212ef96	1035	* @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32
Kojto	112:6f327212ef96	1036	* @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48
Kojto	112:6f327212ef96	1037	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Kojto	112:6f327212ef96	1038	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
Kojto	112:6f327212ef96	1039	* in Range 3.
Kojto	112:6f327212ef96	1040	*
Kojto	112:6f327212ef96	1041	* @param __PLLDIV__: specifies the division factor for PLL VCO input clock
Kojto	112:6f327212ef96	1042	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1043	* @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2
Kojto	112:6f327212ef96	1044	* @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3
Kojto	112:6f327212ef96	1045	* @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4
Kojto	112:6f327212ef96	1046	*
Kojto	112:6f327212ef96	1047	*/
Kojto	112:6f327212ef96	1048	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
Kojto	112:6f327212ef96	1049	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
Kojto	112:6f327212ef96	1050
Kojto	112:6f327212ef96	1051	/** @brief Macro to get the clock source used as system clock.
Kojto	112:6f327212ef96	1052	* @retval The clock source used as system clock. The returned value can be one
Kojto	112:6f327212ef96	1053	* of the following:
Kojto	112:6f327212ef96	1054	* @arg RCC_CFGR_SWS_MSI: MSI used as system clock
Kojto	112:6f327212ef96	1055	* @arg RCC_CFGR_SWS_HSI: HSI used as system clock
Kojto	112:6f327212ef96	1056	* @arg RCC_CFGR_SWS_HSE: HSE used as system clock
Kojto	112:6f327212ef96	1057	* @arg RCC_CFGR_SWS_PLL: PLL used as system clock
Kojto	112:6f327212ef96	1058	*/
Kojto	112:6f327212ef96	1059	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto	112:6f327212ef96	1060
Kojto	112:6f327212ef96	1061	/** @brief macros to manage the specified RCC Flags and interrupts.
Kojto	112:6f327212ef96	1062	*/
Kojto	112:6f327212ef96	1063
Kojto	112:6f327212ef96	1064	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	112:6f327212ef96	1065	* the selected interrupts.).
Kojto	112:6f327212ef96	1066	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	112:6f327212ef96	1067	* This parameter can be any combination of the following values:
Kojto	112:6f327212ef96	1068	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	112:6f327212ef96	1069	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	112:6f327212ef96	1070	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	112:6f327212ef96	1071	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	112:6f327212ef96	1072	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	112:6f327212ef96	1073	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	112:6f327212ef96	1074	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	112:6f327212ef96	1075	*/
Kojto	112:6f327212ef96	1076	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	112:6f327212ef96	1077
Kojto	112:6f327212ef96	1078	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	112:6f327212ef96	1079	* the selected interrupts).
Kojto	112:6f327212ef96	1080	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	112:6f327212ef96	1081	* This parameter can be any combination of the following values:
Kojto	112:6f327212ef96	1082	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	112:6f327212ef96	1083	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	112:6f327212ef96	1084	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	112:6f327212ef96	1085	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	112:6f327212ef96	1086	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	112:6f327212ef96	1087	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	112:6f327212ef96	1088	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	112:6f327212ef96	1089	*/
Kojto	112:6f327212ef96	1090	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	112:6f327212ef96	1091
Kojto	112:6f327212ef96	1092	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto	112:6f327212ef96	1093	* bits to clear the selected interrupt pending bits.
Kojto	112:6f327212ef96	1094	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	112:6f327212ef96	1095	* This parameter can be any combination of the following values:
Kojto	112:6f327212ef96	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	112:6f327212ef96	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	112:6f327212ef96	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	112:6f327212ef96	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	112:6f327212ef96	1100	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	112:6f327212ef96	1101	* @arg RCC_IT_MSIRDY: MSI ready interrupt.
Kojto	112:6f327212ef96	1102	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	112:6f327212ef96	1103	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	112:6f327212ef96	1104	*/
Kojto	112:6f327212ef96	1105	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto	112:6f327212ef96	1106
Kojto	112:6f327212ef96	1107	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	112:6f327212ef96	1108	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	112:6f327212ef96	1109	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1110	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	112:6f327212ef96	1111	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	112:6f327212ef96	1112	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	112:6f327212ef96	1113	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	112:6f327212ef96	1114	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	112:6f327212ef96	1115	* @arg RCC_IT_MSIRDY: MSI ready interrupt.
Kojto	112:6f327212ef96	1116	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	112:6f327212ef96	1117	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	112:6f327212ef96	1118	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	112:6f327212ef96	1119	*/
Kojto	112:6f327212ef96	1120	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	112:6f327212ef96	1121
Kojto	112:6f327212ef96	1122	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	112:6f327212ef96	1123	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto	112:6f327212ef96	1124	*/
Kojto	112:6f327212ef96	1125	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	112:6f327212ef96	1126
Kojto	112:6f327212ef96	1127	/** @brief Check RCC flag is set or not.
Kojto	112:6f327212ef96	1128	* @param __FLAG__: specifies the flag to check.
Kojto	112:6f327212ef96	1129	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1130	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	112:6f327212ef96	1131	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready.
Kojto	112:6f327212ef96	1132	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	112:6f327212ef96	1133	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto	112:6f327212ef96	1134	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	112:6f327212ef96	1135	* @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*)
Kojto	112:6f327212ef96	1136	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto	112:6f327212ef96	1137	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto	112:6f327212ef96	1138	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	112:6f327212ef96	1139	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	112:6f327212ef96	1140	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	112:6f327212ef96	1141	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	112:6f327212ef96	1142	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	112:6f327212ef96	1143	* @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto	112:6f327212ef96	1144	* @note (*) This bit is available in high and medium+ density devices only.
Kojto	112:6f327212ef96	1145	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	112:6f327212ef96	1146	*/
Kojto	112:6f327212ef96	1147	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto	112:6f327212ef96	1148
Kojto	112:6f327212ef96	1149
Kojto	112:6f327212ef96	1150	/** @brief Get oscillator clock selected as PLL input clock
Kojto	112:6f327212ef96	1151	* @retval The clock source used for PLL entry. The returned value can be one
Kojto	112:6f327212ef96	1152	* of the following:
Kojto	112:6f327212ef96	1153	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock
Kojto	112:6f327212ef96	1154	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
Kojto	112:6f327212ef96	1155	*/
Kojto	112:6f327212ef96	1156	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto	112:6f327212ef96	1157
Kojto	112:6f327212ef96	1158	/**
Kojto	112:6f327212ef96	1159	* @}
Kojto	112:6f327212ef96	1160	*/
Kojto	112:6f327212ef96	1161
Kojto	112:6f327212ef96	1162	/* Include RCC HAL Extension module */
Kojto	112:6f327212ef96	1163	#include "stm32l1xx_hal_rcc_ex.h"
Kojto	112:6f327212ef96	1164
Kojto	112:6f327212ef96	1165	/* Exported functions --------------------------------------------------------*/
Kojto	112:6f327212ef96	1166	/** @addtogroup RCC_Private_Functions
Kojto	112:6f327212ef96	1167	* @{
Kojto	112:6f327212ef96	1168	*/
Kojto	112:6f327212ef96	1169
Kojto	112:6f327212ef96	1170	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	112:6f327212ef96	1171	* @{
Kojto	112:6f327212ef96	1172	*/
Kojto	112:6f327212ef96	1173
Kojto	112:6f327212ef96	1174	/* Initialization and de-initialization functions ******************************/
Kojto	112:6f327212ef96	1175	void HAL_RCC_DeInit(void);
Kojto	112:6f327212ef96	1176	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	112:6f327212ef96	1177	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	112:6f327212ef96	1178
Kojto	112:6f327212ef96	1179	/**
Kojto	112:6f327212ef96	1180	* @}
Kojto	112:6f327212ef96	1181	*/
Kojto	112:6f327212ef96	1182
Kojto	112:6f327212ef96	1183	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	112:6f327212ef96	1184	* @{
Kojto	112:6f327212ef96	1185	*/
Kojto	112:6f327212ef96	1186
Kojto	112:6f327212ef96	1187	/* Peripheral Control functions ************************************************/
Kojto	112:6f327212ef96	1188	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	112:6f327212ef96	1189	void HAL_RCC_EnableCSS(void);
Kojto	112:6f327212ef96	1190	void HAL_RCC_DisableCSS(void);
Kojto	112:6f327212ef96	1191	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	112:6f327212ef96	1192	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	112:6f327212ef96	1193	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	112:6f327212ef96	1194	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	112:6f327212ef96	1195	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	112:6f327212ef96	1196	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	112:6f327212ef96	1197
Kojto	112:6f327212ef96	1198	/* CSS NMI IRQ handler */
Kojto	112:6f327212ef96	1199	void HAL_RCC_NMI_IRQHandler(void);
Kojto	112:6f327212ef96	1200
Kojto	112:6f327212ef96	1201	/* User Callbacks in non blocking mode (IT mode) */
Kojto	112:6f327212ef96	1202	void HAL_RCC_CCSCallback(void);
Kojto	112:6f327212ef96	1203
Kojto	112:6f327212ef96	1204	/**
Kojto	112:6f327212ef96	1205	* @}
Kojto	112:6f327212ef96	1206	*/
Kojto	112:6f327212ef96	1207
Kojto	112:6f327212ef96	1208	/**
Kojto	112:6f327212ef96	1209	* @}
Kojto	112:6f327212ef96	1210	*/
Kojto	112:6f327212ef96	1211
Kojto	112:6f327212ef96	1212	/**
Kojto	112:6f327212ef96	1213	* @}
Kojto	112:6f327212ef96	1214	*/
Kojto	112:6f327212ef96	1215
Kojto	112:6f327212ef96	1216	/**
Kojto	112:6f327212ef96	1217	* @}
Kojto	112:6f327212ef96	1218	*/
Kojto	112:6f327212ef96	1219
Kojto	112:6f327212ef96	1220	#ifdef __cplusplus
Kojto	112:6f327212ef96	1221	}
Kojto	112:6f327212ef96	1222	#endif
Kojto	112:6f327212ef96	1223
Kojto	112:6f327212ef96	1224	#endif /* __STM32L1xx_HAL_RCC_H */
Kojto	112:6f327212ef96	1225
Kojto	112:6f327212ef96	1226	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	112:6f327212ef96	1227

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_MOTE_L152RC/stm32l1xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

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