Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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TARGET_MAX32600MBED/clkman_regs.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
101:7cff1c4259d7 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 101:7cff1c4259d7 1 /*******************************************************************************
Kojto 101:7cff1c4259d7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
Kojto 101:7cff1c4259d7 3 *
Kojto 101:7cff1c4259d7 4 * Permission is hereby granted, free of charge, to any person obtaining a
Kojto 101:7cff1c4259d7 5 * copy of this software and associated documentation files (the "Software"),
Kojto 101:7cff1c4259d7 6 * to deal in the Software without restriction, including without limitation
Kojto 101:7cff1c4259d7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
Kojto 101:7cff1c4259d7 8 * and/or sell copies of the Software, and to permit persons to whom the
Kojto 101:7cff1c4259d7 9 * Software is furnished to do so, subject to the following conditions:
Kojto 101:7cff1c4259d7 10 *
Kojto 101:7cff1c4259d7 11 * The above copyright notice and this permission notice shall be included
Kojto 101:7cff1c4259d7 12 * in all copies or substantial portions of the Software.
Kojto 101:7cff1c4259d7 13 *
Kojto 101:7cff1c4259d7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
Kojto 101:7cff1c4259d7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
Kojto 101:7cff1c4259d7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
Kojto 101:7cff1c4259d7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
Kojto 101:7cff1c4259d7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
Kojto 101:7cff1c4259d7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
Kojto 101:7cff1c4259d7 20 * OTHER DEALINGS IN THE SOFTWARE.
Kojto 101:7cff1c4259d7 21 *
Kojto 101:7cff1c4259d7 22 * Except as contained in this notice, the name of Maxim Integrated
Kojto 101:7cff1c4259d7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
Kojto 101:7cff1c4259d7 24 * Products, Inc. Branding Policy.
Kojto 101:7cff1c4259d7 25 *
Kojto 101:7cff1c4259d7 26 * The mere transfer of this software does not imply any licenses
Kojto 101:7cff1c4259d7 27 * of trade secrets, proprietary technology, copyrights, patents,
Kojto 101:7cff1c4259d7 28 * trademarks, maskwork rights, or any other form of intellectual
Kojto 101:7cff1c4259d7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
Kojto 101:7cff1c4259d7 30 * ownership rights.
Kojto 101:7cff1c4259d7 31 *******************************************************************************
Kojto 101:7cff1c4259d7 32 */
Kojto 101:7cff1c4259d7 33
Kojto 101:7cff1c4259d7 34 #ifndef _MXC_CLKMAN_REGS_H_
Kojto 101:7cff1c4259d7 35 #define _MXC_CLKMAN_REGS_H_
Kojto 101:7cff1c4259d7 36
Kojto 101:7cff1c4259d7 37 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 38 extern "C" {
Kojto 101:7cff1c4259d7 39 #endif
Kojto 101:7cff1c4259d7 40
Kojto 101:7cff1c4259d7 41 #include <stdint.h>
Kojto 101:7cff1c4259d7 42
Kojto 101:7cff1c4259d7 43 /**
Kojto 101:7cff1c4259d7 44 * @file clkman_regs.h
Kojto 101:7cff1c4259d7 45 * @addtogroup clkman CLKMAN
Kojto 101:7cff1c4259d7 46 * @{
Kojto 101:7cff1c4259d7 47 */
Kojto 101:7cff1c4259d7 48
Kojto 101:7cff1c4259d7 49 /**
Kojto 101:7cff1c4259d7 50 * @brief Defines clock input selections for the phase locked loop.
Kojto 101:7cff1c4259d7 51 */
Kojto 101:7cff1c4259d7 52 typedef enum {
Kojto 101:7cff1c4259d7 53 /** Input select for high frequency crystal oscillator */
Kojto 101:7cff1c4259d7 54 MXC_E_CLKMAN_PLL_INPUT_SELECT_HFX = 0,
Kojto 101:7cff1c4259d7 55 /** Input select for 24MHz ring oscillator */
Kojto 101:7cff1c4259d7 56 MXC_E_CLKMAN_PLL_INPUT_SELECT_24MHZ_RO,
Kojto 101:7cff1c4259d7 57 } mxc_clkman_pll_input_select_t;
Kojto 101:7cff1c4259d7 58
Kojto 101:7cff1c4259d7 59 /**
Kojto 101:7cff1c4259d7 60 * @brief Defines clock input frequency for the phase locked loop.
Kojto 101:7cff1c4259d7 61 */
Kojto 101:7cff1c4259d7 62 typedef enum {
Kojto 101:7cff1c4259d7 63 /** Input frequency of 24MHz */
Kojto 101:7cff1c4259d7 64 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_24MHZ = 0,
Kojto 101:7cff1c4259d7 65 /** Input frequency of 12MHz */
Kojto 101:7cff1c4259d7 66 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_12MHZ,
Kojto 101:7cff1c4259d7 67 /** Input frequency of 8MHz */
Kojto 101:7cff1c4259d7 68 MXC_E_CLKMAN_PLL_DIVISOR_SELECT_8MHZ,
Kojto 101:7cff1c4259d7 69 } mxc_clkman_pll_divisor_select_t;
Kojto 101:7cff1c4259d7 70
Kojto 101:7cff1c4259d7 71 /**
Kojto 101:7cff1c4259d7 72 * @brief Defines terminal count for PLL stable.
Kojto 101:7cff1c4259d7 73 */
Kojto 101:7cff1c4259d7 74 typedef enum {
Kojto 101:7cff1c4259d7 75 /** Clock stable after 2^8 = 256 clock cycles */
Kojto 101:7cff1c4259d7 76 MXC_E_CLKMAN_STABILITY_COUNT_2_8_CLKS = 0,
Kojto 101:7cff1c4259d7 77 /** Clock stable after 2^9 = 512 clock cycles */
Kojto 101:7cff1c4259d7 78 MXC_E_CLKMAN_STABILITY_COUNT_2_9_CLKS,
Kojto 101:7cff1c4259d7 79 /** Clock stable after 2^10 = 1024 clock cycles */
Kojto 101:7cff1c4259d7 80 MXC_E_CLKMAN_STABILITY_COUNT_2_10_CLKS,
Kojto 101:7cff1c4259d7 81 /** Clock stable after 2^11 = 2048 clock cycles */
Kojto 101:7cff1c4259d7 82 MXC_E_CLKMAN_STABILITY_COUNT_2_11_CLKS,
Kojto 101:7cff1c4259d7 83 /** Clock stable after 2^12 = 4096 clock cycles */
Kojto 101:7cff1c4259d7 84 MXC_E_CLKMAN_STABILITY_COUNT_2_12_CLKS,
Kojto 101:7cff1c4259d7 85 /** Clock stable after 2^13 = 8192 clock cycles */
Kojto 101:7cff1c4259d7 86 MXC_E_CLKMAN_STABILITY_COUNT_2_13_CLKS,
Kojto 101:7cff1c4259d7 87 /** Clock stable after 2^14 = 16384 clock cycles */
Kojto 101:7cff1c4259d7 88 MXC_E_CLKMAN_STABILITY_COUNT_2_14_CLKS,
Kojto 101:7cff1c4259d7 89 /** Clock stable after 2^15 = 32768 clock cycles */
Kojto 101:7cff1c4259d7 90 MXC_E_CLKMAN_STABILITY_COUNT_2_15_CLKS,
Kojto 101:7cff1c4259d7 91 /** Clock stable after 2^16 = 65536 clock cycles */
Kojto 101:7cff1c4259d7 92 MXC_E_CLKMAN_STABILITY_COUNT_2_16_CLKS,
Kojto 101:7cff1c4259d7 93 /** Clock stable after 2^17 = 131072 clock cycles */
Kojto 101:7cff1c4259d7 94 MXC_E_CLKMAN_STABILITY_COUNT_2_17_CLKS,
Kojto 101:7cff1c4259d7 95 /** Clock stable after 2^18 = 262144 clock cycles */
Kojto 101:7cff1c4259d7 96 MXC_E_CLKMAN_STABILITY_COUNT_2_18_CLKS,
Kojto 101:7cff1c4259d7 97 /** Clock stable after 2^19 = 524288 clock cycles */
Kojto 101:7cff1c4259d7 98 MXC_E_CLKMAN_STABILITY_COUNT_2_19_CLKS,
Kojto 101:7cff1c4259d7 99 /** Clock stable after 2^20 = 1048576 clock cycles */
Kojto 101:7cff1c4259d7 100 MXC_E_CLKMAN_STABILITY_COUNT_2_20_CLKS,
Kojto 101:7cff1c4259d7 101 /** Clock stable after 2^21 = 2097152 clock cycles */
Kojto 101:7cff1c4259d7 102 MXC_E_CLKMAN_STABILITY_COUNT_2_21_CLKS,
Kojto 101:7cff1c4259d7 103 /** Clock stable after 2^22 = 4194304 clock cycles */
Kojto 101:7cff1c4259d7 104 MXC_E_CLKMAN_STABILITY_COUNT_2_22_CLKS,
Kojto 101:7cff1c4259d7 105 /** Clock stable after 2^23 = 8388608 clock cycles */
Kojto 101:7cff1c4259d7 106 MXC_E_CLKMAN_STABILITY_COUNT_2_23_CLKS
Kojto 101:7cff1c4259d7 107 } mxc_clkman_stability_count_t;
Kojto 101:7cff1c4259d7 108
Kojto 101:7cff1c4259d7 109 /**
Kojto 101:7cff1c4259d7 110 * @brief Defines clock source selections for system clock.
Kojto 101:7cff1c4259d7 111 */
Kojto 101:7cff1c4259d7 112 typedef enum {
Kojto 101:7cff1c4259d7 113 /** Clock select for 24MHz ring oscillator divided by 8 (3MHz) */
Kojto 101:7cff1c4259d7 114 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO_DIV_8 = 0,
Kojto 101:7cff1c4259d7 115 /** Clock select for 24MHz ring oscillator */
Kojto 101:7cff1c4259d7 116 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_24MHZ_RO,
Kojto 101:7cff1c4259d7 117 /** Clock select for high frequency crystal oscillator */
Kojto 101:7cff1c4259d7 118 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_HFX,
Kojto 101:7cff1c4259d7 119 /** Clock select for 48MHz phase locked loop output divided by 2 (24MHz) */
Kojto 101:7cff1c4259d7 120 MXC_E_CLKMAN_SYSTEM_SOURCE_SELECT_PLL_48MHZ_DIV_2
Kojto 101:7cff1c4259d7 121 } mxc_clkman_system_source_select_t;
Kojto 101:7cff1c4259d7 122
Kojto 101:7cff1c4259d7 123 /**
Kojto 101:7cff1c4259d7 124 * @brief Defines clock source selections for analog to digital converter clock.
Kojto 101:7cff1c4259d7 125 */
Kojto 101:7cff1c4259d7 126 typedef enum {
Kojto 101:7cff1c4259d7 127 /** Clock select for system clock frequency */
Kojto 101:7cff1c4259d7 128 MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM = 0,
Kojto 101:7cff1c4259d7 129 /** Clock select for 8MHz phase locked loop output */
Kojto 101:7cff1c4259d7 130 MXC_E_CLKMAN_ADC_SOURCE_SELECT_PLL_8MHZ,
Kojto 101:7cff1c4259d7 131 /** Clock select for high frequency crystal oscillator */
Kojto 101:7cff1c4259d7 132 MXC_E_CLKMAN_ADC_SOURCE_SELECT_HFX,
Kojto 101:7cff1c4259d7 133 /** Clock select for 24MHz ring oscillator */
Kojto 101:7cff1c4259d7 134 MXC_E_CLKMAN_ADC_SOURCE_SELECT_24MHZ_RO,
Kojto 101:7cff1c4259d7 135 } mxc_clkman_adc_source_select_t;
Kojto 101:7cff1c4259d7 136
Kojto 101:7cff1c4259d7 137 /**
Kojto 101:7cff1c4259d7 138 * @brief Defines clock source selections for watchdog timer clock.
Kojto 101:7cff1c4259d7 139 */
Kojto 101:7cff1c4259d7 140 typedef enum {
Kojto 101:7cff1c4259d7 141 /** Clock select for system clock frequency */
Kojto 101:7cff1c4259d7 142 MXC_E_CLKMAN_WDT_SOURCE_SELECT_SYSTEM = 0,
Kojto 101:7cff1c4259d7 143 /** Clock select for 8MHz phase locked loop output */
Kojto 101:7cff1c4259d7 144 MXC_E_CLKMAN_WDT_SOURCE_SELECT_RTC,
Kojto 101:7cff1c4259d7 145 /** Clock select for high frequency crystal oscillator */
Kojto 101:7cff1c4259d7 146 MXC_E_CLKMAN_WDT_SOURCE_SELECT_24MHZ_RO,
Kojto 101:7cff1c4259d7 147 /** Clock select for 24MHz ring oscillator */
Kojto 101:7cff1c4259d7 148 MXC_E_CLKMAN_WDT_SOURCE_SELECT_NANO,
Kojto 101:7cff1c4259d7 149 } mxc_clkman_wdt_source_select_t;
Kojto 101:7cff1c4259d7 150
Kojto 101:7cff1c4259d7 151 /**
Kojto 101:7cff1c4259d7 152 * @brief Defines clock scales for various clocks.
Kojto 101:7cff1c4259d7 153 */
Kojto 101:7cff1c4259d7 154 typedef enum {
Kojto 101:7cff1c4259d7 155 /** Clock disabled */
Kojto 101:7cff1c4259d7 156 MXC_E_CLKMAN_CLK_SCALE_DISABLED = 0,
Kojto 101:7cff1c4259d7 157 /** Clock enabled */
Kojto 101:7cff1c4259d7 158 MXC_E_CLKMAN_CLK_SCALE_ENABLED,
Kojto 101:7cff1c4259d7 159 /** Clock scale for dividing by 2 */
Kojto 101:7cff1c4259d7 160 MXC_E_CLKMAN_CLK_SCALE_DIV_2,
Kojto 101:7cff1c4259d7 161 /** Clock scale for dividing by 4 */
Kojto 101:7cff1c4259d7 162 MXC_E_CLKMAN_CLK_SCALE_DIV_4,
Kojto 101:7cff1c4259d7 163 /** Clock scale for dividing by 8 */
Kojto 101:7cff1c4259d7 164 MXC_E_CLKMAN_CLK_SCALE_DIV_8,
Kojto 101:7cff1c4259d7 165 /** Clock scale for dividing by 16 */
Kojto 101:7cff1c4259d7 166 MXC_E_CLKMAN_CLK_SCALE_DIV_16,
Kojto 101:7cff1c4259d7 167 /** Clock scale for dividing by 32 */
Kojto 101:7cff1c4259d7 168 MXC_E_CLKMAN_CLK_SCALE_DIV_32,
Kojto 101:7cff1c4259d7 169 /** Clock scale for dividing by 64 */
Kojto 101:7cff1c4259d7 170 MXC_E_CLKMAN_CLK_SCALE_DIV_64,
Kojto 101:7cff1c4259d7 171 /** Clock scale for dividing by 128 */
Kojto 101:7cff1c4259d7 172 MXC_E_CLKMAN_CLK_SCALE_DIV_128,
Kojto 101:7cff1c4259d7 173 /** Clock scale for dividing by 256 */
Kojto 101:7cff1c4259d7 174 MXC_E_CLKMAN_CLK_SCALE_DIV_256
Kojto 101:7cff1c4259d7 175 } mxc_clkman_clk_scale_t;
Kojto 101:7cff1c4259d7 176
Kojto 101:7cff1c4259d7 177 /**
Kojto 101:7cff1c4259d7 178 * @brief Defines Setting of the Clock Gates .
Kojto 101:7cff1c4259d7 179 */
Kojto 101:7cff1c4259d7 180 typedef enum {
Kojto 101:7cff1c4259d7 181 /** Clock Gater is Off */
Kojto 101:7cff1c4259d7 182 MXC_E_CLKMAN_CLK_GATE_OFF = 0,
Kojto 101:7cff1c4259d7 183 /** Clock Gater is Dynamic */
Kojto 101:7cff1c4259d7 184 MXC_E_CLKMAN_CLK_GATE_DYNAMIC,
Kojto 101:7cff1c4259d7 185 /** Clock Gater is On */
Kojto 101:7cff1c4259d7 186 MXC_E_CLKMAN_CLK_GATE_ON
Kojto 101:7cff1c4259d7 187 } mxc_clkman_clk_gate_t;
Kojto 101:7cff1c4259d7 188
Kojto 101:7cff1c4259d7 189 /* Offset Register Description
Kojto 101:7cff1c4259d7 190 ====== ===================================================================== */
Kojto 101:7cff1c4259d7 191 typedef struct {
Kojto 101:7cff1c4259d7 192 __IO uint32_t clk_config; /* 0x0000 System Clock Configuration */
Kojto 101:7cff1c4259d7 193 __IO uint32_t clk_ctrl; /* 0x0004 System Clock Controls */
Kojto 101:7cff1c4259d7 194 __IO uint32_t intfl; /* 0x0008 Interrupt Flags */
Kojto 101:7cff1c4259d7 195 __IO uint32_t inten; /* 0x000C Interrupt Enable/Disable Controls */
Kojto 101:7cff1c4259d7 196 __IO uint32_t trim_calc; /* 0x0010 Trim Calculation Controls */
Kojto 101:7cff1c4259d7 197 __I uint32_t rsv0014[4]; /* 0x0014 */
Kojto 101:7cff1c4259d7 198 __IO uint32_t i2c_timer_ctrl; /* 0x0024 I2C Timer Control */
Kojto 101:7cff1c4259d7 199 __I uint32_t rsv0028[6]; /* 0x0028 */
Kojto 101:7cff1c4259d7 200 __IO uint32_t clk_ctrl_0_system; /* 0x0040 Control Settings for CLK0 - System Clock */
Kojto 101:7cff1c4259d7 201 __IO uint32_t clk_ctrl_1_gpio; /* 0x0044 Control Settings for CLK1 - GPIO Module Clock */
Kojto 101:7cff1c4259d7 202 __IO uint32_t clk_ctrl_2_pt; /* 0x0048 Control Settings for CLK2 - Pulse Train Module Clock */
Kojto 101:7cff1c4259d7 203 __IO uint32_t clk_ctrl_3_spi0; /* 0x004C Control Settings for CLK3 - SPI0 Master Clock */
Kojto 101:7cff1c4259d7 204 __IO uint32_t clk_ctrl_4_spi1; /* 0x0050 Control Settings for CLK4 - SPI1 Master Clock */
Kojto 101:7cff1c4259d7 205 __IO uint32_t clk_ctrl_5_spi2; /* 0x0054 Control Settings for CLK5 - SPI2 Master Clock */
Kojto 101:7cff1c4259d7 206 __IO uint32_t clk_ctrl_6_i2cm; /* 0x0058 Control Settings for CLK6 - Clock for all I2C Masters */
Kojto 101:7cff1c4259d7 207 __IO uint32_t clk_ctrl_7_i2cs; /* 0x005C Control Settings for CLK7 - I2C Slave Clock */
Kojto 101:7cff1c4259d7 208 __IO uint32_t clk_ctrl_8_lcd_chpump; /* 0x0060 Control Settings for CLK8 - LCD Charge Pump Clock */
Kojto 101:7cff1c4259d7 209 __IO uint32_t clk_ctrl_9_puf; /* 0x0064 Control Settings for CLK9 - PUF Clock */
Kojto 101:7cff1c4259d7 210 __IO uint32_t clk_ctrl_10_prng; /* 0x0068 Control Settings for CLK10 - PRNG Clock */
Kojto 101:7cff1c4259d7 211 __IO uint32_t clk_ctrl_11_wdt0; /* 0x006C Control Settings for CLK11 - Watchdog Timer 0 ScaledSysClk */
Kojto 101:7cff1c4259d7 212 __IO uint32_t clk_ctrl_12_wdt1; /* 0x0070 Control Settings for CLK12 - Watchdog Timer 1 ScaledSysClk */
Kojto 101:7cff1c4259d7 213 __IO uint32_t clk_ctrl_13_rtc_int_sync; /* 0x0074 Control Settings for CLK13 - RTC Interrupt Sync Clock */
Kojto 101:7cff1c4259d7 214 __IO uint32_t clk_ctrl_14_dac0; /* 0x0078 Control Settings for CLK14 - 12-bit DAC 0 Clock */
Kojto 101:7cff1c4259d7 215 __IO uint32_t clk_ctrl_15_dac1; /* 0x007C Control Settings for CLK15 - 12-bit DAC 1 Clock */
Kojto 101:7cff1c4259d7 216 __IO uint32_t clk_ctrl_16_dac2; /* 0x0080 Control Settings for CLK16 - 8-bit DAC 0 Clock */
Kojto 101:7cff1c4259d7 217 __IO uint32_t clk_ctrl_17_dac3; /* 0x0084 Control Settings for CLK17 - 8-bit DAC 1 Clock */
Kojto 101:7cff1c4259d7 218 __I uint32_t rsv0088[30]; /* 0x0088 */
Kojto 101:7cff1c4259d7 219 __IO uint32_t crypt_clk_ctrl_0_aes; /* 0x0100 Control Settings for Crypto Clock 0 - AES */
Kojto 101:7cff1c4259d7 220 __IO uint32_t crypt_clk_ctrl_1_maa; /* 0x0104 Control Settings for Crypto Clock 1 - MAA */
Kojto 101:7cff1c4259d7 221 __IO uint32_t crypt_clk_ctrl_2_prng; /* 0x0108 Control Settings for Crypto Clock 2 - PRNG */
Kojto 101:7cff1c4259d7 222 __I uint32_t rsv010C[13]; /* 0x010C */
Kojto 101:7cff1c4259d7 223 __IO uint32_t clk_gate_ctrl0; /* 0x0140 Dynamic Clock Gating Control Register 0 */
Kojto 101:7cff1c4259d7 224 __IO uint32_t clk_gate_ctrl1; /* 0x0144 Dynamic Clock Gating Control Register 1 */
Kojto 101:7cff1c4259d7 225 __IO uint32_t clk_gate_ctrl2; /* 0x0148 Dynamic Clock Gating Control Register 2 */
Kojto 101:7cff1c4259d7 226 } mxc_clkman_regs_t;
Kojto 101:7cff1c4259d7 227
Kojto 101:7cff1c4259d7 228 /*
Kojto 101:7cff1c4259d7 229 Register offsets for module CLKMAN.
Kojto 101:7cff1c4259d7 230 */
Kojto 101:7cff1c4259d7 231 #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL)
Kojto 101:7cff1c4259d7 232 #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL)
Kojto 101:7cff1c4259d7 233 #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL)
Kojto 101:7cff1c4259d7 234 #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL)
Kojto 101:7cff1c4259d7 235 #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL)
Kojto 101:7cff1c4259d7 236 #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000024UL)
Kojto 101:7cff1c4259d7 237 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_0_SYSTEM ((uint32_t)0x00000040UL)
Kojto 101:7cff1c4259d7 238 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_1_GPIO ((uint32_t)0x00000044UL)
Kojto 101:7cff1c4259d7 239 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_2_PT ((uint32_t)0x00000048UL)
Kojto 101:7cff1c4259d7 240 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_3_SPI0 ((uint32_t)0x0000004CUL)
Kojto 101:7cff1c4259d7 241 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_4_SPI1 ((uint32_t)0x00000050UL)
Kojto 101:7cff1c4259d7 242 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_5_SPI2 ((uint32_t)0x00000054UL)
Kojto 101:7cff1c4259d7 243 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_6_I2CM ((uint32_t)0x00000058UL)
Kojto 101:7cff1c4259d7 244 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_7_I2CS ((uint32_t)0x0000005CUL)
Kojto 101:7cff1c4259d7 245 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_8_LCD_CHPUMP ((uint32_t)0x00000060UL)
Kojto 101:7cff1c4259d7 246 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_9_PUF ((uint32_t)0x00000064UL)
Kojto 101:7cff1c4259d7 247 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_10_PRNG ((uint32_t)0x00000068UL)
Kojto 101:7cff1c4259d7 248 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_11_WDT0 ((uint32_t)0x0000006CUL)
Kojto 101:7cff1c4259d7 249 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_12_WDT1 ((uint32_t)0x00000070UL)
Kojto 101:7cff1c4259d7 250 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_13_RTC_INT_SYNC ((uint32_t)0x00000074UL)
Kojto 101:7cff1c4259d7 251 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_14_DAC0 ((uint32_t)0x00000078UL)
Kojto 101:7cff1c4259d7 252 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_15_DAC1 ((uint32_t)0x0000007CUL)
Kojto 101:7cff1c4259d7 253 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_16_DAC2 ((uint32_t)0x00000080UL)
Kojto 101:7cff1c4259d7 254 #define MXC_R_CLKMAN_OFFS_CLK_CTRL_17_DAC3 ((uint32_t)0x00000084UL)
Kojto 101:7cff1c4259d7 255 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL)
Kojto 101:7cff1c4259d7 256 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL)
Kojto 101:7cff1c4259d7 257 #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL)
Kojto 101:7cff1c4259d7 258 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL)
Kojto 101:7cff1c4259d7 259 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL)
Kojto 101:7cff1c4259d7 260 #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL)
Kojto 101:7cff1c4259d7 261
Kojto 101:7cff1c4259d7 262 /*
Kojto 101:7cff1c4259d7 263 Field positions and masks for module CLKMAN.
Kojto 101:7cff1c4259d7 264 */
Kojto 101:7cff1c4259d7 265 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS 0
Kojto 101:7cff1c4259d7 266 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_ENABLE_POS))
Kojto 101:7cff1c4259d7 267 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS 1
Kojto 101:7cff1c4259d7 268 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_BYPASS_POS))
Kojto 101:7cff1c4259d7 269 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS 2
Kojto 101:7cff1c4259d7 270 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_TEST_ENABLE_POS))
Kojto 101:7cff1c4259d7 271 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS 4
Kojto 101:7cff1c4259d7 272 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST ((uint32_t)(0x0000001FUL << MXC_F_CLKMAN_CLK_CONFIG_HFX_GM_ADJUST_POS))
Kojto 101:7cff1c4259d7 273 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS 9
Kojto 101:7cff1c4259d7 274 #define MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL ((uint32_t)(0x00000007UL << MXC_F_CLKMAN_CLK_CONFIG_HFX_DC_CONTROL_POS))
Kojto 101:7cff1c4259d7 275 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS 12
Kojto 101:7cff1c4259d7 276 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE_POS))
Kojto 101:7cff1c4259d7 277 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS 13
Kojto 101:7cff1c4259d7 278 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_RESET_N_POS))
Kojto 101:7cff1c4259d7 279 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS 14
Kojto 101:7cff1c4259d7 280 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_INPUT_SELECT_POS))
Kojto 101:7cff1c4259d7 281 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS 16
Kojto 101:7cff1c4259d7 282 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_DIVISOR_SELECT_POS))
Kojto 101:7cff1c4259d7 283 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS 18
Kojto 101:7cff1c4259d7 284 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_8MHZ_ENABLE_POS))
Kojto 101:7cff1c4259d7 285 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS 19
Kojto 101:7cff1c4259d7 286 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_PLL_BYPASS_POS))
Kojto 101:7cff1c4259d7 287 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS 20
Kojto 101:7cff1c4259d7 288 #define MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_PLL_STABILITY_COUNT_POS))
Kojto 101:7cff1c4259d7 289 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 24
Kojto 101:7cff1c4259d7 290 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS))
Kojto 101:7cff1c4259d7 291 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS 25
Kojto 101:7cff1c4259d7 292 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_RESET_N_POS))
Kojto 101:7cff1c4259d7 293 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 28
Kojto 101:7cff1c4259d7 294 #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS))
Kojto 101:7cff1c4259d7 295
Kojto 101:7cff1c4259d7 296 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 1
Kojto 101:7cff1c4259d7 297 #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS))
Kojto 101:7cff1c4259d7 298 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS 3
Kojto 101:7cff1c4259d7 299 #define MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_AUTO_CLK_DISABLE_POS))
Kojto 101:7cff1c4259d7 300 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS 4
Kojto 101:7cff1c4259d7 301 #define MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N_POS))
Kojto 101:7cff1c4259d7 302 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS 8
Kojto 101:7cff1c4259d7 303 #define MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N_POS))
Kojto 101:7cff1c4259d7 304 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS 9
Kojto 101:7cff1c4259d7 305 #define MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS))
Kojto 101:7cff1c4259d7 306 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS 12
Kojto 101:7cff1c4259d7 307 #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_GATE_N_POS))
Kojto 101:7cff1c4259d7 308 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS 16
Kojto 101:7cff1c4259d7 309 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_GATE_N_POS))
Kojto 101:7cff1c4259d7 310 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS 17
Kojto 101:7cff1c4259d7 311 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG0_SOURCE_SELECT_POS))
Kojto 101:7cff1c4259d7 312 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS 20
Kojto 101:7cff1c4259d7 313 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_GATE_N_POS))
Kojto 101:7cff1c4259d7 314 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS 21
Kojto 101:7cff1c4259d7 315 #define MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WATCHDOG1_SOURCE_SELECT_POS))
Kojto 101:7cff1c4259d7 316 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 24
Kojto 101:7cff1c4259d7 317 #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS))
Kojto 101:7cff1c4259d7 318
Kojto 101:7cff1c4259d7 319 #define MXC_F_CLKMAN_INTFL_RING_STABLE_POS 0
Kojto 101:7cff1c4259d7 320 #define MXC_F_CLKMAN_INTFL_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_RING_STABLE_POS))
Kojto 101:7cff1c4259d7 321 #define MXC_F_CLKMAN_INTFL_PLL_STABLE_POS 1
Kojto 101:7cff1c4259d7 322 #define MXC_F_CLKMAN_INTFL_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_PLL_STABLE_POS))
Kojto 101:7cff1c4259d7 323 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 2
Kojto 101:7cff1c4259d7 324 #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS))
Kojto 101:7cff1c4259d7 325
Kojto 101:7cff1c4259d7 326 #define MXC_F_CLKMAN_INTEN_RING_STABLE_POS 0
Kojto 101:7cff1c4259d7 327 #define MXC_F_CLKMAN_INTEN_RING_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_RING_STABLE_POS))
Kojto 101:7cff1c4259d7 328 #define MXC_F_CLKMAN_INTEN_PLL_STABLE_POS 1
Kojto 101:7cff1c4259d7 329 #define MXC_F_CLKMAN_INTEN_PLL_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_PLL_STABLE_POS))
Kojto 101:7cff1c4259d7 330 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 2
Kojto 101:7cff1c4259d7 331 #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS))
Kojto 101:7cff1c4259d7 332
Kojto 101:7cff1c4259d7 333 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0
Kojto 101:7cff1c4259d7 334 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS))
Kojto 101:7cff1c4259d7 335 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1
Kojto 101:7cff1c4259d7 336 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS))
Kojto 101:7cff1c4259d7 337 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2
Kojto 101:7cff1c4259d7 338 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS))
Kojto 101:7cff1c4259d7 339 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3
Kojto 101:7cff1c4259d7 340 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS))
Kojto 101:7cff1c4259d7 341 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16
Kojto 101:7cff1c4259d7 342 #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS))
Kojto 101:7cff1c4259d7 343
Kojto 101:7cff1c4259d7 344 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0
Kojto 101:7cff1c4259d7 345 #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS))
Kojto 101:7cff1c4259d7 346
Kojto 101:7cff1c4259d7 347 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 348 #define MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_0_SYSTEM_SYS_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 349
Kojto 101:7cff1c4259d7 350 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 351 #define MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_1_GPIO_GPIO_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 352
Kojto 101:7cff1c4259d7 353 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 354 #define MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_2_PT_PULSE_TRAIN_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 355
Kojto 101:7cff1c4259d7 356 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 357 #define MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_3_SPI0_SPI0_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 358
Kojto 101:7cff1c4259d7 359 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 360 #define MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_4_SPI1_SPI1_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 361
Kojto 101:7cff1c4259d7 362 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 363 #define MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_5_SPI2_SPI2_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 364
Kojto 101:7cff1c4259d7 365 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 366 #define MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_6_I2CM_I2CM_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 367
Kojto 101:7cff1c4259d7 368 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 369 #define MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_7_I2CS_I2CS_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 370
Kojto 101:7cff1c4259d7 371 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 372 #define MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_8_LCD_CHPUMP_LCD_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 373
Kojto 101:7cff1c4259d7 374 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 375 #define MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_9_PUF_PUF_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 376
Kojto 101:7cff1c4259d7 377 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 378 #define MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_10_PRNG_PRNG_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 379
Kojto 101:7cff1c4259d7 380 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 381 #define MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_11_WDT0_WATCHDOG0_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 382
Kojto 101:7cff1c4259d7 383 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 384 #define MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_12_WDT1_WATCHDOG1_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 385
Kojto 101:7cff1c4259d7 386 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 387 #define MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_13_RTC_INT_SYNC_RTC_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 388
Kojto 101:7cff1c4259d7 389 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 390 #define MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_14_DAC0_DAC0_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 391
Kojto 101:7cff1c4259d7 392 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 393 #define MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_15_DAC1_DAC1_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 394
Kojto 101:7cff1c4259d7 395 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 396 #define MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_16_DAC2_DAC2_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 397
Kojto 101:7cff1c4259d7 398 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 399 #define MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CTRL_17_DAC3_DAC3_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 400
Kojto 101:7cff1c4259d7 401 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 402 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 403
Kojto 101:7cff1c4259d7 404 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 405 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_UMAA_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 406
Kojto 101:7cff1c4259d7 407 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0
Kojto 101:7cff1c4259d7 408 #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS))
Kojto 101:7cff1c4259d7 409
Kojto 101:7cff1c4259d7 410 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS 0
Kojto 101:7cff1c4259d7 411 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM3_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 412 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS 2
Kojto 101:7cff1c4259d7 413 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSBUS_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 414 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4
Kojto 101:7cff1c4259d7 415 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 416 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6
Kojto 101:7cff1c4259d7 417 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 418 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8
Kojto 101:7cff1c4259d7 419 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 420 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10
Kojto 101:7cff1c4259d7 421 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 422 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12
Kojto 101:7cff1c4259d7 423 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 424 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS 14
Kojto 101:7cff1c4259d7 425 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 426 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS 16
Kojto 101:7cff1c4259d7 427 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_UART1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 428 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS 18
Kojto 101:7cff1c4259d7 429 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 430 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS 20
Kojto 101:7cff1c4259d7 431 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 432 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS 22
Kojto 101:7cff1c4259d7 433 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER2_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 434 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS 24
Kojto 101:7cff1c4259d7 435 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TIMER3_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 436 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 26
Kojto 101:7cff1c4259d7 437 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 438 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS 28
Kojto 101:7cff1c4259d7 439 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 440 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 30
Kojto 101:7cff1c4259d7 441 #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 442
Kojto 101:7cff1c4259d7 443 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS 0
Kojto 101:7cff1c4259d7 444 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TESTACC_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 445 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS 2
Kojto 101:7cff1c4259d7 446 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_ADC_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 447 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS 4
Kojto 101:7cff1c4259d7 448 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 449 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS 6
Kojto 101:7cff1c4259d7 450 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC12_1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 451 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS 8
Kojto 101:7cff1c4259d7 452 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 453 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS 10
Kojto 101:7cff1c4259d7 454 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_DAC8_1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 455 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS 12
Kojto 101:7cff1c4259d7 456 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PMU_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 457 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS 14
Kojto 101:7cff1c4259d7 458 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_LCD_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 459 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 16
Kojto 101:7cff1c4259d7 460 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 461 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 18
Kojto 101:7cff1c4259d7 462 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 463 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS 20
Kojto 101:7cff1c4259d7 464 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 465 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS 22
Kojto 101:7cff1c4259d7 466 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 467 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS 24
Kojto 101:7cff1c4259d7 468 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_SPI2_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 469 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26
Kojto 101:7cff1c4259d7 470 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 471 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28
Kojto 101:7cff1c4259d7 472 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 473 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS 30
Kojto 101:7cff1c4259d7 474 #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CS_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 475
Kojto 101:7cff1c4259d7 476 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS 0
Kojto 101:7cff1c4259d7 477 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_CRC_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 478 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS 2
Kojto 101:7cff1c4259d7 479 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_TPU_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 480 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS 4
Kojto 101:7cff1c4259d7 481 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SSBMUX_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 482 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS 6
Kojto 101:7cff1c4259d7 483 #define MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_PAD_CLK_GATER_POS))
Kojto 101:7cff1c4259d7 484
Kojto 101:7cff1c4259d7 485 #ifdef __cplusplus
Kojto 101:7cff1c4259d7 486 }
Kojto 101:7cff1c4259d7 487 #endif
Kojto 101:7cff1c4259d7 488
Kojto 101:7cff1c4259d7 489 /**
Kojto 101:7cff1c4259d7 490 * @}
Kojto 101:7cff1c4259d7 491 */
Kojto 101:7cff1c4259d7 492
Kojto 101:7cff1c4259d7 493 #endif /* _MXC_CLKMAN_REGS_H_ */