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TARGET_ELMO_F411RE/stm32f4xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 116:c0f6e94411f5

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	108:34e6b704fe68	1	/**
Kojto	108:34e6b704fe68	2	******************************************************************************
Kojto	108:34e6b704fe68	3	* @file stm32f4xx_hal_rcc.h
Kojto	108:34e6b704fe68	4	* @author MCD Application Team
Kojto	110:165afa46840b	5	* @version V1.4.1
Kojto	110:165afa46840b	6	* @date 09-October-2015
Kojto	108:34e6b704fe68	7	* @brief Header file of RCC HAL module.
Kojto	108:34e6b704fe68	8	******************************************************************************
Kojto	108:34e6b704fe68	9	* @attention
Kojto	108:34e6b704fe68	10	*
Kojto	108:34e6b704fe68	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	108:34e6b704fe68	12	*
Kojto	108:34e6b704fe68	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	108:34e6b704fe68	14	* are permitted provided that the following conditions are met:
Kojto	108:34e6b704fe68	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	108:34e6b704fe68	16	* this list of conditions and the following disclaimer.
Kojto	108:34e6b704fe68	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	108:34e6b704fe68	18	* this list of conditions and the following disclaimer in the documentation
Kojto	108:34e6b704fe68	19	* and/or other materials provided with the distribution.
Kojto	108:34e6b704fe68	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	108:34e6b704fe68	21	* may be used to endorse or promote products derived from this software
Kojto	108:34e6b704fe68	22	* without specific prior written permission.
Kojto	108:34e6b704fe68	23	*
Kojto	108:34e6b704fe68	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	108:34e6b704fe68	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	108:34e6b704fe68	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	108:34e6b704fe68	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	108:34e6b704fe68	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	108:34e6b704fe68	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	108:34e6b704fe68	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	108:34e6b704fe68	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	108:34e6b704fe68	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	108:34e6b704fe68	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	108:34e6b704fe68	34	*
Kojto	108:34e6b704fe68	35	******************************************************************************
Kojto	108:34e6b704fe68	36	*/
Kojto	108:34e6b704fe68	37
Kojto	108:34e6b704fe68	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	108:34e6b704fe68	39	#ifndef __STM32F4xx_HAL_RCC_H
Kojto	108:34e6b704fe68	40	#define __STM32F4xx_HAL_RCC_H
Kojto	108:34e6b704fe68	41
Kojto	108:34e6b704fe68	42	#ifdef __cplusplus
Kojto	108:34e6b704fe68	43	extern "C" {
Kojto	108:34e6b704fe68	44	#endif
Kojto	108:34e6b704fe68	45
Kojto	108:34e6b704fe68	46	/* Includes ------------------------------------------------------------------*/
Kojto	108:34e6b704fe68	47	#include "stm32f4xx_hal_def.h"
Kojto	108:34e6b704fe68	48
Kojto	108:34e6b704fe68	49	/* Include RCC HAL Extended module */
Kojto	108:34e6b704fe68	50	/* (include on top of file since RCC structures are defined in extended file) */
Kojto	108:34e6b704fe68	51	#include "stm32f4xx_hal_rcc_ex.h"
Kojto	108:34e6b704fe68	52
Kojto	108:34e6b704fe68	53	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	108:34e6b704fe68	54	* @{
Kojto	108:34e6b704fe68	55	*/
Kojto	108:34e6b704fe68	56
Kojto	108:34e6b704fe68	57	/** @addtogroup RCC
Kojto	108:34e6b704fe68	58	* @{
Kojto	108:34e6b704fe68	59	*/
Kojto	108:34e6b704fe68	60
Kojto	108:34e6b704fe68	61	/* Exported types ------------------------------------------------------------*/
Kojto	108:34e6b704fe68	62	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	108:34e6b704fe68	63	* @{
Kojto	108:34e6b704fe68	64	*/
Kojto	108:34e6b704fe68	65
Kojto	108:34e6b704fe68	66	/**
Kojto	108:34e6b704fe68	67	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	108:34e6b704fe68	68	*/
Kojto	108:34e6b704fe68	69	typedef struct
Kojto	108:34e6b704fe68	70	{
Kojto	108:34e6b704fe68	71	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	108:34e6b704fe68	72	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	108:34e6b704fe68	73
Kojto	108:34e6b704fe68	74	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	108:34e6b704fe68	75	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	108:34e6b704fe68	76
Kojto	108:34e6b704fe68	77	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	108:34e6b704fe68	78	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	108:34e6b704fe68	79
Kojto	108:34e6b704fe68	80	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	108:34e6b704fe68	81	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	108:34e6b704fe68	82
Kojto	108:34e6b704fe68	83	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	108:34e6b704fe68	84	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	108:34e6b704fe68	85
Kojto	108:34e6b704fe68	86	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	108:34e6b704fe68	87	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	108:34e6b704fe68	88
Kojto	108:34e6b704fe68	89	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	108:34e6b704fe68	90
Kojto	108:34e6b704fe68	91	}RCC_OscInitTypeDef;
Kojto	108:34e6b704fe68	92
Kojto	108:34e6b704fe68	93	/**
Kojto	108:34e6b704fe68	94	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	108:34e6b704fe68	95	*/
Kojto	108:34e6b704fe68	96	typedef struct
Kojto	108:34e6b704fe68	97	{
Kojto	108:34e6b704fe68	98	uint32_t ClockType; /*!< The clock to be configured.
Kojto	108:34e6b704fe68	99	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	108:34e6b704fe68	100
Kojto	108:34e6b704fe68	101	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	108:34e6b704fe68	102	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	108:34e6b704fe68	103
Kojto	108:34e6b704fe68	104	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	108:34e6b704fe68	105	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	108:34e6b704fe68	106
Kojto	108:34e6b704fe68	107	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	108:34e6b704fe68	108	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	108:34e6b704fe68	109
Kojto	108:34e6b704fe68	110	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	108:34e6b704fe68	111	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	108:34e6b704fe68	112
Kojto	108:34e6b704fe68	113	}RCC_ClkInitTypeDef;
Kojto	108:34e6b704fe68	114
Kojto	108:34e6b704fe68	115	/**
Kojto	108:34e6b704fe68	116	* @}
Kojto	108:34e6b704fe68	117	*/
Kojto	108:34e6b704fe68	118
Kojto	108:34e6b704fe68	119	/* Exported constants --------------------------------------------------------*/
Kojto	108:34e6b704fe68	120	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	108:34e6b704fe68	121	* @{
Kojto	108:34e6b704fe68	122	*/
Kojto	108:34e6b704fe68	123
Kojto	108:34e6b704fe68	124	/** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto	108:34e6b704fe68	125	* @{
Kojto	108:34e6b704fe68	126	*/
Kojto	108:34e6b704fe68	127	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	108:34e6b704fe68	128	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	108:34e6b704fe68	129	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	108:34e6b704fe68	130	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	108:34e6b704fe68	131	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	108:34e6b704fe68	132	/**
Kojto	108:34e6b704fe68	133	* @}
Kojto	108:34e6b704fe68	134	*/
Kojto	108:34e6b704fe68	135
Kojto	108:34e6b704fe68	136	/** @defgroup RCC_HSE_Config HSE Config
Kojto	108:34e6b704fe68	137	* @{
Kojto	108:34e6b704fe68	138	*/
Kojto	108:34e6b704fe68	139	#define RCC_HSE_OFF ((uint8_t)0x00)
Kojto	108:34e6b704fe68	140	#define RCC_HSE_ON ((uint8_t)0x01)
Kojto	108:34e6b704fe68	141	#define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto	108:34e6b704fe68	142	/**
Kojto	108:34e6b704fe68	143	* @}
Kojto	108:34e6b704fe68	144	*/
Kojto	108:34e6b704fe68	145
Kojto	108:34e6b704fe68	146	/** @defgroup RCC_LSE_Config LSE Config
Kojto	108:34e6b704fe68	147	* @{
Kojto	108:34e6b704fe68	148	*/
Kojto	108:34e6b704fe68	149	#define RCC_LSE_OFF ((uint8_t)0x00)
Kojto	108:34e6b704fe68	150	#define RCC_LSE_ON ((uint8_t)0x01)
Kojto	108:34e6b704fe68	151	#define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto	108:34e6b704fe68	152	/**
Kojto	108:34e6b704fe68	153	* @}
Kojto	108:34e6b704fe68	154	*/
Kojto	108:34e6b704fe68	155
Kojto	108:34e6b704fe68	156	/** @defgroup RCC_HSI_Config HSI Config
Kojto	108:34e6b704fe68	157	* @{
Kojto	108:34e6b704fe68	158	*/
Kojto	108:34e6b704fe68	159	#define RCC_HSI_OFF ((uint8_t)0x00)
Kojto	108:34e6b704fe68	160	#define RCC_HSI_ON ((uint8_t)0x01)
Kojto	108:34e6b704fe68	161	/**
Kojto	108:34e6b704fe68	162	* @}
Kojto	108:34e6b704fe68	163	*/
Kojto	108:34e6b704fe68	164
Kojto	108:34e6b704fe68	165	/** @defgroup RCC_LSI_Config LSI Config
Kojto	108:34e6b704fe68	166	* @{
Kojto	108:34e6b704fe68	167	*/
Kojto	108:34e6b704fe68	168	#define RCC_LSI_OFF ((uint8_t)0x00)
Kojto	108:34e6b704fe68	169	#define RCC_LSI_ON ((uint8_t)0x01)
Kojto	108:34e6b704fe68	170	/**
Kojto	108:34e6b704fe68	171	* @}
Kojto	108:34e6b704fe68	172	*/
Kojto	108:34e6b704fe68	173
Kojto	108:34e6b704fe68	174	/** @defgroup RCC_PLL_Config PLL Config
Kojto	108:34e6b704fe68	175	* @{
Kojto	108:34e6b704fe68	176	*/
Kojto	108:34e6b704fe68	177	#define RCC_PLL_NONE ((uint8_t)0x00)
Kojto	108:34e6b704fe68	178	#define RCC_PLL_OFF ((uint8_t)0x01)
Kojto	108:34e6b704fe68	179	#define RCC_PLL_ON ((uint8_t)0x02)
Kojto	108:34e6b704fe68	180	/**
Kojto	108:34e6b704fe68	181	* @}
Kojto	108:34e6b704fe68	182	*/
Kojto	108:34e6b704fe68	183
Kojto	108:34e6b704fe68	184	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto	108:34e6b704fe68	185	* @{
Kojto	108:34e6b704fe68	186	*/
Kojto	108:34e6b704fe68	187	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto	108:34e6b704fe68	188	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto	108:34e6b704fe68	189	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto	108:34e6b704fe68	190	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto	108:34e6b704fe68	191	/**
Kojto	108:34e6b704fe68	192	* @}
Kojto	108:34e6b704fe68	193	*/
Kojto	108:34e6b704fe68	194
Kojto	108:34e6b704fe68	195	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto	108:34e6b704fe68	196	* @{
Kojto	108:34e6b704fe68	197	*/
Kojto	108:34e6b704fe68	198	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto	108:34e6b704fe68	199	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto	108:34e6b704fe68	200	/**
Kojto	108:34e6b704fe68	201	* @}
Kojto	108:34e6b704fe68	202	*/
Kojto	108:34e6b704fe68	203
Kojto	108:34e6b704fe68	204	/** @defgroup RCC_System_Clock_Type System Clock Type
Kojto	108:34e6b704fe68	205	* @{
Kojto	108:34e6b704fe68	206	*/
Kojto	108:34e6b704fe68	207	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	108:34e6b704fe68	208	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	108:34e6b704fe68	209	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	108:34e6b704fe68	210	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	108:34e6b704fe68	211	/**
Kojto	108:34e6b704fe68	212	* @}
Kojto	108:34e6b704fe68	213	*/
Kojto	108:34e6b704fe68	214
Kojto	108:34e6b704fe68	215	/** @defgroup RCC_System_Clock_Source System Clock Source
Kojto	108:34e6b704fe68	216	* @{
Kojto	108:34e6b704fe68	217	*/
Kojto	108:34e6b704fe68	218	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	108:34e6b704fe68	219	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	108:34e6b704fe68	220	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	108:34e6b704fe68	221	#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
Kojto	108:34e6b704fe68	222	/**
Kojto	108:34e6b704fe68	223	* @}
Kojto	108:34e6b704fe68	224	*/
Kojto	108:34e6b704fe68	225
Kojto	108:34e6b704fe68	226	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	108:34e6b704fe68	227	* @{
Kojto	108:34e6b704fe68	228	*/
Kojto	108:34e6b704fe68	229	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	108:34e6b704fe68	230	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	108:34e6b704fe68	231	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	108:34e6b704fe68	232	#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1)) /!< PLLR used as system clock /
Kojto	108:34e6b704fe68	233	/**
Kojto	108:34e6b704fe68	234	* @}
Kojto	108:34e6b704fe68	235	*/
Kojto	108:34e6b704fe68	236
Kojto	108:34e6b704fe68	237	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto	108:34e6b704fe68	238	* @{
Kojto	108:34e6b704fe68	239	*/
Kojto	108:34e6b704fe68	240	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	108:34e6b704fe68	241	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	108:34e6b704fe68	242	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	108:34e6b704fe68	243	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	108:34e6b704fe68	244	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	108:34e6b704fe68	245	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	108:34e6b704fe68	246	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	108:34e6b704fe68	247	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	108:34e6b704fe68	248	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	108:34e6b704fe68	249	/**
Kojto	108:34e6b704fe68	250	* @}
Kojto	108:34e6b704fe68	251	*/
Kojto	108:34e6b704fe68	252
Kojto	108:34e6b704fe68	253	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
Kojto	108:34e6b704fe68	254	* @{
Kojto	108:34e6b704fe68	255	*/
Kojto	108:34e6b704fe68	256	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto	108:34e6b704fe68	257	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto	108:34e6b704fe68	258	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto	108:34e6b704fe68	259	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto	108:34e6b704fe68	260	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto	108:34e6b704fe68	261	/**
Kojto	108:34e6b704fe68	262	* @}
Kojto	108:34e6b704fe68	263	*/
Kojto	108:34e6b704fe68	264
Kojto	108:34e6b704fe68	265	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto	108:34e6b704fe68	266	* @{
Kojto	108:34e6b704fe68	267	*/
Kojto	108:34e6b704fe68	268	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto	108:34e6b704fe68	269	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto	108:34e6b704fe68	270	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto	108:34e6b704fe68	271	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto	108:34e6b704fe68	272	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto	108:34e6b704fe68	273	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto	108:34e6b704fe68	274	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto	108:34e6b704fe68	275	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto	108:34e6b704fe68	276	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto	108:34e6b704fe68	277	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto	108:34e6b704fe68	278	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto	108:34e6b704fe68	279	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto	108:34e6b704fe68	280	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto	108:34e6b704fe68	281	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto	108:34e6b704fe68	282	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto	108:34e6b704fe68	283	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto	108:34e6b704fe68	284	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto	108:34e6b704fe68	285	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto	108:34e6b704fe68	286	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto	108:34e6b704fe68	287	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto	108:34e6b704fe68	288	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto	108:34e6b704fe68	289	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto	108:34e6b704fe68	290	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto	108:34e6b704fe68	291	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto	108:34e6b704fe68	292	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto	108:34e6b704fe68	293	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto	108:34e6b704fe68	294	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto	108:34e6b704fe68	295	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto	108:34e6b704fe68	296	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto	108:34e6b704fe68	297	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto	108:34e6b704fe68	298	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto	108:34e6b704fe68	299	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto	108:34e6b704fe68	300	/**
Kojto	108:34e6b704fe68	301	* @}
Kojto	108:34e6b704fe68	302	*/
Kojto	108:34e6b704fe68	303
Kojto	108:34e6b704fe68	304	/** @defgroup RCC_MCO_Index MCO Index
Kojto	108:34e6b704fe68	305	* @{
Kojto	108:34e6b704fe68	306	*/
Kojto	108:34e6b704fe68	307	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	108:34e6b704fe68	308	#define RCC_MCO2 ((uint32_t)0x00000001)
Kojto	108:34e6b704fe68	309	/**
Kojto	108:34e6b704fe68	310	* @}
Kojto	108:34e6b704fe68	311	*/
Kojto	108:34e6b704fe68	312
Kojto	108:34e6b704fe68	313	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto	108:34e6b704fe68	314	* @{
Kojto	108:34e6b704fe68	315	*/
Kojto	108:34e6b704fe68	316	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto	108:34e6b704fe68	317	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto	108:34e6b704fe68	318	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto	108:34e6b704fe68	319	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto	108:34e6b704fe68	320	/**
Kojto	108:34e6b704fe68	321	* @}
Kojto	108:34e6b704fe68	322	*/
Kojto	108:34e6b704fe68	323
Kojto	108:34e6b704fe68	324	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
Kojto	108:34e6b704fe68	325	* @{
Kojto	108:34e6b704fe68	326	*/
Kojto	108:34e6b704fe68	327	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto	108:34e6b704fe68	328	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto	108:34e6b704fe68	329	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
Kojto	108:34e6b704fe68	330	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
Kojto	108:34e6b704fe68	331	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto	108:34e6b704fe68	332	/**
Kojto	108:34e6b704fe68	333	* @}
Kojto	108:34e6b704fe68	334	*/
Kojto	108:34e6b704fe68	335
Kojto	108:34e6b704fe68	336	/** @defgroup RCC_Interrupt Interrupts
Kojto	108:34e6b704fe68	337	* @{
Kojto	108:34e6b704fe68	338	*/
Kojto	108:34e6b704fe68	339	#define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto	108:34e6b704fe68	340	#define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto	108:34e6b704fe68	341	#define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto	108:34e6b704fe68	342	#define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto	108:34e6b704fe68	343	#define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto	108:34e6b704fe68	344	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto	108:34e6b704fe68	345	#define RCC_IT_CSS ((uint8_t)0x80)
Kojto	108:34e6b704fe68	346	/**
Kojto	108:34e6b704fe68	347	* @}
Kojto	108:34e6b704fe68	348	*/
Kojto	108:34e6b704fe68	349
Kojto	108:34e6b704fe68	350	/** @defgroup RCC_Flag Flags
Kojto	108:34e6b704fe68	351	* Elements values convention: 0XXYYYYYb
Kojto	108:34e6b704fe68	352	* - YYYYY : Flag position in the register
Kojto	108:34e6b704fe68	353	* - 0XX : Register index
Kojto	108:34e6b704fe68	354	* - 01: CR register
Kojto	108:34e6b704fe68	355	* - 10: BDCR register
Kojto	108:34e6b704fe68	356	* - 11: CSR register
Kojto	108:34e6b704fe68	357	* @{
Kojto	108:34e6b704fe68	358	*/
Kojto	108:34e6b704fe68	359	/* Flags in the CR register */
Kojto	108:34e6b704fe68	360	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto	108:34e6b704fe68	361	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto	108:34e6b704fe68	362	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto	108:34e6b704fe68	363	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto	108:34e6b704fe68	364
Kojto	108:34e6b704fe68	365	/* Flags in the BDCR register */
Kojto	108:34e6b704fe68	366	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto	108:34e6b704fe68	367
Kojto	108:34e6b704fe68	368	/* Flags in the CSR register */
Kojto	108:34e6b704fe68	369	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto	108:34e6b704fe68	370	#define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto	108:34e6b704fe68	371	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto	108:34e6b704fe68	372	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto	108:34e6b704fe68	373	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto	108:34e6b704fe68	374	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto	108:34e6b704fe68	375	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto	108:34e6b704fe68	376	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto	108:34e6b704fe68	377	/**
Kojto	108:34e6b704fe68	378	* @}
Kojto	108:34e6b704fe68	379	*/
Kojto	108:34e6b704fe68	380
Kojto	108:34e6b704fe68	381	/**
Kojto	108:34e6b704fe68	382	* @}
Kojto	108:34e6b704fe68	383	*/
Kojto	108:34e6b704fe68	384
Kojto	108:34e6b704fe68	385	/* Exported macro ------------------------------------------------------------*/
Kojto	108:34e6b704fe68	386	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	108:34e6b704fe68	387	* @{
Kojto	108:34e6b704fe68	388	*/
Kojto	108:34e6b704fe68	389
Kojto	108:34e6b704fe68	390	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	108:34e6b704fe68	391	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	108:34e6b704fe68	392	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	393	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	394	* using it.
Kojto	108:34e6b704fe68	395	* @{
Kojto	108:34e6b704fe68	396	*/
Kojto	108:34e6b704fe68	397	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	398	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	399	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto	108:34e6b704fe68	400	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	401	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto	108:34e6b704fe68	402	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	403	} while(0)
Kojto	108:34e6b704fe68	404	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	405	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	406	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto	108:34e6b704fe68	407	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	408	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto	108:34e6b704fe68	409	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	410	} while(0)
Kojto	108:34e6b704fe68	411	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	412	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	413	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto	108:34e6b704fe68	414	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	415	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto	108:34e6b704fe68	416	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	417	} while(0)
Kojto	108:34e6b704fe68	418	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	419	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	420	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto	108:34e6b704fe68	421	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	422	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto	108:34e6b704fe68	423	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	424	} while(0)
Kojto	108:34e6b704fe68	425	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	426	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	427	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto	108:34e6b704fe68	428	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	429	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto	108:34e6b704fe68	430	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	431	} while(0)
Kojto	108:34e6b704fe68	432	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	433	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	434	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto	108:34e6b704fe68	435	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	436	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto	108:34e6b704fe68	437	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	438	} while(0)
Kojto	108:34e6b704fe68	439
Kojto	108:34e6b704fe68	440	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto	108:34e6b704fe68	441	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto	108:34e6b704fe68	442	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto	108:34e6b704fe68	443	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto	108:34e6b704fe68	444	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto	108:34e6b704fe68	445	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto	108:34e6b704fe68	446
Kojto	108:34e6b704fe68	447	/**
Kojto	108:34e6b704fe68	448	* @}
Kojto	108:34e6b704fe68	449	*/
Kojto	108:34e6b704fe68	450
Kojto	108:34e6b704fe68	451	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	108:34e6b704fe68	452	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	108:34e6b704fe68	453	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	454	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	455	* using it.
Kojto	108:34e6b704fe68	456	* @{
Kojto	108:34e6b704fe68	457	*/
Kojto	108:34e6b704fe68	458	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	459	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	460	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto	108:34e6b704fe68	461	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	462	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto	108:34e6b704fe68	463	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	464	} while(0)
Kojto	108:34e6b704fe68	465	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	466	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	467	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	108:34e6b704fe68	468	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	469	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	108:34e6b704fe68	470	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	471	} while(0)
Kojto	108:34e6b704fe68	472	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	473	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	474	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	108:34e6b704fe68	475	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	476	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	108:34e6b704fe68	477	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	478	} while(0)
Kojto	108:34e6b704fe68	479	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	480	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	481	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	108:34e6b704fe68	482	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	483	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	108:34e6b704fe68	484	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	485	} while(0)
Kojto	108:34e6b704fe68	486	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	487	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	488	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	108:34e6b704fe68	489	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	490	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	108:34e6b704fe68	491	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	492	} while(0)
Kojto	108:34e6b704fe68	493	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	494	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	495	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	108:34e6b704fe68	496	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	497	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	108:34e6b704fe68	498	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	499	} while(0)
Kojto	108:34e6b704fe68	500	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	501	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	502	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	108:34e6b704fe68	503	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	504	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	108:34e6b704fe68	505	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	506	} while(0)
Kojto	110:165afa46840b	507
Kojto	108:34e6b704fe68	508	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto	108:34e6b704fe68	509	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	108:34e6b704fe68	510	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	108:34e6b704fe68	511	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	108:34e6b704fe68	512	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	108:34e6b704fe68	513	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	108:34e6b704fe68	514	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	108:34e6b704fe68	515	/**
Kojto	108:34e6b704fe68	516	* @}
Kojto	108:34e6b704fe68	517	*/
Kojto	108:34e6b704fe68	518
Kojto	108:34e6b704fe68	519	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	108:34e6b704fe68	520	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	108:34e6b704fe68	521	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	108:34e6b704fe68	522	* is disabled and the application software has to enable this clock before
Kojto	108:34e6b704fe68	523	* using it.
Kojto	108:34e6b704fe68	524	* @{
Kojto	108:34e6b704fe68	525	*/
Kojto	108:34e6b704fe68	526	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	527	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	528	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	108:34e6b704fe68	529	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	530	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	108:34e6b704fe68	531	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	532	} while(0)
Kojto	108:34e6b704fe68	533	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	534	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	535	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	108:34e6b704fe68	536	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	537	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	108:34e6b704fe68	538	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	539	} while(0)
Kojto	108:34e6b704fe68	540	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	541	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	542	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	108:34e6b704fe68	543	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	544	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	108:34e6b704fe68	545	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	546	} while(0)
Kojto	108:34e6b704fe68	547	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	548	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	549	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	108:34e6b704fe68	550	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	551	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	108:34e6b704fe68	552	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	553	} while(0)
Kojto	108:34e6b704fe68	554	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	555	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	556	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	108:34e6b704fe68	557	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	558	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	108:34e6b704fe68	559	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	560	} while(0)
Kojto	108:34e6b704fe68	561	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	562	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	563	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	108:34e6b704fe68	564	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	565	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	108:34e6b704fe68	566	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	567	} while(0)
Kojto	108:34e6b704fe68	568	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	569	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	570	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto	108:34e6b704fe68	571	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	572	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto	108:34e6b704fe68	573	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	574	} while(0)
Kojto	108:34e6b704fe68	575	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto	108:34e6b704fe68	576	__IO uint32_t tmpreg; \
Kojto	108:34e6b704fe68	577	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto	108:34e6b704fe68	578	/* Delay after an RCC peripheral clock enabling */ \
Kojto	108:34e6b704fe68	579	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto	108:34e6b704fe68	580	UNUSED(tmpreg); \
Kojto	108:34e6b704fe68	581	} while(0)
Kojto	108:34e6b704fe68	582
Kojto	108:34e6b704fe68	583	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	108:34e6b704fe68	584	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	108:34e6b704fe68	585	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	108:34e6b704fe68	586	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	108:34e6b704fe68	587	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	108:34e6b704fe68	588	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	108:34e6b704fe68	589	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto	108:34e6b704fe68	590	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto	108:34e6b704fe68	591	/**
Kojto	108:34e6b704fe68	592	* @}
Kojto	108:34e6b704fe68	593	*/
Kojto	108:34e6b704fe68	594
Kojto	108:34e6b704fe68	595	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	108:34e6b704fe68	596	* @brief Force or release AHB1 peripheral reset.
Kojto	108:34e6b704fe68	597	* @{
Kojto	108:34e6b704fe68	598	*/
Kojto	108:34e6b704fe68	599	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto	108:34e6b704fe68	600	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
Kojto	108:34e6b704fe68	601	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
Kojto	108:34e6b704fe68	602	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
Kojto	108:34e6b704fe68	603	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
Kojto	108:34e6b704fe68	604	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
Kojto	108:34e6b704fe68	605	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
Kojto	108:34e6b704fe68	606
Kojto	108:34e6b704fe68	607	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto	108:34e6b704fe68	608	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto	108:34e6b704fe68	609	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto	108:34e6b704fe68	610	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto	108:34e6b704fe68	611	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto	108:34e6b704fe68	612	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto	108:34e6b704fe68	613	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto	108:34e6b704fe68	614	/**
Kojto	108:34e6b704fe68	615	* @}
Kojto	108:34e6b704fe68	616	*/
Kojto	108:34e6b704fe68	617
Kojto	108:34e6b704fe68	618	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	108:34e6b704fe68	619	* @brief Force or release APB1 peripheral reset.
Kojto	108:34e6b704fe68	620	* @{
Kojto	108:34e6b704fe68	621	*/
Kojto	108:34e6b704fe68	622	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	108:34e6b704fe68	623	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
Kojto	108:34e6b704fe68	624	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	108:34e6b704fe68	625	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	108:34e6b704fe68	626	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	108:34e6b704fe68	627	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	108:34e6b704fe68	628	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	108:34e6b704fe68	629	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	108:34e6b704fe68	630
Kojto	108:34e6b704fe68	631	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	108:34e6b704fe68	632	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto	108:34e6b704fe68	633	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	108:34e6b704fe68	634	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	108:34e6b704fe68	635	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	108:34e6b704fe68	636	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	108:34e6b704fe68	637	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	108:34e6b704fe68	638	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	108:34e6b704fe68	639	/**
Kojto	108:34e6b704fe68	640	* @}
Kojto	108:34e6b704fe68	641	*/
Kojto	108:34e6b704fe68	642
Kojto	108:34e6b704fe68	643	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	108:34e6b704fe68	644	* @brief Force or release APB2 peripheral reset.
Kojto	108:34e6b704fe68	645	* @{
Kojto	108:34e6b704fe68	646	*/
Kojto	108:34e6b704fe68	647	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	108:34e6b704fe68	648	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	108:34e6b704fe68	649	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	108:34e6b704fe68	650	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	108:34e6b704fe68	651	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
Kojto	108:34e6b704fe68	652	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	108:34e6b704fe68	653	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	108:34e6b704fe68	654	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
Kojto	108:34e6b704fe68	655	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
Kojto	108:34e6b704fe68	656
Kojto	108:34e6b704fe68	657	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	108:34e6b704fe68	658	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	108:34e6b704fe68	659	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	108:34e6b704fe68	660	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	108:34e6b704fe68	661	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto	108:34e6b704fe68	662	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	108:34e6b704fe68	663	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	108:34e6b704fe68	664	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto	108:34e6b704fe68	665	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto	108:34e6b704fe68	666	/**
Kojto	108:34e6b704fe68	667	* @}
Kojto	108:34e6b704fe68	668	*/
Kojto	108:34e6b704fe68	669
Kojto	108:34e6b704fe68	670	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	108:34e6b704fe68	671	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	108:34e6b704fe68	672	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	108:34e6b704fe68	673	* power consumption.
Kojto	108:34e6b704fe68	674	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	108:34e6b704fe68	675	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	108:34e6b704fe68	676	* @{
Kojto	108:34e6b704fe68	677	*/
Kojto	108:34e6b704fe68	678	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
Kojto	108:34e6b704fe68	679	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto	108:34e6b704fe68	680	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto	108:34e6b704fe68	681	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto	108:34e6b704fe68	682	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
Kojto	108:34e6b704fe68	683	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
Kojto	108:34e6b704fe68	684
Kojto	108:34e6b704fe68	685	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto	108:34e6b704fe68	686	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto	108:34e6b704fe68	687	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto	108:34e6b704fe68	688	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto	108:34e6b704fe68	689	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto	108:34e6b704fe68	690	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto	108:34e6b704fe68	691	/**
Kojto	108:34e6b704fe68	692	* @}
Kojto	108:34e6b704fe68	693	*/
Kojto	108:34e6b704fe68	694
Kojto	108:34e6b704fe68	695	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	108:34e6b704fe68	696	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	108:34e6b704fe68	697	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	108:34e6b704fe68	698	* power consumption.
Kojto	108:34e6b704fe68	699	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	108:34e6b704fe68	700	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	108:34e6b704fe68	701	* @{
Kojto	108:34e6b704fe68	702	*/
Kojto	108:34e6b704fe68	703	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
Kojto	108:34e6b704fe68	704	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
Kojto	108:34e6b704fe68	705	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
Kojto	108:34e6b704fe68	706	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
Kojto	108:34e6b704fe68	707	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
Kojto	108:34e6b704fe68	708	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
Kojto	108:34e6b704fe68	709	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
Kojto	108:34e6b704fe68	710
Kojto	108:34e6b704fe68	711	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto	108:34e6b704fe68	712	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto	108:34e6b704fe68	713	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto	108:34e6b704fe68	714	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto	108:34e6b704fe68	715	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto	108:34e6b704fe68	716	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto	108:34e6b704fe68	717	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto	108:34e6b704fe68	718	/**
Kojto	108:34e6b704fe68	719	* @}
Kojto	108:34e6b704fe68	720	*/
Kojto	108:34e6b704fe68	721
Kojto	108:34e6b704fe68	722	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	108:34e6b704fe68	723	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	108:34e6b704fe68	724	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	108:34e6b704fe68	725	* power consumption.
Kojto	108:34e6b704fe68	726	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	108:34e6b704fe68	727	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	108:34e6b704fe68	728	* @{
Kojto	108:34e6b704fe68	729	*/
Kojto	108:34e6b704fe68	730	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
Kojto	108:34e6b704fe68	731	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
Kojto	108:34e6b704fe68	732	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
Kojto	108:34e6b704fe68	733	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
Kojto	108:34e6b704fe68	734	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
Kojto	108:34e6b704fe68	735	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto	108:34e6b704fe68	736	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
Kojto	108:34e6b704fe68	737	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
Kojto	108:34e6b704fe68	738
Kojto	108:34e6b704fe68	739	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto	108:34e6b704fe68	740	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto	108:34e6b704fe68	741	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto	108:34e6b704fe68	742	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto	108:34e6b704fe68	743	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto	108:34e6b704fe68	744	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto	108:34e6b704fe68	745	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto	108:34e6b704fe68	746	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto	108:34e6b704fe68	747	/**
Kojto	108:34e6b704fe68	748	* @}
Kojto	108:34e6b704fe68	749	*/
Kojto	108:34e6b704fe68	750
Kojto	108:34e6b704fe68	751	/** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto	108:34e6b704fe68	752	* @{
Kojto	108:34e6b704fe68	753	*/
Kojto	108:34e6b704fe68	754
Kojto	108:34e6b704fe68	755	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	108:34e6b704fe68	756	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	108:34e6b704fe68	757	* It is used (enabled by hardware) as system clock source after startup
Kojto	108:34e6b704fe68	758	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
Kojto	108:34e6b704fe68	759	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	108:34e6b704fe68	760	* Security System CSS is enabled).
Kojto	108:34e6b704fe68	761	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	108:34e6b704fe68	762	* you have to select another source of the system clock then stop the HSI.
Kojto	108:34e6b704fe68	763	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	108:34e6b704fe68	764	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	108:34e6b704fe68	765	* system clock source.
Kojto	108:34e6b704fe68	766	* This parameter can be: ENABLE or DISABLE.
Kojto	108:34e6b704fe68	767	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	108:34e6b704fe68	768	* clock cycles.
Kojto	108:34e6b704fe68	769	*/
Kojto	108:34e6b704fe68	770	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
Kojto	108:34e6b704fe68	771	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
Kojto	108:34e6b704fe68	772
Kojto	108:34e6b704fe68	773	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	108:34e6b704fe68	774	* @note The calibration is used to compensate for the variations in voltage
Kojto	108:34e6b704fe68	775	* and temperature that influence the frequency of the internal HSI RC.
Kojto	108:34e6b704fe68	776	* @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto	108:34e6b704fe68	777	* This parameter must be a number between 0 and 0x1F.
Kojto	108:34e6b704fe68	778	*/
Kojto	108:34e6b704fe68	779	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Kojto	108:34e6b704fe68	780	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto	108:34e6b704fe68	781	/**
Kojto	108:34e6b704fe68	782	* @}
Kojto	108:34e6b704fe68	783	*/
Kojto	108:34e6b704fe68	784
Kojto	108:34e6b704fe68	785	/** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto	108:34e6b704fe68	786	* @{
Kojto	108:34e6b704fe68	787	*/
Kojto	108:34e6b704fe68	788
Kojto	108:34e6b704fe68	789	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	108:34e6b704fe68	790	* @note After enabling the LSI, the application software should wait on
Kojto	108:34e6b704fe68	791	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	108:34e6b704fe68	792	* be used to clock the IWDG and/or the RTC.
Kojto	108:34e6b704fe68	793	* @note LSI can not be disabled if the IWDG is running.
Kojto	108:34e6b704fe68	794	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	108:34e6b704fe68	795	* clock cycles.
Kojto	108:34e6b704fe68	796	*/
Kojto	108:34e6b704fe68	797	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
Kojto	108:34e6b704fe68	798	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
Kojto	108:34e6b704fe68	799	/**
Kojto	108:34e6b704fe68	800	* @}
Kojto	108:34e6b704fe68	801	*/
Kojto	108:34e6b704fe68	802
Kojto	108:34e6b704fe68	803	/** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto	108:34e6b704fe68	804	* @{
Kojto	108:34e6b704fe68	805	*/
Kojto	108:34e6b704fe68	806
Kojto	108:34e6b704fe68	807	/**
Kojto	108:34e6b704fe68	808	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	108:34e6b704fe68	809	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto	108:34e6b704fe68	810	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Kojto	108:34e6b704fe68	811	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	108:34e6b704fe68	812	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	108:34e6b704fe68	813	* is stable and can be used to clock the PLL and/or system clock.
Kojto	108:34e6b704fe68	814	* @note HSE state can not be changed if it is used directly or through the
Kojto	108:34e6b704fe68	815	* PLL as system clock. In this case, you have to select another source
Kojto	108:34e6b704fe68	816	* of the system clock then change the HSE state (ex. disable it).
Kojto	108:34e6b704fe68	817	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	108:34e6b704fe68	818	* @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto	108:34e6b704fe68	819	* was previously enabled you have to enable it again after calling this
Kojto	108:34e6b704fe68	820	* function.
Kojto	108:34e6b704fe68	821	* @param __STATE__: specifies the new state of the HSE.
Kojto	108:34e6b704fe68	822	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	823	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	108:34e6b704fe68	824	* 6 HSE oscillator clock cycles.
Kojto	108:34e6b704fe68	825	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto	108:34e6b704fe68	826	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto	108:34e6b704fe68	827	*/
Kojto	108:34e6b704fe68	828	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto	108:34e6b704fe68	829	/**
Kojto	108:34e6b704fe68	830	* @}
Kojto	108:34e6b704fe68	831	*/
Kojto	108:34e6b704fe68	832
Kojto	108:34e6b704fe68	833	/** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto	108:34e6b704fe68	834	* @{
Kojto	108:34e6b704fe68	835	*/
Kojto	108:34e6b704fe68	836
Kojto	108:34e6b704fe68	837	/**
Kojto	108:34e6b704fe68	838	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	108:34e6b704fe68	839	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto	108:34e6b704fe68	840	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto	108:34e6b704fe68	841	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	108:34e6b704fe68	842	* this domain after reset, you have to enable write access using
Kojto	108:34e6b704fe68	843	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	108:34e6b704fe68	844	* (to be done once after reset).
Kojto	108:34e6b704fe68	845	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	108:34e6b704fe68	846	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	108:34e6b704fe68	847	* is stable and can be used to clock the RTC.
Kojto	108:34e6b704fe68	848	* @param __STATE__: specifies the new state of the LSE.
Kojto	108:34e6b704fe68	849	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	850	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	108:34e6b704fe68	851	* 6 LSE oscillator clock cycles.
Kojto	108:34e6b704fe68	852	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	108:34e6b704fe68	853	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto	108:34e6b704fe68	854	*/
Kojto	108:34e6b704fe68	855	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto	108:34e6b704fe68	856
Kojto	108:34e6b704fe68	857	/**
Kojto	108:34e6b704fe68	858	* @}
Kojto	108:34e6b704fe68	859	*/
Kojto	108:34e6b704fe68	860
Kojto	108:34e6b704fe68	861	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto	108:34e6b704fe68	862	* @{
Kojto	108:34e6b704fe68	863	*/
Kojto	108:34e6b704fe68	864
Kojto	108:34e6b704fe68	865	/** @brief Macros to enable or disable the RTC clock.
Kojto	108:34e6b704fe68	866	* @note These macros must be used only after the RTC clock source was selected.
Kojto	108:34e6b704fe68	867	*/
Kojto	108:34e6b704fe68	868	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto	108:34e6b704fe68	869	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
Kojto	108:34e6b704fe68	870
Kojto	108:34e6b704fe68	871	/** @brief Macros to configure the RTC clock (RTCCLK).
Kojto	108:34e6b704fe68	872	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	108:34e6b704fe68	873	* access is denied to this domain after reset, you have to enable write
Kojto	108:34e6b704fe68	874	* access using the Power Backup Access macro before to configure
Kojto	108:34e6b704fe68	875	* the RTC clock source (to be done once after reset).
Kojto	108:34e6b704fe68	876	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	108:34e6b704fe68	877	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto	108:34e6b704fe68	878	* a Power On Reset (POR).
Kojto	108:34e6b704fe68	879	* @param __RTCCLKSource__: specifies the RTC clock source.
Kojto	108:34e6b704fe68	880	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	881	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto	108:34e6b704fe68	882	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto	108:34e6b704fe68	883	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto	108:34e6b704fe68	884	* as RTC clock, where x:[2,31]
Kojto	108:34e6b704fe68	885	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	108:34e6b704fe68	886	* work in STOP and STANDBY modes, and can be used as wake-up source.
Kojto	108:34e6b704fe68	887	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	108:34e6b704fe68	888	* cannot be used in STOP and STANDBY modes.
Kojto	108:34e6b704fe68	889	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	108:34e6b704fe68	890	* RTC clock source).
Kojto	108:34e6b704fe68	891	*/
Kojto	108:34e6b704fe68	892	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto	108:34e6b704fe68	893	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto	108:34e6b704fe68	894
Kojto	108:34e6b704fe68	895	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto	108:34e6b704fe68	896	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto	108:34e6b704fe68	897	} while (0)
Kojto	108:34e6b704fe68	898
Kojto	108:34e6b704fe68	899	/** @brief Macros to force or release the Backup domain reset.
Kojto	108:34e6b704fe68	900	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	108:34e6b704fe68	901	* and the RTC clock source selection in RCC_CSR register.
Kojto	108:34e6b704fe68	902	* @note The BKPSRAM is not affected by this reset.
Kojto	108:34e6b704fe68	903	*/
Kojto	108:34e6b704fe68	904	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
Kojto	108:34e6b704fe68	905	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
Kojto	108:34e6b704fe68	906	/**
Kojto	108:34e6b704fe68	907	* @}
Kojto	108:34e6b704fe68	908	*/
Kojto	108:34e6b704fe68	909
Kojto	108:34e6b704fe68	910	/** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto	108:34e6b704fe68	911	* @{
Kojto	108:34e6b704fe68	912	*/
Kojto	108:34e6b704fe68	913
Kojto	108:34e6b704fe68	914	/** @brief Macros to enable or disable the main PLL.
Kojto	108:34e6b704fe68	915	* @note After enabling the main PLL, the application software should wait on
Kojto	108:34e6b704fe68	916	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	108:34e6b704fe68	917	* be used as system clock source.
Kojto	108:34e6b704fe68	918	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	108:34e6b704fe68	919	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	108:34e6b704fe68	920	*/
Kojto	108:34e6b704fe68	921	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
Kojto	108:34e6b704fe68	922	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
Kojto	108:34e6b704fe68	923
Kojto	108:34e6b704fe68	924	/** @brief Macro to configure the PLL clock source.
Kojto	108:34e6b704fe68	925	* @note This function must be used only when the main PLL is disabled.
Kojto	108:34e6b704fe68	926	* @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto	108:34e6b704fe68	927	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	928	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	108:34e6b704fe68	929	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	108:34e6b704fe68	930	*
Kojto	108:34e6b704fe68	931	*/
Kojto	108:34e6b704fe68	932	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto	108:34e6b704fe68	933
Kojto	108:34e6b704fe68	934	/** @brief Macro to configure the PLL multiplication factor.
Kojto	108:34e6b704fe68	935	* @note This function must be used only when the main PLL is disabled.
Kojto	108:34e6b704fe68	936	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	108:34e6b704fe68	937	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	108:34e6b704fe68	938	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	108:34e6b704fe68	939	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	108:34e6b704fe68	940	* of 2 MHz to limit PLL jitter.
Kojto	108:34e6b704fe68	941	*
Kojto	108:34e6b704fe68	942	*/
Kojto	108:34e6b704fe68	943	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto	108:34e6b704fe68	944	/**
Kojto	108:34e6b704fe68	945	* @}
Kojto	110:165afa46840b	946	*/
Kojto	110:165afa46840b	947
Kojto	108:34e6b704fe68	948	/** @defgroup RCC_Get_Clock_source Get Clock source
Kojto	108:34e6b704fe68	949	* @{
Kojto	108:34e6b704fe68	950	*/
Kojto	108:34e6b704fe68	951	/**
Kojto	108:34e6b704fe68	952	* @brief Macro to configure the system clock source.
Kojto	108:34e6b704fe68	953	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto	108:34e6b704fe68	954	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	955	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto	108:34e6b704fe68	956	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto	108:34e6b704fe68	957	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto	108:34e6b704fe68	958	* - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto	108:34e6b704fe68	959	*/
Kojto	108:34e6b704fe68	960	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto	108:34e6b704fe68	961
Kojto	108:34e6b704fe68	962	/** @brief Macro to get the clock source used as system clock.
Kojto	108:34e6b704fe68	963	* @retval The clock source used as system clock. The returned value can be one
Kojto	108:34e6b704fe68	964	* of the following:
Kojto	108:34e6b704fe68	965	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto	108:34e6b704fe68	966	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto	108:34e6b704fe68	967	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto	108:34e6b704fe68	968	* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
Kojto	108:34e6b704fe68	969	*/
Kojto	108:34e6b704fe68	970	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto	108:34e6b704fe68	971
Kojto	108:34e6b704fe68	972	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	108:34e6b704fe68	973	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	108:34e6b704fe68	974	* of the following:
Kojto	108:34e6b704fe68	975	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	108:34e6b704fe68	976	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	108:34e6b704fe68	977	*/
Kojto	108:34e6b704fe68	978	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto	108:34e6b704fe68	979	/**
Kojto	108:34e6b704fe68	980	* @}
Kojto	108:34e6b704fe68	981	*/
Kojto	108:34e6b704fe68	982
Kojto	110:165afa46840b	983	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	110:165afa46840b	984	* @{
Kojto	110:165afa46840b	985	*/
Kojto	110:165afa46840b	986
Kojto	110:165afa46840b	987	/** @brief Macro to configure the MCO1 clock.
Kojto	110:165afa46840b	988	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	110:165afa46840b	989	* This parameter can be one of the following values:
Kojto	110:165afa46840b	990	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto	110:165afa46840b	991	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto	110:165afa46840b	992	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto	110:165afa46840b	993	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto	110:165afa46840b	994	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	110:165afa46840b	995	* This parameter can be one of the following values:
Kojto	110:165afa46840b	996	* @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto	110:165afa46840b	997	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto	110:165afa46840b	998	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto	110:165afa46840b	999	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto	110:165afa46840b	1000	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto	110:165afa46840b	1001	*/
Kojto	110:165afa46840b	1002
Kojto	110:165afa46840b	1003	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	110:165afa46840b	1004	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
Kojto	110:165afa46840b	1005
Kojto	110:165afa46840b	1006	/** @brief Macro to configure the MCO2 clock.
Kojto	110:165afa46840b	1007	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	110:165afa46840b	1008	* This parameter can be one of the following values:
Kojto	110:165afa46840b	1009	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto	110:165afa46840b	1010	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto	110:165afa46840b	1011	* @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto	110:165afa46840b	1012	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto	110:165afa46840b	1013	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto	110:165afa46840b	1014	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	110:165afa46840b	1015	* This parameter can be one of the following values:
Kojto	110:165afa46840b	1016	* @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto	110:165afa46840b	1017	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto	110:165afa46840b	1018	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto	110:165afa46840b	1019	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto	110:165afa46840b	1020	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto	110:165afa46840b	1021	* @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
Kojto	110:165afa46840b	1022	* at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto	110:165afa46840b	1023	*/
Kojto	110:165afa46840b	1024
Kojto	110:165afa46840b	1025	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	110:165afa46840b	1026	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ \| (__MCODIV__ << 3)));
Kojto	110:165afa46840b	1027	/**
Kojto	110:165afa46840b	1028	* @}
Kojto	110:165afa46840b	1029	*/
Kojto	110:165afa46840b	1030
Kojto	108:34e6b704fe68	1031	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto	108:34e6b704fe68	1032	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	108:34e6b704fe68	1033	* @{
Kojto	108:34e6b704fe68	1034	*/
Kojto	108:34e6b704fe68	1035
Kojto	108:34e6b704fe68	1036	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	108:34e6b704fe68	1037	* the selected interrupts).
Kojto	108:34e6b704fe68	1038	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	108:34e6b704fe68	1039	* This parameter can be any combination of the following values:
Kojto	108:34e6b704fe68	1040	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	108:34e6b704fe68	1041	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	108:34e6b704fe68	1042	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	108:34e6b704fe68	1043	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	108:34e6b704fe68	1044	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	108:34e6b704fe68	1045	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	108:34e6b704fe68	1046	*/
Kojto	108:34e6b704fe68	1047	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	108:34e6b704fe68	1048
Kojto	108:34e6b704fe68	1049	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	108:34e6b704fe68	1050	* the selected interrupts).
Kojto	108:34e6b704fe68	1051	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	108:34e6b704fe68	1052	* This parameter can be any combination of the following values:
Kojto	108:34e6b704fe68	1053	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	108:34e6b704fe68	1054	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	108:34e6b704fe68	1055	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	108:34e6b704fe68	1056	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	108:34e6b704fe68	1057	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	108:34e6b704fe68	1058	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	108:34e6b704fe68	1059	*/
Kojto	108:34e6b704fe68	1060	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	108:34e6b704fe68	1061
Kojto	108:34e6b704fe68	1062	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto	108:34e6b704fe68	1063	* bits to clear the selected interrupt pending bits.
Kojto	108:34e6b704fe68	1064	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	108:34e6b704fe68	1065	* This parameter can be any combination of the following values:
Kojto	108:34e6b704fe68	1066	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	108:34e6b704fe68	1067	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	108:34e6b704fe68	1068	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	108:34e6b704fe68	1069	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	108:34e6b704fe68	1070	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	108:34e6b704fe68	1071	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	108:34e6b704fe68	1072	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	108:34e6b704fe68	1073	*/
Kojto	108:34e6b704fe68	1074	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto	108:34e6b704fe68	1075
Kojto	108:34e6b704fe68	1076	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	108:34e6b704fe68	1077	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	108:34e6b704fe68	1078	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1079	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	108:34e6b704fe68	1080	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	108:34e6b704fe68	1081	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	108:34e6b704fe68	1082	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	108:34e6b704fe68	1083	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	108:34e6b704fe68	1084	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	108:34e6b704fe68	1085	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	108:34e6b704fe68	1086	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	108:34e6b704fe68	1087	*/
Kojto	108:34e6b704fe68	1088	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	108:34e6b704fe68	1089
Kojto	108:34e6b704fe68	1090	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto	108:34e6b704fe68	1091	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto	108:34e6b704fe68	1092	*/
Kojto	108:34e6b704fe68	1093	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	108:34e6b704fe68	1094
Kojto	108:34e6b704fe68	1095	/** @brief Check RCC flag is set or not.
Kojto	108:34e6b704fe68	1096	* @param __FLAG__: specifies the flag to check.
Kojto	108:34e6b704fe68	1097	* This parameter can be one of the following values:
Kojto	108:34e6b704fe68	1098	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	108:34e6b704fe68	1099	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	108:34e6b704fe68	1100	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto	108:34e6b704fe68	1101	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto	108:34e6b704fe68	1102	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	108:34e6b704fe68	1103	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto	108:34e6b704fe68	1104	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto	108:34e6b704fe68	1105	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	108:34e6b704fe68	1106	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	108:34e6b704fe68	1107	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	108:34e6b704fe68	1108	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	108:34e6b704fe68	1109	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	108:34e6b704fe68	1110	* @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto	108:34e6b704fe68	1111	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	108:34e6b704fe68	1112	*/
Kojto	108:34e6b704fe68	1113	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	108:34e6b704fe68	1114	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto	108:34e6b704fe68	1115
Kojto	108:34e6b704fe68	1116	/**
Kojto	108:34e6b704fe68	1117	* @}
Kojto	108:34e6b704fe68	1118	*/
Kojto	108:34e6b704fe68	1119
Kojto	108:34e6b704fe68	1120	/**
Kojto	108:34e6b704fe68	1121	* @}
Kojto	108:34e6b704fe68	1122	*/
Kojto	108:34e6b704fe68	1123
Kojto	108:34e6b704fe68	1124	/* Exported functions --------------------------------------------------------*/
Kojto	108:34e6b704fe68	1125	/** @addtogroup RCC_Exported_Functions
Kojto	108:34e6b704fe68	1126	* @{
Kojto	108:34e6b704fe68	1127	*/
Kojto	108:34e6b704fe68	1128
Kojto	108:34e6b704fe68	1129	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	108:34e6b704fe68	1130	* @{
Kojto	108:34e6b704fe68	1131	*/
Kojto	108:34e6b704fe68	1132	/* Initialization and de-initialization functions ******************************/
Kojto	108:34e6b704fe68	1133	void HAL_RCC_DeInit(void);
Kojto	108:34e6b704fe68	1134	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	108:34e6b704fe68	1135	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	108:34e6b704fe68	1136	/**
Kojto	108:34e6b704fe68	1137	* @}
Kojto	108:34e6b704fe68	1138	*/
Kojto	108:34e6b704fe68	1139
Kojto	108:34e6b704fe68	1140	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	108:34e6b704fe68	1141	* @{
Kojto	108:34e6b704fe68	1142	*/
Kojto	108:34e6b704fe68	1143	/* Peripheral Control functions ************************************************/
Kojto	108:34e6b704fe68	1144	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	108:34e6b704fe68	1145	void HAL_RCC_EnableCSS(void);
Kojto	108:34e6b704fe68	1146	void HAL_RCC_DisableCSS(void);
Kojto	108:34e6b704fe68	1147	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	108:34e6b704fe68	1148	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	108:34e6b704fe68	1149	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	108:34e6b704fe68	1150	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	108:34e6b704fe68	1151	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	108:34e6b704fe68	1152	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	108:34e6b704fe68	1153
Kojto	108:34e6b704fe68	1154	/* CSS NMI IRQ handler */
Kojto	108:34e6b704fe68	1155	void HAL_RCC_NMI_IRQHandler(void);
Kojto	108:34e6b704fe68	1156
Kojto	108:34e6b704fe68	1157	/* User Callbacks in non blocking mode (IT mode) */
Kojto	108:34e6b704fe68	1158	void HAL_RCC_CSSCallback(void);
Kojto	108:34e6b704fe68	1159
Kojto	108:34e6b704fe68	1160	/**
Kojto	108:34e6b704fe68	1161	* @}
Kojto	108:34e6b704fe68	1162	*/
Kojto	108:34e6b704fe68	1163
Kojto	108:34e6b704fe68	1164	/**
Kojto	108:34e6b704fe68	1165	* @}
Kojto	108:34e6b704fe68	1166	*/
Kojto	108:34e6b704fe68	1167
Kojto	108:34e6b704fe68	1168	/* Private types -------------------------------------------------------------*/
Kojto	108:34e6b704fe68	1169	/* Private variables ---------------------------------------------------------*/
Kojto	108:34e6b704fe68	1170	/* Private constants ---------------------------------------------------------*/
Kojto	108:34e6b704fe68	1171	/** @defgroup RCC_Private_Constants RCC Private Constants
Kojto	108:34e6b704fe68	1172	* @{
Kojto	108:34e6b704fe68	1173	*/
Kojto	108:34e6b704fe68	1174
Kojto	108:34e6b704fe68	1175	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	108:34e6b704fe68	1176	* @brief RCC registers bit address in the alias region
Kojto	108:34e6b704fe68	1177	* @{
Kojto	108:34e6b704fe68	1178	*/
Kojto	108:34e6b704fe68	1179	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	108:34e6b704fe68	1180	/* --- CR Register ---*/
Kojto	108:34e6b704fe68	1181	/* Alias word address of HSION bit */
Kojto	108:34e6b704fe68	1182	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto	108:34e6b704fe68	1183	#define RCC_HSION_BIT_NUMBER 0x00
Kojto	108:34e6b704fe68	1184	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
Kojto	108:34e6b704fe68	1185	/* Alias word address of CSSON bit */
Kojto	108:34e6b704fe68	1186	#define RCC_CSSON_BIT_NUMBER 0x13
Kojto	108:34e6b704fe68	1187	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
Kojto	108:34e6b704fe68	1188	/* Alias word address of PLLON bit */
Kojto	108:34e6b704fe68	1189	#define RCC_PLLON_BIT_NUMBER 0x18
Kojto	108:34e6b704fe68	1190	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
Kojto	108:34e6b704fe68	1191
Kojto	108:34e6b704fe68	1192	/* --- BDCR Register ---*/
Kojto	108:34e6b704fe68	1193	/* Alias word address of RTCEN bit */
Kojto	108:34e6b704fe68	1194	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto	108:34e6b704fe68	1195	#define RCC_RTCEN_BIT_NUMBER 0x0F
Kojto	108:34e6b704fe68	1196	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
Kojto	108:34e6b704fe68	1197	/* Alias word address of BDRST bit */
Kojto	108:34e6b704fe68	1198	#define RCC_BDRST_BIT_NUMBER 0x10
Kojto	108:34e6b704fe68	1199	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
Kojto	108:34e6b704fe68	1200
Kojto	108:34e6b704fe68	1201	/* --- CSR Register ---*/
Kojto	108:34e6b704fe68	1202	/* Alias word address of LSION bit */
Kojto	108:34e6b704fe68	1203	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto	108:34e6b704fe68	1204	#define RCC_LSION_BIT_NUMBER 0x00
Kojto	108:34e6b704fe68	1205	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
Kojto	108:34e6b704fe68	1206
Kojto	108:34e6b704fe68	1207	/* CR register byte 3 (Bits[23:16]) base address */
Kojto	108:34e6b704fe68	1208	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto	108:34e6b704fe68	1209
Kojto	108:34e6b704fe68	1210	/* CIR register byte 2 (Bits[15:8]) base address */
Kojto	108:34e6b704fe68	1211	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto	108:34e6b704fe68	1212
Kojto	108:34e6b704fe68	1213	/* CIR register byte 3 (Bits[23:16]) base address */
Kojto	108:34e6b704fe68	1214	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto	108:34e6b704fe68	1215
Kojto	108:34e6b704fe68	1216	/* BDCR register base address */
Kojto	108:34e6b704fe68	1217	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto	108:34e6b704fe68	1218
Kojto	108:34e6b704fe68	1219	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	116:c0f6e94411f5	1220	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5000 ms */
Kojto	108:34e6b704fe68	1221
Kojto	108:34e6b704fe68	1222	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto	108:34e6b704fe68	1223	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	1224	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	108:34e6b704fe68	1225
Kojto	108:34e6b704fe68	1226	/**
Kojto	108:34e6b704fe68	1227	* @}
Kojto	108:34e6b704fe68	1228	*/
Kojto	108:34e6b704fe68	1229
Kojto	108:34e6b704fe68	1230	/**
Kojto	108:34e6b704fe68	1231	* @}
Kojto	108:34e6b704fe68	1232	*/
Kojto	108:34e6b704fe68	1233
Kojto	108:34e6b704fe68	1234	/* Private macros ------------------------------------------------------------*/
Kojto	108:34e6b704fe68	1235	/** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto	108:34e6b704fe68	1236	* @{
Kojto	108:34e6b704fe68	1237	*/
Kojto	108:34e6b704fe68	1238
Kojto	108:34e6b704fe68	1239	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	108:34e6b704fe68	1240	* @{
Kojto	108:34e6b704fe68	1241	*/
Kojto	108:34e6b704fe68	1242	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto	108:34e6b704fe68	1243
Kojto	108:34e6b704fe68	1244	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
Kojto	108:34e6b704fe68	1245	((HSE) == RCC_HSE_BYPASS))
Kojto	108:34e6b704fe68	1246
Kojto	108:34e6b704fe68	1247	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
Kojto	108:34e6b704fe68	1248	((LSE) == RCC_LSE_BYPASS))
Kojto	108:34e6b704fe68	1249
Kojto	108:34e6b704fe68	1250	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
Kojto	108:34e6b704fe68	1251
Kojto	108:34e6b704fe68	1252	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
Kojto	108:34e6b704fe68	1253
Kojto	108:34e6b704fe68	1254	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
Kojto	108:34e6b704fe68	1255
Kojto	108:34e6b704fe68	1256	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	1257	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	108:34e6b704fe68	1258
Kojto	108:34e6b704fe68	1259	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	108:34e6b704fe68	1260	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	108:34e6b704fe68	1261	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
Kojto	108:34e6b704fe68	1262	((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto	108:34e6b704fe68	1263
Kojto	108:34e6b704fe68	1264	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	108:34e6b704fe68	1265
Kojto	108:34e6b704fe68	1266	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto	108:34e6b704fe68	1267
Kojto	108:34e6b704fe68	1268	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
Kojto	108:34e6b704fe68	1269
Kojto	108:34e6b704fe68	1270	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto	108:34e6b704fe68	1271
Kojto	108:34e6b704fe68	1272	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	1273	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
Kojto	108:34e6b704fe68	1274	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
Kojto	108:34e6b704fe68	1275	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
Kojto	108:34e6b704fe68	1276	((HCLK) == RCC_SYSCLK_DIV512))
Kojto	108:34e6b704fe68	1277
Kojto	108:34e6b704fe68	1278	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto	108:34e6b704fe68	1279
Kojto	108:34e6b704fe68	1280	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
Kojto	108:34e6b704fe68	1281	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
Kojto	108:34e6b704fe68	1282	((PCLK) == RCC_HCLK_DIV16))
Kojto	108:34e6b704fe68	1283
Kojto	108:34e6b704fe68	1284	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
Kojto	108:34e6b704fe68	1285
Kojto	108:34e6b704fe68	1286	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	108:34e6b704fe68	1287	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto	108:34e6b704fe68	1288
Kojto	108:34e6b704fe68	1289	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
Kojto	108:34e6b704fe68	1290	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
Kojto	108:34e6b704fe68	1291	((DIV) == RCC_MCODIV_5))
Kojto	108:34e6b704fe68	1292	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto	108:34e6b704fe68	1293
Kojto	108:34e6b704fe68	1294	/**
Kojto	108:34e6b704fe68	1295	* @}
Kojto	108:34e6b704fe68	1296	*/
Kojto	108:34e6b704fe68	1297
Kojto	108:34e6b704fe68	1298	/**
Kojto	108:34e6b704fe68	1299	* @}
Kojto	108:34e6b704fe68	1300	*/
Kojto	108:34e6b704fe68	1301
Kojto	108:34e6b704fe68	1302	/**
Kojto	108:34e6b704fe68	1303	* @}
Kojto	108:34e6b704fe68	1304	*/
Kojto	108:34e6b704fe68	1305
Kojto	108:34e6b704fe68	1306	/**
Kojto	108:34e6b704fe68	1307	* @}
Kojto	108:34e6b704fe68	1308	*/
Kojto	108:34e6b704fe68	1309
Kojto	108:34e6b704fe68	1310	#ifdef __cplusplus
Kojto	108:34e6b704fe68	1311	}
Kojto	108:34e6b704fe68	1312	#endif
Kojto	108:34e6b704fe68	1313
Kojto	108:34e6b704fe68	1314	#endif /* __STM32F4xx_HAL_RCC_H */
Kojto	108:34e6b704fe68	1315
Kojto	108:34e6b704fe68	1316	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_ELMO_F411RE/stm32f4xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

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