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TARGET_DISCO_F746NG/stm32f7xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 116:c0f6e94411f5

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	107:4f6c30876dfa	1	/**
Kojto	107:4f6c30876dfa	2	******************************************************************************
Kojto	107:4f6c30876dfa	3	* @file stm32f7xx_hal_rcc.h
Kojto	107:4f6c30876dfa	4	* @author MCD Application Team
Kojto	116:c0f6e94411f5	5	* @version V1.0.4
Kojto	116:c0f6e94411f5	6	* @date 09-December-2015
Kojto	107:4f6c30876dfa	7	* @brief Header file of RCC HAL module.
Kojto	107:4f6c30876dfa	8	******************************************************************************
Kojto	107:4f6c30876dfa	9	* @attention
Kojto	107:4f6c30876dfa	10	*
Kojto	107:4f6c30876dfa	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	107:4f6c30876dfa	12	*
Kojto	107:4f6c30876dfa	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	107:4f6c30876dfa	14	* are permitted provided that the following conditions are met:
Kojto	107:4f6c30876dfa	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	107:4f6c30876dfa	16	* this list of conditions and the following disclaimer.
Kojto	107:4f6c30876dfa	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	107:4f6c30876dfa	18	* this list of conditions and the following disclaimer in the documentation
Kojto	107:4f6c30876dfa	19	* and/or other materials provided with the distribution.
Kojto	107:4f6c30876dfa	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	107:4f6c30876dfa	21	* may be used to endorse or promote products derived from this software
Kojto	107:4f6c30876dfa	22	* without specific prior written permission.
Kojto	107:4f6c30876dfa	23	*
Kojto	107:4f6c30876dfa	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	107:4f6c30876dfa	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	107:4f6c30876dfa	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	107:4f6c30876dfa	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	107:4f6c30876dfa	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	107:4f6c30876dfa	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	107:4f6c30876dfa	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	107:4f6c30876dfa	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	107:4f6c30876dfa	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	107:4f6c30876dfa	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	107:4f6c30876dfa	34	*
Kojto	107:4f6c30876dfa	35	******************************************************************************
Kojto	107:4f6c30876dfa	36	*/
Kojto	107:4f6c30876dfa	37
Kojto	107:4f6c30876dfa	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	107:4f6c30876dfa	39	#ifndef __STM32F7xx_HAL_RCC_H
Kojto	107:4f6c30876dfa	40	#define __STM32F7xx_HAL_RCC_H
Kojto	107:4f6c30876dfa	41
Kojto	107:4f6c30876dfa	42	#ifdef __cplusplus
Kojto	107:4f6c30876dfa	43	extern "C" {
Kojto	107:4f6c30876dfa	44	#endif
Kojto	107:4f6c30876dfa	45
Kojto	107:4f6c30876dfa	46	/* Includes ------------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	47	#include "stm32f7xx_hal_def.h"
Kojto	107:4f6c30876dfa	48
Kojto	107:4f6c30876dfa	49	/** @addtogroup STM32F7xx_HAL_Driver
Kojto	107:4f6c30876dfa	50	* @{
Kojto	107:4f6c30876dfa	51	*/
Kojto	107:4f6c30876dfa	52
Kojto	107:4f6c30876dfa	53	/** @addtogroup RCC
Kojto	107:4f6c30876dfa	54	* @{
Kojto	107:4f6c30876dfa	55	*/
Kojto	107:4f6c30876dfa	56
Kojto	107:4f6c30876dfa	57	/* Exported types ------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	58
Kojto	107:4f6c30876dfa	59	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	107:4f6c30876dfa	60	* @{
Kojto	107:4f6c30876dfa	61	*/
Kojto	107:4f6c30876dfa	62
Kojto	107:4f6c30876dfa	63	/**
Kojto	107:4f6c30876dfa	64	* @brief RCC PLL configuration structure definition
Kojto	107:4f6c30876dfa	65	*/
Kojto	107:4f6c30876dfa	66	typedef struct
Kojto	107:4f6c30876dfa	67	{
Kojto	107:4f6c30876dfa	68	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	107:4f6c30876dfa	69	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	107:4f6c30876dfa	70
Kojto	107:4f6c30876dfa	71	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	107:4f6c30876dfa	72	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	107:4f6c30876dfa	73
Kojto	107:4f6c30876dfa	74	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	107:4f6c30876dfa	75	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	107:4f6c30876dfa	76
Kojto	107:4f6c30876dfa	77	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	116:c0f6e94411f5	78	This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
Kojto	107:4f6c30876dfa	79
Kojto	107:4f6c30876dfa	80	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	107:4f6c30876dfa	81	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	107:4f6c30876dfa	82
Kojto	107:4f6c30876dfa	83	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
Kojto	107:4f6c30876dfa	84	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
Kojto	107:4f6c30876dfa	85
Kojto	107:4f6c30876dfa	86	}RCC_PLLInitTypeDef;
Kojto	107:4f6c30876dfa	87
Kojto	107:4f6c30876dfa	88	/**
Kojto	107:4f6c30876dfa	89	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	107:4f6c30876dfa	90	*/
Kojto	107:4f6c30876dfa	91	typedef struct
Kojto	107:4f6c30876dfa	92	{
Kojto	107:4f6c30876dfa	93	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	107:4f6c30876dfa	94	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	107:4f6c30876dfa	95
Kojto	107:4f6c30876dfa	96	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	107:4f6c30876dfa	97	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	107:4f6c30876dfa	98
Kojto	107:4f6c30876dfa	99	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	107:4f6c30876dfa	100	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	107:4f6c30876dfa	101
Kojto	107:4f6c30876dfa	102	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	107:4f6c30876dfa	103	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	107:4f6c30876dfa	104
Kojto	107:4f6c30876dfa	105	uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	107:4f6c30876dfa	106	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	107:4f6c30876dfa	107
Kojto	107:4f6c30876dfa	108	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	107:4f6c30876dfa	109	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	107:4f6c30876dfa	110
Kojto	107:4f6c30876dfa	111	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	107:4f6c30876dfa	112
Kojto	107:4f6c30876dfa	113	}RCC_OscInitTypeDef;
Kojto	107:4f6c30876dfa	114
Kojto	107:4f6c30876dfa	115	/**
Kojto	107:4f6c30876dfa	116	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	107:4f6c30876dfa	117	*/
Kojto	107:4f6c30876dfa	118	typedef struct
Kojto	107:4f6c30876dfa	119	{
Kojto	107:4f6c30876dfa	120	uint32_t ClockType; /*!< The clock to be configured.
Kojto	107:4f6c30876dfa	121	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	107:4f6c30876dfa	122
Kojto	107:4f6c30876dfa	123	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	107:4f6c30876dfa	124	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	107:4f6c30876dfa	125
Kojto	107:4f6c30876dfa	126	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	107:4f6c30876dfa	127	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	107:4f6c30876dfa	128
Kojto	107:4f6c30876dfa	129	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	107:4f6c30876dfa	130	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	107:4f6c30876dfa	131
Kojto	107:4f6c30876dfa	132	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	107:4f6c30876dfa	133	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	107:4f6c30876dfa	134
Kojto	107:4f6c30876dfa	135	}RCC_ClkInitTypeDef;
Kojto	107:4f6c30876dfa	136
Kojto	107:4f6c30876dfa	137	/**
Kojto	107:4f6c30876dfa	138	* @}
Kojto	107:4f6c30876dfa	139	*/
Kojto	107:4f6c30876dfa	140
Kojto	107:4f6c30876dfa	141	/* Exported constants --------------------------------------------------------*/
Kojto	107:4f6c30876dfa	142	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	107:4f6c30876dfa	143	* @{
Kojto	107:4f6c30876dfa	144	*/
Kojto	107:4f6c30876dfa	145
Kojto	107:4f6c30876dfa	146	/** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto	107:4f6c30876dfa	147	* @{
Kojto	107:4f6c30876dfa	148	*/
Kojto	107:4f6c30876dfa	149	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	150	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	107:4f6c30876dfa	151	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	107:4f6c30876dfa	152	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	107:4f6c30876dfa	153	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	107:4f6c30876dfa	154	/**
Kojto	107:4f6c30876dfa	155	* @}
Kojto	107:4f6c30876dfa	156	*/
Kojto	107:4f6c30876dfa	157
Kojto	107:4f6c30876dfa	158	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	107:4f6c30876dfa	159	* @{
Kojto	107:4f6c30876dfa	160	*/
Kojto	107:4f6c30876dfa	161	#define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	162	#define RCC_HSE_ON RCC_CR_HSEON
Kojto	107:4f6c30876dfa	163	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
Kojto	107:4f6c30876dfa	164	/**
Kojto	107:4f6c30876dfa	165	* @}
Kojto	107:4f6c30876dfa	166	*/
Kojto	107:4f6c30876dfa	167
Kojto	107:4f6c30876dfa	168	/** @defgroup RCC_LSE_Config RCC LSE Config
Kojto	107:4f6c30876dfa	169	* @{
Kojto	107:4f6c30876dfa	170	*/
Kojto	107:4f6c30876dfa	171	#define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	172	#define RCC_LSE_ON RCC_BDCR_LSEON
Kojto	107:4f6c30876dfa	173	#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))
Kojto	107:4f6c30876dfa	174	/**
Kojto	107:4f6c30876dfa	175	* @}
Kojto	107:4f6c30876dfa	176	*/
Kojto	107:4f6c30876dfa	177
Kojto	107:4f6c30876dfa	178	/** @defgroup RCC_HSI_Config RCC HSI Config
Kojto	107:4f6c30876dfa	179	* @{
Kojto	107:4f6c30876dfa	180	*/
Kojto	107:4f6c30876dfa	181	#define RCC_HSI_OFF ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	182	#define RCC_HSI_ON RCC_CR_HSION
Kojto	107:4f6c30876dfa	183	/**
Kojto	107:4f6c30876dfa	184	* @}
Kojto	107:4f6c30876dfa	185	*/
Kojto	107:4f6c30876dfa	186
Kojto	107:4f6c30876dfa	187	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	107:4f6c30876dfa	188	* @{
Kojto	107:4f6c30876dfa	189	*/
Kojto	107:4f6c30876dfa	190	#define RCC_LSI_OFF ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	191	#define RCC_LSI_ON RCC_CSR_LSION
Kojto	107:4f6c30876dfa	192	/**
Kojto	107:4f6c30876dfa	193	* @}
Kojto	107:4f6c30876dfa	194	*/
Kojto	107:4f6c30876dfa	195
Kojto	107:4f6c30876dfa	196	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	107:4f6c30876dfa	197	* @{
Kojto	107:4f6c30876dfa	198	*/
Kojto	107:4f6c30876dfa	199	#define RCC_PLL_NONE ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	200	#define RCC_PLL_OFF ((uint32_t)0x00000001)
Kojto	107:4f6c30876dfa	201	#define RCC_PLL_ON ((uint32_t)0x00000002)
Kojto	107:4f6c30876dfa	202	/**
Kojto	107:4f6c30876dfa	203	* @}
Kojto	107:4f6c30876dfa	204	*/
Kojto	107:4f6c30876dfa	205
Kojto	107:4f6c30876dfa	206	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto	107:4f6c30876dfa	207	* @{
Kojto	107:4f6c30876dfa	208	*/
Kojto	107:4f6c30876dfa	209	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto	107:4f6c30876dfa	210	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto	107:4f6c30876dfa	211	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto	107:4f6c30876dfa	212	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto	107:4f6c30876dfa	213	/**
Kojto	107:4f6c30876dfa	214	* @}
Kojto	107:4f6c30876dfa	215	*/
Kojto	107:4f6c30876dfa	216
Kojto	107:4f6c30876dfa	217	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto	107:4f6c30876dfa	218	* @{
Kojto	107:4f6c30876dfa	219	*/
Kojto	107:4f6c30876dfa	220	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto	107:4f6c30876dfa	221	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto	107:4f6c30876dfa	222	/**
Kojto	107:4f6c30876dfa	223	* @}
Kojto	107:4f6c30876dfa	224	*/
Kojto	107:4f6c30876dfa	225
Kojto	107:4f6c30876dfa	226	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	107:4f6c30876dfa	227	* @{
Kojto	107:4f6c30876dfa	228	*/
Kojto	107:4f6c30876dfa	229	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	107:4f6c30876dfa	230	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	107:4f6c30876dfa	231	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	107:4f6c30876dfa	232	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	107:4f6c30876dfa	233	/**
Kojto	107:4f6c30876dfa	234	* @}
Kojto	107:4f6c30876dfa	235	*/
Kojto	107:4f6c30876dfa	236
Kojto	107:4f6c30876dfa	237	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	107:4f6c30876dfa	238	* @{
Kojto	107:4f6c30876dfa	239	*/
Kojto	107:4f6c30876dfa	240	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	107:4f6c30876dfa	241	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	107:4f6c30876dfa	242	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	107:4f6c30876dfa	243	/**
Kojto	107:4f6c30876dfa	244	* @}
Kojto	107:4f6c30876dfa	245	*/
Kojto	107:4f6c30876dfa	246
Kojto	107:4f6c30876dfa	247
Kojto	107:4f6c30876dfa	248	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	107:4f6c30876dfa	249	* @{
Kojto	107:4f6c30876dfa	250	*/
Kojto	107:4f6c30876dfa	251	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	107:4f6c30876dfa	252	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	107:4f6c30876dfa	253	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	107:4f6c30876dfa	254	/**
Kojto	107:4f6c30876dfa	255	* @}
Kojto	107:4f6c30876dfa	256	*/
Kojto	107:4f6c30876dfa	257
Kojto	107:4f6c30876dfa	258	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto	107:4f6c30876dfa	259	* @{
Kojto	107:4f6c30876dfa	260	*/
Kojto	107:4f6c30876dfa	261	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	107:4f6c30876dfa	262	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	107:4f6c30876dfa	263	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	107:4f6c30876dfa	264	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	107:4f6c30876dfa	265	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	107:4f6c30876dfa	266	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	107:4f6c30876dfa	267	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	107:4f6c30876dfa	268	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	107:4f6c30876dfa	269	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	107:4f6c30876dfa	270	/**
Kojto	107:4f6c30876dfa	271	* @}
Kojto	107:4f6c30876dfa	272	*/
Kojto	107:4f6c30876dfa	273
Kojto	107:4f6c30876dfa	274	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
Kojto	107:4f6c30876dfa	275	* @{
Kojto	107:4f6c30876dfa	276	*/
Kojto	107:4f6c30876dfa	277	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto	107:4f6c30876dfa	278	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto	107:4f6c30876dfa	279	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto	107:4f6c30876dfa	280	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto	107:4f6c30876dfa	281	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto	107:4f6c30876dfa	282	/**
Kojto	107:4f6c30876dfa	283	* @}
Kojto	107:4f6c30876dfa	284	*/
Kojto	107:4f6c30876dfa	285
Kojto	107:4f6c30876dfa	286	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto	107:4f6c30876dfa	287	* @{
Kojto	107:4f6c30876dfa	288	*/
Kojto	107:4f6c30876dfa	289	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto	107:4f6c30876dfa	290	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto	107:4f6c30876dfa	291	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto	107:4f6c30876dfa	292	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto	107:4f6c30876dfa	293	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto	107:4f6c30876dfa	294	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto	107:4f6c30876dfa	295	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto	107:4f6c30876dfa	296	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto	107:4f6c30876dfa	297	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto	107:4f6c30876dfa	298	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto	107:4f6c30876dfa	299	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto	107:4f6c30876dfa	300	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto	107:4f6c30876dfa	301	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto	107:4f6c30876dfa	302	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto	107:4f6c30876dfa	303	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto	107:4f6c30876dfa	304	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto	107:4f6c30876dfa	305	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto	107:4f6c30876dfa	306	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto	107:4f6c30876dfa	307	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto	107:4f6c30876dfa	308	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto	107:4f6c30876dfa	309	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto	107:4f6c30876dfa	310	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto	107:4f6c30876dfa	311	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto	107:4f6c30876dfa	312	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto	107:4f6c30876dfa	313	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto	107:4f6c30876dfa	314	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto	107:4f6c30876dfa	315	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto	107:4f6c30876dfa	316	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto	107:4f6c30876dfa	317	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto	107:4f6c30876dfa	318	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto	107:4f6c30876dfa	319	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto	107:4f6c30876dfa	320	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto	107:4f6c30876dfa	321	/**
Kojto	107:4f6c30876dfa	322	* @}
Kojto	107:4f6c30876dfa	323	*/
Kojto	107:4f6c30876dfa	324
Kojto	107:4f6c30876dfa	325
Kojto	107:4f6c30876dfa	326
Kojto	107:4f6c30876dfa	327	/** @defgroup RCC_MCO_Index RCC MCO Index
Kojto	107:4f6c30876dfa	328	* @{
Kojto	107:4f6c30876dfa	329	*/
Kojto	107:4f6c30876dfa	330	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	331	#define RCC_MCO2 ((uint32_t)0x00000001)
Kojto	107:4f6c30876dfa	332	/**
Kojto	107:4f6c30876dfa	333	* @}
Kojto	107:4f6c30876dfa	334	*/
Kojto	107:4f6c30876dfa	335
Kojto	107:4f6c30876dfa	336	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
Kojto	107:4f6c30876dfa	337	* @{
Kojto	107:4f6c30876dfa	338	*/
Kojto	107:4f6c30876dfa	339	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	340	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto	107:4f6c30876dfa	341	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto	107:4f6c30876dfa	342	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto	107:4f6c30876dfa	343	/**
Kojto	107:4f6c30876dfa	344	* @}
Kojto	107:4f6c30876dfa	345	*/
Kojto	107:4f6c30876dfa	346
Kojto	107:4f6c30876dfa	347	/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
Kojto	107:4f6c30876dfa	348	* @{
Kojto	107:4f6c30876dfa	349	*/
Kojto	107:4f6c30876dfa	350	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	351	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto	107:4f6c30876dfa	352	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	107:4f6c30876dfa	353	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	107:4f6c30876dfa	354	/**
Kojto	107:4f6c30876dfa	355	* @}
Kojto	107:4f6c30876dfa	356	*/
Kojto	107:4f6c30876dfa	357
Kojto	107:4f6c30876dfa	358	/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
Kojto	107:4f6c30876dfa	359	* @{
Kojto	107:4f6c30876dfa	360	*/
Kojto	107:4f6c30876dfa	361	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	362	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto	107:4f6c30876dfa	363	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
Kojto	107:4f6c30876dfa	364	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
Kojto	107:4f6c30876dfa	365	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto	107:4f6c30876dfa	366	/**
Kojto	107:4f6c30876dfa	367	* @}
Kojto	107:4f6c30876dfa	368	*/
Kojto	107:4f6c30876dfa	369
Kojto	107:4f6c30876dfa	370	/** @defgroup RCC_Interrupt RCC Interrupt
Kojto	107:4f6c30876dfa	371	* @{
Kojto	107:4f6c30876dfa	372	*/
Kojto	107:4f6c30876dfa	373	#define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto	107:4f6c30876dfa	374	#define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto	107:4f6c30876dfa	375	#define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto	107:4f6c30876dfa	376	#define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto	107:4f6c30876dfa	377	#define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto	107:4f6c30876dfa	378	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto	107:4f6c30876dfa	379	#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
Kojto	107:4f6c30876dfa	380	#define RCC_IT_CSS ((uint8_t)0x80)
Kojto	107:4f6c30876dfa	381	/**
Kojto	107:4f6c30876dfa	382	* @}
Kojto	107:4f6c30876dfa	383	*/
Kojto	107:4f6c30876dfa	384
Kojto	107:4f6c30876dfa	385	/** @defgroup RCC_Flag RCC Flags
Kojto	107:4f6c30876dfa	386	* Elements values convention: 0XXYYYYYb
Kojto	107:4f6c30876dfa	387	* - YYYYY : Flag position in the register
Kojto	107:4f6c30876dfa	388	* - 0XX : Register index
Kojto	107:4f6c30876dfa	389	* - 01: CR register
Kojto	107:4f6c30876dfa	390	* - 10: BDCR register
Kojto	107:4f6c30876dfa	391	* - 11: CSR register
Kojto	107:4f6c30876dfa	392	* @{
Kojto	107:4f6c30876dfa	393	*/
Kojto	107:4f6c30876dfa	394	/* Flags in the CR register */
Kojto	107:4f6c30876dfa	395	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto	107:4f6c30876dfa	396	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto	107:4f6c30876dfa	397	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto	107:4f6c30876dfa	398	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto	107:4f6c30876dfa	399	#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
Kojto	107:4f6c30876dfa	400
Kojto	107:4f6c30876dfa	401	/* Flags in the BDCR register */
Kojto	107:4f6c30876dfa	402	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto	107:4f6c30876dfa	403
Kojto	107:4f6c30876dfa	404	/* Flags in the CSR register */
Kojto	107:4f6c30876dfa	405	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto	107:4f6c30876dfa	406	#define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto	107:4f6c30876dfa	407	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto	107:4f6c30876dfa	408	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto	107:4f6c30876dfa	409	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto	107:4f6c30876dfa	410	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto	107:4f6c30876dfa	411	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto	107:4f6c30876dfa	412	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto	107:4f6c30876dfa	413	/**
Kojto	107:4f6c30876dfa	414	* @}
Kojto	107:4f6c30876dfa	415	*/
Kojto	107:4f6c30876dfa	416
Kojto	107:4f6c30876dfa	417	/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
Kojto	107:4f6c30876dfa	418	* @{
Kojto	107:4f6c30876dfa	419	*/
Kojto	107:4f6c30876dfa	420	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
Kojto	107:4f6c30876dfa	421	#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
Kojto	107:4f6c30876dfa	422	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
Kojto	107:4f6c30876dfa	423	#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
Kojto	107:4f6c30876dfa	424	/**
Kojto	107:4f6c30876dfa	425	* @}
Kojto	107:4f6c30876dfa	426	*/
Kojto	107:4f6c30876dfa	427
Kojto	107:4f6c30876dfa	428	/**
Kojto	107:4f6c30876dfa	429	* @}
Kojto	107:4f6c30876dfa	430	*/
Kojto	107:4f6c30876dfa	431
Kojto	107:4f6c30876dfa	432	/* Exported macro ------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	433	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	107:4f6c30876dfa	434	* @{
Kojto	107:4f6c30876dfa	435	*/
Kojto	107:4f6c30876dfa	436
Kojto	107:4f6c30876dfa	437	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	438	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	107:4f6c30876dfa	439	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	440	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	441	* using it.
Kojto	107:4f6c30876dfa	442	* @{
Kojto	107:4f6c30876dfa	443	*/
Kojto	107:4f6c30876dfa	444	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	445	__IO uint32_t tmpreg = 0x00; \
Kojto	107:4f6c30876dfa	446	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	107:4f6c30876dfa	447	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	448	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	107:4f6c30876dfa	449	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	450	} while(0)
Kojto	107:4f6c30876dfa	451
Kojto	107:4f6c30876dfa	452	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	453	__IO uint32_t tmpreg = 0x00; \
Kojto	107:4f6c30876dfa	454	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto	107:4f6c30876dfa	455	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	456	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto	107:4f6c30876dfa	457	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	458	} while(0)
Kojto	107:4f6c30876dfa	459
Kojto	107:4f6c30876dfa	460	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	107:4f6c30876dfa	461	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto	107:4f6c30876dfa	462
Kojto	107:4f6c30876dfa	463	/**
Kojto	107:4f6c30876dfa	464	* @}
Kojto	107:4f6c30876dfa	465	*/
Kojto	107:4f6c30876dfa	466
Kojto	107:4f6c30876dfa	467	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	468	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	107:4f6c30876dfa	469	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	470	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	471	* using it.
Kojto	107:4f6c30876dfa	472	* @{
Kojto	107:4f6c30876dfa	473	*/
Kojto	107:4f6c30876dfa	474	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	475	__IO uint32_t tmpreg = 0x00; \
Kojto	107:4f6c30876dfa	476	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	107:4f6c30876dfa	477	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	478	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	107:4f6c30876dfa	479	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	480	} while(0)
Kojto	107:4f6c30876dfa	481
Kojto	107:4f6c30876dfa	482	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	483	__IO uint32_t tmpreg = 0x00; \
Kojto	107:4f6c30876dfa	484	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	107:4f6c30876dfa	485	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	486	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	107:4f6c30876dfa	487	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	488	} while(0)
Kojto	107:4f6c30876dfa	489
Kojto	107:4f6c30876dfa	490	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	107:4f6c30876dfa	491	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	107:4f6c30876dfa	492	/**
Kojto	107:4f6c30876dfa	493	* @}
Kojto	107:4f6c30876dfa	494	*/
Kojto	107:4f6c30876dfa	495
Kojto	107:4f6c30876dfa	496	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	107:4f6c30876dfa	497	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	107:4f6c30876dfa	498	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	499	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	500	* using it.
Kojto	107:4f6c30876dfa	501	* @{
Kojto	107:4f6c30876dfa	502	*/
Kojto	107:4f6c30876dfa	503	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	504	__IO uint32_t tmpreg = 0x00; \
Kojto	107:4f6c30876dfa	505	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	107:4f6c30876dfa	506	/* Delay after an RCC peripheral clock enabling */ \
Kojto	107:4f6c30876dfa	507	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	107:4f6c30876dfa	508	UNUSED(tmpreg); \
Kojto	107:4f6c30876dfa	509	} while(0)
Kojto	107:4f6c30876dfa	510
Kojto	107:4f6c30876dfa	511	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	107:4f6c30876dfa	512
Kojto	107:4f6c30876dfa	513	/**
Kojto	107:4f6c30876dfa	514	* @}
Kojto	107:4f6c30876dfa	515	*/
Kojto	107:4f6c30876dfa	516
Kojto	107:4f6c30876dfa	517	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
Kojto	107:4f6c30876dfa	518	* @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	107:4f6c30876dfa	519	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	520	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	521	* using it.
Kojto	107:4f6c30876dfa	522	* @{
Kojto	107:4f6c30876dfa	523	*/
Kojto	107:4f6c30876dfa	524	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
Kojto	107:4f6c30876dfa	525	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
Kojto	107:4f6c30876dfa	526
Kojto	107:4f6c30876dfa	527	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
Kojto	107:4f6c30876dfa	528	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
Kojto	107:4f6c30876dfa	529	/**
Kojto	107:4f6c30876dfa	530	* @}
Kojto	107:4f6c30876dfa	531	*/
Kojto	107:4f6c30876dfa	532
Kojto	107:4f6c30876dfa	533	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
Kojto	107:4f6c30876dfa	534	* @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	107:4f6c30876dfa	535	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	536	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	537	* using it.
Kojto	107:4f6c30876dfa	538	* @{
Kojto	107:4f6c30876dfa	539	*/
Kojto	107:4f6c30876dfa	540	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
Kojto	107:4f6c30876dfa	541	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
Kojto	107:4f6c30876dfa	542
Kojto	107:4f6c30876dfa	543	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
Kojto	107:4f6c30876dfa	544	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
Kojto	107:4f6c30876dfa	545	/**
Kojto	107:4f6c30876dfa	546	* @}
Kojto	107:4f6c30876dfa	547	*/
Kojto	107:4f6c30876dfa	548
Kojto	107:4f6c30876dfa	549	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
Kojto	107:4f6c30876dfa	550	* @brief EGet the enable or disable status of the APB2 peripheral clock.
Kojto	107:4f6c30876dfa	551	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	107:4f6c30876dfa	552	* is disabled and the application software has to enable this clock before
Kojto	107:4f6c30876dfa	553	* using it.
Kojto	107:4f6c30876dfa	554	* @{
Kojto	107:4f6c30876dfa	555	*/
Kojto	107:4f6c30876dfa	556	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
Kojto	107:4f6c30876dfa	557	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
Kojto	107:4f6c30876dfa	558	/**
Kojto	107:4f6c30876dfa	559	* @}
Kojto	107:4f6c30876dfa	560	*/
Kojto	107:4f6c30876dfa	561
Kojto	107:4f6c30876dfa	562	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
Kojto	107:4f6c30876dfa	563	* @brief Force or release AHB peripheral reset.
Kojto	107:4f6c30876dfa	564	* @{
Kojto	107:4f6c30876dfa	565	*/
Kojto	107:4f6c30876dfa	566	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	567	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	107:4f6c30876dfa	568	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
Kojto	107:4f6c30876dfa	569
Kojto	107:4f6c30876dfa	570	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto	107:4f6c30876dfa	571	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	107:4f6c30876dfa	572	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto	107:4f6c30876dfa	573	/**
Kojto	107:4f6c30876dfa	574	* @}
Kojto	107:4f6c30876dfa	575	*/
Kojto	107:4f6c30876dfa	576
Kojto	107:4f6c30876dfa	577	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	107:4f6c30876dfa	578	* @brief Force or release APB1 peripheral reset.
Kojto	107:4f6c30876dfa	579	* @{
Kojto	107:4f6c30876dfa	580	*/
Kojto	107:4f6c30876dfa	581	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	582	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	107:4f6c30876dfa	583	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	107:4f6c30876dfa	584
Kojto	107:4f6c30876dfa	585	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	107:4f6c30876dfa	586	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	107:4f6c30876dfa	587	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	107:4f6c30876dfa	588	/**
Kojto	107:4f6c30876dfa	589	* @}
Kojto	107:4f6c30876dfa	590	*/
Kojto	107:4f6c30876dfa	591
Kojto	107:4f6c30876dfa	592	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	107:4f6c30876dfa	593	* @brief Force or release APB2 peripheral reset.
Kojto	107:4f6c30876dfa	594	* @{
Kojto	107:4f6c30876dfa	595	*/
Kojto	107:4f6c30876dfa	596	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	107:4f6c30876dfa	597	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	107:4f6c30876dfa	598
Kojto	107:4f6c30876dfa	599	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	107:4f6c30876dfa	600	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	107:4f6c30876dfa	601
Kojto	107:4f6c30876dfa	602	/**
Kojto	107:4f6c30876dfa	603	* @}
Kojto	107:4f6c30876dfa	604	*/
Kojto	107:4f6c30876dfa	605
Kojto	107:4f6c30876dfa	606	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
Kojto	107:4f6c30876dfa	607	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	608	* power consumption.
Kojto	107:4f6c30876dfa	609	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	610	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	611	* @{
Kojto	107:4f6c30876dfa	612	*/
Kojto	107:4f6c30876dfa	613	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	107:4f6c30876dfa	614	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
Kojto	107:4f6c30876dfa	615
Kojto	107:4f6c30876dfa	616	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	107:4f6c30876dfa	617	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto	107:4f6c30876dfa	618
Kojto	107:4f6c30876dfa	619	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	620	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	621	* power consumption.
Kojto	107:4f6c30876dfa	622	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	623	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	624	*/
Kojto	107:4f6c30876dfa	625	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
Kojto	107:4f6c30876dfa	626	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
Kojto	107:4f6c30876dfa	627
Kojto	107:4f6c30876dfa	628	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto	107:4f6c30876dfa	629	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto	107:4f6c30876dfa	630
Kojto	107:4f6c30876dfa	631	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	632	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	633	* power consumption.
Kojto	107:4f6c30876dfa	634	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	635	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	636	*/
Kojto	107:4f6c30876dfa	637	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto	107:4f6c30876dfa	638	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto	107:4f6c30876dfa	639
Kojto	107:4f6c30876dfa	640	/**
Kojto	107:4f6c30876dfa	641	* @}
Kojto	107:4f6c30876dfa	642	*/
Kojto	107:4f6c30876dfa	643
Kojto	107:4f6c30876dfa	644	/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
Kojto	107:4f6c30876dfa	645	* @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	646	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	647	* power consumption.
Kojto	107:4f6c30876dfa	648	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	649	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	650	* @{
Kojto	107:4f6c30876dfa	651	*/
Kojto	107:4f6c30876dfa	652	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
Kojto	107:4f6c30876dfa	653	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
Kojto	107:4f6c30876dfa	654
Kojto	107:4f6c30876dfa	655	#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
Kojto	107:4f6c30876dfa	656	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
Kojto	107:4f6c30876dfa	657	/**
Kojto	107:4f6c30876dfa	658	* @}
Kojto	107:4f6c30876dfa	659	*/
Kojto	107:4f6c30876dfa	660
Kojto	107:4f6c30876dfa	661	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
Kojto	107:4f6c30876dfa	662	* @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	663	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	664	* power consumption.
Kojto	107:4f6c30876dfa	665	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	666	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	667	* @{
Kojto	107:4f6c30876dfa	668	*/
Kojto	107:4f6c30876dfa	669	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
Kojto	107:4f6c30876dfa	670	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
Kojto	107:4f6c30876dfa	671
Kojto	107:4f6c30876dfa	672	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
Kojto	107:4f6c30876dfa	673	#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
Kojto	107:4f6c30876dfa	674	/**
Kojto	107:4f6c30876dfa	675	* @}
Kojto	107:4f6c30876dfa	676	*/
Kojto	107:4f6c30876dfa	677
Kojto	107:4f6c30876dfa	678	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
Kojto	107:4f6c30876dfa	679	* @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	107:4f6c30876dfa	680	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	107:4f6c30876dfa	681	* power consumption.
Kojto	107:4f6c30876dfa	682	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	107:4f6c30876dfa	683	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	107:4f6c30876dfa	684	* @{
Kojto	107:4f6c30876dfa	685	*/
Kojto	107:4f6c30876dfa	686	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
Kojto	107:4f6c30876dfa	687	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
Kojto	107:4f6c30876dfa	688	/**
Kojto	107:4f6c30876dfa	689	* @}
Kojto	107:4f6c30876dfa	690	*/
Kojto	107:4f6c30876dfa	691
Kojto	107:4f6c30876dfa	692	/** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto	107:4f6c30876dfa	693	* @{
Kojto	107:4f6c30876dfa	694	*/
Kojto	107:4f6c30876dfa	695
Kojto	107:4f6c30876dfa	696	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	107:4f6c30876dfa	697	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	698	* It is used (enabled by hardware) as system clock source after startup
Kojto	107:4f6c30876dfa	699	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	107:4f6c30876dfa	700	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	107:4f6c30876dfa	701	* Security System CSS is enabled).
Kojto	107:4f6c30876dfa	702	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	107:4f6c30876dfa	703	* you have to select another source of the system clock then stop the HSI.
Kojto	107:4f6c30876dfa	704	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	107:4f6c30876dfa	705	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	107:4f6c30876dfa	706	* system clock source.
Kojto	107:4f6c30876dfa	707	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	107:4f6c30876dfa	708	* clock cycles.
Kojto	107:4f6c30876dfa	709	*/
Kojto	107:4f6c30876dfa	710	#define __HAL_RCC_HSI_ENABLE() (RCC->CR \|= (RCC_CR_HSION))
Kojto	107:4f6c30876dfa	711	#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
Kojto	107:4f6c30876dfa	712
Kojto	107:4f6c30876dfa	713	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	107:4f6c30876dfa	714	* @note The calibration is used to compensate for the variations in voltage
Kojto	107:4f6c30876dfa	715	* and temperature that influence the frequency of the internal HSI RC.
Kojto	107:4f6c30876dfa	716	* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
Kojto	107:4f6c30876dfa	717	* This parameter must be a number between 0 and 0x1F.
Kojto	107:4f6c30876dfa	718	*/
Kojto	107:4f6c30876dfa	719	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
Kojto	107:4f6c30876dfa	720	RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto	107:4f6c30876dfa	721	/**
Kojto	107:4f6c30876dfa	722	* @}
Kojto	107:4f6c30876dfa	723	*/
Kojto	107:4f6c30876dfa	724
Kojto	107:4f6c30876dfa	725	/** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto	107:4f6c30876dfa	726	* @{
Kojto	107:4f6c30876dfa	727	*/
Kojto	107:4f6c30876dfa	728
Kojto	107:4f6c30876dfa	729	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	107:4f6c30876dfa	730	* @note After enabling the LSI, the application software should wait on
Kojto	107:4f6c30876dfa	731	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	107:4f6c30876dfa	732	* be used to clock the IWDG and/or the RTC.
Kojto	107:4f6c30876dfa	733	* @note LSI can not be disabled if the IWDG is running.
Kojto	107:4f6c30876dfa	734	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	107:4f6c30876dfa	735	* clock cycles.
Kojto	107:4f6c30876dfa	736	*/
Kojto	107:4f6c30876dfa	737	#define __HAL_RCC_LSI_ENABLE() (RCC->CSR \|= (RCC_CSR_LSION))
Kojto	107:4f6c30876dfa	738	#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
Kojto	107:4f6c30876dfa	739	/**
Kojto	107:4f6c30876dfa	740	* @}
Kojto	107:4f6c30876dfa	741	*/
Kojto	107:4f6c30876dfa	742
Kojto	107:4f6c30876dfa	743	/** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto	107:4f6c30876dfa	744	* @{
Kojto	107:4f6c30876dfa	745	*/
Kojto	107:4f6c30876dfa	746	/**
Kojto	107:4f6c30876dfa	747	* @brief Macro to configure the External High Speed oscillator (__HSE__).
Kojto	107:4f6c30876dfa	748	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	107:4f6c30876dfa	749	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	107:4f6c30876dfa	750	* is stable and can be used to clock the PLL and/or system clock.
Kojto	107:4f6c30876dfa	751	* @note HSE state can not be changed if it is used directly or through the
Kojto	107:4f6c30876dfa	752	* PLL as system clock. In this case, you have to select another source
Kojto	107:4f6c30876dfa	753	* of the system clock then change the HSE state (ex. disable it).
Kojto	107:4f6c30876dfa	754	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	755	* @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto	107:4f6c30876dfa	756	* was previously enabled you have to enable it again after calling this
Kojto	107:4f6c30876dfa	757	* function.
Kojto	107:4f6c30876dfa	758	* @param __STATE__: specifies the new state of the HSE.
Kojto	107:4f6c30876dfa	759	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	760	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	107:4f6c30876dfa	761	* 6 HSE oscillator clock cycles.
Kojto	107:4f6c30876dfa	762	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto	107:4f6c30876dfa	763	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto	107:4f6c30876dfa	764	*/
Kojto	107:4f6c30876dfa	765	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
Kojto	107:4f6c30876dfa	766	do { \
Kojto	107:4f6c30876dfa	767	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	768	if((__STATE__) == RCC_HSE_ON) \
Kojto	107:4f6c30876dfa	769	{ \
Kojto	107:4f6c30876dfa	770	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	107:4f6c30876dfa	771	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	772	} \
Kojto	107:4f6c30876dfa	773	else if((__STATE__) == RCC_HSE_BYPASS) \
Kojto	107:4f6c30876dfa	774	{ \
Kojto	107:4f6c30876dfa	775	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	107:4f6c30876dfa	776	SET_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	777	} \
Kojto	107:4f6c30876dfa	778	else \
Kojto	107:4f6c30876dfa	779	{ \
Kojto	107:4f6c30876dfa	780	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
Kojto	107:4f6c30876dfa	781	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
Kojto	107:4f6c30876dfa	782	} \
Kojto	107:4f6c30876dfa	783	} while(0)
Kojto	107:4f6c30876dfa	784	/**
Kojto	107:4f6c30876dfa	785	* @}
Kojto	107:4f6c30876dfa	786	*/
Kojto	107:4f6c30876dfa	787
Kojto	107:4f6c30876dfa	788	/** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto	107:4f6c30876dfa	789	* @{
Kojto	107:4f6c30876dfa	790	*/
Kojto	107:4f6c30876dfa	791
Kojto	107:4f6c30876dfa	792	/**
Kojto	107:4f6c30876dfa	793	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	107:4f6c30876dfa	794	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto	107:4f6c30876dfa	795	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto	107:4f6c30876dfa	796	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	107:4f6c30876dfa	797	* this domain after reset, you have to enable write access using
Kojto	107:4f6c30876dfa	798	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	107:4f6c30876dfa	799	* (to be done once after reset).
Kojto	107:4f6c30876dfa	800	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	107:4f6c30876dfa	801	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	107:4f6c30876dfa	802	* is stable and can be used to clock the RTC.
Kojto	107:4f6c30876dfa	803	* @param __STATE__: specifies the new state of the LSE.
Kojto	107:4f6c30876dfa	804	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	805	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	107:4f6c30876dfa	806	* 6 LSE oscillator clock cycles.
Kojto	107:4f6c30876dfa	807	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	107:4f6c30876dfa	808	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto	107:4f6c30876dfa	809	*/
Kojto	107:4f6c30876dfa	810	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	107:4f6c30876dfa	811	do { \
Kojto	107:4f6c30876dfa	812	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	813	if((__STATE__) == RCC_LSE_ON) \
Kojto	107:4f6c30876dfa	814	{ \
Kojto	107:4f6c30876dfa	815	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	107:4f6c30876dfa	816	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	817	} \
Kojto	107:4f6c30876dfa	818	else if((__STATE__) == RCC_LSE_BYPASS) \
Kojto	107:4f6c30876dfa	819	{ \
Kojto	107:4f6c30876dfa	820	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	107:4f6c30876dfa	821	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	822	} \
Kojto	107:4f6c30876dfa	823	else \
Kojto	107:4f6c30876dfa	824	{ \
Kojto	107:4f6c30876dfa	825	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
Kojto	107:4f6c30876dfa	826	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
Kojto	107:4f6c30876dfa	827	} \
Kojto	107:4f6c30876dfa	828	} while(0)
Kojto	107:4f6c30876dfa	829	/**
Kojto	107:4f6c30876dfa	830	* @}
Kojto	107:4f6c30876dfa	831	*/
Kojto	107:4f6c30876dfa	832
Kojto	107:4f6c30876dfa	833	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto	107:4f6c30876dfa	834	* @{
Kojto	107:4f6c30876dfa	835	*/
Kojto	107:4f6c30876dfa	836
Kojto	107:4f6c30876dfa	837	/** @brief Macros to enable or disable the RTC clock.
Kojto	107:4f6c30876dfa	838	* @note These macros must be used only after the RTC clock source was selected.
Kojto	107:4f6c30876dfa	839	*/
Kojto	107:4f6c30876dfa	840	#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR \|= (RCC_BDCR_RTCEN))
Kojto	107:4f6c30876dfa	841	#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
Kojto	107:4f6c30876dfa	842
Kojto	107:4f6c30876dfa	843	/** @brief Macros to configure the RTC clock (RTCCLK).
Kojto	107:4f6c30876dfa	844	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	107:4f6c30876dfa	845	* access is denied to this domain after reset, you have to enable write
Kojto	107:4f6c30876dfa	846	* access using the Power Backup Access macro before to configure
Kojto	107:4f6c30876dfa	847	* the RTC clock source (to be done once after reset).
Kojto	107:4f6c30876dfa	848	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	107:4f6c30876dfa	849	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto	107:4f6c30876dfa	850	* a Power On Reset (POR).
Kojto	107:4f6c30876dfa	851	* @param __RTCCLKSource__: specifies the RTC clock source.
Kojto	107:4f6c30876dfa	852	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	853	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto	107:4f6c30876dfa	854	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto	107:4f6c30876dfa	855	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto	107:4f6c30876dfa	856	* as RTC clock, where x:[2,31]
Kojto	107:4f6c30876dfa	857	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	107:4f6c30876dfa	858	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	107:4f6c30876dfa	859	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	107:4f6c30876dfa	860	* cannot be used in STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	861	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	107:4f6c30876dfa	862	* RTC clock source).
Kojto	107:4f6c30876dfa	863	*/
Kojto	107:4f6c30876dfa	864	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto	107:4f6c30876dfa	865	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto	107:4f6c30876dfa	866
Kojto	107:4f6c30876dfa	867	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto	107:4f6c30876dfa	868	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto	107:4f6c30876dfa	869	} while (0)
Kojto	107:4f6c30876dfa	870
Kojto	107:4f6c30876dfa	871	/** @brief Macros to force or release the Backup domain reset.
Kojto	107:4f6c30876dfa	872	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	107:4f6c30876dfa	873	* and the RTC clock source selection in RCC_CSR register.
Kojto	107:4f6c30876dfa	874	* @note The BKPSRAM is not affected by this reset.
Kojto	107:4f6c30876dfa	875	*/
Kojto	107:4f6c30876dfa	876	#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR \|= (RCC_BDCR_BDRST))
Kojto	107:4f6c30876dfa	877	#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
Kojto	107:4f6c30876dfa	878	/**
Kojto	107:4f6c30876dfa	879	* @}
Kojto	107:4f6c30876dfa	880	*/
Kojto	107:4f6c30876dfa	881
Kojto	107:4f6c30876dfa	882	/** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto	107:4f6c30876dfa	883	* @{
Kojto	107:4f6c30876dfa	884	*/
Kojto	107:4f6c30876dfa	885
Kojto	107:4f6c30876dfa	886	/** @brief Macros to enable or disable the main PLL.
Kojto	107:4f6c30876dfa	887	* @note After enabling the main PLL, the application software should wait on
Kojto	107:4f6c30876dfa	888	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	107:4f6c30876dfa	889	* be used as system clock source.
Kojto	107:4f6c30876dfa	890	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	107:4f6c30876dfa	891	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	892	*/
Kojto	107:4f6c30876dfa	893	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	107:4f6c30876dfa	894	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	107:4f6c30876dfa	895
Kojto	107:4f6c30876dfa	896
Kojto	107:4f6c30876dfa	897	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	107:4f6c30876dfa	898	* @note This function must be used only when the main PLL is disabled.
Kojto	107:4f6c30876dfa	899	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	107:4f6c30876dfa	900	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	901	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	902	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	903	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	107:4f6c30876dfa	904	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	107:4f6c30876dfa	905	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	107:4f6c30876dfa	906	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	107:4f6c30876dfa	907	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	107:4f6c30876dfa	908	* of 2 MHz to limit PLL jitter.
Kojto	107:4f6c30876dfa	909	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	116:c0f6e94411f5	910	* This parameter must be a number between Min_Data = 100 and Max_Data = 432.
Kojto	107:4f6c30876dfa	911	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	116:c0f6e94411f5	912	* output frequency is between 100 and 432 MHz.
Kojto	107:4f6c30876dfa	913	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	107:4f6c30876dfa	914	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	107:4f6c30876dfa	915	* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
Kojto	107:4f6c30876dfa	916	* the System clock frequency.
Kojto	107:4f6c30876dfa	917	* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
Kojto	107:4f6c30876dfa	918	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	107:4f6c30876dfa	919	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	107:4f6c30876dfa	920	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	107:4f6c30876dfa	921	* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	107:4f6c30876dfa	922	* correctly.
Kojto	107:4f6c30876dfa	923	*/
Kojto	107:4f6c30876dfa	924	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
Kojto	107:4f6c30876dfa	925	(RCC->PLLCFGR = (0x20000000 \| (__PLLM__) \| ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	107:4f6c30876dfa	926	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| (__RCC_PLLSource__) \| \
Kojto	107:4f6c30876dfa	927	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	107:4f6c30876dfa	928
Kojto	107:4f6c30876dfa	929	/** @brief Macro to configure the PLL clock source.
Kojto	107:4f6c30876dfa	930	* @note This function must be used only when the main PLL is disabled.
Kojto	107:4f6c30876dfa	931	* @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto	107:4f6c30876dfa	932	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	933	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	934	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	107:4f6c30876dfa	935	*
Kojto	107:4f6c30876dfa	936	*/
Kojto	107:4f6c30876dfa	937	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto	107:4f6c30876dfa	938
Kojto	107:4f6c30876dfa	939	/** @brief Macro to configure the PLL multiplication factor.
Kojto	107:4f6c30876dfa	940	* @note This function must be used only when the main PLL is disabled.
Kojto	107:4f6c30876dfa	941	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	107:4f6c30876dfa	942	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	107:4f6c30876dfa	943	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	107:4f6c30876dfa	944	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	107:4f6c30876dfa	945	* of 2 MHz to limit PLL jitter.
Kojto	107:4f6c30876dfa	946	*
Kojto	107:4f6c30876dfa	947	*/
Kojto	107:4f6c30876dfa	948	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto	107:4f6c30876dfa	949	/**
Kojto	107:4f6c30876dfa	950	* @}
Kojto	107:4f6c30876dfa	951	*/
Kojto	107:4f6c30876dfa	952
Kojto	107:4f6c30876dfa	953	/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
Kojto	107:4f6c30876dfa	954	* @{
Kojto	107:4f6c30876dfa	955	*/
Kojto	107:4f6c30876dfa	956
Kojto	107:4f6c30876dfa	957	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	107:4f6c30876dfa	958	* @note This function must be called before enabling the I2S APB clock.
Kojto	107:4f6c30876dfa	959	* @param __SOURCE__: specifies the I2S clock source.
Kojto	107:4f6c30876dfa	960	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	961	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	107:4f6c30876dfa	962	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	107:4f6c30876dfa	963	* used as I2S clock source.
Kojto	107:4f6c30876dfa	964	*/
Kojto	107:4f6c30876dfa	965	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
Kojto	116:c0f6e94411f5	966	RCC->CFGR \|= (__SOURCE__); \
Kojto	116:c0f6e94411f5	967	}while(0)
Kojto	107:4f6c30876dfa	968
Kojto	107:4f6c30876dfa	969	/** @brief Macros to enable or disable the PLLI2S.
Kojto	107:4f6c30876dfa	970	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto	107:4f6c30876dfa	971	*/
Kojto	107:4f6c30876dfa	972	#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR \|= (RCC_CR_PLLI2SON))
Kojto	107:4f6c30876dfa	973	#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
Kojto	107:4f6c30876dfa	974	/**
Kojto	107:4f6c30876dfa	975	* @}
Kojto	107:4f6c30876dfa	976	*/
Kojto	107:4f6c30876dfa	977
Kojto	107:4f6c30876dfa	978	/** @defgroup RCC_Get_Clock_source Get Clock source
Kojto	107:4f6c30876dfa	979	* @{
Kojto	107:4f6c30876dfa	980	*/
Kojto	107:4f6c30876dfa	981	/**
Kojto	107:4f6c30876dfa	982	* @brief Macro to configure the system clock source.
Kojto	107:4f6c30876dfa	983	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto	107:4f6c30876dfa	984	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	985	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto	107:4f6c30876dfa	986	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto	107:4f6c30876dfa	987	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto	107:4f6c30876dfa	988	*/
Kojto	107:4f6c30876dfa	989	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto	107:4f6c30876dfa	990
Kojto	107:4f6c30876dfa	991	/** @brief Macro to get the clock source used as system clock.
Kojto	107:4f6c30876dfa	992	* @retval The clock source used as system clock. The returned value can be one
Kojto	107:4f6c30876dfa	993	* of the following:
Kojto	107:4f6c30876dfa	994	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto	107:4f6c30876dfa	995	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto	107:4f6c30876dfa	996	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto	107:4f6c30876dfa	997	*/
Kojto	107:4f6c30876dfa	998	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto	107:4f6c30876dfa	999
Kojto	107:4f6c30876dfa	1000	/**
Kojto	107:4f6c30876dfa	1001	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
Kojto	107:4f6c30876dfa	1002	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	107:4f6c30876dfa	1003	* this domain after reset, you have to enable write access using
Kojto	107:4f6c30876dfa	1004	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	107:4f6c30876dfa	1005	* (to be done once after reset).
Kojto	107:4f6c30876dfa	1006	* @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
Kojto	107:4f6c30876dfa	1007	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	1008	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
Kojto	107:4f6c30876dfa	1009	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
Kojto	107:4f6c30876dfa	1010	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
Kojto	107:4f6c30876dfa	1011	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Kojto	107:4f6c30876dfa	1012	* @retval None
Kojto	107:4f6c30876dfa	1013	*/
Kojto	107:4f6c30876dfa	1014	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
Kojto	107:4f6c30876dfa	1015	(MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
Kojto	107:4f6c30876dfa	1016
Kojto	107:4f6c30876dfa	1017	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	107:4f6c30876dfa	1018	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	107:4f6c30876dfa	1019	* of the following:
Kojto	107:4f6c30876dfa	1020	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	107:4f6c30876dfa	1021	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	107:4f6c30876dfa	1022	*/
Kojto	107:4f6c30876dfa	1023	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto	107:4f6c30876dfa	1024	/**
Kojto	107:4f6c30876dfa	1025	* @}
Kojto	107:4f6c30876dfa	1026	*/
Kojto	116:c0f6e94411f5	1027
Kojto	116:c0f6e94411f5	1028	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	116:c0f6e94411f5	1029	* @{
Kojto	116:c0f6e94411f5	1030	*/
Kojto	116:c0f6e94411f5	1031
Kojto	116:c0f6e94411f5	1032	/** @brief Macro to configure the MCO1 clock.
Kojto	116:c0f6e94411f5	1033	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	116:c0f6e94411f5	1034	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1035	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto	116:c0f6e94411f5	1036	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto	116:c0f6e94411f5	1037	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto	116:c0f6e94411f5	1038	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto	116:c0f6e94411f5	1039	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	116:c0f6e94411f5	1040	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1041	* @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto	116:c0f6e94411f5	1042	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto	116:c0f6e94411f5	1043	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto	116:c0f6e94411f5	1044	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto	116:c0f6e94411f5	1045	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto	116:c0f6e94411f5	1046	*/
Kojto	107:4f6c30876dfa	1047
Kojto	116:c0f6e94411f5	1048	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	116:c0f6e94411f5	1049	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
Kojto	116:c0f6e94411f5	1050
Kojto	116:c0f6e94411f5	1051	/** @brief Macro to configure the MCO2 clock.
Kojto	116:c0f6e94411f5	1052	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	116:c0f6e94411f5	1053	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1054	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto	116:c0f6e94411f5	1055	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
Kojto	116:c0f6e94411f5	1056	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto	116:c0f6e94411f5	1057	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto	116:c0f6e94411f5	1058	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	116:c0f6e94411f5	1059	* This parameter can be one of the following values:
Kojto	116:c0f6e94411f5	1060	* @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto	116:c0f6e94411f5	1061	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto	116:c0f6e94411f5	1062	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto	116:c0f6e94411f5	1063	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto	116:c0f6e94411f5	1064	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto	116:c0f6e94411f5	1065	*/
Kojto	116:c0f6e94411f5	1066
Kojto	116:c0f6e94411f5	1067	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	116:c0f6e94411f5	1068	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3)));
Kojto	116:c0f6e94411f5	1069	/**
Kojto	116:c0f6e94411f5	1070	* @}
Kojto	116:c0f6e94411f5	1071	*/
Kojto	116:c0f6e94411f5	1072
Kojto	107:4f6c30876dfa	1073	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto	107:4f6c30876dfa	1074	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	107:4f6c30876dfa	1075	* @{
Kojto	107:4f6c30876dfa	1076	*/
Kojto	107:4f6c30876dfa	1077
Kojto	107:4f6c30876dfa	1078	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	107:4f6c30876dfa	1079	* the selected interrupts).
Kojto	107:4f6c30876dfa	1080	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	107:4f6c30876dfa	1081	* This parameter can be any combination of the following values:
Kojto	107:4f6c30876dfa	1082	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	107:4f6c30876dfa	1083	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	107:4f6c30876dfa	1084	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	107:4f6c30876dfa	1085	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	107:4f6c30876dfa	1086	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	107:4f6c30876dfa	1087	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	107:4f6c30876dfa	1088	*/
Kojto	107:4f6c30876dfa	1089	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	107:4f6c30876dfa	1090
Kojto	107:4f6c30876dfa	1091	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	107:4f6c30876dfa	1092	* the selected interrupts).
Kojto	107:4f6c30876dfa	1093	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	107:4f6c30876dfa	1094	* This parameter can be any combination of the following values:
Kojto	107:4f6c30876dfa	1095	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	107:4f6c30876dfa	1096	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	107:4f6c30876dfa	1097	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	107:4f6c30876dfa	1098	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	107:4f6c30876dfa	1099	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	107:4f6c30876dfa	1100	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	107:4f6c30876dfa	1101	*/
Kojto	107:4f6c30876dfa	1102	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	107:4f6c30876dfa	1103
Kojto	107:4f6c30876dfa	1104	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto	107:4f6c30876dfa	1105	* bits to clear the selected interrupt pending bits.
Kojto	107:4f6c30876dfa	1106	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	107:4f6c30876dfa	1107	* This parameter can be any combination of the following values:
Kojto	107:4f6c30876dfa	1108	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	107:4f6c30876dfa	1109	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	107:4f6c30876dfa	1110	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	107:4f6c30876dfa	1111	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	107:4f6c30876dfa	1112	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	107:4f6c30876dfa	1113	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	107:4f6c30876dfa	1114	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	107:4f6c30876dfa	1115	*/
Kojto	107:4f6c30876dfa	1116	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto	107:4f6c30876dfa	1117
Kojto	107:4f6c30876dfa	1118	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	107:4f6c30876dfa	1119	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	107:4f6c30876dfa	1120	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	1121	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	107:4f6c30876dfa	1122	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	107:4f6c30876dfa	1123	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	107:4f6c30876dfa	1124	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	107:4f6c30876dfa	1125	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	107:4f6c30876dfa	1126	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	107:4f6c30876dfa	1127	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	107:4f6c30876dfa	1128	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	107:4f6c30876dfa	1129	*/
Kojto	107:4f6c30876dfa	1130	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	107:4f6c30876dfa	1131
Kojto	107:4f6c30876dfa	1132	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto	107:4f6c30876dfa	1133	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto	107:4f6c30876dfa	1134	*/
Kojto	107:4f6c30876dfa	1135	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	107:4f6c30876dfa	1136
Kojto	107:4f6c30876dfa	1137	/** @brief Check RCC flag is set or not.
Kojto	107:4f6c30876dfa	1138	* @param __FLAG__: specifies the flag to check.
Kojto	107:4f6c30876dfa	1139	* This parameter can be one of the following values:
Kojto	107:4f6c30876dfa	1140	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	107:4f6c30876dfa	1141	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	107:4f6c30876dfa	1142	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto	107:4f6c30876dfa	1143	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto	107:4f6c30876dfa	1144	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	107:4f6c30876dfa	1145	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto	107:4f6c30876dfa	1146	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto	107:4f6c30876dfa	1147	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	107:4f6c30876dfa	1148	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	107:4f6c30876dfa	1149	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	107:4f6c30876dfa	1150	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	107:4f6c30876dfa	1151	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	107:4f6c30876dfa	1152	* @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto	107:4f6c30876dfa	1153	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	107:4f6c30876dfa	1154	*/
Kojto	107:4f6c30876dfa	1155	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	107:4f6c30876dfa	1156	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto	107:4f6c30876dfa	1157
Kojto	107:4f6c30876dfa	1158	/**
Kojto	107:4f6c30876dfa	1159	* @}
Kojto	107:4f6c30876dfa	1160	*/
Kojto	107:4f6c30876dfa	1161
Kojto	107:4f6c30876dfa	1162	/**
Kojto	107:4f6c30876dfa	1163	* @}
Kojto	107:4f6c30876dfa	1164	*/
Kojto	107:4f6c30876dfa	1165
Kojto	107:4f6c30876dfa	1166	/* Include RCC HAL Extension module */
Kojto	107:4f6c30876dfa	1167	#include "stm32f7xx_hal_rcc_ex.h"
Kojto	107:4f6c30876dfa	1168
Kojto	107:4f6c30876dfa	1169	/* Exported functions --------------------------------------------------------*/
Kojto	107:4f6c30876dfa	1170	/** @addtogroup RCC_Exported_Functions
Kojto	107:4f6c30876dfa	1171	* @{
Kojto	107:4f6c30876dfa	1172	*/
Kojto	107:4f6c30876dfa	1173
Kojto	107:4f6c30876dfa	1174	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	107:4f6c30876dfa	1175	* @{
Kojto	107:4f6c30876dfa	1176	*/
Kojto	107:4f6c30876dfa	1177	/* Initialization and de-initialization functions ******************************/
Kojto	107:4f6c30876dfa	1178	void HAL_RCC_DeInit(void);
Kojto	107:4f6c30876dfa	1179	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	107:4f6c30876dfa	1180	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	107:4f6c30876dfa	1181	/**
Kojto	107:4f6c30876dfa	1182	* @}
Kojto	107:4f6c30876dfa	1183	*/
Kojto	107:4f6c30876dfa	1184
Kojto	107:4f6c30876dfa	1185	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	107:4f6c30876dfa	1186	* @{
Kojto	107:4f6c30876dfa	1187	*/
Kojto	107:4f6c30876dfa	1188	/* Peripheral Control functions ************************************************/
Kojto	107:4f6c30876dfa	1189	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	107:4f6c30876dfa	1190	void HAL_RCC_EnableCSS(void);
Kojto	107:4f6c30876dfa	1191	void HAL_RCC_DisableCSS(void);
Kojto	107:4f6c30876dfa	1192	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	107:4f6c30876dfa	1193	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	107:4f6c30876dfa	1194	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	107:4f6c30876dfa	1195	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	107:4f6c30876dfa	1196	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	107:4f6c30876dfa	1197	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	107:4f6c30876dfa	1198
Kojto	107:4f6c30876dfa	1199	/* CSS NMI IRQ handler */
Kojto	107:4f6c30876dfa	1200	void HAL_RCC_NMI_IRQHandler(void);
Kojto	107:4f6c30876dfa	1201
Kojto	107:4f6c30876dfa	1202	/* User Callbacks in non blocking mode (IT mode) */
Kojto	107:4f6c30876dfa	1203	void HAL_RCC_CSSCallback(void);
Kojto	107:4f6c30876dfa	1204	/**
Kojto	107:4f6c30876dfa	1205	* @}
Kojto	107:4f6c30876dfa	1206	*/
Kojto	107:4f6c30876dfa	1207
Kojto	107:4f6c30876dfa	1208	/**
Kojto	107:4f6c30876dfa	1209	* @}
Kojto	107:4f6c30876dfa	1210	*/
Kojto	107:4f6c30876dfa	1211
Kojto	107:4f6c30876dfa	1212	/* Private types -------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	1213	/* Private variables ---------------------------------------------------------*/
Kojto	107:4f6c30876dfa	1214	/* Private constants ---------------------------------------------------------*/
Kojto	107:4f6c30876dfa	1215	/** @defgroup RCC_Private_Constants RCC Private Constants
Kojto	107:4f6c30876dfa	1216	* @{
Kojto	107:4f6c30876dfa	1217	*/
Kojto	107:4f6c30876dfa	1218	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto	107:4f6c30876dfa	1219	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	107:4f6c30876dfa	1220	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	107:4f6c30876dfa	1221	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	107:4f6c30876dfa	1222	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	107:4f6c30876dfa	1223
Kojto	107:4f6c30876dfa	1224	/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
Kojto	107:4f6c30876dfa	1225	* @brief RCC registers bit address alias
Kojto	107:4f6c30876dfa	1226	* @{
Kojto	107:4f6c30876dfa	1227	*/
Kojto	107:4f6c30876dfa	1228	/* CIR register byte 2 (Bits[15:8]) base address */
Kojto	107:4f6c30876dfa	1229	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto	107:4f6c30876dfa	1230
Kojto	107:4f6c30876dfa	1231	/* CIR register byte 3 (Bits[23:16]) base address */
Kojto	107:4f6c30876dfa	1232	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto	107:4f6c30876dfa	1233
Kojto	107:4f6c30876dfa	1234	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	107:4f6c30876dfa	1235	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
Kojto	107:4f6c30876dfa	1236	/**
Kojto	107:4f6c30876dfa	1237	* @}
Kojto	107:4f6c30876dfa	1238	*/
Kojto	107:4f6c30876dfa	1239	/**
Kojto	107:4f6c30876dfa	1240	* @}
Kojto	107:4f6c30876dfa	1241	*/
Kojto	107:4f6c30876dfa	1242
Kojto	107:4f6c30876dfa	1243	/* Private macros ------------------------------------------------------------*/
Kojto	107:4f6c30876dfa	1244	/** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto	107:4f6c30876dfa	1245	* @{
Kojto	107:4f6c30876dfa	1246	*/
Kojto	107:4f6c30876dfa	1247
Kojto	107:4f6c30876dfa	1248	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	107:4f6c30876dfa	1249	* @{
Kojto	107:4f6c30876dfa	1250	*/
Kojto	107:4f6c30876dfa	1251	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto	107:4f6c30876dfa	1252
Kojto	107:4f6c30876dfa	1253	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
Kojto	107:4f6c30876dfa	1254	((HSE) == RCC_HSE_BYPASS))
Kojto	107:4f6c30876dfa	1255
Kojto	107:4f6c30876dfa	1256	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
Kojto	107:4f6c30876dfa	1257	((LSE) == RCC_LSE_BYPASS))
Kojto	107:4f6c30876dfa	1258
Kojto	107:4f6c30876dfa	1259	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
Kojto	107:4f6c30876dfa	1260
Kojto	107:4f6c30876dfa	1261	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
Kojto	107:4f6c30876dfa	1262
Kojto	107:4f6c30876dfa	1263	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
Kojto	107:4f6c30876dfa	1264
Kojto	107:4f6c30876dfa	1265	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	107:4f6c30876dfa	1266	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	107:4f6c30876dfa	1267
Kojto	107:4f6c30876dfa	1268	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	107:4f6c30876dfa	1269	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	107:4f6c30876dfa	1270	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	107:4f6c30876dfa	1271	#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
Kojto	107:4f6c30876dfa	1272
Kojto	116:c0f6e94411f5	1273	#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
Kojto	107:4f6c30876dfa	1274
Kojto	107:4f6c30876dfa	1275	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) \|\| ((VALUE) == RCC_PLLP_DIV4) \|\| \
Kojto	107:4f6c30876dfa	1276	((VALUE) == RCC_PLLP_DIV6) \|\| ((VALUE) == RCC_PLLP_DIV8))
Kojto	107:4f6c30876dfa	1277	#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	107:4f6c30876dfa	1278
Kojto	107:4f6c30876dfa	1279	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
Kojto	107:4f6c30876dfa	1280	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
Kojto	107:4f6c30876dfa	1281	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
Kojto	107:4f6c30876dfa	1282	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
Kojto	107:4f6c30876dfa	1283	((HCLK) == RCC_SYSCLK_DIV512))
Kojto	107:4f6c30876dfa	1284
Kojto	107:4f6c30876dfa	1285	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto	107:4f6c30876dfa	1286
Kojto	107:4f6c30876dfa	1287	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
Kojto	107:4f6c30876dfa	1288	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
Kojto	107:4f6c30876dfa	1289	((PCLK) == RCC_HCLK_DIV16))
Kojto	107:4f6c30876dfa	1290
Kojto	107:4f6c30876dfa	1291	#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) \|\| ((MCOX) == RCC_MCO2))
Kojto	107:4f6c30876dfa	1292
Kojto	107:4f6c30876dfa	1293
Kojto	107:4f6c30876dfa	1294	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	107:4f6c30876dfa	1295	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto	107:4f6c30876dfa	1296
Kojto	107:4f6c30876dfa	1297	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
Kojto	107:4f6c30876dfa	1298	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	107:4f6c30876dfa	1299
Kojto	107:4f6c30876dfa	1300	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
Kojto	107:4f6c30876dfa	1301	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
Kojto	107:4f6c30876dfa	1302	((DIV) == RCC_MCODIV_5))
Kojto	107:4f6c30876dfa	1303	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto	107:4f6c30876dfa	1304
Kojto	107:4f6c30876dfa	1305	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	107:4f6c30876dfa	1306	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
Kojto	107:4f6c30876dfa	1307	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
Kojto	107:4f6c30876dfa	1308	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
Kojto	107:4f6c30876dfa	1309	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
Kojto	107:4f6c30876dfa	1310	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
Kojto	107:4f6c30876dfa	1311	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
Kojto	107:4f6c30876dfa	1312	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
Kojto	107:4f6c30876dfa	1313	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
Kojto	107:4f6c30876dfa	1314	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
Kojto	107:4f6c30876dfa	1315	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
Kojto	107:4f6c30876dfa	1316	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
Kojto	107:4f6c30876dfa	1317	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
Kojto	107:4f6c30876dfa	1318	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
Kojto	107:4f6c30876dfa	1319	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
Kojto	107:4f6c30876dfa	1320	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
Kojto	107:4f6c30876dfa	1321
Kojto	107:4f6c30876dfa	1322
Kojto	107:4f6c30876dfa	1323	#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) \|\| \
Kojto	116:c0f6e94411f5	1324	((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
Kojto	116:c0f6e94411f5	1325	((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| \
Kojto	116:c0f6e94411f5	1326	((DRIVE) == RCC_LSEDRIVE_HIGH))
Kojto	107:4f6c30876dfa	1327	/**
Kojto	107:4f6c30876dfa	1328	* @}
Kojto	107:4f6c30876dfa	1329	*/
Kojto	107:4f6c30876dfa	1330
Kojto	107:4f6c30876dfa	1331	/**
Kojto	107:4f6c30876dfa	1332	* @}
Kojto	107:4f6c30876dfa	1333	*/
Kojto	107:4f6c30876dfa	1334
Kojto	107:4f6c30876dfa	1335	/**
Kojto	107:4f6c30876dfa	1336	* @}
Kojto	107:4f6c30876dfa	1337	*/
Kojto	107:4f6c30876dfa	1338
Kojto	107:4f6c30876dfa	1339	/**
Kojto	107:4f6c30876dfa	1340	* @}
Kojto	107:4f6c30876dfa	1341	*/
Kojto	107:4f6c30876dfa	1342
Kojto	107:4f6c30876dfa	1343	#ifdef __cplusplus
Kojto	107:4f6c30876dfa	1344	}
Kojto	107:4f6c30876dfa	1345	#endif
Kojto	107:4f6c30876dfa	1346
Kojto	107:4f6c30876dfa	1347	#endif /* __STM32F7xx_HAL_RCC_H */
Kojto	107:4f6c30876dfa	1348
Kojto	107:4f6c30876dfa	1349	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_DISCO_F746NG/stm32f7xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

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