Elijah Orr / mbed-renbed

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TARGET_DISCO_F746NG/stm32f746xx.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:
elijahorr
Date:
Thu Apr 14 07:28:54 2016 +0000
Revision:
121:672067c3ada4
Parent:
116:c0f6e94411f5 
.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 107:4f6c30876dfa 1 /**
Kojto 107:4f6c30876dfa 2 ******************************************************************************
Kojto 107:4f6c30876dfa 3 * @file stm32f746xx.h
Kojto 107:4f6c30876dfa 4 * @author MCD Application Team
Kojto 116:c0f6e94411f5 5 * @version V1.0.2
Kojto 116:c0f6e94411f5 6 * @date 21-September-2015
Kojto 107:4f6c30876dfa 7 * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File.
Kojto 107:4f6c30876dfa 8 *
Kojto 107:4f6c30876dfa 9 * This file contains:
Kojto 107:4f6c30876dfa 10 * - Data structures and the address mapping for all peripherals
Kojto 107:4f6c30876dfa 11 * - Peripheral's registers declarations and bits definition
Kojto 107:4f6c30876dfa 12 * - Macros to access peripheral’s registers hardware
Kojto 107:4f6c30876dfa 13 *
Kojto 107:4f6c30876dfa 14 ******************************************************************************
Kojto 107:4f6c30876dfa 15 * @attention
Kojto 107:4f6c30876dfa 16 *
Kojto 116:c0f6e94411f5 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 107:4f6c30876dfa 18 *
Kojto 107:4f6c30876dfa 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 107:4f6c30876dfa 20 * are permitted provided that the following conditions are met:
Kojto 107:4f6c30876dfa 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 107:4f6c30876dfa 22 * this list of conditions and the following disclaimer.
Kojto 107:4f6c30876dfa 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 107:4f6c30876dfa 24 * this list of conditions and the following disclaimer in the documentation
Kojto 107:4f6c30876dfa 25 * and/or other materials provided with the distribution.
Kojto 107:4f6c30876dfa 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 107:4f6c30876dfa 27 * may be used to endorse or promote products derived from this software
Kojto 107:4f6c30876dfa 28 * without specific prior written permission.
Kojto 107:4f6c30876dfa 29 *
Kojto 107:4f6c30876dfa 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 107:4f6c30876dfa 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 107:4f6c30876dfa 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 107:4f6c30876dfa 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 107:4f6c30876dfa 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 107:4f6c30876dfa 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 107:4f6c30876dfa 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 107:4f6c30876dfa 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 107:4f6c30876dfa 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 107:4f6c30876dfa 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 107:4f6c30876dfa 40 *
Kojto 107:4f6c30876dfa 41 ******************************************************************************
Kojto 107:4f6c30876dfa 42 */
Kojto 107:4f6c30876dfa 43
Kojto 107:4f6c30876dfa 44 /** @addtogroup CMSIS_Device
Kojto 107:4f6c30876dfa 45 * @{
Kojto 107:4f6c30876dfa 46 */
Kojto 107:4f6c30876dfa 47
Kojto 107:4f6c30876dfa 48 /** @addtogroup stm32f746xx
Kojto 107:4f6c30876dfa 49 * @{
Kojto 107:4f6c30876dfa 50 */
Kojto 107:4f6c30876dfa 51
Kojto 107:4f6c30876dfa 52 #ifndef __STM32F746xx_H
Kojto 107:4f6c30876dfa 53 #define __STM32F746xx_H
Kojto 107:4f6c30876dfa 54
Kojto 107:4f6c30876dfa 55 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 56 extern "C" {
Kojto 107:4f6c30876dfa 57 #endif /* __cplusplus */
Kojto 107:4f6c30876dfa 58
Kojto 107:4f6c30876dfa 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 107:4f6c30876dfa 60 * @{
Kojto 107:4f6c30876dfa 61 */
Kojto 107:4f6c30876dfa 62
Kojto 107:4f6c30876dfa 63 /**
Kojto 107:4f6c30876dfa 64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
Kojto 107:4f6c30876dfa 65 * in @ref Library_configuration_section
Kojto 107:4f6c30876dfa 66 */
Kojto 116:c0f6e94411f5 67 typedef enum
Kojto 107:4f6c30876dfa 68 {
Kojto 107:4f6c30876dfa 69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
Kojto 107:4f6c30876dfa 70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 107:4f6c30876dfa 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
Kojto 107:4f6c30876dfa 72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
Kojto 107:4f6c30876dfa 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
Kojto 107:4f6c30876dfa 74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
Kojto 107:4f6c30876dfa 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
Kojto 107:4f6c30876dfa 76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
Kojto 107:4f6c30876dfa 77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
Kojto 107:4f6c30876dfa 78 /****** STM32 specific Interrupt Numbers **********************************************************************/
Kojto 107:4f6c30876dfa 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 107:4f6c30876dfa 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
Kojto 107:4f6c30876dfa 81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
Kojto 107:4f6c30876dfa 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
Kojto 107:4f6c30876dfa 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
Kojto 107:4f6c30876dfa 84 RCC_IRQn = 5, /*!< RCC global Interrupt */
Kojto 107:4f6c30876dfa 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
Kojto 107:4f6c30876dfa 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
Kojto 107:4f6c30876dfa 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
Kojto 107:4f6c30876dfa 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
Kojto 107:4f6c30876dfa 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
Kojto 107:4f6c30876dfa 90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
Kojto 107:4f6c30876dfa 91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
Kojto 107:4f6c30876dfa 92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
Kojto 107:4f6c30876dfa 93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
Kojto 107:4f6c30876dfa 94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
Kojto 107:4f6c30876dfa 95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
Kojto 107:4f6c30876dfa 96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
Kojto 107:4f6c30876dfa 97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
Kojto 107:4f6c30876dfa 98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
Kojto 107:4f6c30876dfa 99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
Kojto 107:4f6c30876dfa 100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
Kojto 107:4f6c30876dfa 101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
Kojto 107:4f6c30876dfa 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
Kojto 107:4f6c30876dfa 103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
Kojto 107:4f6c30876dfa 104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
Kojto 107:4f6c30876dfa 105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
Kojto 107:4f6c30876dfa 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
Kojto 107:4f6c30876dfa 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
Kojto 107:4f6c30876dfa 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
Kojto 107:4f6c30876dfa 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
Kojto 107:4f6c30876dfa 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
Kojto 107:4f6c30876dfa 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
Kojto 107:4f6c30876dfa 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
Kojto 107:4f6c30876dfa 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
Kojto 107:4f6c30876dfa 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
Kojto 107:4f6c30876dfa 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
Kojto 107:4f6c30876dfa 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
Kojto 107:4f6c30876dfa 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
Kojto 107:4f6c30876dfa 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
Kojto 107:4f6c30876dfa 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
Kojto 107:4f6c30876dfa 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
Kojto 107:4f6c30876dfa 121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
Kojto 107:4f6c30876dfa 122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
Kojto 107:4f6c30876dfa 123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
Kojto 107:4f6c30876dfa 124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
Kojto 107:4f6c30876dfa 125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
Kojto 107:4f6c30876dfa 126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
Kojto 107:4f6c30876dfa 127 FMC_IRQn = 48, /*!< FMC global Interrupt */
Kojto 116:c0f6e94411f5 128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
Kojto 107:4f6c30876dfa 129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
Kojto 107:4f6c30876dfa 130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
Kojto 107:4f6c30876dfa 131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
Kojto 107:4f6c30876dfa 132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
Kojto 107:4f6c30876dfa 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
Kojto 107:4f6c30876dfa 134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
Kojto 107:4f6c30876dfa 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
Kojto 107:4f6c30876dfa 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
Kojto 107:4f6c30876dfa 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
Kojto 107:4f6c30876dfa 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
Kojto 107:4f6c30876dfa 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
Kojto 107:4f6c30876dfa 140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
Kojto 107:4f6c30876dfa 141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
Kojto 107:4f6c30876dfa 142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
Kojto 107:4f6c30876dfa 143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
Kojto 107:4f6c30876dfa 144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
Kojto 107:4f6c30876dfa 145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
Kojto 107:4f6c30876dfa 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
Kojto 107:4f6c30876dfa 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
Kojto 107:4f6c30876dfa 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
Kojto 107:4f6c30876dfa 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
Kojto 107:4f6c30876dfa 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
Kojto 107:4f6c30876dfa 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
Kojto 107:4f6c30876dfa 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
Kojto 107:4f6c30876dfa 153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
Kojto 107:4f6c30876dfa 154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
Kojto 107:4f6c30876dfa 155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
Kojto 107:4f6c30876dfa 156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
Kojto 107:4f6c30876dfa 157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
Kojto 107:4f6c30876dfa 158 RNG_IRQn = 80, /*!< RNG global interrupt */
Kojto 107:4f6c30876dfa 159 FPU_IRQn = 81, /*!< FPU global interrupt */
Kojto 107:4f6c30876dfa 160 UART7_IRQn = 82, /*!< UART7 global interrupt */
Kojto 107:4f6c30876dfa 161 UART8_IRQn = 83, /*!< UART8 global interrupt */
Kojto 107:4f6c30876dfa 162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
Kojto 107:4f6c30876dfa 163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
Kojto 107:4f6c30876dfa 164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
Kojto 107:4f6c30876dfa 165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
Kojto 107:4f6c30876dfa 166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
Kojto 107:4f6c30876dfa 167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
Kojto 107:4f6c30876dfa 168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
Kojto 107:4f6c30876dfa 169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
Kojto 107:4f6c30876dfa 170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
Kojto 107:4f6c30876dfa 171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
Kojto 107:4f6c30876dfa 172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
Kojto 107:4f6c30876dfa 173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
Kojto 107:4f6c30876dfa 174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
Kojto 107:4f6c30876dfa 175 SPDIF_RX_IRQn = 97 /*!< SPDIF-RX global Interrupt */
Kojto 107:4f6c30876dfa 176 } IRQn_Type;
Kojto 107:4f6c30876dfa 177
Kojto 107:4f6c30876dfa 178 /**
Kojto 107:4f6c30876dfa 179 * @}
Kojto 107:4f6c30876dfa 180 */
Kojto 107:4f6c30876dfa 181
Kojto 107:4f6c30876dfa 182 /**
Kojto 107:4f6c30876dfa 183 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
Kojto 107:4f6c30876dfa 184 */
Kojto 116:c0f6e94411f5 185 #define __CM7_REV 0x0001 /*!< Cortex-M7 revision r0p1 */
Kojto 107:4f6c30876dfa 186 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
Kojto 107:4f6c30876dfa 187 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
Kojto 107:4f6c30876dfa 188 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 107:4f6c30876dfa 189 #define __FPU_PRESENT 1 /*!< FPU present */
Kojto 107:4f6c30876dfa 190 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
Kojto 107:4f6c30876dfa 191 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
Kojto 116:c0f6e94411f5 192 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
Kojto 107:4f6c30876dfa 193
Kojto 107:4f6c30876dfa 194
Kojto 107:4f6c30876dfa 195 #include "system_stm32f7xx.h"
Kojto 107:4f6c30876dfa 196 #include <stdint.h>
Kojto 107:4f6c30876dfa 197
Kojto 107:4f6c30876dfa 198 /** @addtogroup Peripheral_registers_structures
Kojto 107:4f6c30876dfa 199 * @{
Kojto 107:4f6c30876dfa 200 */
Kojto 107:4f6c30876dfa 201
Kojto 107:4f6c30876dfa 202 /**
Kojto 107:4f6c30876dfa 203 * @brief Analog to Digital Converter
Kojto 107:4f6c30876dfa 204 */
Kojto 107:4f6c30876dfa 205
Kojto 107:4f6c30876dfa 206 typedef struct
Kojto 107:4f6c30876dfa 207 {
Kojto 107:4f6c30876dfa 208 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 209 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 210 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 211 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 212 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 213 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 214 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 215 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 216 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 217 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 218 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 219 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 220 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 221 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 222 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
Kojto 107:4f6c30876dfa 223 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
Kojto 107:4f6c30876dfa 224 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
Kojto 107:4f6c30876dfa 225 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
Kojto 107:4f6c30876dfa 226 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
Kojto 107:4f6c30876dfa 227 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
Kojto 107:4f6c30876dfa 228 } ADC_TypeDef;
Kojto 107:4f6c30876dfa 229
Kojto 107:4f6c30876dfa 230 typedef struct
Kojto 107:4f6c30876dfa 231 {
Kojto 107:4f6c30876dfa 232 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
Kojto 107:4f6c30876dfa 233 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
Kojto 107:4f6c30876dfa 234 __IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto 107:4f6c30876dfa 235 AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto 107:4f6c30876dfa 236 } ADC_Common_TypeDef;
Kojto 107:4f6c30876dfa 237
Kojto 107:4f6c30876dfa 238
Kojto 107:4f6c30876dfa 239 /**
Kojto 107:4f6c30876dfa 240 * @brief Controller Area Network TxMailBox
Kojto 107:4f6c30876dfa 241 */
Kojto 107:4f6c30876dfa 242
Kojto 107:4f6c30876dfa 243 typedef struct
Kojto 107:4f6c30876dfa 244 {
Kojto 107:4f6c30876dfa 245 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
Kojto 107:4f6c30876dfa 246 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
Kojto 107:4f6c30876dfa 247 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
Kojto 107:4f6c30876dfa 248 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
Kojto 107:4f6c30876dfa 249 } CAN_TxMailBox_TypeDef;
Kojto 107:4f6c30876dfa 250
Kojto 107:4f6c30876dfa 251 /**
Kojto 107:4f6c30876dfa 252 * @brief Controller Area Network FIFOMailBox
Kojto 107:4f6c30876dfa 253 */
Kojto 107:4f6c30876dfa 254
Kojto 107:4f6c30876dfa 255 typedef struct
Kojto 107:4f6c30876dfa 256 {
Kojto 107:4f6c30876dfa 257 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
Kojto 107:4f6c30876dfa 258 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
Kojto 107:4f6c30876dfa 259 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
Kojto 107:4f6c30876dfa 260 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
Kojto 107:4f6c30876dfa 261 } CAN_FIFOMailBox_TypeDef;
Kojto 107:4f6c30876dfa 262
Kojto 107:4f6c30876dfa 263 /**
Kojto 107:4f6c30876dfa 264 * @brief Controller Area Network FilterRegister
Kojto 107:4f6c30876dfa 265 */
Kojto 107:4f6c30876dfa 266
Kojto 107:4f6c30876dfa 267 typedef struct
Kojto 107:4f6c30876dfa 268 {
Kojto 107:4f6c30876dfa 269 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
Kojto 107:4f6c30876dfa 270 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
Kojto 107:4f6c30876dfa 271 } CAN_FilterRegister_TypeDef;
Kojto 107:4f6c30876dfa 272
Kojto 107:4f6c30876dfa 273 /**
Kojto 107:4f6c30876dfa 274 * @brief Controller Area Network
Kojto 107:4f6c30876dfa 275 */
Kojto 107:4f6c30876dfa 276
Kojto 107:4f6c30876dfa 277 typedef struct
Kojto 107:4f6c30876dfa 278 {
Kojto 107:4f6c30876dfa 279 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 280 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 281 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 282 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 283 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 284 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 285 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 286 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 287 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
Kojto 107:4f6c30876dfa 288 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
Kojto 107:4f6c30876dfa 289 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
Kojto 107:4f6c30876dfa 290 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
Kojto 107:4f6c30876dfa 291 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
Kojto 107:4f6c30876dfa 292 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
Kojto 107:4f6c30876dfa 293 uint32_t RESERVED2; /*!< Reserved, 0x208 */
Kojto 107:4f6c30876dfa 294 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
Kojto 107:4f6c30876dfa 295 uint32_t RESERVED3; /*!< Reserved, 0x210 */
Kojto 107:4f6c30876dfa 296 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
Kojto 107:4f6c30876dfa 297 uint32_t RESERVED4; /*!< Reserved, 0x218 */
Kojto 107:4f6c30876dfa 298 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
Kojto 107:4f6c30876dfa 299 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
Kojto 107:4f6c30876dfa 300 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
Kojto 107:4f6c30876dfa 301 } CAN_TypeDef;
Kojto 107:4f6c30876dfa 302
Kojto 107:4f6c30876dfa 303 /**
Kojto 107:4f6c30876dfa 304 * @brief HDMI-CEC
Kojto 107:4f6c30876dfa 305 */
Kojto 107:4f6c30876dfa 306
Kojto 107:4f6c30876dfa 307 typedef struct
Kojto 107:4f6c30876dfa 308 {
Kojto 107:4f6c30876dfa 309 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
Kojto 107:4f6c30876dfa 310 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
Kojto 107:4f6c30876dfa 311 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
Kojto 107:4f6c30876dfa 312 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
Kojto 107:4f6c30876dfa 313 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
Kojto 107:4f6c30876dfa 314 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
Kojto 107:4f6c30876dfa 315 }CEC_TypeDef;
Kojto 107:4f6c30876dfa 316
Kojto 107:4f6c30876dfa 317
Kojto 107:4f6c30876dfa 318 /**
Kojto 107:4f6c30876dfa 319 * @brief CRC calculation unit
Kojto 107:4f6c30876dfa 320 */
Kojto 107:4f6c30876dfa 321
Kojto 107:4f6c30876dfa 322 typedef struct
Kojto 107:4f6c30876dfa 323 {
Kojto 107:4f6c30876dfa 324 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 325 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 326 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 107:4f6c30876dfa 327 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 107:4f6c30876dfa 328 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 329 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 107:4f6c30876dfa 330 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 331 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 332 } CRC_TypeDef;
Kojto 107:4f6c30876dfa 333
Kojto 107:4f6c30876dfa 334 /**
Kojto 107:4f6c30876dfa 335 * @brief Digital to Analog Converter
Kojto 107:4f6c30876dfa 336 */
Kojto 107:4f6c30876dfa 337
Kojto 107:4f6c30876dfa 338 typedef struct
Kojto 107:4f6c30876dfa 339 {
Kojto 107:4f6c30876dfa 340 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 341 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 342 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 343 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 344 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 345 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 346 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 347 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 348 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 349 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 350 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 351 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 352 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 353 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 354 } DAC_TypeDef;
Kojto 107:4f6c30876dfa 355
Kojto 116:c0f6e94411f5 356
Kojto 107:4f6c30876dfa 357 /**
Kojto 107:4f6c30876dfa 358 * @brief Debug MCU
Kojto 107:4f6c30876dfa 359 */
Kojto 107:4f6c30876dfa 360
Kojto 107:4f6c30876dfa 361 typedef struct
Kojto 107:4f6c30876dfa 362 {
Kojto 107:4f6c30876dfa 363 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 364 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 365 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 366 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 367 }DBGMCU_TypeDef;
Kojto 107:4f6c30876dfa 368
Kojto 107:4f6c30876dfa 369 /**
Kojto 107:4f6c30876dfa 370 * @brief DCMI
Kojto 107:4f6c30876dfa 371 */
Kojto 107:4f6c30876dfa 372
Kojto 107:4f6c30876dfa 373 typedef struct
Kojto 107:4f6c30876dfa 374 {
Kojto 107:4f6c30876dfa 375 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 376 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 377 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 378 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 379 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 380 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 381 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 382 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 383 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 384 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 385 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 386 } DCMI_TypeDef;
Kojto 107:4f6c30876dfa 387
Kojto 107:4f6c30876dfa 388 /**
Kojto 107:4f6c30876dfa 389 * @brief DMA Controller
Kojto 107:4f6c30876dfa 390 */
Kojto 107:4f6c30876dfa 391
Kojto 107:4f6c30876dfa 392 typedef struct
Kojto 107:4f6c30876dfa 393 {
Kojto 107:4f6c30876dfa 394 __IO uint32_t CR; /*!< DMA stream x configuration register */
Kojto 107:4f6c30876dfa 395 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
Kojto 107:4f6c30876dfa 396 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
Kojto 107:4f6c30876dfa 397 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
Kojto 107:4f6c30876dfa 398 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
Kojto 107:4f6c30876dfa 399 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
Kojto 107:4f6c30876dfa 400 } DMA_Stream_TypeDef;
Kojto 107:4f6c30876dfa 401
Kojto 107:4f6c30876dfa 402 typedef struct
Kojto 107:4f6c30876dfa 403 {
Kojto 107:4f6c30876dfa 404 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 405 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 406 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 407 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 408 } DMA_TypeDef;
Kojto 107:4f6c30876dfa 409
Kojto 107:4f6c30876dfa 410
Kojto 107:4f6c30876dfa 411 /**
Kojto 107:4f6c30876dfa 412 * @brief DMA2D Controller
Kojto 107:4f6c30876dfa 413 */
Kojto 107:4f6c30876dfa 414
Kojto 107:4f6c30876dfa 415 typedef struct
Kojto 107:4f6c30876dfa 416 {
Kojto 107:4f6c30876dfa 417 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 418 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 419 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 420 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 421 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 422 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 423 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 424 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 425 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 426 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 427 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 428 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 429 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 430 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 431 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
Kojto 107:4f6c30876dfa 432 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
Kojto 107:4f6c30876dfa 433 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
Kojto 107:4f6c30876dfa 434 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
Kojto 107:4f6c30876dfa 435 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
Kojto 107:4f6c30876dfa 436 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
Kojto 107:4f6c30876dfa 437 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
Kojto 107:4f6c30876dfa 438 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
Kojto 107:4f6c30876dfa 439 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
Kojto 107:4f6c30876dfa 440 } DMA2D_TypeDef;
Kojto 107:4f6c30876dfa 441
Kojto 107:4f6c30876dfa 442
Kojto 107:4f6c30876dfa 443 /**
Kojto 107:4f6c30876dfa 444 * @brief Ethernet MAC
Kojto 107:4f6c30876dfa 445 */
Kojto 107:4f6c30876dfa 446
Kojto 107:4f6c30876dfa 447 typedef struct
Kojto 107:4f6c30876dfa 448 {
Kojto 107:4f6c30876dfa 449 __IO uint32_t MACCR;
Kojto 107:4f6c30876dfa 450 __IO uint32_t MACFFR;
Kojto 107:4f6c30876dfa 451 __IO uint32_t MACHTHR;
Kojto 107:4f6c30876dfa 452 __IO uint32_t MACHTLR;
Kojto 107:4f6c30876dfa 453 __IO uint32_t MACMIIAR;
Kojto 107:4f6c30876dfa 454 __IO uint32_t MACMIIDR;
Kojto 107:4f6c30876dfa 455 __IO uint32_t MACFCR;
Kojto 107:4f6c30876dfa 456 __IO uint32_t MACVLANTR; /* 8 */
Kojto 107:4f6c30876dfa 457 uint32_t RESERVED0[2];
Kojto 107:4f6c30876dfa 458 __IO uint32_t MACRWUFFR; /* 11 */
Kojto 107:4f6c30876dfa 459 __IO uint32_t MACPMTCSR;
Kojto 107:4f6c30876dfa 460 uint32_t RESERVED1[2];
Kojto 107:4f6c30876dfa 461 __IO uint32_t MACSR; /* 15 */
Kojto 107:4f6c30876dfa 462 __IO uint32_t MACIMR;
Kojto 107:4f6c30876dfa 463 __IO uint32_t MACA0HR;
Kojto 107:4f6c30876dfa 464 __IO uint32_t MACA0LR;
Kojto 107:4f6c30876dfa 465 __IO uint32_t MACA1HR;
Kojto 107:4f6c30876dfa 466 __IO uint32_t MACA1LR;
Kojto 107:4f6c30876dfa 467 __IO uint32_t MACA2HR;
Kojto 107:4f6c30876dfa 468 __IO uint32_t MACA2LR;
Kojto 107:4f6c30876dfa 469 __IO uint32_t MACA3HR;
Kojto 107:4f6c30876dfa 470 __IO uint32_t MACA3LR; /* 24 */
Kojto 107:4f6c30876dfa 471 uint32_t RESERVED2[40];
Kojto 107:4f6c30876dfa 472 __IO uint32_t MMCCR; /* 65 */
Kojto 107:4f6c30876dfa 473 __IO uint32_t MMCRIR;
Kojto 107:4f6c30876dfa 474 __IO uint32_t MMCTIR;
Kojto 107:4f6c30876dfa 475 __IO uint32_t MMCRIMR;
Kojto 107:4f6c30876dfa 476 __IO uint32_t MMCTIMR; /* 69 */
Kojto 107:4f6c30876dfa 477 uint32_t RESERVED3[14];
Kojto 107:4f6c30876dfa 478 __IO uint32_t MMCTGFSCCR; /* 84 */
Kojto 107:4f6c30876dfa 479 __IO uint32_t MMCTGFMSCCR;
Kojto 107:4f6c30876dfa 480 uint32_t RESERVED4[5];
Kojto 107:4f6c30876dfa 481 __IO uint32_t MMCTGFCR;
Kojto 107:4f6c30876dfa 482 uint32_t RESERVED5[10];
Kojto 107:4f6c30876dfa 483 __IO uint32_t MMCRFCECR;
Kojto 107:4f6c30876dfa 484 __IO uint32_t MMCRFAECR;
Kojto 107:4f6c30876dfa 485 uint32_t RESERVED6[10];
Kojto 107:4f6c30876dfa 486 __IO uint32_t MMCRGUFCR;
Kojto 107:4f6c30876dfa 487 uint32_t RESERVED7[334];
Kojto 107:4f6c30876dfa 488 __IO uint32_t PTPTSCR;
Kojto 107:4f6c30876dfa 489 __IO uint32_t PTPSSIR;
Kojto 107:4f6c30876dfa 490 __IO uint32_t PTPTSHR;
Kojto 107:4f6c30876dfa 491 __IO uint32_t PTPTSLR;
Kojto 107:4f6c30876dfa 492 __IO uint32_t PTPTSHUR;
Kojto 107:4f6c30876dfa 493 __IO uint32_t PTPTSLUR;
Kojto 107:4f6c30876dfa 494 __IO uint32_t PTPTSAR;
Kojto 107:4f6c30876dfa 495 __IO uint32_t PTPTTHR;
Kojto 107:4f6c30876dfa 496 __IO uint32_t PTPTTLR;
Kojto 107:4f6c30876dfa 497 __IO uint32_t RESERVED8;
Kojto 107:4f6c30876dfa 498 __IO uint32_t PTPTSSR;
Kojto 107:4f6c30876dfa 499 uint32_t RESERVED9[565];
Kojto 107:4f6c30876dfa 500 __IO uint32_t DMABMR;
Kojto 107:4f6c30876dfa 501 __IO uint32_t DMATPDR;
Kojto 107:4f6c30876dfa 502 __IO uint32_t DMARPDR;
Kojto 107:4f6c30876dfa 503 __IO uint32_t DMARDLAR;
Kojto 107:4f6c30876dfa 504 __IO uint32_t DMATDLAR;
Kojto 107:4f6c30876dfa 505 __IO uint32_t DMASR;
Kojto 107:4f6c30876dfa 506 __IO uint32_t DMAOMR;
Kojto 107:4f6c30876dfa 507 __IO uint32_t DMAIER;
Kojto 107:4f6c30876dfa 508 __IO uint32_t DMAMFBOCR;
Kojto 107:4f6c30876dfa 509 __IO uint32_t DMARSWTR;
Kojto 107:4f6c30876dfa 510 uint32_t RESERVED10[8];
Kojto 107:4f6c30876dfa 511 __IO uint32_t DMACHTDR;
Kojto 107:4f6c30876dfa 512 __IO uint32_t DMACHRDR;
Kojto 107:4f6c30876dfa 513 __IO uint32_t DMACHTBAR;
Kojto 107:4f6c30876dfa 514 __IO uint32_t DMACHRBAR;
Kojto 107:4f6c30876dfa 515 } ETH_TypeDef;
Kojto 107:4f6c30876dfa 516
Kojto 107:4f6c30876dfa 517 /**
Kojto 107:4f6c30876dfa 518 * @brief External Interrupt/Event Controller
Kojto 107:4f6c30876dfa 519 */
Kojto 107:4f6c30876dfa 520
Kojto 107:4f6c30876dfa 521 typedef struct
Kojto 107:4f6c30876dfa 522 {
Kojto 107:4f6c30876dfa 523 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 524 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 525 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 526 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 527 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 528 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 529 } EXTI_TypeDef;
Kojto 107:4f6c30876dfa 530
Kojto 107:4f6c30876dfa 531 /**
Kojto 107:4f6c30876dfa 532 * @brief FLASH Registers
Kojto 107:4f6c30876dfa 533 */
Kojto 107:4f6c30876dfa 534
Kojto 107:4f6c30876dfa 535 typedef struct
Kojto 107:4f6c30876dfa 536 {
Kojto 107:4f6c30876dfa 537 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 538 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 539 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 540 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 541 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 542 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
Kojto 107:4f6c30876dfa 543 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
Kojto 107:4f6c30876dfa 544 } FLASH_TypeDef;
Kojto 107:4f6c30876dfa 545
Kojto 107:4f6c30876dfa 546
Kojto 107:4f6c30876dfa 547
Kojto 107:4f6c30876dfa 548 /**
Kojto 107:4f6c30876dfa 549 * @brief Flexible Memory Controller
Kojto 107:4f6c30876dfa 550 */
Kojto 107:4f6c30876dfa 551
Kojto 107:4f6c30876dfa 552 typedef struct
Kojto 107:4f6c30876dfa 553 {
Kojto 107:4f6c30876dfa 554 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
Kojto 107:4f6c30876dfa 555 } FMC_Bank1_TypeDef;
Kojto 107:4f6c30876dfa 556
Kojto 107:4f6c30876dfa 557 /**
Kojto 107:4f6c30876dfa 558 * @brief Flexible Memory Controller Bank1E
Kojto 107:4f6c30876dfa 559 */
Kojto 107:4f6c30876dfa 560
Kojto 107:4f6c30876dfa 561 typedef struct
Kojto 107:4f6c30876dfa 562 {
Kojto 107:4f6c30876dfa 563 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
Kojto 107:4f6c30876dfa 564 } FMC_Bank1E_TypeDef;
Kojto 107:4f6c30876dfa 565
Kojto 107:4f6c30876dfa 566 /**
Kojto 107:4f6c30876dfa 567 * @brief Flexible Memory Controller Bank3
Kojto 107:4f6c30876dfa 568 */
Kojto 107:4f6c30876dfa 569
Kojto 107:4f6c30876dfa 570 typedef struct
Kojto 107:4f6c30876dfa 571 {
Kojto 107:4f6c30876dfa 572 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
Kojto 107:4f6c30876dfa 573 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
Kojto 107:4f6c30876dfa 574 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
Kojto 107:4f6c30876dfa 575 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
Kojto 107:4f6c30876dfa 576 uint32_t RESERVED0; /*!< Reserved, 0x90 */
Kojto 107:4f6c30876dfa 577 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
Kojto 107:4f6c30876dfa 578 } FMC_Bank3_TypeDef;
Kojto 107:4f6c30876dfa 579
Kojto 107:4f6c30876dfa 580 /**
Kojto 107:4f6c30876dfa 581 * @brief Flexible Memory Controller Bank5_6
Kojto 107:4f6c30876dfa 582 */
Kojto 107:4f6c30876dfa 583
Kojto 107:4f6c30876dfa 584 typedef struct
Kojto 107:4f6c30876dfa 585 {
Kojto 107:4f6c30876dfa 586 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
Kojto 107:4f6c30876dfa 587 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
Kojto 107:4f6c30876dfa 588 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
Kojto 107:4f6c30876dfa 589 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
Kojto 107:4f6c30876dfa 590 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
Kojto 107:4f6c30876dfa 591 } FMC_Bank5_6_TypeDef;
Kojto 107:4f6c30876dfa 592
Kojto 107:4f6c30876dfa 593
Kojto 107:4f6c30876dfa 594 /**
Kojto 107:4f6c30876dfa 595 * @brief General Purpose I/O
Kojto 107:4f6c30876dfa 596 */
Kojto 107:4f6c30876dfa 597
Kojto 107:4f6c30876dfa 598 typedef struct
Kojto 107:4f6c30876dfa 599 {
Kojto 107:4f6c30876dfa 600 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 601 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 602 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 603 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 604 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 605 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 606 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 607 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 608 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
Kojto 107:4f6c30876dfa 609 } GPIO_TypeDef;
Kojto 107:4f6c30876dfa 610
Kojto 107:4f6c30876dfa 611 /**
Kojto 107:4f6c30876dfa 612 * @brief System configuration controller
Kojto 107:4f6c30876dfa 613 */
Kojto 107:4f6c30876dfa 614
Kojto 107:4f6c30876dfa 615 typedef struct
Kojto 107:4f6c30876dfa 616 {
Kojto 107:4f6c30876dfa 617 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 618 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 619 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
Kojto 107:4f6c30876dfa 620 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 107:4f6c30876dfa 621 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 622 } SYSCFG_TypeDef;
Kojto 107:4f6c30876dfa 623
Kojto 107:4f6c30876dfa 624 /**
Kojto 107:4f6c30876dfa 625 * @brief Inter-integrated Circuit Interface
Kojto 107:4f6c30876dfa 626 */
Kojto 107:4f6c30876dfa 627
Kojto 107:4f6c30876dfa 628 typedef struct
Kojto 107:4f6c30876dfa 629 {
Kojto 107:4f6c30876dfa 630 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 631 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 632 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 633 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 634 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 635 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 636 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 637 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 638 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 639 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 640 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 641 } I2C_TypeDef;
Kojto 107:4f6c30876dfa 642
Kojto 107:4f6c30876dfa 643 /**
Kojto 107:4f6c30876dfa 644 * @brief Independent WATCHDOG
Kojto 107:4f6c30876dfa 645 */
Kojto 107:4f6c30876dfa 646
Kojto 107:4f6c30876dfa 647 typedef struct
Kojto 107:4f6c30876dfa 648 {
Kojto 107:4f6c30876dfa 649 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 650 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 651 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 652 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 653 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 654 } IWDG_TypeDef;
Kojto 107:4f6c30876dfa 655
Kojto 107:4f6c30876dfa 656
Kojto 107:4f6c30876dfa 657 /**
Kojto 107:4f6c30876dfa 658 * @brief LCD-TFT Display Controller
Kojto 107:4f6c30876dfa 659 */
Kojto 107:4f6c30876dfa 660
Kojto 107:4f6c30876dfa 661 typedef struct
Kojto 107:4f6c30876dfa 662 {
Kojto 107:4f6c30876dfa 663 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
Kojto 107:4f6c30876dfa 664 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 665 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 666 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 667 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 668 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 669 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
Kojto 107:4f6c30876dfa 670 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 671 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
Kojto 107:4f6c30876dfa 672 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 673 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
Kojto 107:4f6c30876dfa 674 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 675 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
Kojto 107:4f6c30876dfa 676 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
Kojto 107:4f6c30876dfa 677 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
Kojto 107:4f6c30876dfa 678 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
Kojto 107:4f6c30876dfa 679 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
Kojto 107:4f6c30876dfa 680 } LTDC_TypeDef;
Kojto 107:4f6c30876dfa 681
Kojto 107:4f6c30876dfa 682 /**
Kojto 107:4f6c30876dfa 683 * @brief LCD-TFT Display layer x Controller
Kojto 107:4f6c30876dfa 684 */
Kojto 107:4f6c30876dfa 685
Kojto 107:4f6c30876dfa 686 typedef struct
Kojto 107:4f6c30876dfa 687 {
Kojto 107:4f6c30876dfa 688 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
Kojto 107:4f6c30876dfa 689 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
Kojto 107:4f6c30876dfa 690 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
Kojto 107:4f6c30876dfa 691 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
Kojto 107:4f6c30876dfa 692 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
Kojto 107:4f6c30876dfa 693 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
Kojto 107:4f6c30876dfa 694 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
Kojto 107:4f6c30876dfa 695 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
Kojto 107:4f6c30876dfa 696 uint32_t RESERVED0[2]; /*!< Reserved */
Kojto 107:4f6c30876dfa 697 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
Kojto 107:4f6c30876dfa 698 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
Kojto 107:4f6c30876dfa 699 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
Kojto 107:4f6c30876dfa 700 uint32_t RESERVED1[3]; /*!< Reserved */
Kojto 116:c0f6e94411f5 701 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
Kojto 107:4f6c30876dfa 702
Kojto 107:4f6c30876dfa 703 } LTDC_Layer_TypeDef;
Kojto 107:4f6c30876dfa 704
Kojto 107:4f6c30876dfa 705 /**
Kojto 107:4f6c30876dfa 706 * @brief Power Control
Kojto 107:4f6c30876dfa 707 */
Kojto 107:4f6c30876dfa 708
Kojto 107:4f6c30876dfa 709 typedef struct
Kojto 107:4f6c30876dfa 710 {
Kojto 107:4f6c30876dfa 711 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 712 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 713 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 714 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 715 } PWR_TypeDef;
Kojto 107:4f6c30876dfa 716
Kojto 107:4f6c30876dfa 717
Kojto 107:4f6c30876dfa 718 /**
Kojto 107:4f6c30876dfa 719 * @brief Reset and Clock Control
Kojto 107:4f6c30876dfa 720 */
Kojto 107:4f6c30876dfa 721
Kojto 107:4f6c30876dfa 722 typedef struct
Kojto 107:4f6c30876dfa 723 {
Kojto 107:4f6c30876dfa 724 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 725 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 726 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 727 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 728 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 729 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 730 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 731 uint32_t RESERVED0; /*!< Reserved, 0x1C */
Kojto 107:4f6c30876dfa 732 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 733 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 734 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
Kojto 107:4f6c30876dfa 735 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 736 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 737 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
Kojto 107:4f6c30876dfa 738 uint32_t RESERVED2; /*!< Reserved, 0x3C */
Kojto 107:4f6c30876dfa 739 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
Kojto 107:4f6c30876dfa 740 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
Kojto 107:4f6c30876dfa 741 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
Kojto 107:4f6c30876dfa 742 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
Kojto 107:4f6c30876dfa 743 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
Kojto 107:4f6c30876dfa 744 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
Kojto 107:4f6c30876dfa 745 uint32_t RESERVED4; /*!< Reserved, 0x5C */
Kojto 107:4f6c30876dfa 746 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
Kojto 107:4f6c30876dfa 747 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
Kojto 107:4f6c30876dfa 748 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
Kojto 107:4f6c30876dfa 749 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
Kojto 107:4f6c30876dfa 750 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
Kojto 107:4f6c30876dfa 751 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
Kojto 107:4f6c30876dfa 752 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
Kojto 107:4f6c30876dfa 753 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
Kojto 107:4f6c30876dfa 754 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
Kojto 107:4f6c30876dfa 755 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
Kojto 107:4f6c30876dfa 756 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
Kojto 107:4f6c30876dfa 757
Kojto 107:4f6c30876dfa 758 } RCC_TypeDef;
Kojto 107:4f6c30876dfa 759
Kojto 107:4f6c30876dfa 760 /**
Kojto 107:4f6c30876dfa 761 * @brief Real-Time Clock
Kojto 107:4f6c30876dfa 762 */
Kojto 107:4f6c30876dfa 763
Kojto 107:4f6c30876dfa 764 typedef struct
Kojto 107:4f6c30876dfa 765 {
Kojto 107:4f6c30876dfa 766 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 767 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 768 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 769 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 770 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 771 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 772 uint32_t reserved; /*!< Reserved */
Kojto 107:4f6c30876dfa 773 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 774 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 775 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 776 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 777 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 778 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 779 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 780 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 107:4f6c30876dfa 781 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 107:4f6c30876dfa 782 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
Kojto 107:4f6c30876dfa 783 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 107:4f6c30876dfa 784 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 107:4f6c30876dfa 785 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
Kojto 107:4f6c30876dfa 786 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 107:4f6c30876dfa 787 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 107:4f6c30876dfa 788 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 107:4f6c30876dfa 789 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 107:4f6c30876dfa 790 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 107:4f6c30876dfa 791 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
Kojto 107:4f6c30876dfa 792 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
Kojto 107:4f6c30876dfa 793 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
Kojto 107:4f6c30876dfa 794 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
Kojto 107:4f6c30876dfa 795 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
Kojto 107:4f6c30876dfa 796 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
Kojto 107:4f6c30876dfa 797 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
Kojto 107:4f6c30876dfa 798 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
Kojto 107:4f6c30876dfa 799 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
Kojto 107:4f6c30876dfa 800 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
Kojto 107:4f6c30876dfa 801 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
Kojto 107:4f6c30876dfa 802 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
Kojto 107:4f6c30876dfa 803 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
Kojto 107:4f6c30876dfa 804 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
Kojto 107:4f6c30876dfa 805 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
Kojto 107:4f6c30876dfa 806 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
Kojto 107:4f6c30876dfa 807 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
Kojto 107:4f6c30876dfa 808 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
Kojto 107:4f6c30876dfa 809 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
Kojto 107:4f6c30876dfa 810 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
Kojto 107:4f6c30876dfa 811 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
Kojto 107:4f6c30876dfa 812 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
Kojto 107:4f6c30876dfa 813 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
Kojto 107:4f6c30876dfa 814 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
Kojto 107:4f6c30876dfa 815 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
Kojto 107:4f6c30876dfa 816 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
Kojto 107:4f6c30876dfa 817 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
Kojto 107:4f6c30876dfa 818 } RTC_TypeDef;
Kojto 107:4f6c30876dfa 819
Kojto 107:4f6c30876dfa 820
Kojto 107:4f6c30876dfa 821 /**
Kojto 107:4f6c30876dfa 822 * @brief Serial Audio Interface
Kojto 107:4f6c30876dfa 823 */
Kojto 107:4f6c30876dfa 824
Kojto 107:4f6c30876dfa 825 typedef struct
Kojto 107:4f6c30876dfa 826 {
Kojto 107:4f6c30876dfa 827 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 828 } SAI_TypeDef;
Kojto 107:4f6c30876dfa 829
Kojto 107:4f6c30876dfa 830 typedef struct
Kojto 107:4f6c30876dfa 831 {
Kojto 107:4f6c30876dfa 832 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 833 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 834 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 835 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 836 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 837 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 838 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 839 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 840 } SAI_Block_TypeDef;
Kojto 107:4f6c30876dfa 841
Kojto 107:4f6c30876dfa 842 /**
Kojto 107:4f6c30876dfa 843 * @brief SPDIF-RX Interface
Kojto 107:4f6c30876dfa 844 */
Kojto 107:4f6c30876dfa 845
Kojto 107:4f6c30876dfa 846 typedef struct
Kojto 107:4f6c30876dfa 847 {
Kojto 107:4f6c30876dfa 848 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 849 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 850 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 851 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 852 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 853 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 854 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 855 } SPDIFRX_TypeDef;
Kojto 107:4f6c30876dfa 856
Kojto 107:4f6c30876dfa 857
Kojto 107:4f6c30876dfa 858 /**
Kojto 107:4f6c30876dfa 859 * @brief SD host Interface
Kojto 107:4f6c30876dfa 860 */
Kojto 107:4f6c30876dfa 861
Kojto 107:4f6c30876dfa 862 typedef struct
Kojto 107:4f6c30876dfa 863 {
Kojto 107:4f6c30876dfa 864 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 865 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 866 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 867 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 868 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 869 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 870 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 871 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 872 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 873 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 874 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 875 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 876 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 877 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 878 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
Kojto 107:4f6c30876dfa 879 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
Kojto 107:4f6c30876dfa 880 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
Kojto 107:4f6c30876dfa 881 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
Kojto 107:4f6c30876dfa 882 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
Kojto 107:4f6c30876dfa 883 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
Kojto 107:4f6c30876dfa 884 } SDMMC_TypeDef;
Kojto 107:4f6c30876dfa 885
Kojto 107:4f6c30876dfa 886 /**
Kojto 107:4f6c30876dfa 887 * @brief Serial Peripheral Interface
Kojto 107:4f6c30876dfa 888 */
Kojto 107:4f6c30876dfa 889
Kojto 107:4f6c30876dfa 890 typedef struct
Kojto 107:4f6c30876dfa 891 {
Kojto 107:4f6c30876dfa 892 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 107:4f6c30876dfa 893 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 894 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 895 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 896 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 107:4f6c30876dfa 897 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 107:4f6c30876dfa 898 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 107:4f6c30876dfa 899 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 900 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 901 } SPI_TypeDef;
Kojto 107:4f6c30876dfa 902
Kojto 107:4f6c30876dfa 903 /**
Kojto 107:4f6c30876dfa 904 * @brief QUAD Serial Peripheral Interface
Kojto 107:4f6c30876dfa 905 */
Kojto 107:4f6c30876dfa 906
Kojto 107:4f6c30876dfa 907 typedef struct
Kojto 107:4f6c30876dfa 908 {
Kojto 107:4f6c30876dfa 909 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 910 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 911 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 912 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 913 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 914 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 915 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 916 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 917 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 918 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 919 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 920 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 921 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 922 } QUADSPI_TypeDef;
Kojto 107:4f6c30876dfa 923
Kojto 107:4f6c30876dfa 924 /**
Kojto 107:4f6c30876dfa 925 * @brief TIM
Kojto 107:4f6c30876dfa 926 */
Kojto 107:4f6c30876dfa 927
Kojto 107:4f6c30876dfa 928 typedef struct
Kojto 107:4f6c30876dfa 929 {
Kojto 107:4f6c30876dfa 930 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 931 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 932 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 933 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 934 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 935 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 936 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 937 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 938 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 939 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 940 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 941 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 107:4f6c30876dfa 942 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 107:4f6c30876dfa 943 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 107:4f6c30876dfa 944 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 107:4f6c30876dfa 945 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 107:4f6c30876dfa 946 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 107:4f6c30876dfa 947 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 107:4f6c30876dfa 948 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 107:4f6c30876dfa 949 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
Kojto 107:4f6c30876dfa 950 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 107:4f6c30876dfa 951 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
Kojto 107:4f6c30876dfa 952 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
Kojto 107:4f6c30876dfa 953 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
Kojto 107:4f6c30876dfa 954
Kojto 107:4f6c30876dfa 955 } TIM_TypeDef;
Kojto 107:4f6c30876dfa 956
Kojto 107:4f6c30876dfa 957 /**
Kojto 107:4f6c30876dfa 958 * @brief LPTIMIMER
Kojto 107:4f6c30876dfa 959 */
Kojto 107:4f6c30876dfa 960 typedef struct
Kojto 107:4f6c30876dfa 961 {
Kojto 107:4f6c30876dfa 962 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 963 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 964 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 965 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 966 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 967 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 968 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 969 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 970 } LPTIM_TypeDef;
Kojto 107:4f6c30876dfa 971
Kojto 107:4f6c30876dfa 972
Kojto 107:4f6c30876dfa 973 /**
Kojto 107:4f6c30876dfa 974 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 107:4f6c30876dfa 975 */
Kojto 107:4f6c30876dfa 976
Kojto 107:4f6c30876dfa 977 typedef struct
Kojto 107:4f6c30876dfa 978 {
Kojto 107:4f6c30876dfa 979 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 980 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 981 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 982 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 107:4f6c30876dfa 983 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 107:4f6c30876dfa 984 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 107:4f6c30876dfa 985 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 107:4f6c30876dfa 986 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 107:4f6c30876dfa 987 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 107:4f6c30876dfa 988 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 107:4f6c30876dfa 989 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 107:4f6c30876dfa 990 } USART_TypeDef;
Kojto 107:4f6c30876dfa 991
Kojto 107:4f6c30876dfa 992
Kojto 107:4f6c30876dfa 993 /**
Kojto 107:4f6c30876dfa 994 * @brief Window WATCHDOG
Kojto 107:4f6c30876dfa 995 */
Kojto 107:4f6c30876dfa 996
Kojto 107:4f6c30876dfa 997 typedef struct
Kojto 107:4f6c30876dfa 998 {
Kojto 107:4f6c30876dfa 999 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 1000 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 1001 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 1002 } WWDG_TypeDef;
Kojto 107:4f6c30876dfa 1003
Kojto 116:c0f6e94411f5 1004
Kojto 107:4f6c30876dfa 1005 /**
Kojto 107:4f6c30876dfa 1006 * @brief RNG
Kojto 107:4f6c30876dfa 1007 */
Kojto 107:4f6c30876dfa 1008
Kojto 107:4f6c30876dfa 1009 typedef struct
Kojto 107:4f6c30876dfa 1010 {
Kojto 107:4f6c30876dfa 1011 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
Kojto 107:4f6c30876dfa 1012 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
Kojto 107:4f6c30876dfa 1013 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
Kojto 107:4f6c30876dfa 1014 } RNG_TypeDef;
Kojto 107:4f6c30876dfa 1015
Kojto 107:4f6c30876dfa 1016 /**
Kojto 107:4f6c30876dfa 1017 * @}
Kojto 107:4f6c30876dfa 1018 */
Kojto 107:4f6c30876dfa 1019
Kojto 107:4f6c30876dfa 1020 /**
Kojto 107:4f6c30876dfa 1021 * @brief USB_OTG_Core_Registers
Kojto 107:4f6c30876dfa 1022 */
Kojto 107:4f6c30876dfa 1023 typedef struct
Kojto 107:4f6c30876dfa 1024 {
Kojto 107:4f6c30876dfa 1025 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
Kojto 107:4f6c30876dfa 1026 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
Kojto 107:4f6c30876dfa 1027 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
Kojto 107:4f6c30876dfa 1028 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
Kojto 107:4f6c30876dfa 1029 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
Kojto 107:4f6c30876dfa 1030 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
Kojto 107:4f6c30876dfa 1031 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
Kojto 107:4f6c30876dfa 1032 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
Kojto 107:4f6c30876dfa 1033 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
Kojto 107:4f6c30876dfa 1034 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
Kojto 107:4f6c30876dfa 1035 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
Kojto 107:4f6c30876dfa 1036 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
Kojto 107:4f6c30876dfa 1037 uint32_t Reserved30[2]; /*!< Reserved 030h */
Kojto 107:4f6c30876dfa 1038 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
Kojto 107:4f6c30876dfa 1039 __IO uint32_t CID; /*!< User ID Register 03Ch */
Kojto 107:4f6c30876dfa 1040 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
Kojto 107:4f6c30876dfa 1041 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
Kojto 107:4f6c30876dfa 1042 uint32_t Reserved6; /*!< Reserved 050h */
Kojto 107:4f6c30876dfa 1043 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
Kojto 107:4f6c30876dfa 1044 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
Kojto 107:4f6c30876dfa 1045 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
Kojto 107:4f6c30876dfa 1046 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
Kojto 107:4f6c30876dfa 1047 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
Kojto 107:4f6c30876dfa 1048 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
Kojto 107:4f6c30876dfa 1049 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
Kojto 107:4f6c30876dfa 1050 } USB_OTG_GlobalTypeDef;
Kojto 107:4f6c30876dfa 1051
Kojto 107:4f6c30876dfa 1052
Kojto 107:4f6c30876dfa 1053 /**
Kojto 107:4f6c30876dfa 1054 * @brief USB_OTG_device_Registers
Kojto 107:4f6c30876dfa 1055 */
Kojto 107:4f6c30876dfa 1056 typedef struct
Kojto 107:4f6c30876dfa 1057 {
Kojto 107:4f6c30876dfa 1058 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
Kojto 107:4f6c30876dfa 1059 __IO uint32_t DCTL; /*!< dev Control Register 804h */
Kojto 107:4f6c30876dfa 1060 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
Kojto 107:4f6c30876dfa 1061 uint32_t Reserved0C; /*!< Reserved 80Ch */
Kojto 107:4f6c30876dfa 1062 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
Kojto 107:4f6c30876dfa 1063 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
Kojto 107:4f6c30876dfa 1064 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
Kojto 107:4f6c30876dfa 1065 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
Kojto 107:4f6c30876dfa 1066 uint32_t Reserved20; /*!< Reserved 820h */
Kojto 107:4f6c30876dfa 1067 uint32_t Reserved9; /*!< Reserved 824h */
Kojto 107:4f6c30876dfa 1068 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
Kojto 107:4f6c30876dfa 1069 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
Kojto 107:4f6c30876dfa 1070 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
Kojto 107:4f6c30876dfa 1071 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
Kojto 107:4f6c30876dfa 1072 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
Kojto 107:4f6c30876dfa 1073 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
Kojto 107:4f6c30876dfa 1074 uint32_t Reserved40; /*!< dedicated EP mask 840h */
Kojto 107:4f6c30876dfa 1075 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
Kojto 107:4f6c30876dfa 1076 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
Kojto 107:4f6c30876dfa 1077 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
Kojto 107:4f6c30876dfa 1078 } USB_OTG_DeviceTypeDef;
Kojto 107:4f6c30876dfa 1079
Kojto 107:4f6c30876dfa 1080
Kojto 107:4f6c30876dfa 1081 /**
Kojto 107:4f6c30876dfa 1082 * @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto 107:4f6c30876dfa 1083 */
Kojto 107:4f6c30876dfa 1084 typedef struct
Kojto 107:4f6c30876dfa 1085 {
Kojto 107:4f6c30876dfa 1086 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
Kojto 107:4f6c30876dfa 1087 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
Kojto 107:4f6c30876dfa 1088 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
Kojto 107:4f6c30876dfa 1089 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
Kojto 107:4f6c30876dfa 1090 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
Kojto 107:4f6c30876dfa 1091 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
Kojto 107:4f6c30876dfa 1092 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
Kojto 107:4f6c30876dfa 1093 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto 107:4f6c30876dfa 1094 } USB_OTG_INEndpointTypeDef;
Kojto 107:4f6c30876dfa 1095
Kojto 107:4f6c30876dfa 1096
Kojto 107:4f6c30876dfa 1097 /**
Kojto 107:4f6c30876dfa 1098 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto 107:4f6c30876dfa 1099 */
Kojto 107:4f6c30876dfa 1100 typedef struct
Kojto 107:4f6c30876dfa 1101 {
Kojto 107:4f6c30876dfa 1102 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
Kojto 107:4f6c30876dfa 1103 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
Kojto 107:4f6c30876dfa 1104 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
Kojto 107:4f6c30876dfa 1105 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
Kojto 107:4f6c30876dfa 1106 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
Kojto 107:4f6c30876dfa 1107 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
Kojto 107:4f6c30876dfa 1108 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto 107:4f6c30876dfa 1109 } USB_OTG_OUTEndpointTypeDef;
Kojto 107:4f6c30876dfa 1110
Kojto 107:4f6c30876dfa 1111
Kojto 107:4f6c30876dfa 1112 /**
Kojto 107:4f6c30876dfa 1113 * @brief USB_OTG_Host_Mode_Register_Structures
Kojto 107:4f6c30876dfa 1114 */
Kojto 107:4f6c30876dfa 1115 typedef struct
Kojto 107:4f6c30876dfa 1116 {
Kojto 107:4f6c30876dfa 1117 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
Kojto 107:4f6c30876dfa 1118 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
Kojto 107:4f6c30876dfa 1119 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
Kojto 107:4f6c30876dfa 1120 uint32_t Reserved40C; /*!< Reserved 40Ch */
Kojto 107:4f6c30876dfa 1121 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
Kojto 107:4f6c30876dfa 1122 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
Kojto 107:4f6c30876dfa 1123 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
Kojto 107:4f6c30876dfa 1124 } USB_OTG_HostTypeDef;
Kojto 107:4f6c30876dfa 1125
Kojto 107:4f6c30876dfa 1126 /**
Kojto 107:4f6c30876dfa 1127 * @brief USB_OTG_Host_Channel_Specific_Registers
Kojto 107:4f6c30876dfa 1128 */
Kojto 107:4f6c30876dfa 1129 typedef struct
Kojto 107:4f6c30876dfa 1130 {
Kojto 107:4f6c30876dfa 1131 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
Kojto 107:4f6c30876dfa 1132 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
Kojto 107:4f6c30876dfa 1133 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
Kojto 107:4f6c30876dfa 1134 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
Kojto 107:4f6c30876dfa 1135 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
Kojto 107:4f6c30876dfa 1136 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
Kojto 107:4f6c30876dfa 1137 uint32_t Reserved[2]; /*!< Reserved */
Kojto 107:4f6c30876dfa 1138 } USB_OTG_HostChannelTypeDef;
Kojto 107:4f6c30876dfa 1139 /**
Kojto 107:4f6c30876dfa 1140 * @}
Kojto 107:4f6c30876dfa 1141 */
Kojto 107:4f6c30876dfa 1142
Kojto 116:c0f6e94411f5 1143
Kojto 116:c0f6e94411f5 1144
Kojto 107:4f6c30876dfa 1145 /** @addtogroup Peripheral_memory_map
Kojto 107:4f6c30876dfa 1146 * @{
Kojto 107:4f6c30876dfa 1147 */
Kojto 107:4f6c30876dfa 1148 #define RAMITCM_BASE ((uint32_t)0x00000000) /*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM */
Kojto 107:4f6c30876dfa 1149 #define FLASHITCM_BASE ((uint32_t)0x00200000) /*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM */
Kojto 107:4f6c30876dfa 1150 #define FLASHAXI_BASE ((uint32_t)0x08000000) /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */
Kojto 107:4f6c30876dfa 1151 #define RAMDTCM_BASE ((uint32_t)0x20000000) /*!< Base address of : 64KB system data RAM accessible over DTCM */
Kojto 107:4f6c30876dfa 1152 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Base address of : AHB/ABP Peripherals */
Kojto 107:4f6c30876dfa 1153 #define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Base address of : Backup SRAM(4 KB) */
Kojto 107:4f6c30876dfa 1154 #define QSPI_BASE ((uint32_t)0x90000000) /*!< Base address of : QSPI memories accessible over AXI */
Kojto 107:4f6c30876dfa 1155 #define FMC_R_BASE ((uint32_t)0xA0000000) /*!< Base address of : FMC Control registers */
Kojto 107:4f6c30876dfa 1156 #define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< Base address of : QSPI Control registers */
Kojto 116:c0f6e94411f5 1157 #define SRAM1_BASE ((uint32_t)0x20010000) /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */
Kojto 116:c0f6e94411f5 1158 #define SRAM2_BASE ((uint32_t)0x2004C000) /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
Kojto 107:4f6c30876dfa 1159 #define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
Kojto 107:4f6c30876dfa 1160
Kojto 107:4f6c30876dfa 1161 /* Legacy define */
Kojto 107:4f6c30876dfa 1162 #define FLASH_BASE FLASHAXI_BASE
Kojto 107:4f6c30876dfa 1163
Kojto 107:4f6c30876dfa 1164 /*!< Peripheral memory map */
Kojto 107:4f6c30876dfa 1165 #define APB1PERIPH_BASE PERIPH_BASE
Kojto 107:4f6c30876dfa 1166 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
Kojto 107:4f6c30876dfa 1167 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 107:4f6c30876dfa 1168 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 107:4f6c30876dfa 1169
Kojto 107:4f6c30876dfa 1170 /*!< APB1 peripherals */
Kojto 107:4f6c30876dfa 1171 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Kojto 107:4f6c30876dfa 1172 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Kojto 107:4f6c30876dfa 1173 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Kojto 107:4f6c30876dfa 1174 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Kojto 107:4f6c30876dfa 1175 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
Kojto 107:4f6c30876dfa 1176 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
Kojto 107:4f6c30876dfa 1177 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
Kojto 107:4f6c30876dfa 1178 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
Kojto 107:4f6c30876dfa 1179 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
Kojto 107:4f6c30876dfa 1180 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
Kojto 107:4f6c30876dfa 1181 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Kojto 107:4f6c30876dfa 1182 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Kojto 107:4f6c30876dfa 1183 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Kojto 107:4f6c30876dfa 1184 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Kojto 107:4f6c30876dfa 1185 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Kojto 107:4f6c30876dfa 1186 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
Kojto 107:4f6c30876dfa 1187 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Kojto 107:4f6c30876dfa 1188 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
Kojto 107:4f6c30876dfa 1189 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
Kojto 107:4f6c30876dfa 1190 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
Kojto 107:4f6c30876dfa 1191 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Kojto 107:4f6c30876dfa 1192 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Kojto 107:4f6c30876dfa 1193 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
Kojto 107:4f6c30876dfa 1194 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000)
Kojto 107:4f6c30876dfa 1195 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
Kojto 107:4f6c30876dfa 1196 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
Kojto 107:4f6c30876dfa 1197 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
Kojto 107:4f6c30876dfa 1198 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Kojto 107:4f6c30876dfa 1199 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
Kojto 107:4f6c30876dfa 1200 #define UART7_BASE (APB1PERIPH_BASE + 0x7800)
Kojto 107:4f6c30876dfa 1201 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00)
Kojto 107:4f6c30876dfa 1202
Kojto 107:4f6c30876dfa 1203 /*!< APB2 peripherals */
Kojto 107:4f6c30876dfa 1204 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000)
Kojto 107:4f6c30876dfa 1205 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
Kojto 107:4f6c30876dfa 1206 #define USART1_BASE (APB2PERIPH_BASE + 0x1000)
Kojto 107:4f6c30876dfa 1207 #define USART6_BASE (APB2PERIPH_BASE + 0x1400)
Kojto 107:4f6c30876dfa 1208 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
Kojto 107:4f6c30876dfa 1209 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
Kojto 107:4f6c30876dfa 1210 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
Kojto 107:4f6c30876dfa 1211 #define ADC_BASE (APB2PERIPH_BASE + 0x2300)
Kojto 107:4f6c30876dfa 1212 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00)
Kojto 107:4f6c30876dfa 1213 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Kojto 107:4f6c30876dfa 1214 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400)
Kojto 107:4f6c30876dfa 1215 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
Kojto 107:4f6c30876dfa 1216 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
Kojto 107:4f6c30876dfa 1217 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000)
Kojto 107:4f6c30876dfa 1218 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400)
Kojto 107:4f6c30876dfa 1219 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800)
Kojto 107:4f6c30876dfa 1220 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000)
Kojto 107:4f6c30876dfa 1221 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400)
Kojto 107:4f6c30876dfa 1222 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
Kojto 107:4f6c30876dfa 1223 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
Kojto 107:4f6c30876dfa 1224 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
Kojto 107:4f6c30876dfa 1225 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
Kojto 107:4f6c30876dfa 1226 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
Kojto 107:4f6c30876dfa 1227 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
Kojto 107:4f6c30876dfa 1228 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
Kojto 107:4f6c30876dfa 1229 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
Kojto 116:c0f6e94411f5 1230 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
Kojto 107:4f6c30876dfa 1231 /*!< AHB1 peripherals */
Kojto 107:4f6c30876dfa 1232 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
Kojto 107:4f6c30876dfa 1233 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
Kojto 107:4f6c30876dfa 1234 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
Kojto 107:4f6c30876dfa 1235 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
Kojto 107:4f6c30876dfa 1236 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)
Kojto 107:4f6c30876dfa 1237 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)
Kojto 107:4f6c30876dfa 1238 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)
Kojto 107:4f6c30876dfa 1239 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)
Kojto 107:4f6c30876dfa 1240 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)
Kojto 107:4f6c30876dfa 1241 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)
Kojto 107:4f6c30876dfa 1242 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)
Kojto 107:4f6c30876dfa 1243 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000)
Kojto 107:4f6c30876dfa 1244 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800)
Kojto 107:4f6c30876dfa 1245 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)
Kojto 107:4f6c30876dfa 1246 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)
Kojto 107:4f6c30876dfa 1247 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010)
Kojto 107:4f6c30876dfa 1248 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028)
Kojto 107:4f6c30876dfa 1249 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040)
Kojto 107:4f6c30876dfa 1250 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058)
Kojto 107:4f6c30876dfa 1251 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070)
Kojto 107:4f6c30876dfa 1252 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088)
Kojto 107:4f6c30876dfa 1253 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)
Kojto 107:4f6c30876dfa 1254 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)
Kojto 107:4f6c30876dfa 1255 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)
Kojto 107:4f6c30876dfa 1256 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010)
Kojto 107:4f6c30876dfa 1257 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028)
Kojto 107:4f6c30876dfa 1258 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040)
Kojto 107:4f6c30876dfa 1259 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058)
Kojto 107:4f6c30876dfa 1260 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070)
Kojto 107:4f6c30876dfa 1261 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088)
Kojto 107:4f6c30876dfa 1262 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
Kojto 107:4f6c30876dfa 1263 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
Kojto 107:4f6c30876dfa 1264 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000)
Kojto 107:4f6c30876dfa 1265 #define ETH_MAC_BASE (ETH_BASE)
Kojto 107:4f6c30876dfa 1266 #define ETH_MMC_BASE (ETH_BASE + 0x0100)
Kojto 107:4f6c30876dfa 1267 #define ETH_PTP_BASE (ETH_BASE + 0x0700)
Kojto 107:4f6c30876dfa 1268 #define ETH_DMA_BASE (ETH_BASE + 0x1000)
Kojto 107:4f6c30876dfa 1269 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)
Kojto 107:4f6c30876dfa 1270 /*!< AHB2 peripherals */
Kojto 107:4f6c30876dfa 1271 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)
Kojto 107:4f6c30876dfa 1272 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
Kojto 107:4f6c30876dfa 1273 /*!< FMC Bankx registers base address */
Kojto 107:4f6c30876dfa 1274 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
Kojto 107:4f6c30876dfa 1275 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
Kojto 107:4f6c30876dfa 1276 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
Kojto 107:4f6c30876dfa 1277 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
Kojto 107:4f6c30876dfa 1278
Kojto 107:4f6c30876dfa 1279 /* Debug MCU registers base address */
Kojto 107:4f6c30876dfa 1280 #define DBGMCU_BASE ((uint32_t )0xE0042000)
Kojto 107:4f6c30876dfa 1281
Kojto 107:4f6c30876dfa 1282 /*!< USB registers base address */
Kojto 107:4f6c30876dfa 1283 #define USB_OTG_HS_PERIPH_BASE ((uint32_t )0x40040000)
Kojto 107:4f6c30876dfa 1284 #define USB_OTG_FS_PERIPH_BASE ((uint32_t )0x50000000)
Kojto 107:4f6c30876dfa 1285
Kojto 107:4f6c30876dfa 1286 #define USB_OTG_GLOBAL_BASE ((uint32_t )0x000)
Kojto 107:4f6c30876dfa 1287 #define USB_OTG_DEVICE_BASE ((uint32_t )0x800)
Kojto 107:4f6c30876dfa 1288 #define USB_OTG_IN_ENDPOINT_BASE ((uint32_t )0x900)
Kojto 107:4f6c30876dfa 1289 #define USB_OTG_OUT_ENDPOINT_BASE ((uint32_t )0xB00)
Kojto 107:4f6c30876dfa 1290 #define USB_OTG_EP_REG_SIZE ((uint32_t )0x20)
Kojto 107:4f6c30876dfa 1291 #define USB_OTG_HOST_BASE ((uint32_t )0x400)
Kojto 107:4f6c30876dfa 1292 #define USB_OTG_HOST_PORT_BASE ((uint32_t )0x440)
Kojto 107:4f6c30876dfa 1293 #define USB_OTG_HOST_CHANNEL_BASE ((uint32_t )0x500)
Kojto 107:4f6c30876dfa 1294 #define USB_OTG_HOST_CHANNEL_SIZE ((uint32_t )0x20)
Kojto 107:4f6c30876dfa 1295 #define USB_OTG_PCGCCTL_BASE ((uint32_t )0xE00)
Kojto 107:4f6c30876dfa 1296 #define USB_OTG_FIFO_BASE ((uint32_t )0x1000)
Kojto 107:4f6c30876dfa 1297 #define USB_OTG_FIFO_SIZE ((uint32_t )0x1000)
Kojto 107:4f6c30876dfa 1298
Kojto 107:4f6c30876dfa 1299 /**
Kojto 107:4f6c30876dfa 1300 * @}
Kojto 107:4f6c30876dfa 1301 */
Kojto 107:4f6c30876dfa 1302
Kojto 107:4f6c30876dfa 1303 /** @addtogroup Peripheral_declaration
Kojto 107:4f6c30876dfa 1304 * @{
Kojto 107:4f6c30876dfa 1305 */
Kojto 107:4f6c30876dfa 1306 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 107:4f6c30876dfa 1307 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 107:4f6c30876dfa 1308 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto 107:4f6c30876dfa 1309 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto 107:4f6c30876dfa 1310 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 107:4f6c30876dfa 1311 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto 107:4f6c30876dfa 1312 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto 107:4f6c30876dfa 1313 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto 107:4f6c30876dfa 1314 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 107:4f6c30876dfa 1315 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
Kojto 107:4f6c30876dfa 1316 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 107:4f6c30876dfa 1317 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 107:4f6c30876dfa 1318 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 107:4f6c30876dfa 1319 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 107:4f6c30876dfa 1320 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto 107:4f6c30876dfa 1321 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
Kojto 107:4f6c30876dfa 1322 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 107:4f6c30876dfa 1323 #define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto 107:4f6c30876dfa 1324 #define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto 107:4f6c30876dfa 1325 #define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto 107:4f6c30876dfa 1326 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 107:4f6c30876dfa 1327 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 107:4f6c30876dfa 1328 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto 107:4f6c30876dfa 1329 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
Kojto 107:4f6c30876dfa 1330 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto 107:4f6c30876dfa 1331 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto 107:4f6c30876dfa 1332 #define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto 107:4f6c30876dfa 1333 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 107:4f6c30876dfa 1334 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 107:4f6c30876dfa 1335 #define UART7 ((USART_TypeDef *) UART7_BASE)
Kojto 107:4f6c30876dfa 1336 #define UART8 ((USART_TypeDef *) UART8_BASE)
Kojto 107:4f6c30876dfa 1337 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 107:4f6c30876dfa 1338 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto 107:4f6c30876dfa 1339 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 107:4f6c30876dfa 1340 #define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto 107:4f6c30876dfa 1341 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 107:4f6c30876dfa 1342 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 107:4f6c30876dfa 1343 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto 107:4f6c30876dfa 1344 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto 107:4f6c30876dfa 1345 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
Kojto 107:4f6c30876dfa 1346 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 107:4f6c30876dfa 1347 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto 107:4f6c30876dfa 1348 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 107:4f6c30876dfa 1349 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 107:4f6c30876dfa 1350 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto 107:4f6c30876dfa 1351 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto 107:4f6c30876dfa 1352 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto 107:4f6c30876dfa 1353 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto 107:4f6c30876dfa 1354 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
Kojto 107:4f6c30876dfa 1355 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto 107:4f6c30876dfa 1356 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
Kojto 107:4f6c30876dfa 1357 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto 107:4f6c30876dfa 1358 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto 107:4f6c30876dfa 1359 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
Kojto 107:4f6c30876dfa 1360 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
Kojto 107:4f6c30876dfa 1361 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
Kojto 107:4f6c30876dfa 1362 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
Kojto 107:4f6c30876dfa 1363 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
Kojto 107:4f6c30876dfa 1364 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 107:4f6c30876dfa 1365 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 107:4f6c30876dfa 1366 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 107:4f6c30876dfa 1367 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 107:4f6c30876dfa 1368 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto 107:4f6c30876dfa 1369 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 107:4f6c30876dfa 1370 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto 107:4f6c30876dfa 1371 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 107:4f6c30876dfa 1372 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
Kojto 107:4f6c30876dfa 1373 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
Kojto 107:4f6c30876dfa 1374 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
Kojto 107:4f6c30876dfa 1375 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 107:4f6c30876dfa 1376 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 107:4f6c30876dfa 1377 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 107:4f6c30876dfa 1378 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 107:4f6c30876dfa 1379 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto 107:4f6c30876dfa 1380 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto 107:4f6c30876dfa 1381 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto 107:4f6c30876dfa 1382 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto 107:4f6c30876dfa 1383 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto 107:4f6c30876dfa 1384 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto 107:4f6c30876dfa 1385 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto 107:4f6c30876dfa 1386 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto 107:4f6c30876dfa 1387 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto 107:4f6c30876dfa 1388 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto 107:4f6c30876dfa 1389 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto 107:4f6c30876dfa 1390 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto 107:4f6c30876dfa 1391 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto 107:4f6c30876dfa 1392 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto 107:4f6c30876dfa 1393 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto 107:4f6c30876dfa 1394 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto 107:4f6c30876dfa 1395 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto 107:4f6c30876dfa 1396 #define ETH ((ETH_TypeDef *) ETH_BASE)
Kojto 107:4f6c30876dfa 1397 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
Kojto 107:4f6c30876dfa 1398 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto 107:4f6c30876dfa 1399 #define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto 107:4f6c30876dfa 1400 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto 107:4f6c30876dfa 1401 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto 107:4f6c30876dfa 1402 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto 107:4f6c30876dfa 1403 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto 107:4f6c30876dfa 1404 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto 107:4f6c30876dfa 1405 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 107:4f6c30876dfa 1406 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto 107:4f6c30876dfa 1407 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto 107:4f6c30876dfa 1408
Kojto 107:4f6c30876dfa 1409 /**
Kojto 107:4f6c30876dfa 1410 * @}
Kojto 107:4f6c30876dfa 1411 */
Kojto 107:4f6c30876dfa 1412
Kojto 107:4f6c30876dfa 1413 /** @addtogroup Exported_constants
Kojto 107:4f6c30876dfa 1414 * @{
Kojto 107:4f6c30876dfa 1415 */
Kojto 107:4f6c30876dfa 1416
Kojto 107:4f6c30876dfa 1417 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 107:4f6c30876dfa 1418 * @{
Kojto 107:4f6c30876dfa 1419 */
Kojto 107:4f6c30876dfa 1420
Kojto 107:4f6c30876dfa 1421 /******************************************************************************/
Kojto 107:4f6c30876dfa 1422 /* Peripheral Registers_Bits_Definition */
Kojto 107:4f6c30876dfa 1423 /******************************************************************************/
Kojto 107:4f6c30876dfa 1424
Kojto 107:4f6c30876dfa 1425 /******************************************************************************/
Kojto 107:4f6c30876dfa 1426 /* */
Kojto 107:4f6c30876dfa 1427 /* Analog to Digital Converter */
Kojto 107:4f6c30876dfa 1428 /* */
Kojto 107:4f6c30876dfa 1429 /******************************************************************************/
Kojto 107:4f6c30876dfa 1430 /******************** Bit definition for ADC_SR register ********************/
Kojto 107:4f6c30876dfa 1431 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!<Analog watchdog flag */
Kojto 107:4f6c30876dfa 1432 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!<End of conversion */
Kojto 107:4f6c30876dfa 1433 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!<Injected channel end of conversion */
Kojto 107:4f6c30876dfa 1434 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!<Injected channel Start flag */
Kojto 107:4f6c30876dfa 1435 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!<Regular channel Start flag */
Kojto 107:4f6c30876dfa 1436 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!<Overrun flag */
Kojto 107:4f6c30876dfa 1437
Kojto 107:4f6c30876dfa 1438 /******************* Bit definition for ADC_CR1 register ********************/
Kojto 107:4f6c30876dfa 1439 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 107:4f6c30876dfa 1440 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1441 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1442 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1443 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1444 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1445 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */
Kojto 107:4f6c30876dfa 1446 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */
Kojto 107:4f6c30876dfa 1447 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */
Kojto 107:4f6c30876dfa 1448 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */
Kojto 107:4f6c30876dfa 1449 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */
Kojto 107:4f6c30876dfa 1450 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */
Kojto 107:4f6c30876dfa 1451 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */
Kojto 107:4f6c30876dfa 1452 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */
Kojto 107:4f6c30876dfa 1453 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
Kojto 107:4f6c30876dfa 1454 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1455 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1456 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1457 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */
Kojto 107:4f6c30876dfa 1458 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */
Kojto 107:4f6c30876dfa 1459 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */
Kojto 107:4f6c30876dfa 1460 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1461 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1462 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */
Kojto 107:4f6c30876dfa 1463
Kojto 107:4f6c30876dfa 1464 /******************* Bit definition for ADC_CR2 register ********************/
Kojto 107:4f6c30876dfa 1465 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */
Kojto 107:4f6c30876dfa 1466 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */
Kojto 107:4f6c30876dfa 1467 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */
Kojto 107:4f6c30876dfa 1468 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */
Kojto 107:4f6c30876dfa 1469 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */
Kojto 107:4f6c30876dfa 1470 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */
Kojto 107:4f6c30876dfa 1471 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */
Kojto 107:4f6c30876dfa 1472 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1473 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1474 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1475 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1476 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
Kojto 107:4f6c30876dfa 1477 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1478 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1479 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */
Kojto 107:4f6c30876dfa 1480 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
Kojto 107:4f6c30876dfa 1481 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1482 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1483 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1484 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1485 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
Kojto 107:4f6c30876dfa 1486 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1487 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1488 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */
Kojto 107:4f6c30876dfa 1489
Kojto 107:4f6c30876dfa 1490 /****************** Bit definition for ADC_SMPR1 register *******************/
Kojto 107:4f6c30876dfa 1491 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
Kojto 107:4f6c30876dfa 1492 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1493 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1494 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1495 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
Kojto 107:4f6c30876dfa 1496 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1497 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1498 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1499 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
Kojto 107:4f6c30876dfa 1500 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1501 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1502 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1503 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
Kojto 107:4f6c30876dfa 1504 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1505 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1506 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1507 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
Kojto 107:4f6c30876dfa 1508 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1509 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1510 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1511 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
Kojto 107:4f6c30876dfa 1512 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1513 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1514 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1515 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
Kojto 107:4f6c30876dfa 1516 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1517 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1518 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1519 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
Kojto 107:4f6c30876dfa 1520 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1521 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1522 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1523 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
Kojto 107:4f6c30876dfa 1524 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1525 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1526 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1527
Kojto 107:4f6c30876dfa 1528 /****************** Bit definition for ADC_SMPR2 register *******************/
Kojto 107:4f6c30876dfa 1529 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
Kojto 107:4f6c30876dfa 1530 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1531 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1532 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1533 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
Kojto 107:4f6c30876dfa 1534 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1535 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1536 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1537 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
Kojto 107:4f6c30876dfa 1538 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1539 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1540 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1541 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
Kojto 107:4f6c30876dfa 1542 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1543 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1544 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1545 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
Kojto 107:4f6c30876dfa 1546 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1547 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1548 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1549 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
Kojto 107:4f6c30876dfa 1550 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1551 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1552 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1553 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
Kojto 107:4f6c30876dfa 1554 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1555 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1556 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1557 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
Kojto 107:4f6c30876dfa 1558 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1559 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1560 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1561 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
Kojto 107:4f6c30876dfa 1562 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1563 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1564 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1565 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
Kojto 107:4f6c30876dfa 1566 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1567 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1568 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1569
Kojto 107:4f6c30876dfa 1570 /****************** Bit definition for ADC_JOFR1 register *******************/
Kojto 107:4f6c30876dfa 1571 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 1 */
Kojto 107:4f6c30876dfa 1572
Kojto 107:4f6c30876dfa 1573 /****************** Bit definition for ADC_JOFR2 register *******************/
Kojto 107:4f6c30876dfa 1574 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 2 */
Kojto 107:4f6c30876dfa 1575
Kojto 107:4f6c30876dfa 1576 /****************** Bit definition for ADC_JOFR3 register *******************/
Kojto 107:4f6c30876dfa 1577 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 3 */
Kojto 107:4f6c30876dfa 1578
Kojto 107:4f6c30876dfa 1579 /****************** Bit definition for ADC_JOFR4 register *******************/
Kojto 107:4f6c30876dfa 1580 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x0FFF) /*!<Data offset for injected channel 4 */
Kojto 107:4f6c30876dfa 1581
Kojto 107:4f6c30876dfa 1582 /******************* Bit definition for ADC_HTR register ********************/
Kojto 107:4f6c30876dfa 1583 #define ADC_HTR_HT ((uint32_t)0x0FFF) /*!<Analog watchdog high threshold */
Kojto 107:4f6c30876dfa 1584
Kojto 107:4f6c30876dfa 1585 /******************* Bit definition for ADC_LTR register ********************/
Kojto 107:4f6c30876dfa 1586 #define ADC_LTR_LT ((uint32_t)0x0FFF) /*!<Analog watchdog low threshold */
Kojto 107:4f6c30876dfa 1587
Kojto 107:4f6c30876dfa 1588 /******************* Bit definition for ADC_SQR1 register *******************/
Kojto 107:4f6c30876dfa 1589 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1590 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1591 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1592 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1593 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1594 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1595 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1596 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1597 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1598 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1599 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1600 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1601 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1602 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1603 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1604 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1605 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1606 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1607 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1608 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1609 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1610 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1611 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1612 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1613 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */
Kojto 107:4f6c30876dfa 1614 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1615 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1616 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1617 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1618
Kojto 107:4f6c30876dfa 1619 /******************* Bit definition for ADC_SQR2 register *******************/
Kojto 107:4f6c30876dfa 1620 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1621 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1622 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1623 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1624 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1625 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1626 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1627 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1628 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1629 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1630 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1631 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1632 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1633 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1634 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1635 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1636 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1637 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1638 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1639 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1640 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1641 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1642 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1643 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1644 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1645 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1646 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1647 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1648 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1649 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1650 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1651 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1652 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1653 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1654 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1655 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1656
Kojto 107:4f6c30876dfa 1657 /******************* Bit definition for ADC_SQR3 register *******************/
Kojto 107:4f6c30876dfa 1658 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1659 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1660 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1661 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1662 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1663 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1664 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1665 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1666 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1667 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1668 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1669 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1670 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1671 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1672 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1673 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1674 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1675 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1676 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1677 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1678 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1679 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1680 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1681 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1682 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1683 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1684 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1685 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1686 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1687 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1688 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
Kojto 107:4f6c30876dfa 1689 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1690 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1691 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1692 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1693 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1694
Kojto 107:4f6c30876dfa 1695 /******************* Bit definition for ADC_JSQR register *******************/
Kojto 107:4f6c30876dfa 1696 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
Kojto 107:4f6c30876dfa 1697 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1698 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1699 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1700 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1701 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1702 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
Kojto 107:4f6c30876dfa 1703 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1704 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1705 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1706 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1707 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1708 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
Kojto 107:4f6c30876dfa 1709 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1710 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1711 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1712 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1713 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1714 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
Kojto 107:4f6c30876dfa 1715 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1716 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1717 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1718 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1719 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1720 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */
Kojto 107:4f6c30876dfa 1721 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1722 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1723
Kojto 107:4f6c30876dfa 1724 /******************* Bit definition for ADC_JDR1 register *******************/
Kojto 107:4f6c30876dfa 1725 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
Kojto 107:4f6c30876dfa 1726
Kojto 107:4f6c30876dfa 1727 /******************* Bit definition for ADC_JDR2 register *******************/
Kojto 107:4f6c30876dfa 1728 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
Kojto 107:4f6c30876dfa 1729
Kojto 107:4f6c30876dfa 1730 /******************* Bit definition for ADC_JDR3 register *******************/
Kojto 107:4f6c30876dfa 1731 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
Kojto 107:4f6c30876dfa 1732
Kojto 107:4f6c30876dfa 1733 /******************* Bit definition for ADC_JDR4 register *******************/
Kojto 107:4f6c30876dfa 1734 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */
Kojto 107:4f6c30876dfa 1735
Kojto 107:4f6c30876dfa 1736 /******************** Bit definition for ADC_DR register ********************/
Kojto 107:4f6c30876dfa 1737 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */
Kojto 107:4f6c30876dfa 1738 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */
Kojto 107:4f6c30876dfa 1739
Kojto 107:4f6c30876dfa 1740 /******************* Bit definition for ADC_CSR register ********************/
Kojto 107:4f6c30876dfa 1741 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */
Kojto 107:4f6c30876dfa 1742 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */
Kojto 107:4f6c30876dfa 1743 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */
Kojto 107:4f6c30876dfa 1744 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */
Kojto 107:4f6c30876dfa 1745 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */
Kojto 107:4f6c30876dfa 1746 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */
Kojto 107:4f6c30876dfa 1747 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */
Kojto 107:4f6c30876dfa 1748 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */
Kojto 107:4f6c30876dfa 1749 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */
Kojto 107:4f6c30876dfa 1750 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */
Kojto 107:4f6c30876dfa 1751 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */
Kojto 107:4f6c30876dfa 1752 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */
Kojto 107:4f6c30876dfa 1753 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */
Kojto 107:4f6c30876dfa 1754 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */
Kojto 107:4f6c30876dfa 1755 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */
Kojto 107:4f6c30876dfa 1756 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */
Kojto 107:4f6c30876dfa 1757 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */
Kojto 107:4f6c30876dfa 1758 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */
Kojto 107:4f6c30876dfa 1759
Kojto 107:4f6c30876dfa 1760 /******************* Bit definition for ADC_CCR register ********************/
Kojto 107:4f6c30876dfa 1761 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
Kojto 107:4f6c30876dfa 1762 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1763 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1764 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1765 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1766 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 1767 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
Kojto 107:4f6c30876dfa 1768 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1769 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1770 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1771 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1772 #define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */
Kojto 107:4f6c30876dfa 1773 #define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
Kojto 107:4f6c30876dfa 1774 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1775 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1776 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */
Kojto 107:4f6c30876dfa 1777 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1778 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1779 #define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */
Kojto 107:4f6c30876dfa 1780 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */
Kojto 107:4f6c30876dfa 1781
Kojto 107:4f6c30876dfa 1782 /******************* Bit definition for ADC_CDR register ********************/
Kojto 107:4f6c30876dfa 1783 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */
Kojto 107:4f6c30876dfa 1784 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */
Kojto 107:4f6c30876dfa 1785
Kojto 107:4f6c30876dfa 1786 /******************************************************************************/
Kojto 107:4f6c30876dfa 1787 /* */
Kojto 107:4f6c30876dfa 1788 /* Controller Area Network */
Kojto 107:4f6c30876dfa 1789 /* */
Kojto 107:4f6c30876dfa 1790 /******************************************************************************/
Kojto 107:4f6c30876dfa 1791 /*!<CAN control and status registers */
Kojto 107:4f6c30876dfa 1792 /******************* Bit definition for CAN_MCR register ********************/
Kojto 107:4f6c30876dfa 1793 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
Kojto 107:4f6c30876dfa 1794 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
Kojto 107:4f6c30876dfa 1795 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
Kojto 107:4f6c30876dfa 1796 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
Kojto 107:4f6c30876dfa 1797 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
Kojto 107:4f6c30876dfa 1798 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
Kojto 107:4f6c30876dfa 1799 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
Kojto 107:4f6c30876dfa 1800 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
Kojto 107:4f6c30876dfa 1801 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
Kojto 107:4f6c30876dfa 1802
Kojto 107:4f6c30876dfa 1803 /******************* Bit definition for CAN_MSR register ********************/
Kojto 107:4f6c30876dfa 1804 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
Kojto 107:4f6c30876dfa 1805 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
Kojto 107:4f6c30876dfa 1806 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
Kojto 107:4f6c30876dfa 1807 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
Kojto 107:4f6c30876dfa 1808 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
Kojto 107:4f6c30876dfa 1809 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
Kojto 107:4f6c30876dfa 1810 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
Kojto 107:4f6c30876dfa 1811 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
Kojto 107:4f6c30876dfa 1812 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
Kojto 107:4f6c30876dfa 1813
Kojto 107:4f6c30876dfa 1814 /******************* Bit definition for CAN_TSR register ********************/
Kojto 107:4f6c30876dfa 1815 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
Kojto 107:4f6c30876dfa 1816 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
Kojto 107:4f6c30876dfa 1817 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
Kojto 107:4f6c30876dfa 1818 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
Kojto 107:4f6c30876dfa 1819 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
Kojto 107:4f6c30876dfa 1820 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
Kojto 107:4f6c30876dfa 1821 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
Kojto 107:4f6c30876dfa 1822 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
Kojto 107:4f6c30876dfa 1823 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
Kojto 107:4f6c30876dfa 1824 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
Kojto 107:4f6c30876dfa 1825 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
Kojto 107:4f6c30876dfa 1826 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
Kojto 107:4f6c30876dfa 1827 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
Kojto 107:4f6c30876dfa 1828 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
Kojto 107:4f6c30876dfa 1829 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
Kojto 107:4f6c30876dfa 1830 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
Kojto 107:4f6c30876dfa 1831
Kojto 107:4f6c30876dfa 1832 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
Kojto 107:4f6c30876dfa 1833 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
Kojto 107:4f6c30876dfa 1834 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
Kojto 107:4f6c30876dfa 1835 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
Kojto 107:4f6c30876dfa 1836
Kojto 107:4f6c30876dfa 1837 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
Kojto 107:4f6c30876dfa 1838 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
Kojto 107:4f6c30876dfa 1839 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
Kojto 107:4f6c30876dfa 1840 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
Kojto 107:4f6c30876dfa 1841
Kojto 107:4f6c30876dfa 1842 /******************* Bit definition for CAN_RF0R register *******************/
Kojto 107:4f6c30876dfa 1843 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
Kojto 107:4f6c30876dfa 1844 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
Kojto 107:4f6c30876dfa 1845 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
Kojto 107:4f6c30876dfa 1846 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
Kojto 107:4f6c30876dfa 1847
Kojto 107:4f6c30876dfa 1848 /******************* Bit definition for CAN_RF1R register *******************/
Kojto 107:4f6c30876dfa 1849 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
Kojto 107:4f6c30876dfa 1850 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
Kojto 107:4f6c30876dfa 1851 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
Kojto 107:4f6c30876dfa 1852 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
Kojto 107:4f6c30876dfa 1853
Kojto 107:4f6c30876dfa 1854 /******************** Bit definition for CAN_IER register *******************/
Kojto 107:4f6c30876dfa 1855 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
Kojto 107:4f6c30876dfa 1856 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
Kojto 107:4f6c30876dfa 1857 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
Kojto 107:4f6c30876dfa 1858 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
Kojto 107:4f6c30876dfa 1859 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
Kojto 107:4f6c30876dfa 1860 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
Kojto 107:4f6c30876dfa 1861 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
Kojto 107:4f6c30876dfa 1862 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
Kojto 107:4f6c30876dfa 1863 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
Kojto 107:4f6c30876dfa 1864 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
Kojto 107:4f6c30876dfa 1865 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
Kojto 107:4f6c30876dfa 1866 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
Kojto 107:4f6c30876dfa 1867 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
Kojto 107:4f6c30876dfa 1868 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
Kojto 107:4f6c30876dfa 1869
Kojto 107:4f6c30876dfa 1870 /******************** Bit definition for CAN_ESR register *******************/
Kojto 107:4f6c30876dfa 1871 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
Kojto 107:4f6c30876dfa 1872 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
Kojto 107:4f6c30876dfa 1873 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
Kojto 107:4f6c30876dfa 1874
Kojto 107:4f6c30876dfa 1875 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
Kojto 107:4f6c30876dfa 1876 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1877 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1878 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1879
Kojto 107:4f6c30876dfa 1880 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
Kojto 107:4f6c30876dfa 1881 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
Kojto 107:4f6c30876dfa 1882
Kojto 107:4f6c30876dfa 1883 /******************* Bit definition for CAN_BTR register ********************/
Kojto 107:4f6c30876dfa 1884 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
Kojto 107:4f6c30876dfa 1885 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
Kojto 107:4f6c30876dfa 1886 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1887 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1888 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1889 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 1890 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
Kojto 107:4f6c30876dfa 1891 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1892 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1893 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 1894 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
Kojto 107:4f6c30876dfa 1895 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 1896 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 1897 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
Kojto 107:4f6c30876dfa 1898 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
Kojto 107:4f6c30876dfa 1899
Kojto 107:4f6c30876dfa 1900 /*!<Mailbox registers */
Kojto 107:4f6c30876dfa 1901 /****************** Bit definition for CAN_TI0R register ********************/
Kojto 107:4f6c30876dfa 1902 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 107:4f6c30876dfa 1903 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 107:4f6c30876dfa 1904 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 107:4f6c30876dfa 1905 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 107:4f6c30876dfa 1906 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 107:4f6c30876dfa 1907
Kojto 107:4f6c30876dfa 1908 /****************** Bit definition for CAN_TDT0R register *******************/
Kojto 107:4f6c30876dfa 1909 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 107:4f6c30876dfa 1910 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 107:4f6c30876dfa 1911 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 107:4f6c30876dfa 1912
Kojto 107:4f6c30876dfa 1913 /****************** Bit definition for CAN_TDL0R register *******************/
Kojto 107:4f6c30876dfa 1914 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 107:4f6c30876dfa 1915 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 107:4f6c30876dfa 1916 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 107:4f6c30876dfa 1917 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 107:4f6c30876dfa 1918
Kojto 107:4f6c30876dfa 1919 /****************** Bit definition for CAN_TDH0R register *******************/
Kojto 107:4f6c30876dfa 1920 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 107:4f6c30876dfa 1921 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 107:4f6c30876dfa 1922 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 107:4f6c30876dfa 1923 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 107:4f6c30876dfa 1924
Kojto 107:4f6c30876dfa 1925 /******************* Bit definition for CAN_TI1R register *******************/
Kojto 107:4f6c30876dfa 1926 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 107:4f6c30876dfa 1927 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 107:4f6c30876dfa 1928 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 107:4f6c30876dfa 1929 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 107:4f6c30876dfa 1930 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 107:4f6c30876dfa 1931
Kojto 107:4f6c30876dfa 1932 /******************* Bit definition for CAN_TDT1R register ******************/
Kojto 107:4f6c30876dfa 1933 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 107:4f6c30876dfa 1934 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 107:4f6c30876dfa 1935 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 107:4f6c30876dfa 1936
Kojto 107:4f6c30876dfa 1937 /******************* Bit definition for CAN_TDL1R register ******************/
Kojto 107:4f6c30876dfa 1938 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 107:4f6c30876dfa 1939 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 107:4f6c30876dfa 1940 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 107:4f6c30876dfa 1941 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 107:4f6c30876dfa 1942
Kojto 107:4f6c30876dfa 1943 /******************* Bit definition for CAN_TDH1R register ******************/
Kojto 107:4f6c30876dfa 1944 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 107:4f6c30876dfa 1945 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 107:4f6c30876dfa 1946 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 107:4f6c30876dfa 1947 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 107:4f6c30876dfa 1948
Kojto 107:4f6c30876dfa 1949 /******************* Bit definition for CAN_TI2R register *******************/
Kojto 107:4f6c30876dfa 1950 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
Kojto 107:4f6c30876dfa 1951 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 107:4f6c30876dfa 1952 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 107:4f6c30876dfa 1953 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 107:4f6c30876dfa 1954 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 107:4f6c30876dfa 1955
Kojto 107:4f6c30876dfa 1956 /******************* Bit definition for CAN_TDT2R register ******************/
Kojto 107:4f6c30876dfa 1957 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 107:4f6c30876dfa 1958 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
Kojto 107:4f6c30876dfa 1959 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 107:4f6c30876dfa 1960
Kojto 107:4f6c30876dfa 1961 /******************* Bit definition for CAN_TDL2R register ******************/
Kojto 107:4f6c30876dfa 1962 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 107:4f6c30876dfa 1963 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 107:4f6c30876dfa 1964 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 107:4f6c30876dfa 1965 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 107:4f6c30876dfa 1966
Kojto 107:4f6c30876dfa 1967 /******************* Bit definition for CAN_TDH2R register ******************/
Kojto 107:4f6c30876dfa 1968 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 107:4f6c30876dfa 1969 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 107:4f6c30876dfa 1970 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 107:4f6c30876dfa 1971 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 107:4f6c30876dfa 1972
Kojto 107:4f6c30876dfa 1973 /******************* Bit definition for CAN_RI0R register *******************/
Kojto 107:4f6c30876dfa 1974 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 107:4f6c30876dfa 1975 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 107:4f6c30876dfa 1976 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
Kojto 107:4f6c30876dfa 1977 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 107:4f6c30876dfa 1978
Kojto 107:4f6c30876dfa 1979 /******************* Bit definition for CAN_RDT0R register ******************/
Kojto 107:4f6c30876dfa 1980 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 107:4f6c30876dfa 1981 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 107:4f6c30876dfa 1982 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 107:4f6c30876dfa 1983
Kojto 107:4f6c30876dfa 1984 /******************* Bit definition for CAN_RDL0R register ******************/
Kojto 107:4f6c30876dfa 1985 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 107:4f6c30876dfa 1986 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 107:4f6c30876dfa 1987 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 107:4f6c30876dfa 1988 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 107:4f6c30876dfa 1989
Kojto 107:4f6c30876dfa 1990 /******************* Bit definition for CAN_RDH0R register ******************/
Kojto 107:4f6c30876dfa 1991 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 107:4f6c30876dfa 1992 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 107:4f6c30876dfa 1993 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 107:4f6c30876dfa 1994 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 107:4f6c30876dfa 1995
Kojto 107:4f6c30876dfa 1996 /******************* Bit definition for CAN_RI1R register *******************/
Kojto 107:4f6c30876dfa 1997 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
Kojto 107:4f6c30876dfa 1998 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
Kojto 107:4f6c30876dfa 1999 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
Kojto 107:4f6c30876dfa 2000 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
Kojto 107:4f6c30876dfa 2001
Kojto 107:4f6c30876dfa 2002 /******************* Bit definition for CAN_RDT1R register ******************/
Kojto 107:4f6c30876dfa 2003 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
Kojto 107:4f6c30876dfa 2004 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
Kojto 107:4f6c30876dfa 2005 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
Kojto 107:4f6c30876dfa 2006
Kojto 107:4f6c30876dfa 2007 /******************* Bit definition for CAN_RDL1R register ******************/
Kojto 107:4f6c30876dfa 2008 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
Kojto 107:4f6c30876dfa 2009 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
Kojto 107:4f6c30876dfa 2010 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
Kojto 107:4f6c30876dfa 2011 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
Kojto 107:4f6c30876dfa 2012
Kojto 107:4f6c30876dfa 2013 /******************* Bit definition for CAN_RDH1R register ******************/
Kojto 107:4f6c30876dfa 2014 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
Kojto 107:4f6c30876dfa 2015 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
Kojto 107:4f6c30876dfa 2016 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
Kojto 107:4f6c30876dfa 2017 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
Kojto 107:4f6c30876dfa 2018
Kojto 107:4f6c30876dfa 2019 /*!<CAN filter registers */
Kojto 107:4f6c30876dfa 2020 /******************* Bit definition for CAN_FMR register ********************/
Kojto 107:4f6c30876dfa 2021 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
Kojto 107:4f6c30876dfa 2022 #define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
Kojto 107:4f6c30876dfa 2023
Kojto 107:4f6c30876dfa 2024 /******************* Bit definition for CAN_FM1R register *******************/
Kojto 107:4f6c30876dfa 2025 #define CAN_FM1R_FBM ((uint32_t)0x3FFF) /*!<Filter Mode */
Kojto 107:4f6c30876dfa 2026 #define CAN_FM1R_FBM0 ((uint32_t)0x0001) /*!<Filter Init Mode bit 0 */
Kojto 107:4f6c30876dfa 2027 #define CAN_FM1R_FBM1 ((uint32_t)0x0002) /*!<Filter Init Mode bit 1 */
Kojto 107:4f6c30876dfa 2028 #define CAN_FM1R_FBM2 ((uint32_t)0x0004) /*!<Filter Init Mode bit 2 */
Kojto 107:4f6c30876dfa 2029 #define CAN_FM1R_FBM3 ((uint32_t)0x0008) /*!<Filter Init Mode bit 3 */
Kojto 107:4f6c30876dfa 2030 #define CAN_FM1R_FBM4 ((uint32_t)0x0010) /*!<Filter Init Mode bit 4 */
Kojto 107:4f6c30876dfa 2031 #define CAN_FM1R_FBM5 ((uint32_t)0x0020) /*!<Filter Init Mode bit 5 */
Kojto 107:4f6c30876dfa 2032 #define CAN_FM1R_FBM6 ((uint32_t)0x0040) /*!<Filter Init Mode bit 6 */
Kojto 107:4f6c30876dfa 2033 #define CAN_FM1R_FBM7 ((uint32_t)0x0080) /*!<Filter Init Mode bit 7 */
Kojto 107:4f6c30876dfa 2034 #define CAN_FM1R_FBM8 ((uint32_t)0x0100) /*!<Filter Init Mode bit 8 */
Kojto 107:4f6c30876dfa 2035 #define CAN_FM1R_FBM9 ((uint32_t)0x0200) /*!<Filter Init Mode bit 9 */
Kojto 107:4f6c30876dfa 2036 #define CAN_FM1R_FBM10 ((uint32_t)0x0400) /*!<Filter Init Mode bit 10 */
Kojto 107:4f6c30876dfa 2037 #define CAN_FM1R_FBM11 ((uint32_t)0x0800) /*!<Filter Init Mode bit 11 */
Kojto 107:4f6c30876dfa 2038 #define CAN_FM1R_FBM12 ((uint32_t)0x1000) /*!<Filter Init Mode bit 12 */
Kojto 107:4f6c30876dfa 2039 #define CAN_FM1R_FBM13 ((uint32_t)0x2000) /*!<Filter Init Mode bit 13 */
Kojto 107:4f6c30876dfa 2040
Kojto 107:4f6c30876dfa 2041 /******************* Bit definition for CAN_FS1R register *******************/
Kojto 107:4f6c30876dfa 2042 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
Kojto 107:4f6c30876dfa 2043 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
Kojto 107:4f6c30876dfa 2044 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
Kojto 107:4f6c30876dfa 2045 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
Kojto 107:4f6c30876dfa 2046 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
Kojto 107:4f6c30876dfa 2047 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
Kojto 107:4f6c30876dfa 2048 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
Kojto 107:4f6c30876dfa 2049 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
Kojto 107:4f6c30876dfa 2050 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
Kojto 107:4f6c30876dfa 2051 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
Kojto 107:4f6c30876dfa 2052 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
Kojto 107:4f6c30876dfa 2053 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
Kojto 107:4f6c30876dfa 2054 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
Kojto 107:4f6c30876dfa 2055 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
Kojto 107:4f6c30876dfa 2056 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
Kojto 107:4f6c30876dfa 2057
Kojto 107:4f6c30876dfa 2058 /****************** Bit definition for CAN_FFA1R register *******************/
Kojto 107:4f6c30876dfa 2059 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
Kojto 107:4f6c30876dfa 2060 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
Kojto 107:4f6c30876dfa 2061 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
Kojto 107:4f6c30876dfa 2062 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
Kojto 107:4f6c30876dfa 2063 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
Kojto 107:4f6c30876dfa 2064 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
Kojto 107:4f6c30876dfa 2065 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
Kojto 107:4f6c30876dfa 2066 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
Kojto 107:4f6c30876dfa 2067 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
Kojto 107:4f6c30876dfa 2068 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
Kojto 107:4f6c30876dfa 2069 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
Kojto 107:4f6c30876dfa 2070 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
Kojto 107:4f6c30876dfa 2071 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
Kojto 107:4f6c30876dfa 2072 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
Kojto 107:4f6c30876dfa 2073 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
Kojto 107:4f6c30876dfa 2074
Kojto 107:4f6c30876dfa 2075 /******************* Bit definition for CAN_FA1R register *******************/
Kojto 107:4f6c30876dfa 2076 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
Kojto 107:4f6c30876dfa 2077 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
Kojto 107:4f6c30876dfa 2078 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
Kojto 107:4f6c30876dfa 2079 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
Kojto 107:4f6c30876dfa 2080 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
Kojto 107:4f6c30876dfa 2081 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
Kojto 107:4f6c30876dfa 2082 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
Kojto 107:4f6c30876dfa 2083 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
Kojto 107:4f6c30876dfa 2084 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
Kojto 107:4f6c30876dfa 2085 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
Kojto 107:4f6c30876dfa 2086 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
Kojto 107:4f6c30876dfa 2087 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
Kojto 107:4f6c30876dfa 2088 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
Kojto 107:4f6c30876dfa 2089 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
Kojto 107:4f6c30876dfa 2090 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
Kojto 107:4f6c30876dfa 2091
Kojto 107:4f6c30876dfa 2092 /******************* Bit definition for CAN_F0R1 register *******************/
Kojto 107:4f6c30876dfa 2093 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2094 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2095 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2096 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2097 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2098 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2099 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2100 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2101 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2102 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2103 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2104 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2105 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2106 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2107 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2108 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2109 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2110 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2111 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2112 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2113 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2114 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2115 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2116 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2117 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2118 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2119 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2120 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2121 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2122 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2123 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2124 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2125
Kojto 107:4f6c30876dfa 2126 /******************* Bit definition for CAN_F1R1 register *******************/
Kojto 107:4f6c30876dfa 2127 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2128 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2129 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2130 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2131 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2132 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2133 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2134 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2135 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2136 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2137 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2138 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2139 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2140 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2141 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2142 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2143 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2144 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2145 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2146 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2147 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2148 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2149 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2150 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2151 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2152 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2153 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2154 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2155 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2156 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2157 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2158 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2159
Kojto 107:4f6c30876dfa 2160 /******************* Bit definition for CAN_F2R1 register *******************/
Kojto 107:4f6c30876dfa 2161 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2162 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2163 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2164 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2165 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2166 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2167 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2168 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2169 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2170 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2171 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2172 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2173 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2174 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2175 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2176 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2177 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2178 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2179 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2180 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2181 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2182 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2183 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2184 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2185 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2186 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2187 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2188 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2189 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2190 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2191 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2192 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2193
Kojto 107:4f6c30876dfa 2194 /******************* Bit definition for CAN_F3R1 register *******************/
Kojto 107:4f6c30876dfa 2195 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2196 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2197 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2198 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2199 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2200 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2201 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2202 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2203 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2204 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2205 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2206 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2207 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2208 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2209 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2210 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2211 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2212 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2213 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2214 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2215 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2216 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2217 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2218 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2219 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2220 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2221 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2222 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2223 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2224 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2225 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2226 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2227
Kojto 107:4f6c30876dfa 2228 /******************* Bit definition for CAN_F4R1 register *******************/
Kojto 107:4f6c30876dfa 2229 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2230 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2231 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2232 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2233 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2234 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2235 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2236 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2237 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2238 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2239 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2240 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2241 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2242 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2243 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2244 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2245 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2246 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2247 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2248 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2249 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2250 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2251 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2252 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2253 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2254 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2255 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2256 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2257 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2258 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2259 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2260 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2261
Kojto 107:4f6c30876dfa 2262 /******************* Bit definition for CAN_F5R1 register *******************/
Kojto 107:4f6c30876dfa 2263 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2264 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2265 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2266 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2267 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2268 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2269 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2270 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2271 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2272 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2273 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2274 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2275 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2276 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2277 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2278 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2279 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2280 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2281 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2282 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2283 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2284 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2285 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2286 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2287 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2288 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2289 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2290 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2291 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2292 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2293 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2294 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2295
Kojto 107:4f6c30876dfa 2296 /******************* Bit definition for CAN_F6R1 register *******************/
Kojto 107:4f6c30876dfa 2297 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2298 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2299 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2300 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2301 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2302 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2303 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2304 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2305 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2306 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2307 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2308 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2309 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2310 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2311 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2312 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2313 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2314 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2315 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2316 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2317 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2318 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2319 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2320 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2321 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2322 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2323 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2324 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2325 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2326 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2327 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2328 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2329
Kojto 107:4f6c30876dfa 2330 /******************* Bit definition for CAN_F7R1 register *******************/
Kojto 107:4f6c30876dfa 2331 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2332 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2333 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2334 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2335 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2336 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2337 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2338 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2339 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2340 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2341 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2342 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2343 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2344 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2345 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2346 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2347 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2348 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2349 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2350 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2351 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2352 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2353 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2354 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2355 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2356 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2357 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2358 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2359 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2360 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2361 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2362 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2363
Kojto 107:4f6c30876dfa 2364 /******************* Bit definition for CAN_F8R1 register *******************/
Kojto 107:4f6c30876dfa 2365 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2366 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2367 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2368 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2369 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2370 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2371 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2372 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2373 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2374 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2375 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2376 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2377 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2378 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2379 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2380 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2381 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2382 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2383 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2384 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2385 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2386 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2387 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2388 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2389 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2390 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2391 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2392 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2393 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2394 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2395 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2396 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2397
Kojto 107:4f6c30876dfa 2398 /******************* Bit definition for CAN_F9R1 register *******************/
Kojto 107:4f6c30876dfa 2399 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2400 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2401 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2402 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2403 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2404 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2405 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2406 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2407 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2408 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2409 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2410 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2411 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2412 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2413 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2414 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2415 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2416 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2417 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2418 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2419 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2420 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2421 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2422 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2423 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2424 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2425 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2426 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2427 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2428 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2429 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2430 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2431
Kojto 107:4f6c30876dfa 2432 /******************* Bit definition for CAN_F10R1 register ******************/
Kojto 107:4f6c30876dfa 2433 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2434 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2435 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2436 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2437 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2438 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2439 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2440 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2441 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2442 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2443 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2444 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2445 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2446 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2447 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2448 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2449 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2450 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2451 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2452 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2453 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2454 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2455 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2456 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2457 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2458 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2459 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2460 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2461 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2462 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2463 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2464 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2465
Kojto 107:4f6c30876dfa 2466 /******************* Bit definition for CAN_F11R1 register ******************/
Kojto 107:4f6c30876dfa 2467 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2468 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2469 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2470 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2471 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2472 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2473 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2474 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2475 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2476 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2477 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2478 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2479 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2480 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2481 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2482 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2483 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2484 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2485 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2486 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2487 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2488 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2489 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2490 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2491 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2492 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2493 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2494 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2495 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2496 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2497 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2498 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2499
Kojto 107:4f6c30876dfa 2500 /******************* Bit definition for CAN_F12R1 register ******************/
Kojto 107:4f6c30876dfa 2501 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2502 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2503 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2504 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2505 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2506 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2507 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2508 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2509 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2510 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2511 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2512 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2513 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2514 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2515 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2516 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2517 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2518 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2519 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2520 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2521 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2522 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2523 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2524 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2525 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2526 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2527 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2528 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2529 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2530 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2531 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2532 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2533
Kojto 107:4f6c30876dfa 2534 /******************* Bit definition for CAN_F13R1 register ******************/
Kojto 107:4f6c30876dfa 2535 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2536 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2537 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2538 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2539 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2540 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2541 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2542 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2543 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2544 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2545 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2546 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2547 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2548 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2549 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2550 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2551 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2552 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2553 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2554 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2555 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2556 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2557 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2558 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2559 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2560 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2561 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2562 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2563 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2564 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2565 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2566 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2567
Kojto 107:4f6c30876dfa 2568 /******************* Bit definition for CAN_F0R2 register *******************/
Kojto 107:4f6c30876dfa 2569 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2570 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2571 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2572 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2573 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2574 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2575 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2576 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2577 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2578 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2579 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2580 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2581 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2582 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2583 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2584 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2585 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2586 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2587 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2588 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2589 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2590 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2591 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2592 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2593 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2594 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2595 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2596 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2597 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2598 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2599 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2600 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2601
Kojto 107:4f6c30876dfa 2602 /******************* Bit definition for CAN_F1R2 register *******************/
Kojto 107:4f6c30876dfa 2603 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2604 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2605 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2606 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2607 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2608 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2609 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2610 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2611 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2612 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2613 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2614 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2615 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2616 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2617 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2618 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2619 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2620 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2621 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2622 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2623 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2624 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2625 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2626 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2627 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2628 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2629 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2630 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2631 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2632 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2633 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2634 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2635
Kojto 107:4f6c30876dfa 2636 /******************* Bit definition for CAN_F2R2 register *******************/
Kojto 107:4f6c30876dfa 2637 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2638 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2639 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2640 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2641 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2642 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2643 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2644 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2645 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2646 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2647 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2648 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2649 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2650 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2651 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2652 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2653 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2654 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2655 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2656 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2657 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2658 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2659 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2660 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2661 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2662 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2663 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2664 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2665 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2666 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2667 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2668 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2669
Kojto 107:4f6c30876dfa 2670 /******************* Bit definition for CAN_F3R2 register *******************/
Kojto 107:4f6c30876dfa 2671 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2672 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2673 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2674 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2675 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2676 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2677 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2678 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2679 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2680 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2681 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2682 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2683 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2684 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2685 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2686 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2687 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2688 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2689 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2690 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2691 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2692 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2693 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2694 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2695 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2696 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2697 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2698 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2699 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2700 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2701 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2702 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2703
Kojto 107:4f6c30876dfa 2704 /******************* Bit definition for CAN_F4R2 register *******************/
Kojto 107:4f6c30876dfa 2705 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2706 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2707 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2708 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2709 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2710 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2711 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2712 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2713 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2714 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2715 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2716 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2717 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2718 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2719 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2720 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2721 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2722 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2723 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2724 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2725 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2726 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2727 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2728 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2729 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2730 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2731 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2732 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2733 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2734 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2735 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2736 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2737
Kojto 107:4f6c30876dfa 2738 /******************* Bit definition for CAN_F5R2 register *******************/
Kojto 107:4f6c30876dfa 2739 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2740 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2741 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2742 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2743 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2744 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2745 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2746 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2747 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2748 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2749 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2750 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2751 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2752 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2753 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2754 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2755 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2756 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2757 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2758 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2759 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2760 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2761 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2762 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2763 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2764 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2765 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2766 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2767 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2768 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2769 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2770 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2771
Kojto 107:4f6c30876dfa 2772 /******************* Bit definition for CAN_F6R2 register *******************/
Kojto 107:4f6c30876dfa 2773 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2774 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2775 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2776 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2777 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2778 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2779 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2780 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2781 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2782 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2783 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2784 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2785 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2786 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2787 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2788 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2789 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2790 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2791 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2792 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2793 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2794 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2795 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2796 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2797 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2798 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2799 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2800 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2801 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2802 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2803 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2804 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2805
Kojto 107:4f6c30876dfa 2806 /******************* Bit definition for CAN_F7R2 register *******************/
Kojto 107:4f6c30876dfa 2807 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2808 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2809 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2810 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2811 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2812 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2813 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2814 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2815 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2816 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2817 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2818 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2819 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2820 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2821 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2822 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2823 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2824 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2825 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2826 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2827 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2828 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2829 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2830 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2831 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2832 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2833 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2834 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2835 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2836 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2837 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2838 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2839
Kojto 107:4f6c30876dfa 2840 /******************* Bit definition for CAN_F8R2 register *******************/
Kojto 107:4f6c30876dfa 2841 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2842 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2843 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2844 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2845 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2846 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2847 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2848 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2849 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2850 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2851 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2852 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2853 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2854 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2855 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2856 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2857 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2858 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2859 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2860 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2861 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2862 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2863 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2864 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2865 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2866 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2867 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2868 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2869 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2870 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2871 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2872 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2873
Kojto 107:4f6c30876dfa 2874 /******************* Bit definition for CAN_F9R2 register *******************/
Kojto 107:4f6c30876dfa 2875 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2876 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2877 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2878 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2879 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2880 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2881 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2882 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2883 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2884 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2885 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2886 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2887 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2888 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2889 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2890 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2891 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2892 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2893 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2894 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2895 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2896 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2897 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2898 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2899 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2900 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2901 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2902 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2903 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2904 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2905 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2906 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2907
Kojto 107:4f6c30876dfa 2908 /******************* Bit definition for CAN_F10R2 register ******************/
Kojto 107:4f6c30876dfa 2909 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2910 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2911 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2912 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2913 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2914 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2915 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2916 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2917 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2918 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2919 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2920 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2921 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2922 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2923 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2924 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2925 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2926 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2927 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2928 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2929 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2930 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2931 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2932 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2933 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2934 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2935 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2936 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2937 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2938 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2939 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2940 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2941
Kojto 107:4f6c30876dfa 2942 /******************* Bit definition for CAN_F11R2 register ******************/
Kojto 107:4f6c30876dfa 2943 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2944 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2945 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2946 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2947 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2948 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2949 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2950 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2951 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2952 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2953 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2954 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2955 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2956 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2957 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2958 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2959 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2960 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2961 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2962 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2963 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2964 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2965 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 2966 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 2967 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 2968 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 2969 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 2970 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 2971 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 2972 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 2973 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 2974 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 2975
Kojto 107:4f6c30876dfa 2976 /******************* Bit definition for CAN_F12R2 register ******************/
Kojto 107:4f6c30876dfa 2977 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 2978 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 2979 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 2980 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 2981 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 2982 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 2983 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 2984 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 2985 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 2986 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 2987 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 2988 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 2989 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 2990 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 2991 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 2992 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 2993 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 2994 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 2995 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 2996 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 2997 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 2998 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 2999 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 3000 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 3001 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 3002 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 3003 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 3004 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 3005 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 3006 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 3007 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 3008 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 3009
Kojto 107:4f6c30876dfa 3010 /******************* Bit definition for CAN_F13R2 register ******************/
Kojto 107:4f6c30876dfa 3011 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
Kojto 107:4f6c30876dfa 3012 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
Kojto 107:4f6c30876dfa 3013 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
Kojto 107:4f6c30876dfa 3014 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
Kojto 107:4f6c30876dfa 3015 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
Kojto 107:4f6c30876dfa 3016 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
Kojto 107:4f6c30876dfa 3017 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
Kojto 107:4f6c30876dfa 3018 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
Kojto 107:4f6c30876dfa 3019 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
Kojto 107:4f6c30876dfa 3020 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
Kojto 107:4f6c30876dfa 3021 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
Kojto 107:4f6c30876dfa 3022 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
Kojto 107:4f6c30876dfa 3023 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
Kojto 107:4f6c30876dfa 3024 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
Kojto 107:4f6c30876dfa 3025 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
Kojto 107:4f6c30876dfa 3026 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
Kojto 107:4f6c30876dfa 3027 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
Kojto 107:4f6c30876dfa 3028 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
Kojto 107:4f6c30876dfa 3029 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
Kojto 107:4f6c30876dfa 3030 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
Kojto 107:4f6c30876dfa 3031 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
Kojto 107:4f6c30876dfa 3032 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
Kojto 107:4f6c30876dfa 3033 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
Kojto 107:4f6c30876dfa 3034 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
Kojto 107:4f6c30876dfa 3035 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
Kojto 107:4f6c30876dfa 3036 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
Kojto 107:4f6c30876dfa 3037 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
Kojto 107:4f6c30876dfa 3038 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
Kojto 107:4f6c30876dfa 3039 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
Kojto 107:4f6c30876dfa 3040 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
Kojto 107:4f6c30876dfa 3041 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
Kojto 107:4f6c30876dfa 3042 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
Kojto 107:4f6c30876dfa 3043
Kojto 107:4f6c30876dfa 3044 /******************************************************************************/
Kojto 107:4f6c30876dfa 3045 /* */
Kojto 107:4f6c30876dfa 3046 /* HDMI-CEC (CEC) */
Kojto 107:4f6c30876dfa 3047 /* */
Kojto 107:4f6c30876dfa 3048 /******************************************************************************/
Kojto 107:4f6c30876dfa 3049
Kojto 107:4f6c30876dfa 3050 /******************* Bit definition for CEC_CR register *********************/
Kojto 107:4f6c30876dfa 3051 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
Kojto 107:4f6c30876dfa 3052 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
Kojto 107:4f6c30876dfa 3053 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
Kojto 107:4f6c30876dfa 3054
Kojto 107:4f6c30876dfa 3055 /******************* Bit definition for CEC_CFGR register *******************/
Kojto 107:4f6c30876dfa 3056 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
Kojto 107:4f6c30876dfa 3057 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
Kojto 107:4f6c30876dfa 3058 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
Kojto 107:4f6c30876dfa 3059 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
Kojto 107:4f6c30876dfa 3060 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
Kojto 107:4f6c30876dfa 3061 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
Kojto 107:4f6c30876dfa 3062 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
Kojto 107:4f6c30876dfa 3063 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
Kojto 107:4f6c30876dfa 3064 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
Kojto 107:4f6c30876dfa 3065
Kojto 107:4f6c30876dfa 3066 /******************* Bit definition for CEC_TXDR register *******************/
Kojto 107:4f6c30876dfa 3067 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
Kojto 107:4f6c30876dfa 3068
Kojto 107:4f6c30876dfa 3069 /******************* Bit definition for CEC_RXDR register *******************/
Kojto 107:4f6c30876dfa 3070 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
Kojto 107:4f6c30876dfa 3071
Kojto 107:4f6c30876dfa 3072 /******************* Bit definition for CEC_ISR register ********************/
Kojto 107:4f6c30876dfa 3073 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
Kojto 107:4f6c30876dfa 3074 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
Kojto 107:4f6c30876dfa 3075 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
Kojto 107:4f6c30876dfa 3076 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
Kojto 107:4f6c30876dfa 3077 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
Kojto 107:4f6c30876dfa 3078 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
Kojto 107:4f6c30876dfa 3079 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
Kojto 107:4f6c30876dfa 3080 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
Kojto 107:4f6c30876dfa 3081 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
Kojto 107:4f6c30876dfa 3082 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
Kojto 107:4f6c30876dfa 3083 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
Kojto 107:4f6c30876dfa 3084 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
Kojto 107:4f6c30876dfa 3085 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
Kojto 107:4f6c30876dfa 3086
Kojto 107:4f6c30876dfa 3087 /******************* Bit definition for CEC_IER register ********************/
Kojto 107:4f6c30876dfa 3088 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
Kojto 107:4f6c30876dfa 3089 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
Kojto 107:4f6c30876dfa 3090 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
Kojto 107:4f6c30876dfa 3091 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
Kojto 107:4f6c30876dfa 3092 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
Kojto 107:4f6c30876dfa 3093 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
Kojto 107:4f6c30876dfa 3094 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
Kojto 107:4f6c30876dfa 3095 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
Kojto 107:4f6c30876dfa 3096 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
Kojto 107:4f6c30876dfa 3097 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
Kojto 107:4f6c30876dfa 3098 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
Kojto 107:4f6c30876dfa 3099 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
Kojto 107:4f6c30876dfa 3100 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
Kojto 107:4f6c30876dfa 3101
Kojto 107:4f6c30876dfa 3102 /******************************************************************************/
Kojto 107:4f6c30876dfa 3103 /* */
Kojto 107:4f6c30876dfa 3104 /* CRC calculation unit */
Kojto 107:4f6c30876dfa 3105 /* */
Kojto 107:4f6c30876dfa 3106 /******************************************************************************/
Kojto 107:4f6c30876dfa 3107 /******************* Bit definition for CRC_DR register *********************/
Kojto 107:4f6c30876dfa 3108 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 107:4f6c30876dfa 3109
Kojto 107:4f6c30876dfa 3110 /******************* Bit definition for CRC_IDR register ********************/
Kojto 107:4f6c30876dfa 3111 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
Kojto 107:4f6c30876dfa 3112
Kojto 107:4f6c30876dfa 3113 /******************** Bit definition for CRC_CR register ********************/
Kojto 107:4f6c30876dfa 3114 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Kojto 107:4f6c30876dfa 3115 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
Kojto 107:4f6c30876dfa 3116 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
Kojto 107:4f6c30876dfa 3117 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
Kojto 107:4f6c30876dfa 3118 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Kojto 107:4f6c30876dfa 3119 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 3120 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 3121 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Kojto 107:4f6c30876dfa 3122
Kojto 107:4f6c30876dfa 3123 /******************* Bit definition for CRC_INIT register *******************/
Kojto 107:4f6c30876dfa 3124 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Kojto 107:4f6c30876dfa 3125
Kojto 107:4f6c30876dfa 3126 /******************* Bit definition for CRC_POL register ********************/
Kojto 107:4f6c30876dfa 3127 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
Kojto 107:4f6c30876dfa 3128
Kojto 116:c0f6e94411f5 3129
Kojto 107:4f6c30876dfa 3130 /******************************************************************************/
Kojto 107:4f6c30876dfa 3131 /* */
Kojto 107:4f6c30876dfa 3132 /* Digital to Analog Converter */
Kojto 107:4f6c30876dfa 3133 /* */
Kojto 107:4f6c30876dfa 3134 /******************************************************************************/
Kojto 107:4f6c30876dfa 3135 /******************** Bit definition for DAC_CR register ********************/
Kojto 107:4f6c30876dfa 3136 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
Kojto 107:4f6c30876dfa 3137 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
Kojto 107:4f6c30876dfa 3138 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
Kojto 107:4f6c30876dfa 3139
Kojto 107:4f6c30876dfa 3140 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 107:4f6c30876dfa 3141 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3142 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3143 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3144
Kojto 107:4f6c30876dfa 3145 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 107:4f6c30876dfa 3146 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3147 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3148
Kojto 107:4f6c30876dfa 3149 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 107:4f6c30876dfa 3150 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3151 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3152 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3153 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3154
Kojto 107:4f6c30876dfa 3155 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
Kojto 107:4f6c30876dfa 3156 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
Kojto 107:4f6c30876dfa 3157 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
Kojto 107:4f6c30876dfa 3158 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
Kojto 107:4f6c30876dfa 3159
Kojto 107:4f6c30876dfa 3160 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
Kojto 107:4f6c30876dfa 3161 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3162 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3163 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3164
Kojto 107:4f6c30876dfa 3165 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
Kojto 107:4f6c30876dfa 3166 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3167 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3168
Kojto 107:4f6c30876dfa 3169 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
Kojto 107:4f6c30876dfa 3170 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3171 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3172 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3173 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3174
Kojto 107:4f6c30876dfa 3175 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
Kojto 107:4f6c30876dfa 3176
Kojto 107:4f6c30876dfa 3177 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 107:4f6c30876dfa 3178 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x01) /*!<DAC channel1 software trigger */
Kojto 107:4f6c30876dfa 3179 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x02) /*!<DAC channel2 software trigger */
Kojto 107:4f6c30876dfa 3180
Kojto 107:4f6c30876dfa 3181 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 107:4f6c30876dfa 3182 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
Kojto 107:4f6c30876dfa 3183
Kojto 107:4f6c30876dfa 3184 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 107:4f6c30876dfa 3185 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
Kojto 107:4f6c30876dfa 3186
Kojto 107:4f6c30876dfa 3187 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 107:4f6c30876dfa 3188 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
Kojto 107:4f6c30876dfa 3189
Kojto 107:4f6c30876dfa 3190 /***************** Bit definition for DAC_DHR12R2 register ******************/
Kojto 107:4f6c30876dfa 3191 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
Kojto 107:4f6c30876dfa 3192
Kojto 107:4f6c30876dfa 3193 /***************** Bit definition for DAC_DHR12L2 register ******************/
Kojto 107:4f6c30876dfa 3194 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
Kojto 107:4f6c30876dfa 3195
Kojto 107:4f6c30876dfa 3196 /****************** Bit definition for DAC_DHR8R2 register ******************/
Kojto 107:4f6c30876dfa 3197 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
Kojto 107:4f6c30876dfa 3198
Kojto 107:4f6c30876dfa 3199 /***************** Bit definition for DAC_DHR12RD register ******************/
Kojto 107:4f6c30876dfa 3200 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
Kojto 107:4f6c30876dfa 3201 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
Kojto 107:4f6c30876dfa 3202
Kojto 107:4f6c30876dfa 3203 /***************** Bit definition for DAC_DHR12LD register ******************/
Kojto 107:4f6c30876dfa 3204 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
Kojto 107:4f6c30876dfa 3205 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
Kojto 107:4f6c30876dfa 3206
Kojto 107:4f6c30876dfa 3207 /****************** Bit definition for DAC_DHR8RD register ******************/
Kojto 107:4f6c30876dfa 3208 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
Kojto 107:4f6c30876dfa 3209 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
Kojto 107:4f6c30876dfa 3210
Kojto 107:4f6c30876dfa 3211 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 107:4f6c30876dfa 3212 #define DAC_DOR1_DACC1DOR ((uint32_t)0x0FFF) /*!<DAC channel1 data output */
Kojto 107:4f6c30876dfa 3213
Kojto 107:4f6c30876dfa 3214 /******************* Bit definition for DAC_DOR2 register *******************/
Kojto 107:4f6c30876dfa 3215 #define DAC_DOR2_DACC2DOR ((uint32_t)0x0FFF) /*!<DAC channel2 data output */
Kojto 107:4f6c30876dfa 3216
Kojto 107:4f6c30876dfa 3217 /******************** Bit definition for DAC_SR register ********************/
Kojto 107:4f6c30876dfa 3218 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
Kojto 107:4f6c30876dfa 3219 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
Kojto 107:4f6c30876dfa 3220
Kojto 116:c0f6e94411f5 3221
Kojto 107:4f6c30876dfa 3222 /******************************************************************************/
Kojto 107:4f6c30876dfa 3223 /* */
Kojto 107:4f6c30876dfa 3224 /* Debug MCU */
Kojto 107:4f6c30876dfa 3225 /* */
Kojto 107:4f6c30876dfa 3226 /******************************************************************************/
Kojto 107:4f6c30876dfa 3227
Kojto 107:4f6c30876dfa 3228 /******************************************************************************/
Kojto 107:4f6c30876dfa 3229 /* */
Kojto 107:4f6c30876dfa 3230 /* DCMI */
Kojto 107:4f6c30876dfa 3231 /* */
Kojto 107:4f6c30876dfa 3232 /******************************************************************************/
Kojto 107:4f6c30876dfa 3233 /******************** Bits definition for DCMI_CR register ******************/
Kojto 107:4f6c30876dfa 3234 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3235 #define DCMI_CR_CM ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3236 #define DCMI_CR_CROP ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3237 #define DCMI_CR_JPEG ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3238 #define DCMI_CR_ESS ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3239 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3240 #define DCMI_CR_HSPOL ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3241 #define DCMI_CR_VSPOL ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 3242 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3243 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3244 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3245 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3246 #define DCMI_CR_CRE ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 3247 #define DCMI_CR_ENABLE ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 3248 #define DCMI_CR_BSM ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 3249 #define DCMI_CR_BSM_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3250 #define DCMI_CR_BSM_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 3251 #define DCMI_CR_OEBS ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3252 #define DCMI_CR_LSM ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3253 #define DCMI_CR_OELS ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3254
Kojto 107:4f6c30876dfa 3255 /******************** Bits definition for DCMI_SR register ******************/
Kojto 107:4f6c30876dfa 3256 #define DCMI_SR_HSYNC ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3257 #define DCMI_SR_VSYNC ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3258 #define DCMI_SR_FNE ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3259
Kojto 107:4f6c30876dfa 3260 /******************** Bits definition for DCMI_RISR register ****************/
Kojto 107:4f6c30876dfa 3261 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3262 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3263 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3264 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3265 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3266
Kojto 107:4f6c30876dfa 3267 /******************** Bits definition for DCMI_IER register *****************/
Kojto 107:4f6c30876dfa 3268 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3269 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3270 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3271 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3272 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3273
Kojto 107:4f6c30876dfa 3274 /******************** Bits definition for DCMI_MISR register ****************/
Kojto 107:4f6c30876dfa 3275 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3276 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3277 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3278 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3279 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3280
Kojto 107:4f6c30876dfa 3281 /******************** Bits definition for DCMI_ICR register *****************/
Kojto 107:4f6c30876dfa 3282 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3283 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3284 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3285 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3286 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3287
Kojto 107:4f6c30876dfa 3288 /******************************************************************************/
Kojto 107:4f6c30876dfa 3289 /* */
Kojto 107:4f6c30876dfa 3290 /* DMA Controller */
Kojto 107:4f6c30876dfa 3291 /* */
Kojto 107:4f6c30876dfa 3292 /******************************************************************************/
Kojto 107:4f6c30876dfa 3293 /******************** Bits definition for DMA_SxCR register *****************/
Kojto 107:4f6c30876dfa 3294 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)
Kojto 107:4f6c30876dfa 3295 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 3296 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)
Kojto 116:c0f6e94411f5 3297 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 3298 #define DMA_SxCR_MBURST ((uint32_t)0x01800000)
Kojto 107:4f6c30876dfa 3299 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 3300 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 3301 #define DMA_SxCR_PBURST ((uint32_t)0x00600000)
Kojto 107:4f6c30876dfa 3302 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 3303 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 3304 #define DMA_SxCR_ACK ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3305 #define DMA_SxCR_CT ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3306 #define DMA_SxCR_DBM ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3307 #define DMA_SxCR_PL ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 3308 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3309 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 3310 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 3311 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000)
Kojto 107:4f6c30876dfa 3312 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 3313 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 3314 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800)
Kojto 107:4f6c30876dfa 3315 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3316 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 3317 #define DMA_SxCR_MINC ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3318 #define DMA_SxCR_PINC ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3319 #define DMA_SxCR_CIRC ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3320 #define DMA_SxCR_DIR ((uint32_t)0x000000C0)
Kojto 107:4f6c30876dfa 3321 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3322 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 3323 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3324 #define DMA_SxCR_TCIE ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3325 #define DMA_SxCR_HTIE ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3326 #define DMA_SxCR_TEIE ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3327 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3328 #define DMA_SxCR_EN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3329
Kojto 107:4f6c30876dfa 3330 /******************** Bits definition for DMA_SxCNDTR register **************/
Kojto 107:4f6c30876dfa 3331 #define DMA_SxNDT ((uint32_t)0x0000FFFF)
Kojto 107:4f6c30876dfa 3332 #define DMA_SxNDT_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3333 #define DMA_SxNDT_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3334 #define DMA_SxNDT_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3335 #define DMA_SxNDT_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3336 #define DMA_SxNDT_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3337 #define DMA_SxNDT_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3338 #define DMA_SxNDT_6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3339 #define DMA_SxNDT_7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 3340 #define DMA_SxNDT_8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3341 #define DMA_SxNDT_9 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3342 #define DMA_SxNDT_10 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3343 #define DMA_SxNDT_11 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3344 #define DMA_SxNDT_12 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 3345 #define DMA_SxNDT_13 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 3346 #define DMA_SxNDT_14 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 3347 #define DMA_SxNDT_15 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 3348
Kojto 107:4f6c30876dfa 3349 /******************** Bits definition for DMA_SxFCR register ****************/
Kojto 107:4f6c30876dfa 3350 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 3351 #define DMA_SxFCR_FS ((uint32_t)0x00000038)
Kojto 107:4f6c30876dfa 3352 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3353 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3354 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3355 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3356 #define DMA_SxFCR_FTH ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 3357 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3358 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3359
Kojto 107:4f6c30876dfa 3360 /******************** Bits definition for DMA_LISR register *****************/
Kojto 107:4f6c30876dfa 3361 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 3362 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 3363 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 3364 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 3365 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 3366 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 3367 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3368 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3369 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3370 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3371 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3372 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3373 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3374 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3375 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3376 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3377 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3378 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3379 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3380 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3381
Kojto 107:4f6c30876dfa 3382 /******************** Bits definition for DMA_HISR register *****************/
Kojto 107:4f6c30876dfa 3383 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 3384 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 3385 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 3386 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 3387 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 3388 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 3389 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3390 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3391 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3392 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3393 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3394 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3395 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3396 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3397 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3398 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3399 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3400 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3401 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3402 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3403
Kojto 107:4f6c30876dfa 3404 /******************** Bits definition for DMA_LIFCR register ****************/
Kojto 107:4f6c30876dfa 3405 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 3406 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 3407 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 3408 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 3409 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 3410 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 3411 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3412 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3413 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3414 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3415 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3416 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3417 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3418 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3419 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3420 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3421 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3422 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3423 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3424 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3425
Kojto 107:4f6c30876dfa 3426 /******************** Bits definition for DMA_HIFCR register ****************/
Kojto 107:4f6c30876dfa 3427 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 3428 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 3429 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 3430 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 3431 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 3432 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 3433 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3434 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3435 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3436 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3437 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3438 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3439 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3440 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3441 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3442 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3443 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3444 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3445 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3446 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3447
Kojto 107:4f6c30876dfa 3448 /******************************************************************************/
Kojto 107:4f6c30876dfa 3449 /* */
Kojto 107:4f6c30876dfa 3450 /* AHB Master DMA2D Controller (DMA2D) */
Kojto 107:4f6c30876dfa 3451 /* */
Kojto 107:4f6c30876dfa 3452 /******************************************************************************/
Kojto 107:4f6c30876dfa 3453
Kojto 107:4f6c30876dfa 3454 /******************** Bit definition for DMA2D_CR register ******************/
Kojto 107:4f6c30876dfa 3455
Kojto 107:4f6c30876dfa 3456 #define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */
Kojto 107:4f6c30876dfa 3457 #define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */
Kojto 107:4f6c30876dfa 3458 #define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */
Kojto 107:4f6c30876dfa 3459 #define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */
Kojto 107:4f6c30876dfa 3460 #define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */
Kojto 107:4f6c30876dfa 3461 #define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */
Kojto 107:4f6c30876dfa 3462 #define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */
Kojto 107:4f6c30876dfa 3463 #define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */
Kojto 107:4f6c30876dfa 3464 #define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */
Kojto 107:4f6c30876dfa 3465 #define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */
Kojto 107:4f6c30876dfa 3466
Kojto 107:4f6c30876dfa 3467 /******************** Bit definition for DMA2D_ISR register *****************/
Kojto 107:4f6c30876dfa 3468
Kojto 107:4f6c30876dfa 3469 #define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */
Kojto 107:4f6c30876dfa 3470 #define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */
Kojto 107:4f6c30876dfa 3471 #define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */
Kojto 107:4f6c30876dfa 3472 #define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */
Kojto 107:4f6c30876dfa 3473 #define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */
Kojto 107:4f6c30876dfa 3474 #define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */
Kojto 107:4f6c30876dfa 3475
Kojto 107:4f6c30876dfa 3476 /******************** Bit definition for DMA2D_IFSR register ****************/
Kojto 107:4f6c30876dfa 3477
Kojto 107:4f6c30876dfa 3478 #define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */
Kojto 107:4f6c30876dfa 3479 #define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */
Kojto 107:4f6c30876dfa 3480 #define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */
Kojto 107:4f6c30876dfa 3481 #define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */
Kojto 107:4f6c30876dfa 3482 #define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */
Kojto 107:4f6c30876dfa 3483 #define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */
Kojto 107:4f6c30876dfa 3484
Kojto 107:4f6c30876dfa 3485 /******************** Bit definition for DMA2D_FGMAR register ***************/
Kojto 107:4f6c30876dfa 3486
Kojto 107:4f6c30876dfa 3487 #define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 107:4f6c30876dfa 3488
Kojto 107:4f6c30876dfa 3489 /******************** Bit definition for DMA2D_FGOR register ****************/
Kojto 107:4f6c30876dfa 3490
Kojto 107:4f6c30876dfa 3491 #define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
Kojto 107:4f6c30876dfa 3492
Kojto 107:4f6c30876dfa 3493 /******************** Bit definition for DMA2D_BGMAR register ***************/
Kojto 107:4f6c30876dfa 3494
Kojto 107:4f6c30876dfa 3495 #define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 107:4f6c30876dfa 3496
Kojto 107:4f6c30876dfa 3497 /******************** Bit definition for DMA2D_BGOR register ****************/
Kojto 107:4f6c30876dfa 3498
Kojto 107:4f6c30876dfa 3499 #define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
Kojto 107:4f6c30876dfa 3500
Kojto 107:4f6c30876dfa 3501 /******************** Bit definition for DMA2D_FGPFCCR register *************/
Kojto 107:4f6c30876dfa 3502
Kojto 107:4f6c30876dfa 3503 #define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
Kojto 107:4f6c30876dfa 3504 #define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
Kojto 107:4f6c30876dfa 3505 #define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
Kojto 107:4f6c30876dfa 3506 #define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
Kojto 107:4f6c30876dfa 3507 #define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */
Kojto 107:4f6c30876dfa 3508 #define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
Kojto 107:4f6c30876dfa 3509
Kojto 107:4f6c30876dfa 3510 /******************** Bit definition for DMA2D_FGCOLR register **************/
Kojto 107:4f6c30876dfa 3511
Kojto 107:4f6c30876dfa 3512 #define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
Kojto 107:4f6c30876dfa 3513 #define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
Kojto 107:4f6c30876dfa 3514 #define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
Kojto 107:4f6c30876dfa 3515
Kojto 107:4f6c30876dfa 3516 /******************** Bit definition for DMA2D_BGPFCCR register *************/
Kojto 107:4f6c30876dfa 3517
Kojto 107:4f6c30876dfa 3518 #define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */
Kojto 107:4f6c30876dfa 3519 #define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */
Kojto 107:4f6c30876dfa 3520 #define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */
Kojto 107:4f6c30876dfa 3521 #define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */
Kojto 107:4f6c30876dfa 3522 #define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */
Kojto 107:4f6c30876dfa 3523 #define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */
Kojto 107:4f6c30876dfa 3524
Kojto 107:4f6c30876dfa 3525 /******************** Bit definition for DMA2D_BGCOLR register **************/
Kojto 107:4f6c30876dfa 3526
Kojto 107:4f6c30876dfa 3527 #define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */
Kojto 107:4f6c30876dfa 3528 #define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */
Kojto 107:4f6c30876dfa 3529 #define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */
Kojto 107:4f6c30876dfa 3530
Kojto 107:4f6c30876dfa 3531 /******************** Bit definition for DMA2D_FGCMAR register **************/
Kojto 107:4f6c30876dfa 3532
Kojto 107:4f6c30876dfa 3533 #define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 107:4f6c30876dfa 3534
Kojto 107:4f6c30876dfa 3535 /******************** Bit definition for DMA2D_BGCMAR register **************/
Kojto 107:4f6c30876dfa 3536
Kojto 107:4f6c30876dfa 3537 #define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 107:4f6c30876dfa 3538
Kojto 107:4f6c30876dfa 3539 /******************** Bit definition for DMA2D_OPFCCR register **************/
Kojto 107:4f6c30876dfa 3540
Kojto 107:4f6c30876dfa 3541 #define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */
Kojto 107:4f6c30876dfa 3542
Kojto 107:4f6c30876dfa 3543 /******************** Bit definition for DMA2D_OCOLR register ***************/
Kojto 107:4f6c30876dfa 3544
Kojto 107:4f6c30876dfa 3545 /*!<Mode_ARGB8888/RGB888 */
Kojto 107:4f6c30876dfa 3546
Kojto 107:4f6c30876dfa 3547 #define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */
Kojto 107:4f6c30876dfa 3548 #define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */
Kojto 107:4f6c30876dfa 3549 #define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */
Kojto 107:4f6c30876dfa 3550 #define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */
Kojto 107:4f6c30876dfa 3551
Kojto 107:4f6c30876dfa 3552 /*!<Mode_RGB565 */
Kojto 107:4f6c30876dfa 3553 #define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */
Kojto 107:4f6c30876dfa 3554 #define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */
Kojto 107:4f6c30876dfa 3555 #define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */
Kojto 107:4f6c30876dfa 3556
Kojto 107:4f6c30876dfa 3557 /*!<Mode_ARGB1555 */
Kojto 107:4f6c30876dfa 3558 #define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */
Kojto 107:4f6c30876dfa 3559 #define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */
Kojto 107:4f6c30876dfa 3560 #define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */
Kojto 107:4f6c30876dfa 3561 #define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */
Kojto 107:4f6c30876dfa 3562
Kojto 107:4f6c30876dfa 3563 /*!<Mode_ARGB4444 */
Kojto 107:4f6c30876dfa 3564 #define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */
Kojto 107:4f6c30876dfa 3565 #define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */
Kojto 107:4f6c30876dfa 3566 #define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */
Kojto 107:4f6c30876dfa 3567 #define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */
Kojto 107:4f6c30876dfa 3568
Kojto 107:4f6c30876dfa 3569 /******************** Bit definition for DMA2D_OMAR register ****************/
Kojto 107:4f6c30876dfa 3570
Kojto 107:4f6c30876dfa 3571 #define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 107:4f6c30876dfa 3572
Kojto 107:4f6c30876dfa 3573 /******************** Bit definition for DMA2D_OOR register *****************/
Kojto 107:4f6c30876dfa 3574
Kojto 107:4f6c30876dfa 3575 #define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */
Kojto 107:4f6c30876dfa 3576
Kojto 107:4f6c30876dfa 3577 /******************** Bit definition for DMA2D_NLR register *****************/
Kojto 107:4f6c30876dfa 3578
Kojto 107:4f6c30876dfa 3579 #define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */
Kojto 107:4f6c30876dfa 3580 #define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */
Kojto 107:4f6c30876dfa 3581
Kojto 107:4f6c30876dfa 3582 /******************** Bit definition for DMA2D_LWR register *****************/
Kojto 107:4f6c30876dfa 3583
Kojto 107:4f6c30876dfa 3584 #define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */
Kojto 107:4f6c30876dfa 3585
Kojto 107:4f6c30876dfa 3586 /******************** Bit definition for DMA2D_AMTCR register ***************/
Kojto 107:4f6c30876dfa 3587
Kojto 107:4f6c30876dfa 3588 #define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */
Kojto 107:4f6c30876dfa 3589 #define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */
Kojto 107:4f6c30876dfa 3590
Kojto 107:4f6c30876dfa 3591
Kojto 107:4f6c30876dfa 3592
Kojto 107:4f6c30876dfa 3593 /******************** Bit definition for DMA2D_FGCLUT register **************/
Kojto 107:4f6c30876dfa 3594
Kojto 107:4f6c30876dfa 3595 /******************** Bit definition for DMA2D_BGCLUT register **************/
Kojto 107:4f6c30876dfa 3596
Kojto 107:4f6c30876dfa 3597
Kojto 107:4f6c30876dfa 3598 /******************************************************************************/
Kojto 107:4f6c30876dfa 3599 /* */
Kojto 107:4f6c30876dfa 3600 /* External Interrupt/Event Controller */
Kojto 107:4f6c30876dfa 3601 /* */
Kojto 107:4f6c30876dfa 3602 /******************************************************************************/
Kojto 107:4f6c30876dfa 3603 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 107:4f6c30876dfa 3604 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 107:4f6c30876dfa 3605 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 107:4f6c30876dfa 3606 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 107:4f6c30876dfa 3607 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 107:4f6c30876dfa 3608 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 107:4f6c30876dfa 3609 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 107:4f6c30876dfa 3610 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 107:4f6c30876dfa 3611 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 107:4f6c30876dfa 3612 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 107:4f6c30876dfa 3613 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 107:4f6c30876dfa 3614 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 107:4f6c30876dfa 3615 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 107:4f6c30876dfa 3616 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 107:4f6c30876dfa 3617 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 107:4f6c30876dfa 3618 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 107:4f6c30876dfa 3619 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 107:4f6c30876dfa 3620 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 107:4f6c30876dfa 3621 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 107:4f6c30876dfa 3622 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
Kojto 107:4f6c30876dfa 3623 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 107:4f6c30876dfa 3624 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
Kojto 107:4f6c30876dfa 3625 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 107:4f6c30876dfa 3626 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 107:4f6c30876dfa 3627 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Kojto 107:4f6c30876dfa 3628
Kojto 107:4f6c30876dfa 3629 /******************* Bit definition for EXTI_EMR register *******************/
Kojto 107:4f6c30876dfa 3630 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 107:4f6c30876dfa 3631 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 107:4f6c30876dfa 3632 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 107:4f6c30876dfa 3633 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 107:4f6c30876dfa 3634 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 107:4f6c30876dfa 3635 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 107:4f6c30876dfa 3636 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 107:4f6c30876dfa 3637 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 107:4f6c30876dfa 3638 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 107:4f6c30876dfa 3639 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 107:4f6c30876dfa 3640 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 107:4f6c30876dfa 3641 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 107:4f6c30876dfa 3642 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 107:4f6c30876dfa 3643 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 107:4f6c30876dfa 3644 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 107:4f6c30876dfa 3645 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 107:4f6c30876dfa 3646 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 107:4f6c30876dfa 3647 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 107:4f6c30876dfa 3648 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
Kojto 107:4f6c30876dfa 3649 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 107:4f6c30876dfa 3650 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
Kojto 107:4f6c30876dfa 3651 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 107:4f6c30876dfa 3652 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 107:4f6c30876dfa 3653 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Kojto 107:4f6c30876dfa 3654
Kojto 107:4f6c30876dfa 3655 /****************** Bit definition for EXTI_RTSR register *******************/
Kojto 107:4f6c30876dfa 3656 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 107:4f6c30876dfa 3657 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 107:4f6c30876dfa 3658 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 107:4f6c30876dfa 3659 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 107:4f6c30876dfa 3660 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 107:4f6c30876dfa 3661 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 107:4f6c30876dfa 3662 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 107:4f6c30876dfa 3663 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 107:4f6c30876dfa 3664 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 107:4f6c30876dfa 3665 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 107:4f6c30876dfa 3666 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 107:4f6c30876dfa 3667 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 107:4f6c30876dfa 3668 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 107:4f6c30876dfa 3669 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 107:4f6c30876dfa 3670 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 107:4f6c30876dfa 3671 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 107:4f6c30876dfa 3672 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 107:4f6c30876dfa 3673 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 107:4f6c30876dfa 3674 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
Kojto 107:4f6c30876dfa 3675 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 107:4f6c30876dfa 3676 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
Kojto 107:4f6c30876dfa 3677 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
Kojto 107:4f6c30876dfa 3678 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
Kojto 107:4f6c30876dfa 3679 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
Kojto 107:4f6c30876dfa 3680
Kojto 107:4f6c30876dfa 3681 /****************** Bit definition for EXTI_FTSR register *******************/
Kojto 107:4f6c30876dfa 3682 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 107:4f6c30876dfa 3683 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 107:4f6c30876dfa 3684 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 107:4f6c30876dfa 3685 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 107:4f6c30876dfa 3686 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 107:4f6c30876dfa 3687 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 107:4f6c30876dfa 3688 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 107:4f6c30876dfa 3689 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 107:4f6c30876dfa 3690 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 107:4f6c30876dfa 3691 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 107:4f6c30876dfa 3692 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 107:4f6c30876dfa 3693 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 107:4f6c30876dfa 3694 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 107:4f6c30876dfa 3695 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 107:4f6c30876dfa 3696 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 107:4f6c30876dfa 3697 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 107:4f6c30876dfa 3698 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 107:4f6c30876dfa 3699 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 107:4f6c30876dfa 3700 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
Kojto 107:4f6c30876dfa 3701 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 107:4f6c30876dfa 3702 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
Kojto 107:4f6c30876dfa 3703 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
Kojto 107:4f6c30876dfa 3704 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
Kojto 107:4f6c30876dfa 3705 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
Kojto 107:4f6c30876dfa 3706
Kojto 107:4f6c30876dfa 3707 /****************** Bit definition for EXTI_SWIER register ******************/
Kojto 107:4f6c30876dfa 3708 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 107:4f6c30876dfa 3709 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 107:4f6c30876dfa 3710 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 107:4f6c30876dfa 3711 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 107:4f6c30876dfa 3712 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 107:4f6c30876dfa 3713 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 107:4f6c30876dfa 3714 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 107:4f6c30876dfa 3715 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 107:4f6c30876dfa 3716 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 107:4f6c30876dfa 3717 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 107:4f6c30876dfa 3718 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 107:4f6c30876dfa 3719 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 107:4f6c30876dfa 3720 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 107:4f6c30876dfa 3721 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 107:4f6c30876dfa 3722 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 107:4f6c30876dfa 3723 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 107:4f6c30876dfa 3724 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 107:4f6c30876dfa 3725 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 107:4f6c30876dfa 3726 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
Kojto 107:4f6c30876dfa 3727 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 107:4f6c30876dfa 3728 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
Kojto 107:4f6c30876dfa 3729 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
Kojto 107:4f6c30876dfa 3730 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
Kojto 107:4f6c30876dfa 3731 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
Kojto 107:4f6c30876dfa 3732
Kojto 107:4f6c30876dfa 3733 /******************* Bit definition for EXTI_PR register ********************/
Kojto 107:4f6c30876dfa 3734 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
Kojto 107:4f6c30876dfa 3735 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
Kojto 107:4f6c30876dfa 3736 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
Kojto 107:4f6c30876dfa 3737 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
Kojto 107:4f6c30876dfa 3738 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
Kojto 107:4f6c30876dfa 3739 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
Kojto 107:4f6c30876dfa 3740 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
Kojto 107:4f6c30876dfa 3741 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
Kojto 107:4f6c30876dfa 3742 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
Kojto 107:4f6c30876dfa 3743 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
Kojto 107:4f6c30876dfa 3744 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
Kojto 107:4f6c30876dfa 3745 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
Kojto 107:4f6c30876dfa 3746 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
Kojto 107:4f6c30876dfa 3747 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
Kojto 107:4f6c30876dfa 3748 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
Kojto 107:4f6c30876dfa 3749 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
Kojto 107:4f6c30876dfa 3750 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
Kojto 107:4f6c30876dfa 3751 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
Kojto 107:4f6c30876dfa 3752 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
Kojto 107:4f6c30876dfa 3753 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
Kojto 107:4f6c30876dfa 3754 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
Kojto 107:4f6c30876dfa 3755 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
Kojto 107:4f6c30876dfa 3756 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
Kojto 107:4f6c30876dfa 3757 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
Kojto 107:4f6c30876dfa 3758
Kojto 107:4f6c30876dfa 3759 /******************************************************************************/
Kojto 107:4f6c30876dfa 3760 /* */
Kojto 107:4f6c30876dfa 3761 /* FLASH */
Kojto 107:4f6c30876dfa 3762 /* */
Kojto 107:4f6c30876dfa 3763 /******************************************************************************/
Kojto 107:4f6c30876dfa 3764 /******************* Bits definition for FLASH_ACR register *****************/
Kojto 107:4f6c30876dfa 3765 #define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 3766 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 3767 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3768 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3769 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 3770 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3771 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)
Kojto 107:4f6c30876dfa 3772 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)
Kojto 107:4f6c30876dfa 3773 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)
Kojto 107:4f6c30876dfa 3774 #define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3775 #define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)
Kojto 107:4f6c30876dfa 3776 #define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)
Kojto 107:4f6c30876dfa 3777 #define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)
Kojto 107:4f6c30876dfa 3778 #define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)
Kojto 107:4f6c30876dfa 3779 #define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)
Kojto 107:4f6c30876dfa 3780 #define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)
Kojto 107:4f6c30876dfa 3781 #define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 3782 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3783 #define FLASH_ACR_ARTEN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3784 #define FLASH_ACR_ARTRST ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3785
Kojto 107:4f6c30876dfa 3786 /******************* Bits definition for FLASH_SR register ******************/
Kojto 107:4f6c30876dfa 3787 #define FLASH_SR_EOP ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3788 #define FLASH_SR_OPERR ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3789 #define FLASH_SR_WRPERR ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3790 #define FLASH_SR_PGAERR ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3791 #define FLASH_SR_PGPERR ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3792 #define FLASH_SR_ERSERR ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 3793 #define FLASH_SR_BSY ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3794
Kojto 107:4f6c30876dfa 3795 /******************* Bits definition for FLASH_CR register ******************/
Kojto 107:4f6c30876dfa 3796 #define FLASH_CR_PG ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3797 #define FLASH_CR_SER ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3798 #define FLASH_CR_MER ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3799 #define FLASH_CR_SNB ((uint32_t)0x00000078)
Kojto 107:4f6c30876dfa 3800 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3801 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3802 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3803 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3804 #define FLASH_CR_PSIZE ((uint32_t)0x00000300)
Kojto 107:4f6c30876dfa 3805 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3806 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3807 #define FLASH_CR_STRT ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3808 #define FLASH_CR_EOPIE ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 3809 #define FLASH_CR_ERRIE ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 3810 #define FLASH_CR_LOCK ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 3811
Kojto 107:4f6c30876dfa 3812 /******************* Bits definition for FLASH_OPTCR register ***************/
Kojto 107:4f6c30876dfa 3813 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 3814 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 3815 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)
Kojto 107:4f6c30876dfa 3816 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 3817 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 3818 #define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 3819 #define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 3820 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 3821 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 3822 #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)
Kojto 107:4f6c30876dfa 3823 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 3824 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 3825 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 3826 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 3827 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 3828 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 3829 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 3830 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 3831 #define FLASH_OPTCR_nWRP ((uint32_t)0x00FF0000)
Kojto 107:4f6c30876dfa 3832 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 3833 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 3834 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 3835 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 3836 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 3837 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 3838 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 3839 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 3840 #define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 3841 #define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 3842
Kojto 107:4f6c30876dfa 3843 /******************* Bits definition for FLASH_OPTCR1 register ***************/
Kojto 107:4f6c30876dfa 3844 #define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF)
Kojto 107:4f6c30876dfa 3845 #define FLASH_OPTCR1_BOOT_ADD1 ((uint32_t)0xFFFF0000)
Kojto 107:4f6c30876dfa 3846
Kojto 107:4f6c30876dfa 3847 /******************************************************************************/
Kojto 107:4f6c30876dfa 3848 /* */
Kojto 107:4f6c30876dfa 3849 /* Flexible Memory Controller */
Kojto 107:4f6c30876dfa 3850 /* */
Kojto 107:4f6c30876dfa 3851 /******************************************************************************/
Kojto 107:4f6c30876dfa 3852 /****************** Bit definition for FMC_BCR1 register *******************/
Kojto 107:4f6c30876dfa 3853 #define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 107:4f6c30876dfa 3854 #define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 107:4f6c30876dfa 3855
Kojto 107:4f6c30876dfa 3856 #define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 107:4f6c30876dfa 3857 #define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3858 #define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3859
Kojto 107:4f6c30876dfa 3860 #define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 107:4f6c30876dfa 3861 #define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3862 #define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3863
Kojto 107:4f6c30876dfa 3864 #define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 107:4f6c30876dfa 3865 #define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 107:4f6c30876dfa 3866 #define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 107:4f6c30876dfa 3867 #define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
Kojto 107:4f6c30876dfa 3868 #define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 107:4f6c30876dfa 3869 #define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 107:4f6c30876dfa 3870 #define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 107:4f6c30876dfa 3871 #define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 107:4f6c30876dfa 3872 #define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 107:4f6c30876dfa 3873 #define FMC_BCR1_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
Kojto 107:4f6c30876dfa 3874 #define FMC_BCR1_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3875 #define FMC_BCR1_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3876 #define FMC_BCR1_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3877 #define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 107:4f6c30876dfa 3878 #define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */
Kojto 107:4f6c30876dfa 3879 #define FMC_BCR1_WFDIS ((uint32_t)0x00200000) /*!<Write FIFO Disable */
Kojto 107:4f6c30876dfa 3880
Kojto 107:4f6c30876dfa 3881 /****************** Bit definition for FMC_BCR2 register *******************/
Kojto 107:4f6c30876dfa 3882 #define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 107:4f6c30876dfa 3883 #define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 107:4f6c30876dfa 3884
Kojto 107:4f6c30876dfa 3885 #define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 107:4f6c30876dfa 3886 #define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3887 #define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3888
Kojto 107:4f6c30876dfa 3889 #define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 107:4f6c30876dfa 3890 #define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3891 #define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3892
Kojto 107:4f6c30876dfa 3893 #define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 107:4f6c30876dfa 3894 #define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 107:4f6c30876dfa 3895 #define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 107:4f6c30876dfa 3896 #define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
Kojto 107:4f6c30876dfa 3897 #define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 107:4f6c30876dfa 3898 #define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 107:4f6c30876dfa 3899 #define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 107:4f6c30876dfa 3900 #define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 107:4f6c30876dfa 3901 #define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 107:4f6c30876dfa 3902 #define FMC_BCR2_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
Kojto 107:4f6c30876dfa 3903 #define FMC_BCR2_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3904 #define FMC_BCR2_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3905 #define FMC_BCR2_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3906 #define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 107:4f6c30876dfa 3907
Kojto 107:4f6c30876dfa 3908 /****************** Bit definition for FMC_BCR3 register *******************/
Kojto 107:4f6c30876dfa 3909 #define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 107:4f6c30876dfa 3910 #define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 107:4f6c30876dfa 3911
Kojto 107:4f6c30876dfa 3912 #define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 107:4f6c30876dfa 3913 #define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3914 #define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3915
Kojto 107:4f6c30876dfa 3916 #define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 107:4f6c30876dfa 3917 #define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3918 #define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3919
Kojto 107:4f6c30876dfa 3920 #define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 107:4f6c30876dfa 3921 #define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 107:4f6c30876dfa 3922 #define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 107:4f6c30876dfa 3923 #define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
Kojto 107:4f6c30876dfa 3924 #define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 107:4f6c30876dfa 3925 #define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 107:4f6c30876dfa 3926 #define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 107:4f6c30876dfa 3927 #define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 107:4f6c30876dfa 3928 #define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 107:4f6c30876dfa 3929 #define FMC_BCR3_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
Kojto 107:4f6c30876dfa 3930 #define FMC_BCR3_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3931 #define FMC_BCR3_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3932 #define FMC_BCR3_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3933 #define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 107:4f6c30876dfa 3934
Kojto 107:4f6c30876dfa 3935 /****************** Bit definition for FMC_BCR4 register *******************/
Kojto 107:4f6c30876dfa 3936 #define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */
Kojto 107:4f6c30876dfa 3937 #define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */
Kojto 107:4f6c30876dfa 3938
Kojto 107:4f6c30876dfa 3939 #define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */
Kojto 107:4f6c30876dfa 3940 #define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3941 #define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3942
Kojto 107:4f6c30876dfa 3943 #define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */
Kojto 107:4f6c30876dfa 3944 #define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3945 #define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3946
Kojto 107:4f6c30876dfa 3947 #define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */
Kojto 107:4f6c30876dfa 3948 #define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */
Kojto 107:4f6c30876dfa 3949 #define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */
Kojto 107:4f6c30876dfa 3950 #define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */
Kojto 107:4f6c30876dfa 3951 #define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */
Kojto 107:4f6c30876dfa 3952 #define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */
Kojto 107:4f6c30876dfa 3953 #define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */
Kojto 107:4f6c30876dfa 3954 #define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */
Kojto 107:4f6c30876dfa 3955 #define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */
Kojto 107:4f6c30876dfa 3956 #define FMC_BCR4_CPSIZE ((uint32_t)0x00070000) /*!<CRAM page size */
Kojto 107:4f6c30876dfa 3957 #define FMC_BCR4_CPSIZE_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3958 #define FMC_BCR4_CPSIZE_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3959 #define FMC_BCR4_CPSIZE_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3960 #define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */
Kojto 107:4f6c30876dfa 3961
Kojto 107:4f6c30876dfa 3962 /****************** Bit definition for FMC_BTR1 register ******************/
Kojto 107:4f6c30876dfa 3963 #define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 3964 #define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3965 #define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3966 #define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3967 #define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3968
Kojto 107:4f6c30876dfa 3969 #define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 3970 #define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3971 #define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3972 #define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3973 #define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3974
Kojto 107:4f6c30876dfa 3975 #define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 3976 #define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3977 #define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3978 #define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3979 #define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3980 #define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 3981 #define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 3982 #define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 3983 #define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 3984
Kojto 107:4f6c30876dfa 3985 #define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 3986 #define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3987 #define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3988 #define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3989 #define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3990
Kojto 107:4f6c30876dfa 3991 #define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 107:4f6c30876dfa 3992 #define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3993 #define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 3994 #define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 3995 #define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 3996
Kojto 107:4f6c30876dfa 3997 #define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 107:4f6c30876dfa 3998 #define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 3999 #define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4000 #define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4001 #define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4002
Kojto 107:4f6c30876dfa 4003 #define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4004 #define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4005 #define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4006
Kojto 107:4f6c30876dfa 4007 /****************** Bit definition for FMC_BTR2 register *******************/
Kojto 107:4f6c30876dfa 4008 #define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4009 #define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4010 #define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4011 #define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4012 #define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4013
Kojto 107:4f6c30876dfa 4014 #define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4015 #define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4016 #define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4017 #define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4018 #define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4019
Kojto 107:4f6c30876dfa 4020 #define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4021 #define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4022 #define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4023 #define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4024 #define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4025 #define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4026 #define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4027 #define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4028 #define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4029
Kojto 107:4f6c30876dfa 4030 #define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4031 #define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4032 #define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4033 #define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4034 #define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4035
Kojto 107:4f6c30876dfa 4036 #define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 107:4f6c30876dfa 4037 #define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4038 #define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4039 #define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4040 #define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4041
Kojto 107:4f6c30876dfa 4042 #define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 107:4f6c30876dfa 4043 #define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4044 #define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4045 #define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4046 #define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4047
Kojto 107:4f6c30876dfa 4048 #define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4049 #define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4050 #define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4051
Kojto 107:4f6c30876dfa 4052 /******************* Bit definition for FMC_BTR3 register *******************/
Kojto 107:4f6c30876dfa 4053 #define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4054 #define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4055 #define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4056 #define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4057 #define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4058
Kojto 107:4f6c30876dfa 4059 #define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4060 #define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4061 #define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4062 #define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4063 #define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4064
Kojto 107:4f6c30876dfa 4065 #define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4066 #define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4067 #define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4068 #define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4069 #define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4070 #define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4071 #define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4072 #define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4073 #define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4074
Kojto 107:4f6c30876dfa 4075 #define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4076 #define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4077 #define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4078 #define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4079 #define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4080
Kojto 107:4f6c30876dfa 4081 #define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 107:4f6c30876dfa 4082 #define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4083 #define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4084 #define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4085 #define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4086
Kojto 107:4f6c30876dfa 4087 #define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 107:4f6c30876dfa 4088 #define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4089 #define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4090 #define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4091 #define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4092
Kojto 107:4f6c30876dfa 4093 #define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4094 #define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4095 #define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4096
Kojto 107:4f6c30876dfa 4097 /****************** Bit definition for FMC_BTR4 register *******************/
Kojto 107:4f6c30876dfa 4098 #define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4099 #define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4100 #define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4101 #define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4102 #define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4103
Kojto 107:4f6c30876dfa 4104 #define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4105 #define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4106 #define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4107 #define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4108 #define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4109
Kojto 107:4f6c30876dfa 4110 #define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4111 #define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4112 #define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4113 #define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4114 #define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4115 #define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4116 #define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4117 #define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4118 #define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4119
Kojto 107:4f6c30876dfa 4120 #define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4121 #define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4122 #define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4123 #define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4124 #define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4125
Kojto 107:4f6c30876dfa 4126 #define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */
Kojto 107:4f6c30876dfa 4127 #define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4128 #define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4129 #define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4130 #define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4131
Kojto 107:4f6c30876dfa 4132 #define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */
Kojto 107:4f6c30876dfa 4133 #define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4134 #define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4135 #define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4136 #define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4137
Kojto 107:4f6c30876dfa 4138 #define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4139 #define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4140 #define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4141
Kojto 107:4f6c30876dfa 4142 /****************** Bit definition for FMC_BWTR1 register ******************/
Kojto 107:4f6c30876dfa 4143 #define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4144 #define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4145 #define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4146 #define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4147 #define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4148
Kojto 107:4f6c30876dfa 4149 #define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4150 #define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4151 #define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4152 #define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4153 #define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4154
Kojto 107:4f6c30876dfa 4155 #define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4156 #define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4157 #define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4158 #define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4159 #define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4160 #define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4161 #define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4162 #define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4163 #define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4164
Kojto 107:4f6c30876dfa 4165 #define FMC_BWTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4166 #define FMC_BWTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4167 #define FMC_BWTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4168 #define FMC_BWTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4169 #define FMC_BWTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4170
Kojto 107:4f6c30876dfa 4171 #define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4172 #define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4173 #define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4174
Kojto 107:4f6c30876dfa 4175 /****************** Bit definition for FMC_BWTR2 register ******************/
Kojto 107:4f6c30876dfa 4176 #define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4177 #define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4178 #define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4179 #define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4180 #define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4181
Kojto 107:4f6c30876dfa 4182 #define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4183 #define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4184 #define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4185 #define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4186 #define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4187
Kojto 107:4f6c30876dfa 4188 #define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4189 #define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4190 #define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4191 #define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4192 #define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4193 #define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4194 #define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4195 #define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4196 #define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4197
Kojto 107:4f6c30876dfa 4198 #define FMC_BWTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4199 #define FMC_BWTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4200 #define FMC_BWTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4201 #define FMC_BWTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4202 #define FMC_BWTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4203
Kojto 107:4f6c30876dfa 4204 #define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4205 #define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4206 #define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4207
Kojto 107:4f6c30876dfa 4208 /****************** Bit definition for FMC_BWTR3 register ******************/
Kojto 107:4f6c30876dfa 4209 #define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4210 #define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4211 #define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4212 #define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4213 #define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4214
Kojto 107:4f6c30876dfa 4215 #define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4216 #define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4217 #define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4218 #define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4219 #define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4220
Kojto 107:4f6c30876dfa 4221 #define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4222 #define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4223 #define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4224 #define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4225 #define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4226 #define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4227 #define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4228 #define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4229 #define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4230
Kojto 107:4f6c30876dfa 4231 #define FMC_BWTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4232 #define FMC_BWTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4233 #define FMC_BWTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4234 #define FMC_BWTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4235 #define FMC_BWTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4236
Kojto 107:4f6c30876dfa 4237 #define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4238 #define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4239 #define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4240
Kojto 107:4f6c30876dfa 4241 /****************** Bit definition for FMC_BWTR4 register ******************/
Kojto 107:4f6c30876dfa 4242 #define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */
Kojto 107:4f6c30876dfa 4243 #define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4244 #define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4245 #define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4246 #define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4247
Kojto 107:4f6c30876dfa 4248 #define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
Kojto 107:4f6c30876dfa 4249 #define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4250 #define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4251 #define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4252 #define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4253
Kojto 107:4f6c30876dfa 4254 #define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */
Kojto 107:4f6c30876dfa 4255 #define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4256 #define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4257 #define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4258 #define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4259 #define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4260 #define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4261 #define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4262 #define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4263
Kojto 107:4f6c30876dfa 4264 #define FMC_BWTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
Kojto 107:4f6c30876dfa 4265 #define FMC_BWTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4266 #define FMC_BWTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4267 #define FMC_BWTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4268 #define FMC_BWTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4269
Kojto 107:4f6c30876dfa 4270 #define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */
Kojto 107:4f6c30876dfa 4271 #define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4272 #define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4273
Kojto 107:4f6c30876dfa 4274 /****************** Bit definition for FMC_PCR register *******************/
Kojto 107:4f6c30876dfa 4275 #define FMC_PCR_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */
Kojto 107:4f6c30876dfa 4276 #define FMC_PCR_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */
Kojto 107:4f6c30876dfa 4277 #define FMC_PCR_PTYP ((uint32_t)0x00000008) /*!<Memory type */
Kojto 107:4f6c30876dfa 4278
Kojto 107:4f6c30876dfa 4279 #define FMC_PCR_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */
Kojto 107:4f6c30876dfa 4280 #define FMC_PCR_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4281 #define FMC_PCR_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4282
Kojto 107:4f6c30876dfa 4283 #define FMC_PCR_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */
Kojto 107:4f6c30876dfa 4284
Kojto 107:4f6c30876dfa 4285 #define FMC_PCR_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */
Kojto 107:4f6c30876dfa 4286 #define FMC_PCR_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4287 #define FMC_PCR_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4288 #define FMC_PCR_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4289 #define FMC_PCR_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4290
Kojto 107:4f6c30876dfa 4291 #define FMC_PCR_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */
Kojto 107:4f6c30876dfa 4292 #define FMC_PCR_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4293 #define FMC_PCR_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4294 #define FMC_PCR_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4295 #define FMC_PCR_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4296
Kojto 107:4f6c30876dfa 4297 #define FMC_PCR_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */
Kojto 107:4f6c30876dfa 4298 #define FMC_PCR_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4299 #define FMC_PCR_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4300 #define FMC_PCR_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4301
Kojto 107:4f6c30876dfa 4302 /******************* Bit definition for FMC_SR register *******************/
Kojto 107:4f6c30876dfa 4303 #define FMC_SR_IRS ((uint32_t)0x01) /*!<Interrupt Rising Edge status */
Kojto 107:4f6c30876dfa 4304 #define FMC_SR_ILS ((uint32_t)0x02) /*!<Interrupt Level status */
Kojto 107:4f6c30876dfa 4305 #define FMC_SR_IFS ((uint32_t)0x04) /*!<Interrupt Falling Edge status */
Kojto 107:4f6c30876dfa 4306 #define FMC_SR_IREN ((uint32_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */
Kojto 107:4f6c30876dfa 4307 #define FMC_SR_ILEN ((uint32_t)0x10) /*!<Interrupt Level detection Enable bit */
Kojto 107:4f6c30876dfa 4308 #define FMC_SR_IFEN ((uint32_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */
Kojto 107:4f6c30876dfa 4309 #define FMC_SR_FEMPT ((uint32_t)0x40) /*!<FIFO empty */
Kojto 107:4f6c30876dfa 4310
Kojto 107:4f6c30876dfa 4311 /****************** Bit definition for FMC_PMEM register ******************/
Kojto 107:4f6c30876dfa 4312 #define FMC_PMEM_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
Kojto 107:4f6c30876dfa 4313 #define FMC_PMEM_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4314 #define FMC_PMEM_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4315 #define FMC_PMEM_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4316 #define FMC_PMEM_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4317 #define FMC_PMEM_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4318 #define FMC_PMEM_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4319 #define FMC_PMEM_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4320 #define FMC_PMEM_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4321
Kojto 107:4f6c30876dfa 4322 #define FMC_PMEM_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
Kojto 107:4f6c30876dfa 4323 #define FMC_PMEM_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4324 #define FMC_PMEM_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4325 #define FMC_PMEM_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4326 #define FMC_PMEM_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4327 #define FMC_PMEM_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4328 #define FMC_PMEM_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4329 #define FMC_PMEM_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4330 #define FMC_PMEM_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4331
Kojto 107:4f6c30876dfa 4332 #define FMC_PMEM_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
Kojto 107:4f6c30876dfa 4333 #define FMC_PMEM_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4334 #define FMC_PMEM_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4335 #define FMC_PMEM_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4336 #define FMC_PMEM_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4337 #define FMC_PMEM_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4338 #define FMC_PMEM_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4339 #define FMC_PMEM_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4340 #define FMC_PMEM_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4341
Kojto 107:4f6c30876dfa 4342 #define FMC_PMEM_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
Kojto 107:4f6c30876dfa 4343 #define FMC_PMEM_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4344 #define FMC_PMEM_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4345 #define FMC_PMEM_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4346 #define FMC_PMEM_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4347 #define FMC_PMEM_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4348 #define FMC_PMEM_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4349 #define FMC_PMEM_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4350 #define FMC_PMEM_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4351
Kojto 107:4f6c30876dfa 4352 /****************** Bit definition for FMC_PATT register ******************/
Kojto 107:4f6c30876dfa 4353 #define FMC_PATT_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
Kojto 107:4f6c30876dfa 4354 #define FMC_PATT_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4355 #define FMC_PATT_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4356 #define FMC_PATT_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4357 #define FMC_PATT_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4358 #define FMC_PATT_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4359 #define FMC_PATT_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4360 #define FMC_PATT_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4361 #define FMC_PATT_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4362
Kojto 107:4f6c30876dfa 4363 #define FMC_PATT_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
Kojto 107:4f6c30876dfa 4364 #define FMC_PATT_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4365 #define FMC_PATT_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4366 #define FMC_PATT_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4367 #define FMC_PATT_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4368 #define FMC_PATT_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4369 #define FMC_PATT_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4370 #define FMC_PATT_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4371 #define FMC_PATT_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4372
Kojto 107:4f6c30876dfa 4373 #define FMC_PATT_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
Kojto 107:4f6c30876dfa 4374 #define FMC_PATT_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4375 #define FMC_PATT_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4376 #define FMC_PATT_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4377 #define FMC_PATT_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4378 #define FMC_PATT_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4379 #define FMC_PATT_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4380 #define FMC_PATT_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4381 #define FMC_PATT_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4382
Kojto 107:4f6c30876dfa 4383 #define FMC_PATT_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
Kojto 107:4f6c30876dfa 4384 #define FMC_PATT_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4385 #define FMC_PATT_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4386 #define FMC_PATT_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4387 #define FMC_PATT_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4388 #define FMC_PATT_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 4389 #define FMC_PATT_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 4390 #define FMC_PATT_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 4391 #define FMC_PATT_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 4392
Kojto 107:4f6c30876dfa 4393 /****************** Bit definition for FMC_ECCR register ******************/
Kojto 107:4f6c30876dfa 4394 #define FMC_ECCR_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */
Kojto 107:4f6c30876dfa 4395
Kojto 107:4f6c30876dfa 4396 /****************** Bit definition for FMC_SDCR1 register ******************/
Kojto 107:4f6c30876dfa 4397 #define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
Kojto 107:4f6c30876dfa 4398 #define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4399 #define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4400
Kojto 107:4f6c30876dfa 4401 #define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
Kojto 107:4f6c30876dfa 4402 #define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4403 #define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4404
Kojto 107:4f6c30876dfa 4405 #define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
Kojto 107:4f6c30876dfa 4406 #define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4407 #define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4408
Kojto 107:4f6c30876dfa 4409 #define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
Kojto 107:4f6c30876dfa 4410
Kojto 107:4f6c30876dfa 4411 #define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
Kojto 107:4f6c30876dfa 4412 #define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4413 #define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4414
Kojto 107:4f6c30876dfa 4415 #define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */
Kojto 107:4f6c30876dfa 4416
Kojto 107:4f6c30876dfa 4417 #define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */
Kojto 107:4f6c30876dfa 4418 #define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4419 #define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4420
Kojto 107:4f6c30876dfa 4421 #define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */
Kojto 107:4f6c30876dfa 4422
Kojto 107:4f6c30876dfa 4423 #define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */
Kojto 107:4f6c30876dfa 4424 #define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4425 #define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4426
Kojto 107:4f6c30876dfa 4427 /****************** Bit definition for FMC_SDCR2 register ******************/
Kojto 107:4f6c30876dfa 4428 #define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */
Kojto 107:4f6c30876dfa 4429 #define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4430 #define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4431
Kojto 107:4f6c30876dfa 4432 #define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */
Kojto 107:4f6c30876dfa 4433 #define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4434 #define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4435
Kojto 107:4f6c30876dfa 4436 #define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */
Kojto 107:4f6c30876dfa 4437 #define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4438 #define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4439
Kojto 107:4f6c30876dfa 4440 #define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */
Kojto 107:4f6c30876dfa 4441
Kojto 107:4f6c30876dfa 4442 #define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */
Kojto 107:4f6c30876dfa 4443 #define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4444 #define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4445
Kojto 107:4f6c30876dfa 4446 #define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */
Kojto 107:4f6c30876dfa 4447
Kojto 107:4f6c30876dfa 4448 #define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */
Kojto 107:4f6c30876dfa 4449 #define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4450 #define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4451
Kojto 107:4f6c30876dfa 4452 #define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */
Kojto 107:4f6c30876dfa 4453
Kojto 107:4f6c30876dfa 4454 #define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */
Kojto 107:4f6c30876dfa 4455 #define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4456 #define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4457
Kojto 107:4f6c30876dfa 4458 /****************** Bit definition for FMC_SDTR1 register ******************/
Kojto 107:4f6c30876dfa 4459 #define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 107:4f6c30876dfa 4460 #define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4461 #define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4462 #define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4463 #define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4464
Kojto 107:4f6c30876dfa 4465 #define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 107:4f6c30876dfa 4466 #define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4467 #define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4468 #define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4469 #define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4470
Kojto 107:4f6c30876dfa 4471 #define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 107:4f6c30876dfa 4472 #define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4473 #define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4474 #define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4475 #define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4476
Kojto 107:4f6c30876dfa 4477 #define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 107:4f6c30876dfa 4478 #define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4479 #define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4480 #define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4481
Kojto 107:4f6c30876dfa 4482 #define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 107:4f6c30876dfa 4483 #define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4484 #define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4485 #define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4486
Kojto 107:4f6c30876dfa 4487 #define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 107:4f6c30876dfa 4488 #define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4489 #define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4490 #define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4491
Kojto 107:4f6c30876dfa 4492 #define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
Kojto 107:4f6c30876dfa 4493 #define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4494 #define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4495 #define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4496
Kojto 107:4f6c30876dfa 4497 /****************** Bit definition for FMC_SDTR2 register ******************/
Kojto 107:4f6c30876dfa 4498 #define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */
Kojto 107:4f6c30876dfa 4499 #define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4500 #define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4501 #define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4502 #define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4503
Kojto 107:4f6c30876dfa 4504 #define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */
Kojto 107:4f6c30876dfa 4505 #define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4506 #define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4507 #define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4508 #define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4509
Kojto 107:4f6c30876dfa 4510 #define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */
Kojto 107:4f6c30876dfa 4511 #define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4512 #define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4513 #define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4514 #define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4515
Kojto 107:4f6c30876dfa 4516 #define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */
Kojto 107:4f6c30876dfa 4517 #define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4518 #define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4519 #define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4520
Kojto 107:4f6c30876dfa 4521 #define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */
Kojto 107:4f6c30876dfa 4522 #define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4523 #define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4524 #define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4525
Kojto 107:4f6c30876dfa 4526 #define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */
Kojto 107:4f6c30876dfa 4527 #define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4528 #define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4529 #define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4530
Kojto 107:4f6c30876dfa 4531 #define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */
Kojto 107:4f6c30876dfa 4532 #define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4533 #define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4534 #define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4535
Kojto 107:4f6c30876dfa 4536 /****************** Bit definition for FMC_SDCMR register ******************/
Kojto 107:4f6c30876dfa 4537 #define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */
Kojto 107:4f6c30876dfa 4538 #define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4539 #define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4540 #define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4541
Kojto 107:4f6c30876dfa 4542 #define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */
Kojto 107:4f6c30876dfa 4543
Kojto 107:4f6c30876dfa 4544 #define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */
Kojto 107:4f6c30876dfa 4545
Kojto 107:4f6c30876dfa 4546 #define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */
Kojto 107:4f6c30876dfa 4547 #define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4548 #define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4549 #define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 4550 #define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 4551
Kojto 107:4f6c30876dfa 4552 #define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */
Kojto 107:4f6c30876dfa 4553
Kojto 107:4f6c30876dfa 4554 /****************** Bit definition for FMC_SDRTR register ******************/
Kojto 107:4f6c30876dfa 4555 #define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */
Kojto 107:4f6c30876dfa 4556
Kojto 107:4f6c30876dfa 4557 #define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */
Kojto 107:4f6c30876dfa 4558
Kojto 107:4f6c30876dfa 4559 #define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */
Kojto 107:4f6c30876dfa 4560
Kojto 107:4f6c30876dfa 4561 /****************** Bit definition for FMC_SDSR register ******************/
Kojto 107:4f6c30876dfa 4562 #define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */
Kojto 107:4f6c30876dfa 4563
Kojto 107:4f6c30876dfa 4564 #define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */
Kojto 107:4f6c30876dfa 4565 #define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4566 #define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4567
Kojto 107:4f6c30876dfa 4568 #define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */
Kojto 107:4f6c30876dfa 4569 #define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 4570 #define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 4571
Kojto 107:4f6c30876dfa 4572 #define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */
Kojto 107:4f6c30876dfa 4573
Kojto 107:4f6c30876dfa 4574 /******************************************************************************/
Kojto 107:4f6c30876dfa 4575 /* */
Kojto 107:4f6c30876dfa 4576 /* General Purpose I/O */
Kojto 107:4f6c30876dfa 4577 /* */
Kojto 107:4f6c30876dfa 4578 /******************************************************************************/
Kojto 107:4f6c30876dfa 4579 /****************** Bits definition for GPIO_MODER register *****************/
Kojto 107:4f6c30876dfa 4580 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 4581 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4582 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4583
Kojto 107:4f6c30876dfa 4584 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 107:4f6c30876dfa 4585 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4586 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4587
Kojto 107:4f6c30876dfa 4588 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 107:4f6c30876dfa 4589 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4590 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4591
Kojto 107:4f6c30876dfa 4592 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 107:4f6c30876dfa 4593 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4594 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4595
Kojto 107:4f6c30876dfa 4596 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 107:4f6c30876dfa 4597 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4598 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4599
Kojto 107:4f6c30876dfa 4600 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 107:4f6c30876dfa 4601 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4602 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4603
Kojto 107:4f6c30876dfa 4604 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 107:4f6c30876dfa 4605 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4606 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4607
Kojto 107:4f6c30876dfa 4608 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 107:4f6c30876dfa 4609 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4610 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4611
Kojto 107:4f6c30876dfa 4612 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 4613 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 4614 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 4615
Kojto 107:4f6c30876dfa 4616 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 107:4f6c30876dfa 4617 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 4618 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 4619
Kojto 107:4f6c30876dfa 4620 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 4621 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 4622 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 4623
Kojto 107:4f6c30876dfa 4624 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 107:4f6c30876dfa 4625 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 4626 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 4627
Kojto 107:4f6c30876dfa 4628 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 107:4f6c30876dfa 4629 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 4630 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 4631
Kojto 107:4f6c30876dfa 4632 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 107:4f6c30876dfa 4633 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 4634 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 4635
Kojto 107:4f6c30876dfa 4636 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 107:4f6c30876dfa 4637 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 4638 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 4639
Kojto 107:4f6c30876dfa 4640 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 107:4f6c30876dfa 4641 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 4642 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 4643
Kojto 107:4f6c30876dfa 4644 /****************** Bits definition for GPIO_OTYPER register ****************/
Kojto 107:4f6c30876dfa 4645 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4646 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4647 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4648 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4649 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4650 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4651 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4652 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4653 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4654 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4655 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4656 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4657 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4658 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4659 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4660 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4661
Kojto 107:4f6c30876dfa 4662 /****************** Bits definition for GPIO_OSPEEDR register ***************/
Kojto 107:4f6c30876dfa 4663 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 4664 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4665 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4666
Kojto 107:4f6c30876dfa 4667 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 107:4f6c30876dfa 4668 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4669 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4670
Kojto 107:4f6c30876dfa 4671 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 107:4f6c30876dfa 4672 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4673 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4674
Kojto 107:4f6c30876dfa 4675 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 107:4f6c30876dfa 4676 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4677 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4678
Kojto 107:4f6c30876dfa 4679 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 107:4f6c30876dfa 4680 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4681 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4682
Kojto 107:4f6c30876dfa 4683 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 107:4f6c30876dfa 4684 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4685 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4686
Kojto 107:4f6c30876dfa 4687 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 107:4f6c30876dfa 4688 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4689 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4690
Kojto 107:4f6c30876dfa 4691 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 107:4f6c30876dfa 4692 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4693 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4694
Kojto 107:4f6c30876dfa 4695 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 4696 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 4697 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 4698
Kojto 107:4f6c30876dfa 4699 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 107:4f6c30876dfa 4700 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 4701 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 4702
Kojto 107:4f6c30876dfa 4703 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 4704 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 4705 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 4706
Kojto 107:4f6c30876dfa 4707 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 107:4f6c30876dfa 4708 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 4709 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 4710
Kojto 107:4f6c30876dfa 4711 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 107:4f6c30876dfa 4712 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 4713 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 4714
Kojto 107:4f6c30876dfa 4715 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 107:4f6c30876dfa 4716 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 4717 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 4718
Kojto 107:4f6c30876dfa 4719 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 107:4f6c30876dfa 4720 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 4721 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 4722
Kojto 107:4f6c30876dfa 4723 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 107:4f6c30876dfa 4724 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 4725 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 4726
Kojto 107:4f6c30876dfa 4727 /****************** Bits definition for GPIO_PUPDR register *****************/
Kojto 107:4f6c30876dfa 4728 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 4729 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4730 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4731
Kojto 107:4f6c30876dfa 4732 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 107:4f6c30876dfa 4733 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4734 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4735
Kojto 107:4f6c30876dfa 4736 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 107:4f6c30876dfa 4737 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4738 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4739
Kojto 107:4f6c30876dfa 4740 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 107:4f6c30876dfa 4741 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4742 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4743
Kojto 107:4f6c30876dfa 4744 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 107:4f6c30876dfa 4745 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4746 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4747
Kojto 107:4f6c30876dfa 4748 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 107:4f6c30876dfa 4749 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4750 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4751
Kojto 107:4f6c30876dfa 4752 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 107:4f6c30876dfa 4753 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4754 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4755
Kojto 107:4f6c30876dfa 4756 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 107:4f6c30876dfa 4757 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4758 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4759
Kojto 107:4f6c30876dfa 4760 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 4761 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 4762 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 4763
Kojto 107:4f6c30876dfa 4764 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 107:4f6c30876dfa 4765 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 4766 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 4767
Kojto 107:4f6c30876dfa 4768 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 4769 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 4770 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 4771
Kojto 107:4f6c30876dfa 4772 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 107:4f6c30876dfa 4773 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 4774 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 4775
Kojto 107:4f6c30876dfa 4776 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 107:4f6c30876dfa 4777 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 4778 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 4779
Kojto 107:4f6c30876dfa 4780 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 107:4f6c30876dfa 4781 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 4782 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 4783
Kojto 107:4f6c30876dfa 4784 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 107:4f6c30876dfa 4785 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 4786 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 4787
Kojto 107:4f6c30876dfa 4788 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 107:4f6c30876dfa 4789 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 4790 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 4791
Kojto 107:4f6c30876dfa 4792 /****************** Bits definition for GPIO_IDR register *******************/
Kojto 107:4f6c30876dfa 4793 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4794 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4795 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4796 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4797 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4798 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4799 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4800 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4801 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4802 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4803 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4804 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4805 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4806 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4807 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4808 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4809
Kojto 107:4f6c30876dfa 4810 /****************** Bits definition for GPIO_ODR register *******************/
Kojto 107:4f6c30876dfa 4811 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4812 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4813 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4814 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4815 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4816 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4817 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4818 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4819 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4820 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4821 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4822 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4823 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4824 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4825 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4826 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4827
Kojto 107:4f6c30876dfa 4828 /****************** Bits definition for GPIO_BSRR register ******************/
Kojto 107:4f6c30876dfa 4829 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4830 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4831 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4832 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4833 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4834 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4835 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4836 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4837 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4838 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4839 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4840 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4841 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4842 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4843 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4844 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4845 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 4846 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 4847 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 4848 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 4849 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 4850 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 4851 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 4852 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 4853 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 4854 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 4855 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 4856 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 4857 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 4858 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 4859 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 4860 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 4861
Kojto 107:4f6c30876dfa 4862 /****************** Bit definition for GPIO_LCKR register *********************/
Kojto 107:4f6c30876dfa 4863 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 4864 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 4865 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 4866 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 4867 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 4868 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 4869 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 4870 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 4871 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 4872 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 4873 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 4874 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 4875 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 4876 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 4877 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 4878 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 4879 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 4880
Kojto 116:c0f6e94411f5 4881
Kojto 107:4f6c30876dfa 4882 /******************************************************************************/
Kojto 107:4f6c30876dfa 4883 /* */
Kojto 107:4f6c30876dfa 4884 /* Inter-integrated Circuit Interface (I2C) */
Kojto 107:4f6c30876dfa 4885 /* */
Kojto 107:4f6c30876dfa 4886 /******************************************************************************/
Kojto 107:4f6c30876dfa 4887 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 107:4f6c30876dfa 4888 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 107:4f6c30876dfa 4889 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 107:4f6c30876dfa 4890 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 107:4f6c30876dfa 4891 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 107:4f6c30876dfa 4892 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 107:4f6c30876dfa 4893 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 107:4f6c30876dfa 4894 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 107:4f6c30876dfa 4895 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 116:c0f6e94411f5 4896 #define I2C_CR1_DNF ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 107:4f6c30876dfa 4897 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 107:4f6c30876dfa 4898 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 107:4f6c30876dfa 4899 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 107:4f6c30876dfa 4900 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 107:4f6c30876dfa 4901 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 107:4f6c30876dfa 4902 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 107:4f6c30876dfa 4903 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Kojto 107:4f6c30876dfa 4904 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 107:4f6c30876dfa 4905 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 107:4f6c30876dfa 4906 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 107:4f6c30876dfa 4907 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 107:4f6c30876dfa 4908 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 107:4f6c30876dfa 4909
Kojto 116:c0f6e94411f5 4910 /* Legacy define */
Kojto 116:c0f6e94411f5 4911 #define I2C_CR1_DFN I2C_CR1_DNF /*!< Digital noise filter */
Kojto 116:c0f6e94411f5 4912
Kojto 107:4f6c30876dfa 4913 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 107:4f6c30876dfa 4914 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 107:4f6c30876dfa 4915 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 107:4f6c30876dfa 4916 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 107:4f6c30876dfa 4917 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 107:4f6c30876dfa 4918 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 107:4f6c30876dfa 4919 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 107:4f6c30876dfa 4920 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 107:4f6c30876dfa 4921 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 107:4f6c30876dfa 4922 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 107:4f6c30876dfa 4923 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 107:4f6c30876dfa 4924 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 107:4f6c30876dfa 4925
Kojto 107:4f6c30876dfa 4926 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 107:4f6c30876dfa 4927 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 107:4f6c30876dfa 4928 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 107:4f6c30876dfa 4929 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 107:4f6c30876dfa 4930
Kojto 107:4f6c30876dfa 4931 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 107:4f6c30876dfa 4932 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 107:4f6c30876dfa 4933 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 107:4f6c30876dfa 4934 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000) /*!< No mask */
Kojto 107:4f6c30876dfa 4935 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 107:4f6c30876dfa 4936 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 107:4f6c30876dfa 4937 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 107:4f6c30876dfa 4938 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 107:4f6c30876dfa 4939 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 107:4f6c30876dfa 4940 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 107:4f6c30876dfa 4941 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700) /*!< OA2[7:1] is masked, No comparison is done */
Kojto 107:4f6c30876dfa 4942 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 107:4f6c30876dfa 4943
Kojto 107:4f6c30876dfa 4944 /******************* Bit definition for I2C_TIMINGR register *******************/
Kojto 107:4f6c30876dfa 4945 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 107:4f6c30876dfa 4946 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 107:4f6c30876dfa 4947 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 107:4f6c30876dfa 4948 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 107:4f6c30876dfa 4949 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 107:4f6c30876dfa 4950
Kojto 107:4f6c30876dfa 4951 /******************* Bit definition for I2C_TIMEOUTR register *******************/
Kojto 107:4f6c30876dfa 4952 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 107:4f6c30876dfa 4953 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 107:4f6c30876dfa 4954 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 107:4f6c30876dfa 4955 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B */
Kojto 107:4f6c30876dfa 4956 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 107:4f6c30876dfa 4957
Kojto 107:4f6c30876dfa 4958 /****************** Bit definition for I2C_ISR register *********************/
Kojto 107:4f6c30876dfa 4959 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 107:4f6c30876dfa 4960 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 107:4f6c30876dfa 4961 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 107:4f6c30876dfa 4962 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode) */
Kojto 107:4f6c30876dfa 4963 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 107:4f6c30876dfa 4964 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 107:4f6c30876dfa 4965 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 107:4f6c30876dfa 4966 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 107:4f6c30876dfa 4967 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 107:4f6c30876dfa 4968 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 107:4f6c30876dfa 4969 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 107:4f6c30876dfa 4970 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 107:4f6c30876dfa 4971 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 107:4f6c30876dfa 4972 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 107:4f6c30876dfa 4973 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 107:4f6c30876dfa 4974 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 107:4f6c30876dfa 4975 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 107:4f6c30876dfa 4976
Kojto 107:4f6c30876dfa 4977 /****************** Bit definition for I2C_ICR register *********************/
Kojto 107:4f6c30876dfa 4978 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 107:4f6c30876dfa 4979 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 107:4f6c30876dfa 4980 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 107:4f6c30876dfa 4981 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 107:4f6c30876dfa 4982 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 107:4f6c30876dfa 4983 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 107:4f6c30876dfa 4984 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 107:4f6c30876dfa 4985 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 107:4f6c30876dfa 4986 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 107:4f6c30876dfa 4987
Kojto 107:4f6c30876dfa 4988 /****************** Bit definition for I2C_PECR register *********************/
Kojto 107:4f6c30876dfa 4989 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 107:4f6c30876dfa 4990
Kojto 107:4f6c30876dfa 4991 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 107:4f6c30876dfa 4992 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 107:4f6c30876dfa 4993
Kojto 107:4f6c30876dfa 4994 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 107:4f6c30876dfa 4995 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 107:4f6c30876dfa 4996
Kojto 107:4f6c30876dfa 4997
Kojto 107:4f6c30876dfa 4998 /******************************************************************************/
Kojto 107:4f6c30876dfa 4999 /* */
Kojto 107:4f6c30876dfa 5000 /* Independent WATCHDOG */
Kojto 107:4f6c30876dfa 5001 /* */
Kojto 107:4f6c30876dfa 5002 /******************************************************************************/
Kojto 107:4f6c30876dfa 5003 /******************* Bit definition for IWDG_KR register ********************/
Kojto 107:4f6c30876dfa 5004 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!<Key value (write only, read 0000h) */
Kojto 107:4f6c30876dfa 5005
Kojto 107:4f6c30876dfa 5006 /******************* Bit definition for IWDG_PR register ********************/
Kojto 107:4f6c30876dfa 5007 #define IWDG_PR_PR ((uint32_t)0x07) /*!<PR[2:0] (Prescaler divider) */
Kojto 107:4f6c30876dfa 5008 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 5009 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 5010 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 5011
Kojto 107:4f6c30876dfa 5012 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 107:4f6c30876dfa 5013 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!<Watchdog counter reload value */
Kojto 107:4f6c30876dfa 5014
Kojto 107:4f6c30876dfa 5015 /******************* Bit definition for IWDG_SR register ********************/
Kojto 107:4f6c30876dfa 5016 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
Kojto 107:4f6c30876dfa 5017 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
Kojto 107:4f6c30876dfa 5018 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
Kojto 107:4f6c30876dfa 5019
Kojto 107:4f6c30876dfa 5020 /******************* Bit definition for IWDG_KR register ********************/
Kojto 107:4f6c30876dfa 5021 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
Kojto 107:4f6c30876dfa 5022
Kojto 107:4f6c30876dfa 5023 /******************************************************************************/
Kojto 107:4f6c30876dfa 5024 /* */
Kojto 107:4f6c30876dfa 5025 /* LCD-TFT Display Controller (LTDC) */
Kojto 107:4f6c30876dfa 5026 /* */
Kojto 107:4f6c30876dfa 5027 /******************************************************************************/
Kojto 107:4f6c30876dfa 5028
Kojto 107:4f6c30876dfa 5029 /******************** Bit definition for LTDC_SSCR register *****************/
Kojto 107:4f6c30876dfa 5030
Kojto 107:4f6c30876dfa 5031 #define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */
Kojto 107:4f6c30876dfa 5032 #define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */
Kojto 107:4f6c30876dfa 5033
Kojto 107:4f6c30876dfa 5034 /******************** Bit definition for LTDC_BPCR register *****************/
Kojto 107:4f6c30876dfa 5035
Kojto 107:4f6c30876dfa 5036 #define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */
Kojto 107:4f6c30876dfa 5037 #define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */
Kojto 107:4f6c30876dfa 5038
Kojto 107:4f6c30876dfa 5039 /******************** Bit definition for LTDC_AWCR register *****************/
Kojto 107:4f6c30876dfa 5040
Kojto 107:4f6c30876dfa 5041 #define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */
Kojto 107:4f6c30876dfa 5042 #define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */
Kojto 107:4f6c30876dfa 5043
Kojto 107:4f6c30876dfa 5044 /******************** Bit definition for LTDC_TWCR register *****************/
Kojto 107:4f6c30876dfa 5045
Kojto 107:4f6c30876dfa 5046 #define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */
Kojto 107:4f6c30876dfa 5047 #define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */
Kojto 107:4f6c30876dfa 5048
Kojto 107:4f6c30876dfa 5049 /******************** Bit definition for LTDC_GCR register ******************/
Kojto 107:4f6c30876dfa 5050
Kojto 107:4f6c30876dfa 5051 #define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */
Kojto 107:4f6c30876dfa 5052 #define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */
Kojto 107:4f6c30876dfa 5053 #define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */
Kojto 107:4f6c30876dfa 5054 #define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */
Kojto 107:4f6c30876dfa 5055 #define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */
Kojto 107:4f6c30876dfa 5056 #define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */
Kojto 107:4f6c30876dfa 5057 #define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */
Kojto 107:4f6c30876dfa 5058 #define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */
Kojto 107:4f6c30876dfa 5059 #define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */
Kojto 107:4f6c30876dfa 5060
Kojto 107:4f6c30876dfa 5061 /******************** Bit definition for LTDC_SRCR register *****************/
Kojto 107:4f6c30876dfa 5062
Kojto 107:4f6c30876dfa 5063 #define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */
Kojto 107:4f6c30876dfa 5064 #define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */
Kojto 107:4f6c30876dfa 5065
Kojto 107:4f6c30876dfa 5066 /******************** Bit definition for LTDC_BCCR register *****************/
Kojto 107:4f6c30876dfa 5067
Kojto 107:4f6c30876dfa 5068 #define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */
Kojto 107:4f6c30876dfa 5069 #define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */
Kojto 107:4f6c30876dfa 5070 #define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */
Kojto 107:4f6c30876dfa 5071
Kojto 107:4f6c30876dfa 5072 /******************** Bit definition for LTDC_IER register ******************/
Kojto 107:4f6c30876dfa 5073
Kojto 107:4f6c30876dfa 5074 #define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */
Kojto 107:4f6c30876dfa 5075 #define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */
Kojto 107:4f6c30876dfa 5076 #define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */
Kojto 107:4f6c30876dfa 5077 #define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */
Kojto 107:4f6c30876dfa 5078
Kojto 107:4f6c30876dfa 5079 /******************** Bit definition for LTDC_ISR register ******************/
Kojto 107:4f6c30876dfa 5080
Kojto 107:4f6c30876dfa 5081 #define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */
Kojto 107:4f6c30876dfa 5082 #define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */
Kojto 107:4f6c30876dfa 5083 #define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */
Kojto 107:4f6c30876dfa 5084 #define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */
Kojto 107:4f6c30876dfa 5085
Kojto 107:4f6c30876dfa 5086 /******************** Bit definition for LTDC_ICR register ******************/
Kojto 107:4f6c30876dfa 5087
Kojto 107:4f6c30876dfa 5088 #define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */
Kojto 107:4f6c30876dfa 5089 #define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */
Kojto 107:4f6c30876dfa 5090 #define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */
Kojto 107:4f6c30876dfa 5091 #define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */
Kojto 107:4f6c30876dfa 5092
Kojto 107:4f6c30876dfa 5093 /******************** Bit definition for LTDC_LIPCR register ****************/
Kojto 107:4f6c30876dfa 5094
Kojto 107:4f6c30876dfa 5095 #define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */
Kojto 107:4f6c30876dfa 5096
Kojto 107:4f6c30876dfa 5097 /******************** Bit definition for LTDC_CPSR register *****************/
Kojto 107:4f6c30876dfa 5098
Kojto 107:4f6c30876dfa 5099 #define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */
Kojto 107:4f6c30876dfa 5100 #define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */
Kojto 107:4f6c30876dfa 5101
Kojto 107:4f6c30876dfa 5102 /******************** Bit definition for LTDC_CDSR register *****************/
Kojto 107:4f6c30876dfa 5103
Kojto 107:4f6c30876dfa 5104 #define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */
Kojto 107:4f6c30876dfa 5105 #define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */
Kojto 107:4f6c30876dfa 5106 #define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */
Kojto 107:4f6c30876dfa 5107 #define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */
Kojto 107:4f6c30876dfa 5108
Kojto 107:4f6c30876dfa 5109 /******************** Bit definition for LTDC_LxCR register *****************/
Kojto 107:4f6c30876dfa 5110
Kojto 107:4f6c30876dfa 5111 #define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */
Kojto 107:4f6c30876dfa 5112 #define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */
Kojto 107:4f6c30876dfa 5113 #define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */
Kojto 107:4f6c30876dfa 5114
Kojto 107:4f6c30876dfa 5115 /******************** Bit definition for LTDC_LxWHPCR register **************/
Kojto 107:4f6c30876dfa 5116
Kojto 107:4f6c30876dfa 5117 #define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */
Kojto 107:4f6c30876dfa 5118 #define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */
Kojto 107:4f6c30876dfa 5119
Kojto 107:4f6c30876dfa 5120 /******************** Bit definition for LTDC_LxWVPCR register **************/
Kojto 107:4f6c30876dfa 5121
Kojto 107:4f6c30876dfa 5122 #define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */
Kojto 107:4f6c30876dfa 5123 #define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */
Kojto 107:4f6c30876dfa 5124
Kojto 107:4f6c30876dfa 5125 /******************** Bit definition for LTDC_LxCKCR register ***************/
Kojto 107:4f6c30876dfa 5126
Kojto 107:4f6c30876dfa 5127 #define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */
Kojto 107:4f6c30876dfa 5128 #define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */
Kojto 107:4f6c30876dfa 5129 #define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */
Kojto 107:4f6c30876dfa 5130
Kojto 107:4f6c30876dfa 5131 /******************** Bit definition for LTDC_LxPFCR register ***************/
Kojto 107:4f6c30876dfa 5132
Kojto 107:4f6c30876dfa 5133 #define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */
Kojto 107:4f6c30876dfa 5134
Kojto 107:4f6c30876dfa 5135 /******************** Bit definition for LTDC_LxCACR register ***************/
Kojto 107:4f6c30876dfa 5136
Kojto 107:4f6c30876dfa 5137 #define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */
Kojto 107:4f6c30876dfa 5138
Kojto 107:4f6c30876dfa 5139 /******************** Bit definition for LTDC_LxDCCR register ***************/
Kojto 107:4f6c30876dfa 5140
Kojto 107:4f6c30876dfa 5141 #define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */
Kojto 107:4f6c30876dfa 5142 #define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */
Kojto 107:4f6c30876dfa 5143 #define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */
Kojto 107:4f6c30876dfa 5144 #define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */
Kojto 107:4f6c30876dfa 5145
Kojto 107:4f6c30876dfa 5146 /******************** Bit definition for LTDC_LxBFCR register ***************/
Kojto 107:4f6c30876dfa 5147
Kojto 107:4f6c30876dfa 5148 #define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */
Kojto 107:4f6c30876dfa 5149 #define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */
Kojto 107:4f6c30876dfa 5150
Kojto 107:4f6c30876dfa 5151 /******************** Bit definition for LTDC_LxCFBAR register **************/
Kojto 107:4f6c30876dfa 5152
Kojto 107:4f6c30876dfa 5153 #define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */
Kojto 107:4f6c30876dfa 5154
Kojto 107:4f6c30876dfa 5155 /******************** Bit definition for LTDC_LxCFBLR register **************/
Kojto 107:4f6c30876dfa 5156
Kojto 107:4f6c30876dfa 5157 #define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */
Kojto 107:4f6c30876dfa 5158 #define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */
Kojto 107:4f6c30876dfa 5159
Kojto 107:4f6c30876dfa 5160 /******************** Bit definition for LTDC_LxCFBLNR register *************/
Kojto 107:4f6c30876dfa 5161
Kojto 107:4f6c30876dfa 5162 #define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */
Kojto 107:4f6c30876dfa 5163
Kojto 107:4f6c30876dfa 5164 /******************** Bit definition for LTDC_LxCLUTWR register *************/
Kojto 107:4f6c30876dfa 5165
Kojto 107:4f6c30876dfa 5166 #define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */
Kojto 107:4f6c30876dfa 5167 #define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */
Kojto 107:4f6c30876dfa 5168 #define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */
Kojto 107:4f6c30876dfa 5169 #define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */
Kojto 107:4f6c30876dfa 5170
Kojto 107:4f6c30876dfa 5171 /******************************************************************************/
Kojto 107:4f6c30876dfa 5172 /* */
Kojto 107:4f6c30876dfa 5173 /* Power Control */
Kojto 107:4f6c30876dfa 5174 /* */
Kojto 107:4f6c30876dfa 5175 /******************************************************************************/
Kojto 107:4f6c30876dfa 5176 /******************** Bit definition for PWR_CR1 register ********************/
Kojto 107:4f6c30876dfa 5177 #define PWR_CR1_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */
Kojto 107:4f6c30876dfa 5178 #define PWR_CR1_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 107:4f6c30876dfa 5179 #define PWR_CR1_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 107:4f6c30876dfa 5180 #define PWR_CR1_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 107:4f6c30876dfa 5181
Kojto 107:4f6c30876dfa 5182 #define PWR_CR1_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 107:4f6c30876dfa 5183 #define PWR_CR1_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5184 #define PWR_CR1_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5185 #define PWR_CR1_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5186
Kojto 107:4f6c30876dfa 5187 /*!< PVD level configuration */
Kojto 107:4f6c30876dfa 5188 #define PWR_CR1_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 107:4f6c30876dfa 5189 #define PWR_CR1_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 107:4f6c30876dfa 5190 #define PWR_CR1_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 107:4f6c30876dfa 5191 #define PWR_CR1_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 107:4f6c30876dfa 5192 #define PWR_CR1_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 107:4f6c30876dfa 5193 #define PWR_CR1_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 107:4f6c30876dfa 5194 #define PWR_CR1_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 107:4f6c30876dfa 5195 #define PWR_CR1_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 107:4f6c30876dfa 5196
Kojto 107:4f6c30876dfa 5197 #define PWR_CR1_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 107:4f6c30876dfa 5198 #define PWR_CR1_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
Kojto 107:4f6c30876dfa 5199
Kojto 107:4f6c30876dfa 5200 #define PWR_CR1_LPUDS ((uint32_t)0x00000400) /*!< Low-power regulator in deepsleep under-drive mode */
Kojto 107:4f6c30876dfa 5201 #define PWR_CR1_MRUDS ((uint32_t)0x00000800) /*!< Main regulator in deepsleep under-drive mode */
Kojto 107:4f6c30876dfa 5202
Kojto 107:4f6c30876dfa 5203 #define PWR_CR1_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
Kojto 107:4f6c30876dfa 5204
Kojto 107:4f6c30876dfa 5205 #define PWR_CR1_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
Kojto 107:4f6c30876dfa 5206 #define PWR_CR1_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5207 #define PWR_CR1_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5208
Kojto 107:4f6c30876dfa 5209 #define PWR_CR1_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */
Kojto 107:4f6c30876dfa 5210 #define PWR_CR1_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */
Kojto 107:4f6c30876dfa 5211 #define PWR_CR1_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */
Kojto 107:4f6c30876dfa 5212 #define PWR_CR1_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5213 #define PWR_CR1_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5214
Kojto 107:4f6c30876dfa 5215 /******************* Bit definition for PWR_CSR1 register ********************/
Kojto 107:4f6c30876dfa 5216 #define PWR_CSR1_WUIF ((uint32_t)0x00000001) /*!< Wake up internal Flag */
Kojto 107:4f6c30876dfa 5217 #define PWR_CSR1_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 107:4f6c30876dfa 5218 #define PWR_CSR1_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 107:4f6c30876dfa 5219 #define PWR_CSR1_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */
Kojto 107:4f6c30876dfa 5220 #define PWR_CSR1_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */
Kojto 107:4f6c30876dfa 5221 #define PWR_CSR1_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */
Kojto 107:4f6c30876dfa 5222
Kojto 107:4f6c30876dfa 5223 #define PWR_CSR1_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */
Kojto 107:4f6c30876dfa 5224 #define PWR_CSR1_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */
Kojto 107:4f6c30876dfa 5225 #define PWR_CSR1_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */
Kojto 107:4f6c30876dfa 5226
Kojto 107:4f6c30876dfa 5227 /******************** Bit definition for PWR_CR2 register ********************/
Kojto 107:4f6c30876dfa 5228 #define PWR_CR2_CWUPF1 ((uint32_t)0x00000001) /*!< Clear Wakeup Pin Flag for PA0 */
Kojto 107:4f6c30876dfa 5229 #define PWR_CR2_CWUPF2 ((uint32_t)0x00000002) /*!< Clear Wakeup Pin Flag for PA2 */
Kojto 107:4f6c30876dfa 5230 #define PWR_CR2_CWUPF3 ((uint32_t)0x00000004) /*!< Clear Wakeup Pin Flag for PC1 */
Kojto 107:4f6c30876dfa 5231 #define PWR_CR2_CWUPF4 ((uint32_t)0x00000008) /*!< Clear Wakeup Pin Flag for PC13 */
Kojto 107:4f6c30876dfa 5232 #define PWR_CR2_CWUPF5 ((uint32_t)0x00000010) /*!< Clear Wakeup Pin Flag for PI8 */
Kojto 107:4f6c30876dfa 5233 #define PWR_CR2_CWUPF6 ((uint32_t)0x00000020) /*!< Clear Wakeup Pin Flag for PI11 */
Kojto 107:4f6c30876dfa 5234
Kojto 107:4f6c30876dfa 5235 #define PWR_CR2_WUPP1 ((uint32_t)0x00000100) /*!< Wakeup Pin Polarity bit for PA0 */
Kojto 107:4f6c30876dfa 5236 #define PWR_CR2_WUPP2 ((uint32_t)0x00000200) /*!< Wakeup Pin Polarity bit for PA2 */
Kojto 107:4f6c30876dfa 5237 #define PWR_CR2_WUPP3 ((uint32_t)0x00000400) /*!< Wakeup Pin Polarity bit for PC1 */
Kojto 107:4f6c30876dfa 5238 #define PWR_CR2_WUPP4 ((uint32_t)0x00000800) /*!< Wakeup Pin Polarity bit for PC13 */
Kojto 107:4f6c30876dfa 5239 #define PWR_CR2_WUPP5 ((uint32_t)0x00001000) /*!< Wakeup Pin Polarity bit for PI8 */
Kojto 107:4f6c30876dfa 5240 #define PWR_CR2_WUPP6 ((uint32_t)0x00002000) /*!< Wakeup Pin Polarity bit for PI11 */
Kojto 107:4f6c30876dfa 5241
Kojto 107:4f6c30876dfa 5242 /******************* Bit definition for PWR_CSR2 register ********************/
Kojto 107:4f6c30876dfa 5243 #define PWR_CSR2_WUPF1 ((uint32_t)0x00000001) /*!< Wakeup Pin Flag for PA0 */
Kojto 107:4f6c30876dfa 5244 #define PWR_CSR2_WUPF2 ((uint32_t)0x00000002) /*!< Wakeup Pin Flag for PA2 */
Kojto 107:4f6c30876dfa 5245 #define PWR_CSR2_WUPF3 ((uint32_t)0x00000004) /*!< Wakeup Pin Flag for PC1 */
Kojto 107:4f6c30876dfa 5246 #define PWR_CSR2_WUPF4 ((uint32_t)0x00000008) /*!< Wakeup Pin Flag for PC13 */
Kojto 107:4f6c30876dfa 5247 #define PWR_CSR2_WUPF5 ((uint32_t)0x00000010) /*!< Wakeup Pin Flag for PI8 */
Kojto 107:4f6c30876dfa 5248 #define PWR_CSR2_WUPF6 ((uint32_t)0x00000020) /*!< Wakeup Pin Flag for PI11 */
Kojto 107:4f6c30876dfa 5249
Kojto 107:4f6c30876dfa 5250 #define PWR_CSR2_EWUP1 ((uint32_t)0x00000100) /*!< Enable Wakeup Pin PA0 */
Kojto 107:4f6c30876dfa 5251 #define PWR_CSR2_EWUP2 ((uint32_t)0x00000200) /*!< Enable Wakeup Pin PA2 */
Kojto 107:4f6c30876dfa 5252 #define PWR_CSR2_EWUP3 ((uint32_t)0x00000400) /*!< Enable Wakeup Pin PC1 */
Kojto 107:4f6c30876dfa 5253 #define PWR_CSR2_EWUP4 ((uint32_t)0x00000800) /*!< Enable Wakeup Pin PC13 */
Kojto 107:4f6c30876dfa 5254 #define PWR_CSR2_EWUP5 ((uint32_t)0x00001000) /*!< Enable Wakeup Pin PI8 */
Kojto 107:4f6c30876dfa 5255 #define PWR_CSR2_EWUP6 ((uint32_t)0x00002000) /*!< Enable Wakeup Pin PI11 */
Kojto 107:4f6c30876dfa 5256
Kojto 107:4f6c30876dfa 5257 /******************************************************************************/
Kojto 107:4f6c30876dfa 5258 /* */
Kojto 107:4f6c30876dfa 5259 /* QUADSPI */
Kojto 107:4f6c30876dfa 5260 /* */
Kojto 107:4f6c30876dfa 5261 /******************************************************************************/
Kojto 107:4f6c30876dfa 5262 /***************** Bit definition for QUADSPI_CR register *******************/
Kojto 107:4f6c30876dfa 5263 #define QUADSPI_CR_EN ((uint32_t)0x00000001) /*!< Enable */
Kojto 107:4f6c30876dfa 5264 #define QUADSPI_CR_ABORT ((uint32_t)0x00000002) /*!< Abort request */
Kojto 107:4f6c30876dfa 5265 #define QUADSPI_CR_DMAEN ((uint32_t)0x00000004) /*!< DMA Enable */
Kojto 107:4f6c30876dfa 5266 #define QUADSPI_CR_TCEN ((uint32_t)0x00000008) /*!< Timeout Counter Enable */
Kojto 107:4f6c30876dfa 5267 #define QUADSPI_CR_SSHIFT ((uint32_t)0x00000010) /*!< Sample Shift */
Kojto 107:4f6c30876dfa 5268 #define QUADSPI_CR_DFM ((uint32_t)0x00000040) /*!< Dual Flash Mode */
Kojto 107:4f6c30876dfa 5269 #define QUADSPI_CR_FSEL ((uint32_t)0x00000080) /*!< Flash Select */
Kojto 107:4f6c30876dfa 5270 #define QUADSPI_CR_FTHRES ((uint32_t)0x00000F00) /*!< FTHRES[3:0] FIFO Level */
Kojto 107:4f6c30876dfa 5271 #define QUADSPI_CR_FTHRES_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5272 #define QUADSPI_CR_FTHRES_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5273 #define QUADSPI_CR_FTHRES_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5274 #define QUADSPI_CR_FTHRES_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5275 #define QUADSPI_CR_TEIE ((uint32_t)0x00010000) /*!< Transfer Error Interrupt Enable */
Kojto 107:4f6c30876dfa 5276 #define QUADSPI_CR_TCIE ((uint32_t)0x00020000) /*!< Transfer Complete Interrupt Enable */
Kojto 107:4f6c30876dfa 5277 #define QUADSPI_CR_FTIE ((uint32_t)0x00040000) /*!< FIFO Threshold Interrupt Enable */
Kojto 107:4f6c30876dfa 5278 #define QUADSPI_CR_SMIE ((uint32_t)0x00080000) /*!< Status Match Interrupt Enable */
Kojto 107:4f6c30876dfa 5279 #define QUADSPI_CR_TOIE ((uint32_t)0x00100000) /*!< TimeOut Interrupt Enable */
Kojto 107:4f6c30876dfa 5280 #define QUADSPI_CR_APMS ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5281 #define QUADSPI_CR_PMM ((uint32_t)0x00800000) /*!< Polling Match Mode */
Kojto 107:4f6c30876dfa 5282 #define QUADSPI_CR_PRESCALER ((uint32_t)0xFF000000) /*!< PRESCALER[7:0] Clock prescaler */
Kojto 107:4f6c30876dfa 5283 #define QUADSPI_CR_PRESCALER_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5284 #define QUADSPI_CR_PRESCALER_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5285 #define QUADSPI_CR_PRESCALER_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5286 #define QUADSPI_CR_PRESCALER_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5287 #define QUADSPI_CR_PRESCALER_4 ((uint32_t)0x10000000) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 5288 #define QUADSPI_CR_PRESCALER_5 ((uint32_t)0x20000000) /*!< Bit 5 */
Kojto 107:4f6c30876dfa 5289 #define QUADSPI_CR_PRESCALER_6 ((uint32_t)0x40000000) /*!< Bit 6 */
Kojto 107:4f6c30876dfa 5290 #define QUADSPI_CR_PRESCALER_7 ((uint32_t)0x80000000) /*!< Bit 7 */
Kojto 107:4f6c30876dfa 5291
Kojto 107:4f6c30876dfa 5292 /***************** Bit definition for QUADSPI_DCR register ******************/
Kojto 107:4f6c30876dfa 5293 #define QUADSPI_DCR_CKMODE ((uint32_t)0x00000001) /*!< Mode 0 / Mode 3 */
Kojto 107:4f6c30876dfa 5294 #define QUADSPI_DCR_CSHT ((uint32_t)0x00000700) /*!< CSHT[2:0]: ChipSelect High Time */
Kojto 107:4f6c30876dfa 5295 #define QUADSPI_DCR_CSHT_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5296 #define QUADSPI_DCR_CSHT_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5297 #define QUADSPI_DCR_CSHT_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5298 #define QUADSPI_DCR_FSIZE ((uint32_t)0x001F0000) /*!< FSIZE[4:0]: Flash Size */
Kojto 107:4f6c30876dfa 5299 #define QUADSPI_DCR_FSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5300 #define QUADSPI_DCR_FSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5301 #define QUADSPI_DCR_FSIZE_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5302 #define QUADSPI_DCR_FSIZE_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5303 #define QUADSPI_DCR_FSIZE_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 5304
Kojto 107:4f6c30876dfa 5305 /****************** Bit definition for QUADSPI_SR register *******************/
Kojto 107:4f6c30876dfa 5306 #define QUADSPI_SR_TEF ((uint32_t)0x00000001) /*!< Transfer Error Flag */
Kojto 107:4f6c30876dfa 5307 #define QUADSPI_SR_TCF ((uint32_t)0x00000002) /*!< Transfer Complete Flag */
Kojto 107:4f6c30876dfa 5308 #define QUADSPI_SR_FTF ((uint32_t)0x00000004) /*!< FIFO Threshlod Flag */
Kojto 107:4f6c30876dfa 5309 #define QUADSPI_SR_SMF ((uint32_t)0x00000008) /*!< Status Match Flag */
Kojto 107:4f6c30876dfa 5310 #define QUADSPI_SR_TOF ((uint32_t)0x00000010) /*!< Timeout Flag */
Kojto 107:4f6c30876dfa 5311 #define QUADSPI_SR_BUSY ((uint32_t)0x00000020) /*!< Busy */
Kojto 107:4f6c30876dfa 5312 #define QUADSPI_SR_FLEVEL ((uint32_t)0x00001F00) /*!< FIFO Threshlod Flag */
Kojto 107:4f6c30876dfa 5313 #define QUADSPI_SR_FLEVEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5314 #define QUADSPI_SR_FLEVEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5315 #define QUADSPI_SR_FLEVEL_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5316 #define QUADSPI_SR_FLEVEL_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5317 #define QUADSPI_SR_FLEVEL_4 ((uint32_t)0x00001000) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 5318
Kojto 107:4f6c30876dfa 5319 /****************** Bit definition for QUADSPI_FCR register ******************/
Kojto 107:4f6c30876dfa 5320 #define QUADSPI_FCR_CTEF ((uint32_t)0x00000001) /*!< Clear Transfer Error Flag */
Kojto 107:4f6c30876dfa 5321 #define QUADSPI_FCR_CTCF ((uint32_t)0x00000002) /*!< Clear Transfer Complete Flag */
Kojto 107:4f6c30876dfa 5322 #define QUADSPI_FCR_CSMF ((uint32_t)0x00000008) /*!< Clear Status Match Flag */
Kojto 107:4f6c30876dfa 5323 #define QUADSPI_FCR_CTOF ((uint32_t)0x00000010) /*!< Clear Timeout Flag */
Kojto 107:4f6c30876dfa 5324
Kojto 107:4f6c30876dfa 5325 /****************** Bit definition for QUADSPI_DLR register ******************/
Kojto 107:4f6c30876dfa 5326 #define QUADSPI_DLR_DL ((uint32_t)0xFFFFFFFF) /*!< DL[31:0]: Data Length */
Kojto 107:4f6c30876dfa 5327
Kojto 107:4f6c30876dfa 5328 /****************** Bit definition for QUADSPI_CCR register ******************/
Kojto 107:4f6c30876dfa 5329 #define QUADSPI_CCR_INSTRUCTION ((uint32_t)0x000000FF) /*!< INSTRUCTION[7:0]: Instruction */
Kojto 107:4f6c30876dfa 5330 #define QUADSPI_CCR_INSTRUCTION_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5331 #define QUADSPI_CCR_INSTRUCTION_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5332 #define QUADSPI_CCR_INSTRUCTION_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5333 #define QUADSPI_CCR_INSTRUCTION_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5334 #define QUADSPI_CCR_INSTRUCTION_4 ((uint32_t)0x00000010) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 5335 #define QUADSPI_CCR_INSTRUCTION_5 ((uint32_t)0x00000020) /*!< Bit 5 */
Kojto 107:4f6c30876dfa 5336 #define QUADSPI_CCR_INSTRUCTION_6 ((uint32_t)0x00000040) /*!< Bit 6 */
Kojto 107:4f6c30876dfa 5337 #define QUADSPI_CCR_INSTRUCTION_7 ((uint32_t)0x00000080) /*!< Bit 7 */
Kojto 107:4f6c30876dfa 5338 #define QUADSPI_CCR_IMODE ((uint32_t)0x00000300) /*!< IMODE[1:0]: Instruction Mode */
Kojto 107:4f6c30876dfa 5339 #define QUADSPI_CCR_IMODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5340 #define QUADSPI_CCR_IMODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5341 #define QUADSPI_CCR_ADMODE ((uint32_t)0x00000C00) /*!< ADMODE[1:0]: Address Mode */
Kojto 107:4f6c30876dfa 5342 #define QUADSPI_CCR_ADMODE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5343 #define QUADSPI_CCR_ADMODE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5344 #define QUADSPI_CCR_ADSIZE ((uint32_t)0x00003000) /*!< ADSIZE[1:0]: Address Size */
Kojto 107:4f6c30876dfa 5345 #define QUADSPI_CCR_ADSIZE_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5346 #define QUADSPI_CCR_ADSIZE_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5347 #define QUADSPI_CCR_ABMODE ((uint32_t)0x0000C000) /*!< ABMODE[1:0]: Alternate Bytes Mode */
Kojto 107:4f6c30876dfa 5348 #define QUADSPI_CCR_ABMODE_0 ((uint32_t)0x00004000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5349 #define QUADSPI_CCR_ABMODE_1 ((uint32_t)0x00008000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5350 #define QUADSPI_CCR_ABSIZE ((uint32_t)0x00030000) /*!< ABSIZE[1:0]: Instruction Mode */
Kojto 107:4f6c30876dfa 5351 #define QUADSPI_CCR_ABSIZE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5352 #define QUADSPI_CCR_ABSIZE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5353 #define QUADSPI_CCR_DCYC ((uint32_t)0x007C0000) /*!< DCYC[4:0]: Dummy Cycles */
Kojto 107:4f6c30876dfa 5354 #define QUADSPI_CCR_DCYC_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5355 #define QUADSPI_CCR_DCYC_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5356 #define QUADSPI_CCR_DCYC_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5357 #define QUADSPI_CCR_DCYC_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5358 #define QUADSPI_CCR_DCYC_4 ((uint32_t)0x00400000) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 5359 #define QUADSPI_CCR_DMODE ((uint32_t)0x03000000) /*!< DMODE[1:0]: Data Mode */
Kojto 107:4f6c30876dfa 5360 #define QUADSPI_CCR_DMODE_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5361 #define QUADSPI_CCR_DMODE_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5362 #define QUADSPI_CCR_FMODE ((uint32_t)0x0C000000) /*!< FMODE[1:0]: Functional Mode */
Kojto 107:4f6c30876dfa 5363 #define QUADSPI_CCR_FMODE_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5364 #define QUADSPI_CCR_FMODE_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5365 #define QUADSPI_CCR_SIOO ((uint32_t)0x10000000) /*!< SIOO: Send Instruction Only Once Mode */
Kojto 107:4f6c30876dfa 5366 #define QUADSPI_CCR_DHHC ((uint32_t)0x40000000) /*!< DHHC: Delay Half Hclk Cycle */
Kojto 107:4f6c30876dfa 5367 #define QUADSPI_CCR_DDRM ((uint32_t)0x80000000) /*!< DDRM: Double Data Rate Mode */
Kojto 107:4f6c30876dfa 5368 /****************** Bit definition for QUADSPI_AR register *******************/
Kojto 107:4f6c30876dfa 5369 #define QUADSPI_AR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< ADDRESS[31:0]: Address */
Kojto 107:4f6c30876dfa 5370
Kojto 107:4f6c30876dfa 5371 /****************** Bit definition for QUADSPI_ABR register ******************/
Kojto 107:4f6c30876dfa 5372 #define QUADSPI_ABR_ALTERNATE ((uint32_t)0xFFFFFFFF) /*!< ALTERNATE[31:0]: Alternate Bytes */
Kojto 107:4f6c30876dfa 5373
Kojto 107:4f6c30876dfa 5374 /****************** Bit definition for QUADSPI_DR register *******************/
Kojto 107:4f6c30876dfa 5375 #define QUADSPI_DR_DATA ((uint32_t)0xFFFFFFFF) /*!< DATA[31:0]: Data */
Kojto 107:4f6c30876dfa 5376
Kojto 107:4f6c30876dfa 5377 /****************** Bit definition for QUADSPI_PSMKR register ****************/
Kojto 107:4f6c30876dfa 5378 #define QUADSPI_PSMKR_MASK ((uint32_t)0xFFFFFFFF) /*!< MASK[31:0]: Status Mask */
Kojto 107:4f6c30876dfa 5379
Kojto 107:4f6c30876dfa 5380 /****************** Bit definition for QUADSPI_PSMAR register ****************/
Kojto 107:4f6c30876dfa 5381 #define QUADSPI_PSMAR_MATCH ((uint32_t)0xFFFFFFFF) /*!< MATCH[31:0]: Status Match */
Kojto 107:4f6c30876dfa 5382
Kojto 107:4f6c30876dfa 5383 /****************** Bit definition for QUADSPI_PIR register *****************/
Kojto 107:4f6c30876dfa 5384 #define QUADSPI_PIR_INTERVAL ((uint32_t)0x0000FFFF) /*!< INTERVAL[15:0]: Polling Interval */
Kojto 107:4f6c30876dfa 5385
Kojto 107:4f6c30876dfa 5386 /****************** Bit definition for QUADSPI_LPTR register *****************/
Kojto 107:4f6c30876dfa 5387 #define QUADSPI_LPTR_TIMEOUT ((uint32_t)0x0000FFFF) /*!< TIMEOUT[15:0]: Timeout period */
Kojto 107:4f6c30876dfa 5388
Kojto 107:4f6c30876dfa 5389 /******************************************************************************/
Kojto 107:4f6c30876dfa 5390 /* */
Kojto 107:4f6c30876dfa 5391 /* Reset and Clock Control */
Kojto 107:4f6c30876dfa 5392 /* */
Kojto 107:4f6c30876dfa 5393 /******************************************************************************/
Kojto 107:4f6c30876dfa 5394 /******************** Bit definition for RCC_CR register ********************/
Kojto 107:4f6c30876dfa 5395 #define RCC_CR_HSION ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5396 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5397
Kojto 107:4f6c30876dfa 5398 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
Kojto 107:4f6c30876dfa 5399 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 5400 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 5401 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 5402 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 5403 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 5404
Kojto 107:4f6c30876dfa 5405 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
Kojto 107:4f6c30876dfa 5406 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 5407 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 5408 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 5409 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 5410 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 5411 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 5412 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 5413 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 5414
Kojto 107:4f6c30876dfa 5415 #define RCC_CR_HSEON ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5416 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5417 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5418 #define RCC_CR_CSSON ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5419 #define RCC_CR_PLLON ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5420 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5421 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5422 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5423 #define RCC_CR_PLLSAION ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5424 #define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5425
Kojto 107:4f6c30876dfa 5426 /******************** Bit definition for RCC_PLLCFGR register ***************/
Kojto 107:4f6c30876dfa 5427 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)
Kojto 107:4f6c30876dfa 5428 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5429 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5430 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5431 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5432 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5433 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5434
Kojto 107:4f6c30876dfa 5435 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)
Kojto 107:4f6c30876dfa 5436 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5437 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5438 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5439 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5440 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5441 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5442 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5443 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5444 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5445
Kojto 107:4f6c30876dfa 5446 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 5447 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5448 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5449
Kojto 107:4f6c30876dfa 5450 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5451 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5452 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 5453
Kojto 107:4f6c30876dfa 5454 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 5455 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5456 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5457 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5458 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5459
Kojto 116:c0f6e94411f5 5460
Kojto 107:4f6c30876dfa 5461 /******************** Bit definition for RCC_CFGR register ******************/
Kojto 107:4f6c30876dfa 5462 /*!< SW configuration */
Kojto 107:4f6c30876dfa 5463 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 107:4f6c30876dfa 5464 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5465 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5466
Kojto 107:4f6c30876dfa 5467 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 107:4f6c30876dfa 5468 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 107:4f6c30876dfa 5469 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 107:4f6c30876dfa 5470
Kojto 107:4f6c30876dfa 5471 /*!< SWS configuration */
Kojto 107:4f6c30876dfa 5472 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 107:4f6c30876dfa 5473 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5474 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5475
Kojto 107:4f6c30876dfa 5476 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 107:4f6c30876dfa 5477 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 107:4f6c30876dfa 5478 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 107:4f6c30876dfa 5479
Kojto 107:4f6c30876dfa 5480 /*!< HPRE configuration */
Kojto 107:4f6c30876dfa 5481 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 107:4f6c30876dfa 5482 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5483 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5484 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5485 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 5486
Kojto 107:4f6c30876dfa 5487 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 107:4f6c30876dfa 5488 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 107:4f6c30876dfa 5489 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 107:4f6c30876dfa 5490 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 107:4f6c30876dfa 5491 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 107:4f6c30876dfa 5492 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 107:4f6c30876dfa 5493 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 107:4f6c30876dfa 5494 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 107:4f6c30876dfa 5495 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 107:4f6c30876dfa 5496
Kojto 107:4f6c30876dfa 5497 /*!< PPRE1 configuration */
Kojto 107:4f6c30876dfa 5498 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 107:4f6c30876dfa 5499 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5500 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5501 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5502
Kojto 107:4f6c30876dfa 5503 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 107:4f6c30876dfa 5504 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */
Kojto 107:4f6c30876dfa 5505 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */
Kojto 107:4f6c30876dfa 5506 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */
Kojto 107:4f6c30876dfa 5507 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */
Kojto 107:4f6c30876dfa 5508
Kojto 107:4f6c30876dfa 5509 /*!< PPRE2 configuration */
Kojto 107:4f6c30876dfa 5510 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 107:4f6c30876dfa 5511 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 5512 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 5513 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 5514
Kojto 107:4f6c30876dfa 5515 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 107:4f6c30876dfa 5516 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */
Kojto 107:4f6c30876dfa 5517 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */
Kojto 107:4f6c30876dfa 5518 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */
Kojto 107:4f6c30876dfa 5519 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */
Kojto 107:4f6c30876dfa 5520
Kojto 107:4f6c30876dfa 5521 /*!< RTCPRE configuration */
Kojto 107:4f6c30876dfa 5522 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)
Kojto 107:4f6c30876dfa 5523 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5524 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5525 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5526 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5527 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5528
Kojto 107:4f6c30876dfa 5529 /*!< MCO1 configuration */
Kojto 107:4f6c30876dfa 5530 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000)
Kojto 107:4f6c30876dfa 5531 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5532 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5533
Kojto 107:4f6c30876dfa 5534 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5535
Kojto 107:4f6c30876dfa 5536 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)
Kojto 107:4f6c30876dfa 5537 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5538 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5539 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5540
Kojto 107:4f6c30876dfa 5541 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)
Kojto 107:4f6c30876dfa 5542 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5543 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5544 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5545
Kojto 107:4f6c30876dfa 5546 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)
Kojto 107:4f6c30876dfa 5547 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5548 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 5549
Kojto 107:4f6c30876dfa 5550 /******************** Bit definition for RCC_CIR register *******************/
Kojto 107:4f6c30876dfa 5551 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5552 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5553 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5554 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5555 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5556 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5557 #define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5558 #define RCC_CIR_CSSF ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5559 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5560 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5561 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5562 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5563 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5564 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5565 #define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5566 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5567 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5568 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5569 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5570 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5571 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5572 #define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5573 #define RCC_CIR_CSSC ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5574
Kojto 107:4f6c30876dfa 5575 /******************** Bit definition for RCC_AHB1RSTR register **************/
Kojto 107:4f6c30876dfa 5576 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5577 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5578 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5579 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5580 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5581 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5582 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5583 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5584 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5585 #define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5586 #define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5587 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5588 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5589 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5590 #define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5591 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5592 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5593
Kojto 107:4f6c30876dfa 5594 /******************** Bit definition for RCC_AHB2RSTR register **************/
Kojto 107:4f6c30876dfa 5595 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5596 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5597 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5598
Kojto 107:4f6c30876dfa 5599 /******************** Bit definition for RCC_AHB3RSTR register **************/
Kojto 107:4f6c30876dfa 5600
Kojto 107:4f6c30876dfa 5601 #define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5602 #define RCC_AHB3RSTR_QSPIRST ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5603
Kojto 107:4f6c30876dfa 5604 /******************** Bit definition for RCC_APB1RSTR register **************/
Kojto 107:4f6c30876dfa 5605 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5606 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5607 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5608 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5609 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5610 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5611 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5612 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5613 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5614 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5615 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5616 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5617 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 5618 #define RCC_APB1RSTR_SPDIFRXRST ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5619 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5620 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5621 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5622 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5623 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5624 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5625 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5626 #define RCC_APB1RSTR_I2C4RST ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5627 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5628 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5629 #define RCC_APB1RSTR_CECRST ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5630 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5631 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5632 #define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5633 #define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 5634
Kojto 107:4f6c30876dfa 5635 /******************** Bit definition for RCC_APB2RSTR register **************/
Kojto 107:4f6c30876dfa 5636 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5637 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5638 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5639 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5640 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5641 #define RCC_APB2RSTR_SDMMC1RST ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5642 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5643 #define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5644 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5645 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5646 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5647 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5648 #define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5649 #define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5650 #define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5651 #define RCC_APB2RSTR_SAI2RST ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5652 #define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5653
Kojto 107:4f6c30876dfa 5654 /******************** Bit definition for RCC_AHB1ENR register ***************/
Kojto 107:4f6c30876dfa 5655 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5656 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5657 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5658 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5659 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5660 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5661 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5662 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5663 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5664 #define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5665 #define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5666 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5667 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5668 #define RCC_AHB1ENR_DTCMRAMEN ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5669 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5670 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5671 #define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5672 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5673 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5674 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5675 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5676 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5677 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5678
Kojto 107:4f6c30876dfa 5679 /******************** Bit definition for RCC_AHB2ENR register ***************/
Kojto 107:4f6c30876dfa 5680 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5681 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5682 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5683
Kojto 107:4f6c30876dfa 5684 /******************** Bit definition for RCC_AHB3ENR register ***************/
Kojto 107:4f6c30876dfa 5685
Kojto 107:4f6c30876dfa 5686 #define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5687 #define RCC_AHB3ENR_QSPIEN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5688
Kojto 107:4f6c30876dfa 5689 /******************** Bit definition for RCC_APB1ENR register ***************/
Kojto 107:4f6c30876dfa 5690 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5691 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5692 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5693 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5694 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5695 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5696 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5697 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5698 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5699 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5700 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5701 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5702 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 5703 #define RCC_APB1ENR_SPDIFRXEN ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5704 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5705 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5706 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5707 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5708 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5709 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5710 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5711 #define RCC_APB1ENR_I2C4EN ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5712 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5713 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5714 #define RCC_APB1ENR_CECEN ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5715 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5716 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5717 #define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5718 #define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 5719
Kojto 107:4f6c30876dfa 5720 /******************** Bit definition for RCC_APB2ENR register ***************/
Kojto 107:4f6c30876dfa 5721 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5722 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5723 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5724 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5725 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5726 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5727 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5728 #define RCC_APB2ENR_SDMMC1EN ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5729 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5730 #define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5731 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5732 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5733 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5734 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5735 #define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5736 #define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5737 #define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5738 #define RCC_APB2ENR_SAI2EN ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5739 #define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5740
Kojto 107:4f6c30876dfa 5741 /******************** Bit definition for RCC_AHB1LPENR register *************/
Kojto 107:4f6c30876dfa 5742 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5743 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5744 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5745 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5746 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5747 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5748 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5749 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5750 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5751 #define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5752 #define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5753
Kojto 107:4f6c30876dfa 5754 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5755 #define RCC_AHB1LPENR_AXILPEN ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5756 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 5757 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5758 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5759 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5760 #define RCC_AHB1LPENR_DTCMLPEN ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5761 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5762 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5763 #define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5764 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5765 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5766 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5767 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5768 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5769 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5770
Kojto 107:4f6c30876dfa 5771 /******************** Bit definition for RCC_AHB2LPENR register *************/
Kojto 107:4f6c30876dfa 5772 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5773 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5774 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5775
Kojto 107:4f6c30876dfa 5776 /******************** Bit definition for RCC_AHB3LPENR register *************/
Kojto 107:4f6c30876dfa 5777 #define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5778 #define RCC_AHB3LPENR_QSPILPEN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5779 /******************** Bit definition for RCC_APB1LPENR register *************/
Kojto 107:4f6c30876dfa 5780 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5781 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5782 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5783 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5784 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5785 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5786 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5787 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5788 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5789 #define RCC_APB1LPENR_LPTIM1LPEN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5790 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5791 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5792 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 5793 #define RCC_APB1LPENR_SPDIFRXLPEN ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5794 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5795 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5796 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5797 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5798 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5799 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5800 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5801 #define RCC_APB1LPENR_I2C4LPEN ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5802 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5803 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5804 #define RCC_APB1LPENR_CECLPEN ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5805 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5806 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5807 #define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5808 #define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 5809
Kojto 107:4f6c30876dfa 5810 /******************** Bit definition for RCC_APB2LPENR register *************/
Kojto 107:4f6c30876dfa 5811 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5812 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5813 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5814 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5815 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5816 #define RCC_APB2LPENR_ADC2LPEN ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5817 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5818 #define RCC_APB2LPENR_SDMMC1LPEN ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5819 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5820 #define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5821 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5822 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5823 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5824 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5825 #define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5826 #define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5827 #define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5828 #define RCC_APB2LPENR_SAI2LPEN ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5829 #define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5830
Kojto 107:4f6c30876dfa 5831 /******************** Bit definition for RCC_BDCR register ******************/
Kojto 107:4f6c30876dfa 5832 #define RCC_BDCR_LSEON ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5833 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5834 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5835 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018)
Kojto 107:4f6c30876dfa 5836 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5837 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5838 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)
Kojto 107:4f6c30876dfa 5839 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5840 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5841 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 5842 #define RCC_BDCR_BDRST ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5843
Kojto 107:4f6c30876dfa 5844 /******************** Bit definition for RCC_CSR register *******************/
Kojto 107:4f6c30876dfa 5845 #define RCC_CSR_LSION ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5846 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5847 #define RCC_CSR_RMVF ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5848 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5849 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5850 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5851 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5852 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5853 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5854 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 5855
Kojto 107:4f6c30876dfa 5856 /******************** Bit definition for RCC_SSCGR register *****************/
Kojto 107:4f6c30876dfa 5857 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)
Kojto 107:4f6c30876dfa 5858 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)
Kojto 107:4f6c30876dfa 5859 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5860 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 5861
Kojto 107:4f6c30876dfa 5862 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
Kojto 107:4f6c30876dfa 5863 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)
Kojto 107:4f6c30876dfa 5864 #define RCC_PLLI2SCFGR_PLLI2SN_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5865 #define RCC_PLLI2SCFGR_PLLI2SN_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5866 #define RCC_PLLI2SCFGR_PLLI2SN_2 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5867 #define RCC_PLLI2SCFGR_PLLI2SN_3 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5868 #define RCC_PLLI2SCFGR_PLLI2SN_4 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5869 #define RCC_PLLI2SCFGR_PLLI2SN_5 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5870 #define RCC_PLLI2SCFGR_PLLI2SN_6 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5871 #define RCC_PLLI2SCFGR_PLLI2SN_7 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5872 #define RCC_PLLI2SCFGR_PLLI2SN_8 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5873
Kojto 107:4f6c30876dfa 5874 #define RCC_PLLI2SCFGR_PLLI2SP ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 5875 #define RCC_PLLI2SCFGR_PLLI2SP_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5876 #define RCC_PLLI2SCFGR_PLLI2SP_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5877
Kojto 107:4f6c30876dfa 5878 #define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 5879 #define RCC_PLLI2SCFGR_PLLI2SQ_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5880 #define RCC_PLLI2SCFGR_PLLI2SQ_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5881 #define RCC_PLLI2SCFGR_PLLI2SQ_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5882 #define RCC_PLLI2SCFGR_PLLI2SQ_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5883
Kojto 107:4f6c30876dfa 5884 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)
Kojto 107:4f6c30876dfa 5885 #define RCC_PLLI2SCFGR_PLLI2SR_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5886 #define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5887 #define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5888
Kojto 107:4f6c30876dfa 5889 /******************** Bit definition for RCC_PLLSAICFGR register ************/
Kojto 107:4f6c30876dfa 5890 #define RCC_PLLSAICFGR_PLLSAIN ((uint32_t)0x00007FC0)
Kojto 107:4f6c30876dfa 5891 #define RCC_PLLSAICFGR_PLLSAIN_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5892 #define RCC_PLLSAICFGR_PLLSAIN_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5893 #define RCC_PLLSAICFGR_PLLSAIN_2 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5894 #define RCC_PLLSAICFGR_PLLSAIN_3 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5895 #define RCC_PLLSAICFGR_PLLSAIN_4 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5896 #define RCC_PLLSAICFGR_PLLSAIN_5 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5897 #define RCC_PLLSAICFGR_PLLSAIN_6 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5898 #define RCC_PLLSAICFGR_PLLSAIN_7 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5899 #define RCC_PLLSAICFGR_PLLSAIN_8 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5900
Kojto 107:4f6c30876dfa 5901 #define RCC_PLLSAICFGR_PLLSAIP ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 5902 #define RCC_PLLSAICFGR_PLLSAIP_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5903 #define RCC_PLLSAICFGR_PLLSAIP_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5904
Kojto 107:4f6c30876dfa 5905 #define RCC_PLLSAICFGR_PLLSAIQ ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 5906 #define RCC_PLLSAICFGR_PLLSAIQ_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5907 #define RCC_PLLSAICFGR_PLLSAIQ_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5908 #define RCC_PLLSAICFGR_PLLSAIQ_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5909 #define RCC_PLLSAICFGR_PLLSAIQ_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5910
Kojto 107:4f6c30876dfa 5911 #define RCC_PLLSAICFGR_PLLSAIR ((uint32_t)0x70000000)
Kojto 107:4f6c30876dfa 5912 #define RCC_PLLSAICFGR_PLLSAIR_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5913 #define RCC_PLLSAICFGR_PLLSAIR_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 5914 #define RCC_PLLSAICFGR_PLLSAIR_2 ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 5915
Kojto 107:4f6c30876dfa 5916 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
Kojto 107:4f6c30876dfa 5917 #define RCC_DCKCFGR1_PLLI2SDIVQ ((uint32_t)0x0000001F)
Kojto 107:4f6c30876dfa 5918 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5919 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5920 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5921 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5922 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5923
Kojto 107:4f6c30876dfa 5924 #define RCC_DCKCFGR1_PLLSAIDIVQ ((uint32_t)0x00001F00)
Kojto 107:4f6c30876dfa 5925 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5926 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5927 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5928 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5929 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5930
Kojto 107:4f6c30876dfa 5931 #define RCC_DCKCFGR1_PLLSAIDIVR ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 5932 #define RCC_DCKCFGR1_PLLSAIDIVR_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5933 #define RCC_DCKCFGR1_PLLSAIDIVR_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5934
Kojto 107:4f6c30876dfa 5935 #define RCC_DCKCFGR1_SAI1SEL ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 5936 #define RCC_DCKCFGR1_SAI1SEL_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5937 #define RCC_DCKCFGR1_SAI1SEL_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5938
Kojto 107:4f6c30876dfa 5939 #define RCC_DCKCFGR1_SAI2SEL ((uint32_t)0x00C00000)
Kojto 107:4f6c30876dfa 5940 #define RCC_DCKCFGR1_SAI2SEL_0 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5941 #define RCC_DCKCFGR1_SAI2SEL_1 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5942
Kojto 107:4f6c30876dfa 5943 #define RCC_DCKCFGR1_TIMPRE ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5944
Kojto 107:4f6c30876dfa 5945 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
Kojto 107:4f6c30876dfa 5946 #define RCC_DCKCFGR2_USART1SEL ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 5947 #define RCC_DCKCFGR2_USART1SEL_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 5948 #define RCC_DCKCFGR2_USART1SEL_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 5949 #define RCC_DCKCFGR2_USART2SEL ((uint32_t)0x0000000C)
Kojto 107:4f6c30876dfa 5950 #define RCC_DCKCFGR2_USART2SEL_0 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5951 #define RCC_DCKCFGR2_USART2SEL_1 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5952 #define RCC_DCKCFGR2_USART3SEL ((uint32_t)0x00000030)
Kojto 107:4f6c30876dfa 5953 #define RCC_DCKCFGR2_USART3SEL_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 5954 #define RCC_DCKCFGR2_USART3SEL_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 5955 #define RCC_DCKCFGR2_UART4SEL ((uint32_t)0x000000C0)
Kojto 107:4f6c30876dfa 5956 #define RCC_DCKCFGR2_UART4SEL_0 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 5957 #define RCC_DCKCFGR2_UART4SEL_1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 5958 #define RCC_DCKCFGR2_UART5SEL ((uint32_t)0x00000300)
Kojto 107:4f6c30876dfa 5959 #define RCC_DCKCFGR2_UART5SEL_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 5960 #define RCC_DCKCFGR2_UART5SEL_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 5961 #define RCC_DCKCFGR2_USART6SEL ((uint32_t)0x00000C00)
Kojto 107:4f6c30876dfa 5962 #define RCC_DCKCFGR2_USART6SEL_0 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 5963 #define RCC_DCKCFGR2_USART6SEL_1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 5964 #define RCC_DCKCFGR2_UART7SEL ((uint32_t)0x00003000)
Kojto 107:4f6c30876dfa 5965 #define RCC_DCKCFGR2_UART7SEL_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 5966 #define RCC_DCKCFGR2_UART7SEL_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 5967 #define RCC_DCKCFGR2_UART8SEL ((uint32_t)0x0000C000)
Kojto 107:4f6c30876dfa 5968 #define RCC_DCKCFGR2_UART8SEL_0 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 5969 #define RCC_DCKCFGR2_UART8SEL_1 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 5970 #define RCC_DCKCFGR2_I2C1SEL ((uint32_t)0x00030000)
Kojto 107:4f6c30876dfa 5971 #define RCC_DCKCFGR2_I2C1SEL_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 5972 #define RCC_DCKCFGR2_I2C1SEL_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 5973 #define RCC_DCKCFGR2_I2C2SEL ((uint32_t)0x000C0000)
Kojto 107:4f6c30876dfa 5974 #define RCC_DCKCFGR2_I2C2SEL_0 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 5975 #define RCC_DCKCFGR2_I2C2SEL_1 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 5976 #define RCC_DCKCFGR2_I2C3SEL ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 5977 #define RCC_DCKCFGR2_I2C3SEL_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 5978 #define RCC_DCKCFGR2_I2C3SEL_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 5979 #define RCC_DCKCFGR2_I2C4SEL ((uint32_t)0x00C00000)
Kojto 107:4f6c30876dfa 5980 #define RCC_DCKCFGR2_I2C4SEL_0 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 5981 #define RCC_DCKCFGR2_I2C4SEL_1 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 5982 #define RCC_DCKCFGR2_LPTIM1SEL ((uint32_t)0x03000000)
Kojto 107:4f6c30876dfa 5983 #define RCC_DCKCFGR2_LPTIM1SEL_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 5984 #define RCC_DCKCFGR2_LPTIM1SEL_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 5985 #define RCC_DCKCFGR2_CECSEL ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 5986 #define RCC_DCKCFGR2_CK48MSEL ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 5987 #define RCC_DCKCFGR2_SDMMC1SEL ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 5988
Kojto 107:4f6c30876dfa 5989 /******************************************************************************/
Kojto 107:4f6c30876dfa 5990 /* */
Kojto 107:4f6c30876dfa 5991 /* RNG */
Kojto 107:4f6c30876dfa 5992 /* */
Kojto 107:4f6c30876dfa 5993 /******************************************************************************/
Kojto 107:4f6c30876dfa 5994 /******************** Bits definition for RNG_CR register *******************/
Kojto 107:4f6c30876dfa 5995 #define RNG_CR_RNGEN ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 5996 #define RNG_CR_IE ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 5997
Kojto 107:4f6c30876dfa 5998 /******************** Bits definition for RNG_SR register *******************/
Kojto 107:4f6c30876dfa 5999 #define RNG_SR_DRDY ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6000 #define RNG_SR_CECS ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6001 #define RNG_SR_SECS ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6002 #define RNG_SR_CEIS ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6003 #define RNG_SR_SEIS ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6004
Kojto 107:4f6c30876dfa 6005 /******************************************************************************/
Kojto 107:4f6c30876dfa 6006 /* */
Kojto 107:4f6c30876dfa 6007 /* Real-Time Clock (RTC) */
Kojto 107:4f6c30876dfa 6008 /* */
Kojto 107:4f6c30876dfa 6009 /******************************************************************************/
Kojto 107:4f6c30876dfa 6010 /******************** Bits definition for RTC_TR register *******************/
Kojto 107:4f6c30876dfa 6011 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6012 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 6013 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6014 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6015 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 107:4f6c30876dfa 6016 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6017 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6018 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6019 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6020 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 107:4f6c30876dfa 6021 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6022 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6023 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6024 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 107:4f6c30876dfa 6025 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6026 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6027 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6028 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6029 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 107:4f6c30876dfa 6030 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6031 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6032 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6033 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 6034 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6035 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6036 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6037 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6038
Kojto 107:4f6c30876dfa 6039 /******************** Bits definition for RTC_DR register *******************/
Kojto 107:4f6c30876dfa 6040 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 107:4f6c30876dfa 6041 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6042 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6043 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6044 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 6045 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 107:4f6c30876dfa 6046 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6047 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6048 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6049 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6050 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 107:4f6c30876dfa 6051 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6052 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6053 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6054 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6055 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 107:4f6c30876dfa 6056 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6057 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6058 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6059 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6060 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 107:4f6c30876dfa 6061 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6062 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6063 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 6064 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6065 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6066 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6067 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6068
Kojto 107:4f6c30876dfa 6069 /******************** Bits definition for RTC_CR register *******************/
Kojto 107:4f6c30876dfa 6070 #define RTC_CR_ITSE ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 6071 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 6072 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 107:4f6c30876dfa 6073 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6074 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6075 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6076 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6077 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6078 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6079 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6080 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6081 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6082 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6083 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6084 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6085 #define RTC_CR_WUTE ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6086 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6087 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6088 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6089 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6090 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6091 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6092 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
Kojto 107:4f6c30876dfa 6093 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6094 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6095 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6096
Kojto 107:4f6c30876dfa 6097 /******************** Bits definition for RTC_ISR register ******************/
Kojto 107:4f6c30876dfa 6098 #define RTC_ISR_ITSF ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6099 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6100 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6101 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6102 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6103 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6104 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6105 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6106 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6107 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6108 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 6109 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6110 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6111 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6112 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6113 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6114 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6115 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6116
Kojto 107:4f6c30876dfa 6117 /******************** Bits definition for RTC_PRER register *****************/
Kojto 107:4f6c30876dfa 6118 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 107:4f6c30876dfa 6119 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 107:4f6c30876dfa 6120
Kojto 107:4f6c30876dfa 6121 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 107:4f6c30876dfa 6122 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
Kojto 107:4f6c30876dfa 6123
Kojto 107:4f6c30876dfa 6124 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 107:4f6c30876dfa 6125 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 6126 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 6127 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 107:4f6c30876dfa 6128 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 6129 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 6130 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 6131 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 6132 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 6133 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 6134 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 6135 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 6136 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6137 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 6138 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6139 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6140 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 107:4f6c30876dfa 6141 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6142 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6143 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6144 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6145 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6146 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 107:4f6c30876dfa 6147 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6148 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6149 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6150 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 107:4f6c30876dfa 6151 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6152 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6153 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6154 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6155 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 6156 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 107:4f6c30876dfa 6157 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6158 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6159 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6160 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 6161 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6162 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6163 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6164 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6165
Kojto 107:4f6c30876dfa 6166 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 107:4f6c30876dfa 6167 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 6168 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
Kojto 107:4f6c30876dfa 6169 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
Kojto 107:4f6c30876dfa 6170 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
Kojto 107:4f6c30876dfa 6171 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
Kojto 107:4f6c30876dfa 6172 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 6173 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 6174 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 6175 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 6176 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 6177 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 6178 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6179 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 6180 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6181 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6182 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
Kojto 107:4f6c30876dfa 6183 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6184 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6185 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6186 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6187 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6188 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
Kojto 107:4f6c30876dfa 6189 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6190 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6191 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6192 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
Kojto 107:4f6c30876dfa 6193 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6194 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6195 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6196 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6197 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 6198 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
Kojto 107:4f6c30876dfa 6199 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6200 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6201 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6202 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 6203 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6204 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6205 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6206 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6207
Kojto 107:4f6c30876dfa 6208 /******************** Bits definition for RTC_WPR register ******************/
Kojto 107:4f6c30876dfa 6209 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 107:4f6c30876dfa 6210
Kojto 107:4f6c30876dfa 6211 /******************** Bits definition for RTC_SSR register ******************/
Kojto 107:4f6c30876dfa 6212 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 107:4f6c30876dfa 6213
Kojto 107:4f6c30876dfa 6214 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 107:4f6c30876dfa 6215 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 107:4f6c30876dfa 6216 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 107:4f6c30876dfa 6217
Kojto 107:4f6c30876dfa 6218 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 107:4f6c30876dfa 6219 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6220 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 107:4f6c30876dfa 6221 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6222 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6223 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 107:4f6c30876dfa 6224 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6225 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6226 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6227 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6228 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 107:4f6c30876dfa 6229 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6230 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6231 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6232 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 107:4f6c30876dfa 6233 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6234 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6235 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6236 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6237 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 107:4f6c30876dfa 6238 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6239 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6240 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6241 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 6242 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6243 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6244 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6245 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6246
Kojto 107:4f6c30876dfa 6247 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 107:4f6c30876dfa 6248 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 107:4f6c30876dfa 6249 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6250 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6251 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6252 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6253 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 107:4f6c30876dfa 6254 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6255 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6256 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6257 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6258 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 107:4f6c30876dfa 6259 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6260 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6261 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 107:4f6c30876dfa 6262 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6263 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6264 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6265 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6266
Kojto 107:4f6c30876dfa 6267 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 107:4f6c30876dfa 6268 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 107:4f6c30876dfa 6269
Kojto 107:4f6c30876dfa 6270 /******************** Bits definition for RTC_CAL register *****************/
Kojto 107:4f6c30876dfa 6271 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6272 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6273 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6274 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 107:4f6c30876dfa 6275 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6276 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6277 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6278 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6279 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6280 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6281 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6282 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 6283 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6284
Kojto 107:4f6c30876dfa 6285 /******************** Bits definition for RTC_TAMPCR register ****************/
Kojto 107:4f6c30876dfa 6286 #define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 6287 #define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 6288 #define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 6289 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 6290 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 6291 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 6292 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 6293 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 6294 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 6295 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 6296 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 107:4f6c30876dfa 6297 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 6298 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 6299 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 107:4f6c30876dfa 6300 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6301 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 6302 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 107:4f6c30876dfa 6303 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 6304 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 6305 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6306 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 6307 #define RTC_TAMPCR_TAMP3_TRG ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 6308 #define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6309 #define RTC_TAMPCR_TAMP2_TRG ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 6310 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6311 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6312 #define RTC_TAMPCR_TAMP1_TRG ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6313 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 6314
Kojto 107:4f6c30876dfa 6315 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 107:4f6c30876dfa 6316 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 6317 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 6318 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 6319 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 6320 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 6321 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 107:4f6c30876dfa 6322
Kojto 107:4f6c30876dfa 6323 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 107:4f6c30876dfa 6324 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
Kojto 107:4f6c30876dfa 6325 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 6326 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 6327 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 6328 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 107:4f6c30876dfa 6329 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
Kojto 107:4f6c30876dfa 6330
Kojto 107:4f6c30876dfa 6331 /******************** Bits definition for RTC_OR register ****************/
Kojto 107:4f6c30876dfa 6332 #define RTC_OR_TSINSEL ((uint32_t)0x00000006)
Kojto 107:4f6c30876dfa 6333 #define RTC_OR_TSINSEL_0 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 6334 #define RTC_OR_TSINSEL_1 ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 6335 #define RTC_OR_ALARMTYPE ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 6336
Kojto 107:4f6c30876dfa 6337
Kojto 107:4f6c30876dfa 6338 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 107:4f6c30876dfa 6339 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6340
Kojto 107:4f6c30876dfa 6341 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 107:4f6c30876dfa 6342 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6343
Kojto 107:4f6c30876dfa 6344 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 107:4f6c30876dfa 6345 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6346
Kojto 107:4f6c30876dfa 6347 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 107:4f6c30876dfa 6348 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6349
Kojto 107:4f6c30876dfa 6350 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 107:4f6c30876dfa 6351 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6352
Kojto 107:4f6c30876dfa 6353 /******************** Bits definition for RTC_BKP5R register ****************/
Kojto 107:4f6c30876dfa 6354 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6355
Kojto 107:4f6c30876dfa 6356 /******************** Bits definition for RTC_BKP6R register ****************/
Kojto 107:4f6c30876dfa 6357 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6358
Kojto 107:4f6c30876dfa 6359 /******************** Bits definition for RTC_BKP7R register ****************/
Kojto 107:4f6c30876dfa 6360 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6361
Kojto 107:4f6c30876dfa 6362 /******************** Bits definition for RTC_BKP8R register ****************/
Kojto 107:4f6c30876dfa 6363 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6364
Kojto 107:4f6c30876dfa 6365 /******************** Bits definition for RTC_BKP9R register ****************/
Kojto 107:4f6c30876dfa 6366 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6367
Kojto 107:4f6c30876dfa 6368 /******************** Bits definition for RTC_BKP10R register ***************/
Kojto 107:4f6c30876dfa 6369 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6370
Kojto 107:4f6c30876dfa 6371 /******************** Bits definition for RTC_BKP11R register ***************/
Kojto 107:4f6c30876dfa 6372 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6373
Kojto 107:4f6c30876dfa 6374 /******************** Bits definition for RTC_BKP12R register ***************/
Kojto 107:4f6c30876dfa 6375 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6376
Kojto 107:4f6c30876dfa 6377 /******************** Bits definition for RTC_BKP13R register ***************/
Kojto 107:4f6c30876dfa 6378 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6379
Kojto 107:4f6c30876dfa 6380 /******************** Bits definition for RTC_BKP14R register ***************/
Kojto 107:4f6c30876dfa 6381 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6382
Kojto 107:4f6c30876dfa 6383 /******************** Bits definition for RTC_BKP15R register ***************/
Kojto 107:4f6c30876dfa 6384 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6385
Kojto 107:4f6c30876dfa 6386 /******************** Bits definition for RTC_BKP16R register ***************/
Kojto 107:4f6c30876dfa 6387 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6388
Kojto 107:4f6c30876dfa 6389 /******************** Bits definition for RTC_BKP17R register ***************/
Kojto 107:4f6c30876dfa 6390 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6391
Kojto 107:4f6c30876dfa 6392 /******************** Bits definition for RTC_BKP18R register ***************/
Kojto 107:4f6c30876dfa 6393 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6394
Kojto 107:4f6c30876dfa 6395 /******************** Bits definition for RTC_BKP19R register ***************/
Kojto 107:4f6c30876dfa 6396 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6397
Kojto 107:4f6c30876dfa 6398 /******************** Bits definition for RTC_BKP20R register ***************/
Kojto 107:4f6c30876dfa 6399 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6400
Kojto 107:4f6c30876dfa 6401 /******************** Bits definition for RTC_BKP21R register ***************/
Kojto 107:4f6c30876dfa 6402 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6403
Kojto 107:4f6c30876dfa 6404 /******************** Bits definition for RTC_BKP22R register ***************/
Kojto 107:4f6c30876dfa 6405 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6406
Kojto 107:4f6c30876dfa 6407 /******************** Bits definition for RTC_BKP23R register ***************/
Kojto 107:4f6c30876dfa 6408 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6409
Kojto 107:4f6c30876dfa 6410 /******************** Bits definition for RTC_BKP24R register ***************/
Kojto 107:4f6c30876dfa 6411 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6412
Kojto 107:4f6c30876dfa 6413 /******************** Bits definition for RTC_BKP25R register ***************/
Kojto 107:4f6c30876dfa 6414 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6415
Kojto 107:4f6c30876dfa 6416 /******************** Bits definition for RTC_BKP26R register ***************/
Kojto 107:4f6c30876dfa 6417 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6418
Kojto 107:4f6c30876dfa 6419 /******************** Bits definition for RTC_BKP27R register ***************/
Kojto 107:4f6c30876dfa 6420 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6421
Kojto 107:4f6c30876dfa 6422 /******************** Bits definition for RTC_BKP28R register ***************/
Kojto 107:4f6c30876dfa 6423 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6424
Kojto 107:4f6c30876dfa 6425 /******************** Bits definition for RTC_BKP29R register ***************/
Kojto 107:4f6c30876dfa 6426 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6427
Kojto 107:4f6c30876dfa 6428 /******************** Bits definition for RTC_BKP30R register ***************/
Kojto 107:4f6c30876dfa 6429 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6430
Kojto 107:4f6c30876dfa 6431 /******************** Bits definition for RTC_BKP31R register ***************/
Kojto 107:4f6c30876dfa 6432 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6433
Kojto 107:4f6c30876dfa 6434 /******************** Number of backup registers ******************************/
Kojto 107:4f6c30876dfa 6435 #define RTC_BKP_NUMBER ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 6436
Kojto 107:4f6c30876dfa 6437
Kojto 107:4f6c30876dfa 6438 /******************************************************************************/
Kojto 107:4f6c30876dfa 6439 /* */
Kojto 107:4f6c30876dfa 6440 /* Serial Audio Interface */
Kojto 107:4f6c30876dfa 6441 /* */
Kojto 107:4f6c30876dfa 6442 /******************************************************************************/
Kojto 107:4f6c30876dfa 6443 /******************** Bit definition for SAI_GCR register *******************/
Kojto 107:4f6c30876dfa 6444 #define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
Kojto 107:4f6c30876dfa 6445 #define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6446 #define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6447
Kojto 107:4f6c30876dfa 6448 #define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
Kojto 107:4f6c30876dfa 6449 #define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6450 #define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6451
Kojto 107:4f6c30876dfa 6452 /******************* Bit definition for SAI_xCR1 register *******************/
Kojto 107:4f6c30876dfa 6453 #define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */
Kojto 107:4f6c30876dfa 6454 #define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6455 #define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6456
Kojto 107:4f6c30876dfa 6457 #define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */
Kojto 107:4f6c30876dfa 6458 #define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6459 #define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6460
Kojto 107:4f6c30876dfa 6461 #define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */
Kojto 107:4f6c30876dfa 6462 #define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6463 #define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6464 #define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6465
Kojto 107:4f6c30876dfa 6466 #define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */
Kojto 107:4f6c30876dfa 6467 #define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */
Kojto 107:4f6c30876dfa 6468
Kojto 107:4f6c30876dfa 6469 #define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */
Kojto 107:4f6c30876dfa 6470 #define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6471 #define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6472
Kojto 107:4f6c30876dfa 6473 #define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */
Kojto 107:4f6c30876dfa 6474 #define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */
Kojto 107:4f6c30876dfa 6475 #define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */
Kojto 107:4f6c30876dfa 6476 #define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */
Kojto 107:4f6c30876dfa 6477 #define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */
Kojto 107:4f6c30876dfa 6478
Kojto 107:4f6c30876dfa 6479 #define SAI_xCR1_MCKDIV ((uint32_t)0x00F00000) /*!<MCKDIV[3:0] (Master ClocK Divider) */
Kojto 107:4f6c30876dfa 6480 #define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6481 #define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6482 #define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6483 #define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6484
Kojto 107:4f6c30876dfa 6485 /******************* Bit definition for SAI_xCR2 register *******************/
Kojto 107:4f6c30876dfa 6486 #define SAI_xCR2_FTH ((uint32_t)0x00000007) /*!<FTH[2:0](Fifo THreshold) */
Kojto 107:4f6c30876dfa 6487 #define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6488 #define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6489 #define SAI_xCR2_FTH_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6490
Kojto 107:4f6c30876dfa 6491 #define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */
Kojto 107:4f6c30876dfa 6492 #define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */
Kojto 107:4f6c30876dfa 6493 #define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */
Kojto 107:4f6c30876dfa 6494 #define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */
Kojto 107:4f6c30876dfa 6495
Kojto 107:4f6c30876dfa 6496 #define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */
Kojto 107:4f6c30876dfa 6497 #define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6498 #define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6499 #define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6500 #define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6501 #define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 6502 #define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 6503
Kojto 116:c0f6e94411f5 6504 #define SAI_xCR2_CPL ((uint32_t)0x00002000) /*!< Complement Bit */
Kojto 107:4f6c30876dfa 6505
Kojto 107:4f6c30876dfa 6506 #define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */
Kojto 107:4f6c30876dfa 6507 #define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6508 #define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6509
Kojto 107:4f6c30876dfa 6510 /****************** Bit definition for SAI_xFRCR register *******************/
Kojto 107:4f6c30876dfa 6511 #define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */
Kojto 107:4f6c30876dfa 6512 #define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6513 #define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6514 #define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6515 #define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6516 #define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 6517 #define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 6518 #define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 6519 #define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 6520
Kojto 107:4f6c30876dfa 6521 #define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */
Kojto 107:4f6c30876dfa 6522 #define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6523 #define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6524 #define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6525 #define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6526 #define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 6527 #define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 6528 #define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 6529
Kojto 107:4f6c30876dfa 6530 #define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */
Kojto 107:4f6c30876dfa 6531 #define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */
Kojto 107:4f6c30876dfa 6532 #define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */
Kojto 107:4f6c30876dfa 6533
Kojto 107:4f6c30876dfa 6534 /****************** Bit definition for SAI_xSLOTR register *******************/
Kojto 107:4f6c30876dfa 6535 #define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */
Kojto 107:4f6c30876dfa 6536 #define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6537 #define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6538 #define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6539 #define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6540 #define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 6541
Kojto 107:4f6c30876dfa 6542 #define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */
Kojto 107:4f6c30876dfa 6543 #define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6544 #define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6545
Kojto 107:4f6c30876dfa 6546 #define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
Kojto 107:4f6c30876dfa 6547 #define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6548 #define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6549 #define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6550 #define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6551
Kojto 107:4f6c30876dfa 6552 #define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */
Kojto 107:4f6c30876dfa 6553
Kojto 107:4f6c30876dfa 6554 /******************* Bit definition for SAI_xIMR register *******************/
Kojto 107:4f6c30876dfa 6555 #define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */
Kojto 107:4f6c30876dfa 6556 #define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */
Kojto 107:4f6c30876dfa 6557 #define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */
Kojto 107:4f6c30876dfa 6558 #define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */
Kojto 107:4f6c30876dfa 6559 #define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */
Kojto 107:4f6c30876dfa 6560 #define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */
Kojto 107:4f6c30876dfa 6561 #define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */
Kojto 107:4f6c30876dfa 6562
Kojto 107:4f6c30876dfa 6563 /******************** Bit definition for SAI_xSR register *******************/
Kojto 107:4f6c30876dfa 6564 #define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */
Kojto 107:4f6c30876dfa 6565 #define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */
Kojto 107:4f6c30876dfa 6566 #define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */
Kojto 107:4f6c30876dfa 6567 #define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */
Kojto 107:4f6c30876dfa 6568 #define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */
Kojto 107:4f6c30876dfa 6569 #define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */
Kojto 107:4f6c30876dfa 6570 #define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */
Kojto 107:4f6c30876dfa 6571
Kojto 107:4f6c30876dfa 6572 #define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */
Kojto 107:4f6c30876dfa 6573 #define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6574 #define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6575 #define SAI_xSR_FLVL_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6576
Kojto 107:4f6c30876dfa 6577 /****************** Bit definition for SAI_xCLRFR register ******************/
Kojto 107:4f6c30876dfa 6578 #define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */
Kojto 107:4f6c30876dfa 6579 #define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */
Kojto 107:4f6c30876dfa 6580 #define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */
Kojto 107:4f6c30876dfa 6581 #define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */
Kojto 107:4f6c30876dfa 6582 #define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */
Kojto 107:4f6c30876dfa 6583 #define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */
Kojto 107:4f6c30876dfa 6584 #define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */
Kojto 107:4f6c30876dfa 6585
Kojto 107:4f6c30876dfa 6586 /****************** Bit definition for SAI_xDR register *********************/
Kojto 107:4f6c30876dfa 6587 #define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF)
Kojto 107:4f6c30876dfa 6588
Kojto 107:4f6c30876dfa 6589 /******************************************************************************/
Kojto 107:4f6c30876dfa 6590 /* */
Kojto 107:4f6c30876dfa 6591 /* SPDIF-RX Interface */
Kojto 107:4f6c30876dfa 6592 /* */
Kojto 107:4f6c30876dfa 6593 /******************************************************************************/
Kojto 107:4f6c30876dfa 6594 /******************** Bit definition for SPDIF_CR register *******************/
Kojto 107:4f6c30876dfa 6595 #define SPDIFRX_CR_SPDIFEN ((uint32_t)0x00000003) /*!<Peripheral Block Enable */
Kojto 107:4f6c30876dfa 6596 #define SPDIFRX_CR_RXDMAEN ((uint32_t)0x00000004) /*!<Receiver DMA Enable for data flow */
Kojto 107:4f6c30876dfa 6597 #define SPDIFRX_CR_RXSTEO ((uint32_t)0x00000008) /*!<Stereo Mode */
Kojto 107:4f6c30876dfa 6598 #define SPDIFRX_CR_DRFMT ((uint32_t)0x00000030) /*!<RX Data format */
Kojto 107:4f6c30876dfa 6599 #define SPDIFRX_CR_PMSK ((uint32_t)0x00000040) /*!<Mask Parity error bit */
Kojto 107:4f6c30876dfa 6600 #define SPDIFRX_CR_VMSK ((uint32_t)0x00000080) /*!<Mask of Validity bit */
Kojto 107:4f6c30876dfa 6601 #define SPDIFRX_CR_CUMSK ((uint32_t)0x00000100) /*!<Mask of channel status and user bits */
Kojto 107:4f6c30876dfa 6602 #define SPDIFRX_CR_PTMSK ((uint32_t)0x00000200) /*!<Mask of Preamble Type bits */
Kojto 107:4f6c30876dfa 6603 #define SPDIFRX_CR_CBDMAEN ((uint32_t)0x00000400) /*!<Control Buffer DMA ENable for control flow */
Kojto 107:4f6c30876dfa 6604 #define SPDIFRX_CR_CHSEL ((uint32_t)0x00000800) /*!<Channel Selection */
Kojto 107:4f6c30876dfa 6605 #define SPDIFRX_CR_NBTR ((uint32_t)0x00003000) /*!<Maximum allowed re-tries during synchronization phase */
Kojto 107:4f6c30876dfa 6606 #define SPDIFRX_CR_WFA ((uint32_t)0x00004000) /*!<Wait For Activity */
Kojto 107:4f6c30876dfa 6607 #define SPDIFRX_CR_INSEL ((uint32_t)0x00070000) /*!<SPDIF input selection */
Kojto 107:4f6c30876dfa 6608
Kojto 107:4f6c30876dfa 6609 /******************* Bit definition for SPDIFRX_IMR register *******************/
Kojto 107:4f6c30876dfa 6610 #define SPDIFRX_IMR_RXNEIE ((uint32_t)0x00000001) /*!<RXNE interrupt enable */
Kojto 107:4f6c30876dfa 6611 #define SPDIFRX_IMR_CSRNEIE ((uint32_t)0x00000002) /*!<Control Buffer Ready Interrupt Enable */
Kojto 107:4f6c30876dfa 6612 #define SPDIFRX_IMR_PERRIE ((uint32_t)0x00000004) /*!<Parity error interrupt enable */
Kojto 107:4f6c30876dfa 6613 #define SPDIFRX_IMR_OVRIE ((uint32_t)0x00000008) /*!<Overrun error Interrupt Enable */
Kojto 107:4f6c30876dfa 6614 #define SPDIFRX_IMR_SBLKIE ((uint32_t)0x00000010) /*!<Synchronization Block Detected Interrupt Enable */
Kojto 107:4f6c30876dfa 6615 #define SPDIFRX_IMR_SYNCDIE ((uint32_t)0x00000020) /*!<Synchronization Done */
Kojto 107:4f6c30876dfa 6616 #define SPDIFRX_IMR_IFEIE ((uint32_t)0x00000040) /*!<Serial Interface Error Interrupt Enable */
Kojto 107:4f6c30876dfa 6617
Kojto 107:4f6c30876dfa 6618 /******************* Bit definition for SPDIFRX_SR register *******************/
Kojto 107:4f6c30876dfa 6619 #define SPDIFRX_SR_RXNE ((uint32_t)0x00000001) /*!<Read data register not empty */
Kojto 107:4f6c30876dfa 6620 #define SPDIFRX_SR_CSRNE ((uint32_t)0x00000002) /*!<The Control Buffer register is not empty */
Kojto 107:4f6c30876dfa 6621 #define SPDIFRX_SR_PERR ((uint32_t)0x00000004) /*!<Parity error */
Kojto 107:4f6c30876dfa 6622 #define SPDIFRX_SR_OVR ((uint32_t)0x00000008) /*!<Overrun error */
Kojto 107:4f6c30876dfa 6623 #define SPDIFRX_SR_SBD ((uint32_t)0x00000010) /*!<Synchronization Block Detected */
Kojto 107:4f6c30876dfa 6624 #define SPDIFRX_SR_SYNCD ((uint32_t)0x00000020) /*!<Synchronization Done */
Kojto 107:4f6c30876dfa 6625 #define SPDIFRX_SR_FERR ((uint32_t)0x00000040) /*!<Framing error */
Kojto 107:4f6c30876dfa 6626 #define SPDIFRX_SR_SERR ((uint32_t)0x00000080) /*!<Synchronization error */
Kojto 107:4f6c30876dfa 6627 #define SPDIFRX_SR_TERR ((uint32_t)0x00000100) /*!<Time-out error */
Kojto 107:4f6c30876dfa 6628 #define SPDIFRX_SR_WIDTH5 ((uint32_t)0x7FFF0000) /*!<Duration of 5 symbols counted with spdif_clk */
Kojto 107:4f6c30876dfa 6629
Kojto 107:4f6c30876dfa 6630 /******************* Bit definition for SPDIFRX_IFCR register *******************/
Kojto 107:4f6c30876dfa 6631 #define SPDIFRX_IFCR_PERRCF ((uint32_t)0x00000004) /*!<Clears the Parity error flag */
Kojto 107:4f6c30876dfa 6632 #define SPDIFRX_IFCR_OVRCF ((uint32_t)0x00000008) /*!<Clears the Overrun error flag */
Kojto 107:4f6c30876dfa 6633 #define SPDIFRX_IFCR_SBDCF ((uint32_t)0x00000010) /*!<Clears the Synchronization Block Detected flag */
Kojto 107:4f6c30876dfa 6634 #define SPDIFRX_IFCR_SYNCDCF ((uint32_t)0x00000020) /*!<Clears the Synchronization Done flag */
Kojto 107:4f6c30876dfa 6635
Kojto 107:4f6c30876dfa 6636 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
Kojto 107:4f6c30876dfa 6637 #define SPDIFRX_DR0_DR ((uint32_t)0x00FFFFFF) /*!<Data value */
Kojto 107:4f6c30876dfa 6638 #define SPDIFRX_DR0_PE ((uint32_t)0x01000000) /*!<Parity Error bit */
Kojto 107:4f6c30876dfa 6639 #define SPDIFRX_DR0_V ((uint32_t)0x02000000) /*!<Validity bit */
Kojto 107:4f6c30876dfa 6640 #define SPDIFRX_DR0_U ((uint32_t)0x04000000) /*!<User bit */
Kojto 107:4f6c30876dfa 6641 #define SPDIFRX_DR0_C ((uint32_t)0x08000000) /*!<Channel Status bit */
Kojto 107:4f6c30876dfa 6642 #define SPDIFRX_DR0_PT ((uint32_t)0x30000000) /*!<Preamble Type */
Kojto 107:4f6c30876dfa 6643
Kojto 107:4f6c30876dfa 6644 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
Kojto 107:4f6c30876dfa 6645 #define SPDIFRX_DR1_DR ((uint32_t)0xFFFFFF00) /*!<Data value */
Kojto 107:4f6c30876dfa 6646 #define SPDIFRX_DR1_PT ((uint32_t)0x00000030) /*!<Preamble Type */
Kojto 107:4f6c30876dfa 6647 #define SPDIFRX_DR1_C ((uint32_t)0x00000008) /*!<Channel Status bit */
Kojto 107:4f6c30876dfa 6648 #define SPDIFRX_DR1_U ((uint32_t)0x00000004) /*!<User bit */
Kojto 107:4f6c30876dfa 6649 #define SPDIFRX_DR1_V ((uint32_t)0x00000002) /*!<Validity bit */
Kojto 107:4f6c30876dfa 6650 #define SPDIFRX_DR1_PE ((uint32_t)0x00000001) /*!<Parity Error bit */
Kojto 107:4f6c30876dfa 6651
Kojto 107:4f6c30876dfa 6652 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
Kojto 107:4f6c30876dfa 6653 #define SPDIFRX_DR1_DRNL1 ((uint32_t)0xFFFF0000) /*!<Data value Channel B */
Kojto 107:4f6c30876dfa 6654 #define SPDIFRX_DR1_DRNL2 ((uint32_t)0x0000FFFF) /*!<Data value Channel A */
Kojto 107:4f6c30876dfa 6655
Kojto 107:4f6c30876dfa 6656 /******************* Bit definition for SPDIFRX_CSR register *******************/
Kojto 107:4f6c30876dfa 6657 #define SPDIFRX_CSR_USR ((uint32_t)0x0000FFFF) /*!<User data information */
Kojto 107:4f6c30876dfa 6658 #define SPDIFRX_CSR_CS ((uint32_t)0x00FF0000) /*!<Channel A status information */
Kojto 107:4f6c30876dfa 6659 #define SPDIFRX_CSR_SOB ((uint32_t)0x01000000) /*!<Start Of Block */
Kojto 107:4f6c30876dfa 6660
Kojto 107:4f6c30876dfa 6661 /******************* Bit definition for SPDIFRX_DIR register *******************/
Kojto 107:4f6c30876dfa 6662 #define SPDIFRX_DIR_THI ((uint32_t)0x000013FF) /*!<Threshold LOW */
Kojto 107:4f6c30876dfa 6663 #define SPDIFRX_DIR_TLO ((uint32_t)0x1FFF0000) /*!<Threshold HIGH */
Kojto 107:4f6c30876dfa 6664
Kojto 107:4f6c30876dfa 6665
Kojto 107:4f6c30876dfa 6666 /******************************************************************************/
Kojto 107:4f6c30876dfa 6667 /* */
Kojto 107:4f6c30876dfa 6668 /* SD host Interface */
Kojto 107:4f6c30876dfa 6669 /* */
Kojto 107:4f6c30876dfa 6670 /******************************************************************************/
Kojto 107:4f6c30876dfa 6671 /****************** Bit definition for SDMMC_POWER register ******************/
Kojto 107:4f6c30876dfa 6672 #define SDMMC_POWER_PWRCTRL ((uint32_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */
Kojto 107:4f6c30876dfa 6673 #define SDMMC_POWER_PWRCTRL_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6674 #define SDMMC_POWER_PWRCTRL_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6675
Kojto 107:4f6c30876dfa 6676 /****************** Bit definition for SDMMC_CLKCR register ******************/
Kojto 107:4f6c30876dfa 6677 #define SDMMC_CLKCR_CLKDIV ((uint32_t)0x00FF) /*!<Clock divide factor */
Kojto 107:4f6c30876dfa 6678 #define SDMMC_CLKCR_CLKEN ((uint32_t)0x0100) /*!<Clock enable bit */
Kojto 107:4f6c30876dfa 6679 #define SDMMC_CLKCR_PWRSAV ((uint32_t)0x0200) /*!<Power saving configuration bit */
Kojto 107:4f6c30876dfa 6680 #define SDMMC_CLKCR_BYPASS ((uint32_t)0x0400) /*!<Clock divider bypass enable bit */
Kojto 107:4f6c30876dfa 6681
Kojto 107:4f6c30876dfa 6682 #define SDMMC_CLKCR_WIDBUS ((uint32_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
Kojto 107:4f6c30876dfa 6683 #define SDMMC_CLKCR_WIDBUS_0 ((uint32_t)0x0800) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6684 #define SDMMC_CLKCR_WIDBUS_1 ((uint32_t)0x1000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6685
Kojto 107:4f6c30876dfa 6686 #define SDMMC_CLKCR_NEGEDGE ((uint32_t)0x2000) /*!<SDMMC_CK dephasing selection bit */
Kojto 107:4f6c30876dfa 6687 #define SDMMC_CLKCR_HWFC_EN ((uint32_t)0x4000) /*!<HW Flow Control enable */
Kojto 107:4f6c30876dfa 6688
Kojto 107:4f6c30876dfa 6689 /******************* Bit definition for SDMMC_ARG register *******************/
Kojto 107:4f6c30876dfa 6690 #define SDMMC_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */
Kojto 107:4f6c30876dfa 6691
Kojto 107:4f6c30876dfa 6692 /******************* Bit definition for SDMMC_CMD register *******************/
Kojto 107:4f6c30876dfa 6693 #define SDMMC_CMD_CMDINDEX ((uint32_t)0x003F) /*!<Command Index */
Kojto 107:4f6c30876dfa 6694
Kojto 107:4f6c30876dfa 6695 #define SDMMC_CMD_WAITRESP ((uint32_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */
Kojto 107:4f6c30876dfa 6696 #define SDMMC_CMD_WAITRESP_0 ((uint32_t)0x0040) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 6697 #define SDMMC_CMD_WAITRESP_1 ((uint32_t)0x0080) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 6698
Kojto 107:4f6c30876dfa 6699 #define SDMMC_CMD_WAITINT ((uint32_t)0x0100) /*!<CPSM Waits for Interrupt Request */
Kojto 107:4f6c30876dfa 6700 #define SDMMC_CMD_WAITPEND ((uint32_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
Kojto 107:4f6c30876dfa 6701 #define SDMMC_CMD_CPSMEN ((uint32_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */
Kojto 107:4f6c30876dfa 6702 #define SDMMC_CMD_SDIOSUSPEND ((uint32_t)0x0800) /*!<SD I/O suspend command */
Kojto 107:4f6c30876dfa 6703
Kojto 107:4f6c30876dfa 6704 /***************** Bit definition for SDMMC_RESPCMD register *****************/
Kojto 107:4f6c30876dfa 6705 #define SDMMC_RESPCMD_RESPCMD ((uint32_t)0x3F) /*!<Response command index */
Kojto 107:4f6c30876dfa 6706
Kojto 107:4f6c30876dfa 6707 /****************** Bit definition for SDMMC_RESP0 register ******************/
Kojto 107:4f6c30876dfa 6708 #define SDMMC_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 107:4f6c30876dfa 6709
Kojto 107:4f6c30876dfa 6710 /****************** Bit definition for SDMMC_RESP1 register ******************/
Kojto 107:4f6c30876dfa 6711 #define SDMMC_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 107:4f6c30876dfa 6712
Kojto 107:4f6c30876dfa 6713 /****************** Bit definition for SDMMC_RESP2 register ******************/
Kojto 107:4f6c30876dfa 6714 #define SDMMC_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 107:4f6c30876dfa 6715
Kojto 107:4f6c30876dfa 6716 /****************** Bit definition for SDMMC_RESP3 register ******************/
Kojto 107:4f6c30876dfa 6717 #define SDMMC_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 107:4f6c30876dfa 6718
Kojto 107:4f6c30876dfa 6719 /****************** Bit definition for SDMMC_RESP4 register ******************/
Kojto 107:4f6c30876dfa 6720 #define SDMMC_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */
Kojto 107:4f6c30876dfa 6721
Kojto 107:4f6c30876dfa 6722 /****************** Bit definition for SDMMC_DTIMER register *****************/
Kojto 107:4f6c30876dfa 6723 #define SDMMC_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */
Kojto 107:4f6c30876dfa 6724
Kojto 107:4f6c30876dfa 6725 /****************** Bit definition for SDMMC_DLEN register *******************/
Kojto 107:4f6c30876dfa 6726 #define SDMMC_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */
Kojto 107:4f6c30876dfa 6727
Kojto 107:4f6c30876dfa 6728 /****************** Bit definition for SDMMC_DCTRL register ******************/
Kojto 107:4f6c30876dfa 6729 #define SDMMC_DCTRL_DTEN ((uint32_t)0x0001) /*!<Data transfer enabled bit */
Kojto 107:4f6c30876dfa 6730 #define SDMMC_DCTRL_DTDIR ((uint32_t)0x0002) /*!<Data transfer direction selection */
Kojto 107:4f6c30876dfa 6731 #define SDMMC_DCTRL_DTMODE ((uint32_t)0x0004) /*!<Data transfer mode selection */
Kojto 107:4f6c30876dfa 6732 #define SDMMC_DCTRL_DMAEN ((uint32_t)0x0008) /*!<DMA enabled bit */
Kojto 107:4f6c30876dfa 6733
Kojto 107:4f6c30876dfa 6734 #define SDMMC_DCTRL_DBLOCKSIZE ((uint32_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */
Kojto 107:4f6c30876dfa 6735 #define SDMMC_DCTRL_DBLOCKSIZE_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6736 #define SDMMC_DCTRL_DBLOCKSIZE_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6737 #define SDMMC_DCTRL_DBLOCKSIZE_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 6738 #define SDMMC_DCTRL_DBLOCKSIZE_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 6739
Kojto 107:4f6c30876dfa 6740 #define SDMMC_DCTRL_RWSTART ((uint32_t)0x0100) /*!<Read wait start */
Kojto 107:4f6c30876dfa 6741 #define SDMMC_DCTRL_RWSTOP ((uint32_t)0x0200) /*!<Read wait stop */
Kojto 107:4f6c30876dfa 6742 #define SDMMC_DCTRL_RWMOD ((uint32_t)0x0400) /*!<Read wait mode */
Kojto 107:4f6c30876dfa 6743 #define SDMMC_DCTRL_SDIOEN ((uint32_t)0x0800) /*!<SD I/O enable functions */
Kojto 107:4f6c30876dfa 6744
Kojto 107:4f6c30876dfa 6745 /****************** Bit definition for SDMMC_DCOUNT register *****************/
Kojto 107:4f6c30876dfa 6746 #define SDMMC_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */
Kojto 107:4f6c30876dfa 6747
Kojto 107:4f6c30876dfa 6748 /****************** Bit definition for SDMMC_STA register ********************/
Kojto 107:4f6c30876dfa 6749 #define SDMMC_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */
Kojto 107:4f6c30876dfa 6750 #define SDMMC_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */
Kojto 107:4f6c30876dfa 6751 #define SDMMC_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */
Kojto 107:4f6c30876dfa 6752 #define SDMMC_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */
Kojto 107:4f6c30876dfa 6753 #define SDMMC_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */
Kojto 107:4f6c30876dfa 6754 #define SDMMC_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */
Kojto 107:4f6c30876dfa 6755 #define SDMMC_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */
Kojto 107:4f6c30876dfa 6756 #define SDMMC_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */
Kojto 107:4f6c30876dfa 6757 #define SDMMC_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */
Kojto 107:4f6c30876dfa 6758 #define SDMMC_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */
Kojto 107:4f6c30876dfa 6759 #define SDMMC_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */
Kojto 107:4f6c30876dfa 6760 #define SDMMC_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */
Kojto 107:4f6c30876dfa 6761 #define SDMMC_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */
Kojto 107:4f6c30876dfa 6762 #define SDMMC_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
Kojto 107:4f6c30876dfa 6763 #define SDMMC_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
Kojto 107:4f6c30876dfa 6764 #define SDMMC_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */
Kojto 107:4f6c30876dfa 6765 #define SDMMC_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */
Kojto 107:4f6c30876dfa 6766 #define SDMMC_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */
Kojto 107:4f6c30876dfa 6767 #define SDMMC_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */
Kojto 107:4f6c30876dfa 6768 #define SDMMC_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */
Kojto 107:4f6c30876dfa 6769 #define SDMMC_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */
Kojto 107:4f6c30876dfa 6770 #define SDMMC_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDMMC interrupt received */
Kojto 107:4f6c30876dfa 6771
Kojto 107:4f6c30876dfa 6772 /******************* Bit definition for SDMMC_ICR register *******************/
Kojto 107:4f6c30876dfa 6773 #define SDMMC_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */
Kojto 107:4f6c30876dfa 6774 #define SDMMC_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */
Kojto 107:4f6c30876dfa 6775 #define SDMMC_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */
Kojto 107:4f6c30876dfa 6776 #define SDMMC_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */
Kojto 107:4f6c30876dfa 6777 #define SDMMC_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */
Kojto 107:4f6c30876dfa 6778 #define SDMMC_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */
Kojto 107:4f6c30876dfa 6779 #define SDMMC_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */
Kojto 107:4f6c30876dfa 6780 #define SDMMC_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */
Kojto 107:4f6c30876dfa 6781 #define SDMMC_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */
Kojto 107:4f6c30876dfa 6782 #define SDMMC_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */
Kojto 107:4f6c30876dfa 6783 #define SDMMC_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDMMCIT flag clear bit */
Kojto 107:4f6c30876dfa 6784
Kojto 107:4f6c30876dfa 6785 /****************** Bit definition for SDMMC_MASK register *******************/
Kojto 107:4f6c30876dfa 6786 #define SDMMC_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */
Kojto 107:4f6c30876dfa 6787 #define SDMMC_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */
Kojto 107:4f6c30876dfa 6788 #define SDMMC_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */
Kojto 107:4f6c30876dfa 6789 #define SDMMC_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */
Kojto 107:4f6c30876dfa 6790 #define SDMMC_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */
Kojto 107:4f6c30876dfa 6791 #define SDMMC_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */
Kojto 107:4f6c30876dfa 6792 #define SDMMC_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */
Kojto 107:4f6c30876dfa 6793 #define SDMMC_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */
Kojto 107:4f6c30876dfa 6794 #define SDMMC_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */
Kojto 107:4f6c30876dfa 6795 #define SDMMC_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */
Kojto 107:4f6c30876dfa 6796 #define SDMMC_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */
Kojto 107:4f6c30876dfa 6797 #define SDMMC_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */
Kojto 107:4f6c30876dfa 6798 #define SDMMC_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */
Kojto 107:4f6c30876dfa 6799 #define SDMMC_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */
Kojto 107:4f6c30876dfa 6800 #define SDMMC_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */
Kojto 107:4f6c30876dfa 6801 #define SDMMC_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */
Kojto 107:4f6c30876dfa 6802 #define SDMMC_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */
Kojto 107:4f6c30876dfa 6803 #define SDMMC_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */
Kojto 107:4f6c30876dfa 6804 #define SDMMC_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */
Kojto 107:4f6c30876dfa 6805 #define SDMMC_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */
Kojto 107:4f6c30876dfa 6806 #define SDMMC_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */
Kojto 107:4f6c30876dfa 6807 #define SDMMC_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDMMC Mode Interrupt Received interrupt Enable */
Kojto 107:4f6c30876dfa 6808
Kojto 107:4f6c30876dfa 6809 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
Kojto 107:4f6c30876dfa 6810 #define SDMMC_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */
Kojto 107:4f6c30876dfa 6811
Kojto 107:4f6c30876dfa 6812 /****************** Bit definition for SDMMC_FIFO register *******************/
Kojto 107:4f6c30876dfa 6813 #define SDMMC_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */
Kojto 107:4f6c30876dfa 6814
Kojto 107:4f6c30876dfa 6815 /******************************************************************************/
Kojto 107:4f6c30876dfa 6816 /* */
Kojto 107:4f6c30876dfa 6817 /* Serial Peripheral Interface (SPI) */
Kojto 107:4f6c30876dfa 6818 /* */
Kojto 107:4f6c30876dfa 6819 /******************************************************************************/
Kojto 107:4f6c30876dfa 6820 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 107:4f6c30876dfa 6821 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 107:4f6c30876dfa 6822 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 107:4f6c30876dfa 6823 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 107:4f6c30876dfa 6824 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 107:4f6c30876dfa 6825 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 6826 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 6827 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 6828 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 107:4f6c30876dfa 6829 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 107:4f6c30876dfa 6830 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 107:4f6c30876dfa 6831 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 107:4f6c30876dfa 6832 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 107:4f6c30876dfa 6833 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Kojto 107:4f6c30876dfa 6834 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 107:4f6c30876dfa 6835 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 107:4f6c30876dfa 6836 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 107:4f6c30876dfa 6837 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 107:4f6c30876dfa 6838
Kojto 107:4f6c30876dfa 6839 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 107:4f6c30876dfa 6840 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 107:4f6c30876dfa 6841 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 107:4f6c30876dfa 6842 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 107:4f6c30876dfa 6843 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Kojto 107:4f6c30876dfa 6844 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Kojto 107:4f6c30876dfa 6845 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 107:4f6c30876dfa 6846 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 107:4f6c30876dfa 6847 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 107:4f6c30876dfa 6848 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Kojto 107:4f6c30876dfa 6849 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 6850 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 6851 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 6852 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 6853 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Kojto 107:4f6c30876dfa 6854 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Kojto 107:4f6c30876dfa 6855 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Kojto 107:4f6c30876dfa 6856
Kojto 107:4f6c30876dfa 6857 /******************** Bit definition for SPI_SR register ********************/
Kojto 107:4f6c30876dfa 6858 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 107:4f6c30876dfa 6859 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 107:4f6c30876dfa 6860 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Kojto 107:4f6c30876dfa 6861 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Kojto 107:4f6c30876dfa 6862 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 107:4f6c30876dfa 6863 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 107:4f6c30876dfa 6864 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 107:4f6c30876dfa 6865 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 107:4f6c30876dfa 6866 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Kojto 107:4f6c30876dfa 6867 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Kojto 107:4f6c30876dfa 6868 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 6869 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 6870 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Kojto 107:4f6c30876dfa 6871 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 6872 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 6873
Kojto 107:4f6c30876dfa 6874 /******************** Bit definition for SPI_DR register ********************/
Kojto 107:4f6c30876dfa 6875 #define SPI_DR_DR ((uint32_t)0xFFFF) /*!< Data Register */
Kojto 107:4f6c30876dfa 6876
Kojto 107:4f6c30876dfa 6877 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 107:4f6c30876dfa 6878 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFF) /*!< CRC polynomial register */
Kojto 107:4f6c30876dfa 6879
Kojto 107:4f6c30876dfa 6880 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 107:4f6c30876dfa 6881 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFF) /*!< Rx CRC Register */
Kojto 107:4f6c30876dfa 6882
Kojto 107:4f6c30876dfa 6883 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 107:4f6c30876dfa 6884 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFF) /*!< Tx CRC Register */
Kojto 107:4f6c30876dfa 6885
Kojto 107:4f6c30876dfa 6886 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 107:4f6c30876dfa 6887 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 107:4f6c30876dfa 6888 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 107:4f6c30876dfa 6889 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6890 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6891 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 107:4f6c30876dfa 6892 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 107:4f6c30876dfa 6893 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6894 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6895 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 107:4f6c30876dfa 6896 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 107:4f6c30876dfa 6897 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 6898 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 6899 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 107:4f6c30876dfa 6900 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 107:4f6c30876dfa 6901 #define SPI_I2SCFGR_ASTRTEN ((uint32_t)0x00001000) /*!<Asynchronous start enable */
Kojto 107:4f6c30876dfa 6902
Kojto 107:4f6c30876dfa 6903 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 107:4f6c30876dfa 6904 #define SPI_I2SPR_I2SDIV ((uint32_t)0x00FF) /*!<I2S Linear prescaler */
Kojto 107:4f6c30876dfa 6905 #define SPI_I2SPR_ODD ((uint32_t)0x0100) /*!<Odd factor for the prescaler */
Kojto 107:4f6c30876dfa 6906 #define SPI_I2SPR_MCKOE ((uint32_t)0x0200) /*!<Master Clock Output Enable */
Kojto 107:4f6c30876dfa 6907
Kojto 107:4f6c30876dfa 6908
Kojto 107:4f6c30876dfa 6909 /******************************************************************************/
Kojto 107:4f6c30876dfa 6910 /* */
Kojto 107:4f6c30876dfa 6911 /* SYSCFG */
Kojto 107:4f6c30876dfa 6912 /* */
Kojto 107:4f6c30876dfa 6913 /******************************************************************************/
Kojto 107:4f6c30876dfa 6914 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
Kojto 116:c0f6e94411f5 6915 #define SYSCFG_MEMRMP_MEM_BOOT ((uint32_t)0x00000001) /*!< Boot information after Reset */
Kojto 116:c0f6e94411f5 6916
Kojto 107:4f6c30876dfa 6917
Kojto 107:4f6c30876dfa 6918 #define SYSCFG_MEMRMP_SWP_FMC ((uint32_t)0x00000C00) /*!< FMC Memory Mapping swapping */
Kojto 107:4f6c30876dfa 6919 #define SYSCFG_MEMRMP_SWP_FMC_0 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 6920 #define SYSCFG_MEMRMP_SWP_FMC_1 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 6921
Kojto 107:4f6c30876dfa 6922 /****************** Bit definition for SYSCFG_PMC register ******************/
Kojto 116:c0f6e94411f5 6923
Kojto 107:4f6c30876dfa 6924 #define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
Kojto 107:4f6c30876dfa 6925 #define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
Kojto 107:4f6c30876dfa 6926 #define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
Kojto 107:4f6c30876dfa 6927 #define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
Kojto 107:4f6c30876dfa 6928
Kojto 107:4f6c30876dfa 6929 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */
Kojto 107:4f6c30876dfa 6930
Kojto 107:4f6c30876dfa 6931 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 107:4f6c30876dfa 6932 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
Kojto 107:4f6c30876dfa 6933 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x00F0) /*!<EXTI 1 configuration */
Kojto 107:4f6c30876dfa 6934 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x0F00) /*!<EXTI 2 configuration */
Kojto 107:4f6c30876dfa 6935 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0xF000) /*!<EXTI 3 configuration */
Kojto 107:4f6c30876dfa 6936 /**
Kojto 107:4f6c30876dfa 6937 * @brief EXTI0 configuration
Kojto 107:4f6c30876dfa 6938 */
Kojto 107:4f6c30876dfa 6939 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x0000) /*!<PA[0] pin */
Kojto 107:4f6c30876dfa 6940 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x0001) /*!<PB[0] pin */
Kojto 107:4f6c30876dfa 6941 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x0002) /*!<PC[0] pin */
Kojto 107:4f6c30876dfa 6942 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x0003) /*!<PD[0] pin */
Kojto 107:4f6c30876dfa 6943 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x0004) /*!<PE[0] pin */
Kojto 107:4f6c30876dfa 6944 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x0005) /*!<PF[0] pin */
Kojto 107:4f6c30876dfa 6945 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x0006) /*!<PG[0] pin */
Kojto 107:4f6c30876dfa 6946 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x0007) /*!<PH[0] pin */
Kojto 107:4f6c30876dfa 6947 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x0008) /*!<PI[0] pin */
Kojto 107:4f6c30876dfa 6948 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x0009) /*!<PJ[0] pin */
Kojto 107:4f6c30876dfa 6949 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x000A) /*!<PK[0] pin */
Kojto 107:4f6c30876dfa 6950
Kojto 107:4f6c30876dfa 6951 /**
Kojto 107:4f6c30876dfa 6952 * @brief EXTI1 configuration
Kojto 107:4f6c30876dfa 6953 */
Kojto 107:4f6c30876dfa 6954 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x0000) /*!<PA[1] pin */
Kojto 107:4f6c30876dfa 6955 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x0010) /*!<PB[1] pin */
Kojto 107:4f6c30876dfa 6956 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x0020) /*!<PC[1] pin */
Kojto 107:4f6c30876dfa 6957 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x0030) /*!<PD[1] pin */
Kojto 107:4f6c30876dfa 6958 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x0040) /*!<PE[1] pin */
Kojto 107:4f6c30876dfa 6959 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x0050) /*!<PF[1] pin */
Kojto 107:4f6c30876dfa 6960 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x0060) /*!<PG[1] pin */
Kojto 107:4f6c30876dfa 6961 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x0070) /*!<PH[1] pin */
Kojto 107:4f6c30876dfa 6962 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x0080) /*!<PI[1] pin */
Kojto 107:4f6c30876dfa 6963 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x0090) /*!<PJ[1] pin */
Kojto 107:4f6c30876dfa 6964 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x00A0) /*!<PK[1] pin */
Kojto 107:4f6c30876dfa 6965
Kojto 107:4f6c30876dfa 6966 /**
Kojto 107:4f6c30876dfa 6967 * @brief EXTI2 configuration
Kojto 107:4f6c30876dfa 6968 */
Kojto 107:4f6c30876dfa 6969 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x0000) /*!<PA[2] pin */
Kojto 107:4f6c30876dfa 6970 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x0100) /*!<PB[2] pin */
Kojto 107:4f6c30876dfa 6971 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x0200) /*!<PC[2] pin */
Kojto 107:4f6c30876dfa 6972 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x0300) /*!<PD[2] pin */
Kojto 107:4f6c30876dfa 6973 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x0400) /*!<PE[2] pin */
Kojto 107:4f6c30876dfa 6974 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x0500) /*!<PF[2] pin */
Kojto 107:4f6c30876dfa 6975 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x0600) /*!<PG[2] pin */
Kojto 107:4f6c30876dfa 6976 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x0700) /*!<PH[2] pin */
Kojto 107:4f6c30876dfa 6977 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x0800) /*!<PI[2] pin */
Kojto 107:4f6c30876dfa 6978 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x0900) /*!<PJ[2] pin */
Kojto 107:4f6c30876dfa 6979 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x0A00) /*!<PK[2] pin */
Kojto 107:4f6c30876dfa 6980
Kojto 107:4f6c30876dfa 6981 /**
Kojto 107:4f6c30876dfa 6982 * @brief EXTI3 configuration
Kojto 107:4f6c30876dfa 6983 */
Kojto 107:4f6c30876dfa 6984 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x0000) /*!<PA[3] pin */
Kojto 107:4f6c30876dfa 6985 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x1000) /*!<PB[3] pin */
Kojto 107:4f6c30876dfa 6986 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x2000) /*!<PC[3] pin */
Kojto 107:4f6c30876dfa 6987 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x3000) /*!<PD[3] pin */
Kojto 107:4f6c30876dfa 6988 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x4000) /*!<PE[3] pin */
Kojto 107:4f6c30876dfa 6989 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x5000) /*!<PF[3] pin */
Kojto 107:4f6c30876dfa 6990 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x6000) /*!<PG[3] pin */
Kojto 107:4f6c30876dfa 6991 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x7000) /*!<PH[3] pin */
Kojto 107:4f6c30876dfa 6992 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x8000) /*!<PI[3] pin */
Kojto 107:4f6c30876dfa 6993 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x9000) /*!<PJ[3] pin */
Kojto 107:4f6c30876dfa 6994 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0xA000) /*!<PK[3] pin */
Kojto 107:4f6c30876dfa 6995
Kojto 107:4f6c30876dfa 6996 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
Kojto 107:4f6c30876dfa 6997 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x000F) /*!<EXTI 4 configuration */
Kojto 107:4f6c30876dfa 6998 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x00F0) /*!<EXTI 5 configuration */
Kojto 107:4f6c30876dfa 6999 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x0F00) /*!<EXTI 6 configuration */
Kojto 107:4f6c30876dfa 7000 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0xF000) /*!<EXTI 7 configuration */
Kojto 107:4f6c30876dfa 7001 /**
Kojto 107:4f6c30876dfa 7002 * @brief EXTI4 configuration
Kojto 107:4f6c30876dfa 7003 */
Kojto 107:4f6c30876dfa 7004 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x0000) /*!<PA[4] pin */
Kojto 107:4f6c30876dfa 7005 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x0001) /*!<PB[4] pin */
Kojto 107:4f6c30876dfa 7006 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x0002) /*!<PC[4] pin */
Kojto 107:4f6c30876dfa 7007 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x0003) /*!<PD[4] pin */
Kojto 107:4f6c30876dfa 7008 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x0004) /*!<PE[4] pin */
Kojto 107:4f6c30876dfa 7009 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x0005) /*!<PF[4] pin */
Kojto 107:4f6c30876dfa 7010 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x0006) /*!<PG[4] pin */
Kojto 107:4f6c30876dfa 7011 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x0007) /*!<PH[4] pin */
Kojto 107:4f6c30876dfa 7012 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x0008) /*!<PI[4] pin */
Kojto 107:4f6c30876dfa 7013 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x0009) /*!<PJ[4] pin */
Kojto 107:4f6c30876dfa 7014 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x000A) /*!<PK[4] pin */
Kojto 107:4f6c30876dfa 7015
Kojto 107:4f6c30876dfa 7016 /**
Kojto 107:4f6c30876dfa 7017 * @brief EXTI5 configuration
Kojto 107:4f6c30876dfa 7018 */
Kojto 107:4f6c30876dfa 7019 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x0000) /*!<PA[5] pin */
Kojto 107:4f6c30876dfa 7020 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x0010) /*!<PB[5] pin */
Kojto 107:4f6c30876dfa 7021 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x0020) /*!<PC[5] pin */
Kojto 107:4f6c30876dfa 7022 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x0030) /*!<PD[5] pin */
Kojto 107:4f6c30876dfa 7023 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x0040) /*!<PE[5] pin */
Kojto 107:4f6c30876dfa 7024 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x0050) /*!<PF[5] pin */
Kojto 107:4f6c30876dfa 7025 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x0060) /*!<PG[5] pin */
Kojto 107:4f6c30876dfa 7026 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x0070) /*!<PH[5] pin */
Kojto 107:4f6c30876dfa 7027 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x0080) /*!<PI[5] pin */
Kojto 107:4f6c30876dfa 7028 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x0090) /*!<PJ[5] pin */
Kojto 107:4f6c30876dfa 7029 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x00A0) /*!<PK[5] pin */
Kojto 107:4f6c30876dfa 7030
Kojto 107:4f6c30876dfa 7031 /**
Kojto 107:4f6c30876dfa 7032 * @brief EXTI6 configuration
Kojto 107:4f6c30876dfa 7033 */
Kojto 107:4f6c30876dfa 7034 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x0000) /*!<PA[6] pin */
Kojto 107:4f6c30876dfa 7035 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x0100) /*!<PB[6] pin */
Kojto 107:4f6c30876dfa 7036 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x0200) /*!<PC[6] pin */
Kojto 107:4f6c30876dfa 7037 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x0300) /*!<PD[6] pin */
Kojto 107:4f6c30876dfa 7038 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x0400) /*!<PE[6] pin */
Kojto 107:4f6c30876dfa 7039 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x0500) /*!<PF[6] pin */
Kojto 107:4f6c30876dfa 7040 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x0600) /*!<PG[6] pin */
Kojto 107:4f6c30876dfa 7041 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x0700) /*!<PH[6] pin */
Kojto 107:4f6c30876dfa 7042 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x0800) /*!<PI[6] pin */
Kojto 107:4f6c30876dfa 7043 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x0900) /*!<PJ[6] pin */
Kojto 107:4f6c30876dfa 7044 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x0A00) /*!<PK[6] pin */
Kojto 107:4f6c30876dfa 7045
Kojto 107:4f6c30876dfa 7046 /**
Kojto 107:4f6c30876dfa 7047 * @brief EXTI7 configuration
Kojto 107:4f6c30876dfa 7048 */
Kojto 107:4f6c30876dfa 7049 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x0000) /*!<PA[7] pin */
Kojto 107:4f6c30876dfa 7050 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x1000) /*!<PB[7] pin */
Kojto 107:4f6c30876dfa 7051 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x2000) /*!<PC[7] pin */
Kojto 107:4f6c30876dfa 7052 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x3000) /*!<PD[7] pin */
Kojto 107:4f6c30876dfa 7053 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x4000) /*!<PE[7] pin */
Kojto 107:4f6c30876dfa 7054 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x5000) /*!<PF[7] pin */
Kojto 107:4f6c30876dfa 7055 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x6000) /*!<PG[7] pin */
Kojto 107:4f6c30876dfa 7056 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x7000) /*!<PH[7] pin */
Kojto 107:4f6c30876dfa 7057 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x8000) /*!<PI[7] pin */
Kojto 107:4f6c30876dfa 7058 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x9000) /*!<PJ[7] pin */
Kojto 107:4f6c30876dfa 7059 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0xA000) /*!<PK[7] pin */
Kojto 107:4f6c30876dfa 7060
Kojto 107:4f6c30876dfa 7061 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
Kojto 107:4f6c30876dfa 7062 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x000F) /*!<EXTI 8 configuration */
Kojto 107:4f6c30876dfa 7063 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x00F0) /*!<EXTI 9 configuration */
Kojto 107:4f6c30876dfa 7064 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x0F00) /*!<EXTI 10 configuration */
Kojto 107:4f6c30876dfa 7065 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0xF000) /*!<EXTI 11 configuration */
Kojto 107:4f6c30876dfa 7066
Kojto 107:4f6c30876dfa 7067 /**
Kojto 107:4f6c30876dfa 7068 * @brief EXTI8 configuration
Kojto 107:4f6c30876dfa 7069 */
Kojto 107:4f6c30876dfa 7070 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x0000) /*!<PA[8] pin */
Kojto 107:4f6c30876dfa 7071 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x0001) /*!<PB[8] pin */
Kojto 107:4f6c30876dfa 7072 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x0002) /*!<PC[8] pin */
Kojto 107:4f6c30876dfa 7073 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x0003) /*!<PD[8] pin */
Kojto 107:4f6c30876dfa 7074 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x0004) /*!<PE[8] pin */
Kojto 107:4f6c30876dfa 7075 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x0005) /*!<PF[8] pin */
Kojto 107:4f6c30876dfa 7076 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x0006) /*!<PG[8] pin */
Kojto 107:4f6c30876dfa 7077 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x0007) /*!<PH[8] pin */
Kojto 107:4f6c30876dfa 7078 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x0008) /*!<PI[8] pin */
Kojto 107:4f6c30876dfa 7079 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x0009) /*!<PJ[8] pin */
Kojto 107:4f6c30876dfa 7080
Kojto 107:4f6c30876dfa 7081 /**
Kojto 107:4f6c30876dfa 7082 * @brief EXTI9 configuration
Kojto 107:4f6c30876dfa 7083 */
Kojto 107:4f6c30876dfa 7084 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x0000) /*!<PA[9] pin */
Kojto 107:4f6c30876dfa 7085 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x0010) /*!<PB[9] pin */
Kojto 107:4f6c30876dfa 7086 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x0020) /*!<PC[9] pin */
Kojto 107:4f6c30876dfa 7087 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x0030) /*!<PD[9] pin */
Kojto 107:4f6c30876dfa 7088 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x0040) /*!<PE[9] pin */
Kojto 107:4f6c30876dfa 7089 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x0050) /*!<PF[9] pin */
Kojto 107:4f6c30876dfa 7090 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x0060) /*!<PG[9] pin */
Kojto 107:4f6c30876dfa 7091 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x0070) /*!<PH[9] pin */
Kojto 107:4f6c30876dfa 7092 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x0080) /*!<PI[9] pin */
Kojto 107:4f6c30876dfa 7093 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x0090) /*!<PJ[9] pin */
Kojto 107:4f6c30876dfa 7094
Kojto 107:4f6c30876dfa 7095 /**
Kojto 107:4f6c30876dfa 7096 * @brief EXTI10 configuration
Kojto 107:4f6c30876dfa 7097 */
Kojto 107:4f6c30876dfa 7098 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x0000) /*!<PA[10] pin */
Kojto 107:4f6c30876dfa 7099 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x0100) /*!<PB[10] pin */
Kojto 107:4f6c30876dfa 7100 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x0200) /*!<PC[10] pin */
Kojto 107:4f6c30876dfa 7101 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x0300) /*!<PD[10] pin */
Kojto 107:4f6c30876dfa 7102 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x0400) /*!<PE[10] pin */
Kojto 107:4f6c30876dfa 7103 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x0500) /*!<PF[10] pin */
Kojto 107:4f6c30876dfa 7104 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x0600) /*!<PG[10] pin */
Kojto 107:4f6c30876dfa 7105 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x0700) /*!<PH[10] pin */
Kojto 107:4f6c30876dfa 7106 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x0800) /*!<PI[10] pin */
Kojto 107:4f6c30876dfa 7107 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x0900) /*!<PJ[10] pin */
Kojto 107:4f6c30876dfa 7108
Kojto 107:4f6c30876dfa 7109 /**
Kojto 107:4f6c30876dfa 7110 * @brief EXTI11 configuration
Kojto 107:4f6c30876dfa 7111 */
Kojto 107:4f6c30876dfa 7112 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x0000) /*!<PA[11] pin */
Kojto 107:4f6c30876dfa 7113 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x1000) /*!<PB[11] pin */
Kojto 107:4f6c30876dfa 7114 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x2000) /*!<PC[11] pin */
Kojto 107:4f6c30876dfa 7115 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x3000) /*!<PD[11] pin */
Kojto 107:4f6c30876dfa 7116 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x4000) /*!<PE[11] pin */
Kojto 107:4f6c30876dfa 7117 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x5000) /*!<PF[11] pin */
Kojto 107:4f6c30876dfa 7118 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x6000) /*!<PG[11] pin */
Kojto 107:4f6c30876dfa 7119 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x7000) /*!<PH[11] pin */
Kojto 107:4f6c30876dfa 7120 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x8000) /*!<PI[11] pin */
Kojto 107:4f6c30876dfa 7121 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x9000) /*!<PJ[11] pin */
Kojto 107:4f6c30876dfa 7122
Kojto 107:4f6c30876dfa 7123
Kojto 107:4f6c30876dfa 7124 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
Kojto 107:4f6c30876dfa 7125 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x000F) /*!<EXTI 12 configuration */
Kojto 107:4f6c30876dfa 7126 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x00F0) /*!<EXTI 13 configuration */
Kojto 107:4f6c30876dfa 7127 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x0F00) /*!<EXTI 14 configuration */
Kojto 107:4f6c30876dfa 7128 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0xF000) /*!<EXTI 15 configuration */
Kojto 107:4f6c30876dfa 7129 /**
Kojto 107:4f6c30876dfa 7130 * @brief EXTI12 configuration
Kojto 107:4f6c30876dfa 7131 */
Kojto 107:4f6c30876dfa 7132 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x0000) /*!<PA[12] pin */
Kojto 107:4f6c30876dfa 7133 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x0001) /*!<PB[12] pin */
Kojto 107:4f6c30876dfa 7134 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x0002) /*!<PC[12] pin */
Kojto 107:4f6c30876dfa 7135 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x0003) /*!<PD[12] pin */
Kojto 107:4f6c30876dfa 7136 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x0004) /*!<PE[12] pin */
Kojto 107:4f6c30876dfa 7137 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x0005) /*!<PF[12] pin */
Kojto 107:4f6c30876dfa 7138 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x0006) /*!<PG[12] pin */
Kojto 107:4f6c30876dfa 7139 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x0007) /*!<PH[12] pin */
Kojto 107:4f6c30876dfa 7140 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x0008) /*!<PI[12] pin */
Kojto 107:4f6c30876dfa 7141 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x0009) /*!<PJ[12] pin */
Kojto 107:4f6c30876dfa 7142
Kojto 107:4f6c30876dfa 7143 /**
Kojto 107:4f6c30876dfa 7144 * @brief EXTI13 configuration
Kojto 107:4f6c30876dfa 7145 */
Kojto 107:4f6c30876dfa 7146 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x0000) /*!<PA[13] pin */
Kojto 107:4f6c30876dfa 7147 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x0010) /*!<PB[13] pin */
Kojto 107:4f6c30876dfa 7148 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x0020) /*!<PC[13] pin */
Kojto 107:4f6c30876dfa 7149 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x0030) /*!<PD[13] pin */
Kojto 107:4f6c30876dfa 7150 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x0040) /*!<PE[13] pin */
Kojto 107:4f6c30876dfa 7151 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x0050) /*!<PF[13] pin */
Kojto 107:4f6c30876dfa 7152 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x0060) /*!<PG[13] pin */
Kojto 107:4f6c30876dfa 7153 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x0070) /*!<PH[13] pin */
Kojto 107:4f6c30876dfa 7154 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x0008) /*!<PI[13] pin */
Kojto 107:4f6c30876dfa 7155 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x0009) /*!<PJ[13] pin */
Kojto 107:4f6c30876dfa 7156
Kojto 107:4f6c30876dfa 7157 /**
Kojto 107:4f6c30876dfa 7158 * @brief EXTI14 configuration
Kojto 107:4f6c30876dfa 7159 */
Kojto 107:4f6c30876dfa 7160 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x0000) /*!<PA[14] pin */
Kojto 107:4f6c30876dfa 7161 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x0100) /*!<PB[14] pin */
Kojto 107:4f6c30876dfa 7162 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x0200) /*!<PC[14] pin */
Kojto 107:4f6c30876dfa 7163 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x0300) /*!<PD[14] pin */
Kojto 107:4f6c30876dfa 7164 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x0400) /*!<PE[14] pin */
Kojto 107:4f6c30876dfa 7165 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x0500) /*!<PF[14] pin */
Kojto 107:4f6c30876dfa 7166 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x0600) /*!<PG[14] pin */
Kojto 107:4f6c30876dfa 7167 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x0700) /*!<PH[14] pin */
Kojto 107:4f6c30876dfa 7168 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x0800) /*!<PI[14] pin */
Kojto 107:4f6c30876dfa 7169 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x0900) /*!<PJ[14] pin */
Kojto 107:4f6c30876dfa 7170
Kojto 107:4f6c30876dfa 7171 /**
Kojto 107:4f6c30876dfa 7172 * @brief EXTI15 configuration
Kojto 107:4f6c30876dfa 7173 */
Kojto 107:4f6c30876dfa 7174 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x0000) /*!<PA[15] pin */
Kojto 107:4f6c30876dfa 7175 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x1000) /*!<PB[15] pin */
Kojto 107:4f6c30876dfa 7176 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x2000) /*!<PC[15] pin */
Kojto 107:4f6c30876dfa 7177 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x3000) /*!<PD[15] pin */
Kojto 107:4f6c30876dfa 7178 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x4000) /*!<PE[15] pin */
Kojto 107:4f6c30876dfa 7179 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x5000) /*!<PF[15] pin */
Kojto 107:4f6c30876dfa 7180 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x6000) /*!<PG[15] pin */
Kojto 107:4f6c30876dfa 7181 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x7000) /*!<PH[15] pin */
Kojto 107:4f6c30876dfa 7182 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x8000) /*!<PI[15] pin */
Kojto 107:4f6c30876dfa 7183 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x9000) /*!<PJ[15] pin */
Kojto 107:4f6c30876dfa 7184
Kojto 107:4f6c30876dfa 7185 /****************** Bit definition for SYSCFG_CMPCR register ****************/
Kojto 107:4f6c30876dfa 7186 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell power-down */
Kojto 107:4f6c30876dfa 7187 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell ready flag*/
Kojto 107:4f6c30876dfa 7188
Kojto 107:4f6c30876dfa 7189 /******************************************************************************/
Kojto 107:4f6c30876dfa 7190 /* */
Kojto 107:4f6c30876dfa 7191 /* TIM */
Kojto 107:4f6c30876dfa 7192 /* */
Kojto 107:4f6c30876dfa 7193 /******************************************************************************/
Kojto 107:4f6c30876dfa 7194 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 107:4f6c30876dfa 7195 #define TIM_CR1_CEN ((uint32_t)0x0001) /*!<Counter enable */
Kojto 107:4f6c30876dfa 7196 #define TIM_CR1_UDIS ((uint32_t)0x0002) /*!<Update disable */
Kojto 107:4f6c30876dfa 7197 #define TIM_CR1_URS ((uint32_t)0x0004) /*!<Update request source */
Kojto 107:4f6c30876dfa 7198 #define TIM_CR1_OPM ((uint32_t)0x0008) /*!<One pulse mode */
Kojto 107:4f6c30876dfa 7199 #define TIM_CR1_DIR ((uint32_t)0x0010) /*!<Direction */
Kojto 107:4f6c30876dfa 7200
Kojto 107:4f6c30876dfa 7201 #define TIM_CR1_CMS ((uint32_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 107:4f6c30876dfa 7202 #define TIM_CR1_CMS_0 ((uint32_t)0x0020) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7203 #define TIM_CR1_CMS_1 ((uint32_t)0x0040) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7204
Kojto 107:4f6c30876dfa 7205 #define TIM_CR1_ARPE ((uint32_t)0x0080) /*!<Auto-reload preload enable */
Kojto 107:4f6c30876dfa 7206
Kojto 107:4f6c30876dfa 7207 #define TIM_CR1_CKD ((uint32_t)0x0300) /*!<CKD[1:0] bits (clock division) */
Kojto 107:4f6c30876dfa 7208 #define TIM_CR1_CKD_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7209 #define TIM_CR1_CKD_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7210 #define TIM_CR1_UIFREMAP ((uint32_t)0x0800) /*!<UIF status bit */
Kojto 107:4f6c30876dfa 7211
Kojto 107:4f6c30876dfa 7212 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 107:4f6c30876dfa 7213 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 107:4f6c30876dfa 7214 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 107:4f6c30876dfa 7215 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 107:4f6c30876dfa 7216
Kojto 107:4f6c30876dfa 7217 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
Kojto 107:4f6c30876dfa 7218 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
Kojto 107:4f6c30876dfa 7219
Kojto 107:4f6c30876dfa 7220 #define TIM_CR2_MMS ((uint32_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 107:4f6c30876dfa 7221 #define TIM_CR2_MMS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7222 #define TIM_CR2_MMS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7223 #define TIM_CR2_MMS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7224
Kojto 107:4f6c30876dfa 7225 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 107:4f6c30876dfa 7226 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7227 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7228 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7229 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7230
Kojto 107:4f6c30876dfa 7231 #define TIM_CR2_TI1S ((uint32_t)0x0080) /*!<TI1 Selection */
Kojto 107:4f6c30876dfa 7232 #define TIM_CR2_OIS1 ((uint32_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
Kojto 107:4f6c30876dfa 7233 #define TIM_CR2_OIS1N ((uint32_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
Kojto 107:4f6c30876dfa 7234 #define TIM_CR2_OIS2 ((uint32_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
Kojto 107:4f6c30876dfa 7235 #define TIM_CR2_OIS2N ((uint32_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
Kojto 107:4f6c30876dfa 7236 #define TIM_CR2_OIS3 ((uint32_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
Kojto 107:4f6c30876dfa 7237 #define TIM_CR2_OIS3N ((uint32_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
Kojto 107:4f6c30876dfa 7238 #define TIM_CR2_OIS4 ((uint32_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
Kojto 107:4f6c30876dfa 7239
Kojto 107:4f6c30876dfa 7240 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 107:4f6c30876dfa 7241 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 107:4f6c30876dfa 7242 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7243 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7244 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7245 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7246 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 107:4f6c30876dfa 7247
Kojto 107:4f6c30876dfa 7248 #define TIM_SMCR_TS ((uint32_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 107:4f6c30876dfa 7249 #define TIM_SMCR_TS_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7250 #define TIM_SMCR_TS_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7251 #define TIM_SMCR_TS_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7252
Kojto 107:4f6c30876dfa 7253 #define TIM_SMCR_MSM ((uint32_t)0x0080) /*!<Master/slave mode */
Kojto 107:4f6c30876dfa 7254
Kojto 107:4f6c30876dfa 7255 #define TIM_SMCR_ETF ((uint32_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 107:4f6c30876dfa 7256 #define TIM_SMCR_ETF_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7257 #define TIM_SMCR_ETF_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7258 #define TIM_SMCR_ETF_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7259 #define TIM_SMCR_ETF_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7260
Kojto 107:4f6c30876dfa 7261 #define TIM_SMCR_ETPS ((uint32_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 107:4f6c30876dfa 7262 #define TIM_SMCR_ETPS_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7263 #define TIM_SMCR_ETPS_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7264
Kojto 107:4f6c30876dfa 7265
Kojto 107:4f6c30876dfa 7266 #define TIM_SMCR_ECE ((uint32_t)0x4000) /*!<External clock enable */
Kojto 107:4f6c30876dfa 7267 #define TIM_SMCR_ETP ((uint32_t)0x8000) /*!<External trigger polarity */
Kojto 107:4f6c30876dfa 7268
Kojto 107:4f6c30876dfa 7269 /******************* Bit definition for TIM_DIER register *******************/
Kojto 107:4f6c30876dfa 7270 #define TIM_DIER_UIE ((uint32_t)0x0001) /*!<Update interrupt enable */
Kojto 107:4f6c30876dfa 7271 #define TIM_DIER_CC1IE ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
Kojto 107:4f6c30876dfa 7272 #define TIM_DIER_CC2IE ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
Kojto 107:4f6c30876dfa 7273 #define TIM_DIER_CC3IE ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
Kojto 107:4f6c30876dfa 7274 #define TIM_DIER_CC4IE ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
Kojto 107:4f6c30876dfa 7275 #define TIM_DIER_COMIE ((uint32_t)0x0020) /*!<COM interrupt enable */
Kojto 107:4f6c30876dfa 7276 #define TIM_DIER_TIE ((uint32_t)0x0040) /*!<Trigger interrupt enable */
Kojto 107:4f6c30876dfa 7277 #define TIM_DIER_BIE ((uint32_t)0x0080) /*!<Break interrupt enable */
Kojto 107:4f6c30876dfa 7278 #define TIM_DIER_UDE ((uint32_t)0x0100) /*!<Update DMA request enable */
Kojto 107:4f6c30876dfa 7279 #define TIM_DIER_CC1DE ((uint32_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
Kojto 107:4f6c30876dfa 7280 #define TIM_DIER_CC2DE ((uint32_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
Kojto 107:4f6c30876dfa 7281 #define TIM_DIER_CC3DE ((uint32_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
Kojto 107:4f6c30876dfa 7282 #define TIM_DIER_CC4DE ((uint32_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
Kojto 107:4f6c30876dfa 7283 #define TIM_DIER_COMDE ((uint32_t)0x2000) /*!<COM DMA request enable */
Kojto 107:4f6c30876dfa 7284 #define TIM_DIER_TDE ((uint32_t)0x4000) /*!<Trigger DMA request enable */
Kojto 107:4f6c30876dfa 7285
Kojto 107:4f6c30876dfa 7286 /******************** Bit definition for TIM_SR register ********************/
Kojto 107:4f6c30876dfa 7287 #define TIM_SR_UIF ((uint32_t)0x0001) /*!<Update interrupt Flag */
Kojto 107:4f6c30876dfa 7288 #define TIM_SR_CC1IF ((uint32_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 107:4f6c30876dfa 7289 #define TIM_SR_CC2IF ((uint32_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 107:4f6c30876dfa 7290 #define TIM_SR_CC3IF ((uint32_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 107:4f6c30876dfa 7291 #define TIM_SR_CC4IF ((uint32_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 107:4f6c30876dfa 7292 #define TIM_SR_COMIF ((uint32_t)0x0020) /*!<COM interrupt Flag */
Kojto 107:4f6c30876dfa 7293 #define TIM_SR_TIF ((uint32_t)0x0040) /*!<Trigger interrupt Flag */
Kojto 107:4f6c30876dfa 7294 #define TIM_SR_BIF ((uint32_t)0x0080) /*!<Break interrupt Flag */
Kojto 107:4f6c30876dfa 7295 #define TIM_SR_B2IF ((uint32_t)0x0100) /*!<Break2 interrupt Flag */
Kojto 107:4f6c30876dfa 7296 #define TIM_SR_CC1OF ((uint32_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 107:4f6c30876dfa 7297 #define TIM_SR_CC2OF ((uint32_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 107:4f6c30876dfa 7298 #define TIM_SR_CC3OF ((uint32_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 107:4f6c30876dfa 7299 #define TIM_SR_CC4OF ((uint32_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 107:4f6c30876dfa 7300
Kojto 107:4f6c30876dfa 7301 /******************* Bit definition for TIM_EGR register ********************/
Kojto 107:4f6c30876dfa 7302 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 107:4f6c30876dfa 7303 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 107:4f6c30876dfa 7304 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 107:4f6c30876dfa 7305 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 107:4f6c30876dfa 7306 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 107:4f6c30876dfa 7307 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 107:4f6c30876dfa 7308 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 107:4f6c30876dfa 7309 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 107:4f6c30876dfa 7310 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break2 Generation */
Kojto 107:4f6c30876dfa 7311
Kojto 107:4f6c30876dfa 7312 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 107:4f6c30876dfa 7313 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 107:4f6c30876dfa 7314 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7315 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7316
Kojto 107:4f6c30876dfa 7317 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 107:4f6c30876dfa 7318 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 107:4f6c30876dfa 7319
Kojto 107:4f6c30876dfa 7320 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 107:4f6c30876dfa 7321 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7322 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7323 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7324 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7325
Kojto 107:4f6c30876dfa 7326 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 107:4f6c30876dfa 7327
Kojto 107:4f6c30876dfa 7328 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 107:4f6c30876dfa 7329 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7330 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7331
Kojto 107:4f6c30876dfa 7332 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 107:4f6c30876dfa 7333 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 107:4f6c30876dfa 7334
Kojto 107:4f6c30876dfa 7335 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 107:4f6c30876dfa 7336 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7337 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7338 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7339 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7340
Kojto 107:4f6c30876dfa 7341 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 107:4f6c30876dfa 7342
Kojto 107:4f6c30876dfa 7343 /*----------------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 7344
Kojto 107:4f6c30876dfa 7345 #define TIM_CCMR1_IC1PSC ((uint32_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 107:4f6c30876dfa 7346 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7347 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7348
Kojto 107:4f6c30876dfa 7349 #define TIM_CCMR1_IC1F ((uint32_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 107:4f6c30876dfa 7350 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7351 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7352 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7353 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7354
Kojto 107:4f6c30876dfa 7355 #define TIM_CCMR1_IC2PSC ((uint32_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 107:4f6c30876dfa 7356 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7357 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7358
Kojto 107:4f6c30876dfa 7359 #define TIM_CCMR1_IC2F ((uint32_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 107:4f6c30876dfa 7360 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7361 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7362 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7363 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7364
Kojto 107:4f6c30876dfa 7365 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 107:4f6c30876dfa 7366 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 107:4f6c30876dfa 7367 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7368 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7369
Kojto 107:4f6c30876dfa 7370 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 107:4f6c30876dfa 7371 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 107:4f6c30876dfa 7372
Kojto 107:4f6c30876dfa 7373 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 107:4f6c30876dfa 7374 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7375 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7376 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7377 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7378
Kojto 107:4f6c30876dfa 7379
Kojto 107:4f6c30876dfa 7380
Kojto 107:4f6c30876dfa 7381 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 107:4f6c30876dfa 7382
Kojto 107:4f6c30876dfa 7383 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 107:4f6c30876dfa 7384 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7385 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7386
Kojto 107:4f6c30876dfa 7387 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 107:4f6c30876dfa 7388 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 107:4f6c30876dfa 7389
Kojto 107:4f6c30876dfa 7390 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 107:4f6c30876dfa 7391 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7392 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7393 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7394 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7395
Kojto 107:4f6c30876dfa 7396 #define TIM_CCMR2_OC4CE ((uint32_t)0x8000) /*!<Output Compare 4 Clear Enable */
Kojto 107:4f6c30876dfa 7397
Kojto 107:4f6c30876dfa 7398 /*----------------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 7399
Kojto 107:4f6c30876dfa 7400 #define TIM_CCMR2_IC3PSC ((uint32_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 107:4f6c30876dfa 7401 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x0004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7402 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x0008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7403
Kojto 107:4f6c30876dfa 7404 #define TIM_CCMR2_IC3F ((uint32_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 107:4f6c30876dfa 7405 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x0010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7406 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x0020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7407 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x0040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7408 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x0080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7409
Kojto 107:4f6c30876dfa 7410 #define TIM_CCMR2_IC4PSC ((uint32_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 107:4f6c30876dfa 7411 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7412 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7413
Kojto 107:4f6c30876dfa 7414 #define TIM_CCMR2_IC4F ((uint32_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 107:4f6c30876dfa 7415 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x1000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7416 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x2000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7417 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x4000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7418 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x8000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7419
Kojto 107:4f6c30876dfa 7420 /******************* Bit definition for TIM_CCER register *******************/
Kojto 107:4f6c30876dfa 7421 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 107:4f6c30876dfa 7422 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 107:4f6c30876dfa 7423 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 107:4f6c30876dfa 7424 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 107:4f6c30876dfa 7425 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 107:4f6c30876dfa 7426 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 107:4f6c30876dfa 7427 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 107:4f6c30876dfa 7428 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 107:4f6c30876dfa 7429 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 107:4f6c30876dfa 7430 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 107:4f6c30876dfa 7431 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 107:4f6c30876dfa 7432 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 107:4f6c30876dfa 7433 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 107:4f6c30876dfa 7434 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 107:4f6c30876dfa 7435 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 107:4f6c30876dfa 7436 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
Kojto 107:4f6c30876dfa 7437 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
Kojto 107:4f6c30876dfa 7438 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
Kojto 107:4f6c30876dfa 7439 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
Kojto 107:4f6c30876dfa 7440
Kojto 107:4f6c30876dfa 7441
Kojto 107:4f6c30876dfa 7442 /******************* Bit definition for TIM_CNT register ********************/
Kojto 107:4f6c30876dfa 7443 #define TIM_CNT_CNT ((uint32_t)0xFFFF) /*!<Counter Value */
Kojto 107:4f6c30876dfa 7444
Kojto 107:4f6c30876dfa 7445 /******************* Bit definition for TIM_PSC register ********************/
Kojto 107:4f6c30876dfa 7446 #define TIM_PSC_PSC ((uint32_t)0xFFFF) /*!<Prescaler Value */
Kojto 107:4f6c30876dfa 7447
Kojto 107:4f6c30876dfa 7448 /******************* Bit definition for TIM_ARR register ********************/
Kojto 107:4f6c30876dfa 7449 #define TIM_ARR_ARR ((uint32_t)0xFFFF) /*!<actual auto-reload Value */
Kojto 107:4f6c30876dfa 7450
Kojto 107:4f6c30876dfa 7451 /******************* Bit definition for TIM_RCR register ********************/
Kojto 107:4f6c30876dfa 7452 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
Kojto 107:4f6c30876dfa 7453
Kojto 107:4f6c30876dfa 7454 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 107:4f6c30876dfa 7455 #define TIM_CCR1_CCR1 ((uint32_t)0xFFFF) /*!<Capture/Compare 1 Value */
Kojto 107:4f6c30876dfa 7456
Kojto 107:4f6c30876dfa 7457 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 107:4f6c30876dfa 7458 #define TIM_CCR2_CCR2 ((uint32_t)0xFFFF) /*!<Capture/Compare 2 Value */
Kojto 107:4f6c30876dfa 7459
Kojto 107:4f6c30876dfa 7460 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 107:4f6c30876dfa 7461 #define TIM_CCR3_CCR3 ((uint32_t)0xFFFF) /*!<Capture/Compare 3 Value */
Kojto 107:4f6c30876dfa 7462
Kojto 107:4f6c30876dfa 7463 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 107:4f6c30876dfa 7464 #define TIM_CCR4_CCR4 ((uint32_t)0xFFFF) /*!<Capture/Compare 4 Value */
Kojto 107:4f6c30876dfa 7465
Kojto 107:4f6c30876dfa 7466 /******************* Bit definition for TIM_BDTR register *******************/
Kojto 107:4f6c30876dfa 7467 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 107:4f6c30876dfa 7468 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7469 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7470 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7471 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7472 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 7473 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 7474 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 7475 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 7476
Kojto 107:4f6c30876dfa 7477 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 107:4f6c30876dfa 7478 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7479 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7480
Kojto 107:4f6c30876dfa 7481 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 107:4f6c30876dfa 7482 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 107:4f6c30876dfa 7483 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Kojto 107:4f6c30876dfa 7484 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Kojto 107:4f6c30876dfa 7485 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 107:4f6c30876dfa 7486 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 107:4f6c30876dfa 7487 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
Kojto 107:4f6c30876dfa 7488 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
Kojto 107:4f6c30876dfa 7489 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
Kojto 107:4f6c30876dfa 7490 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
Kojto 107:4f6c30876dfa 7491
Kojto 107:4f6c30876dfa 7492 /******************* Bit definition for TIM_DCR register ********************/
Kojto 107:4f6c30876dfa 7493 #define TIM_DCR_DBA ((uint32_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 107:4f6c30876dfa 7494 #define TIM_DCR_DBA_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7495 #define TIM_DCR_DBA_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7496 #define TIM_DCR_DBA_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7497 #define TIM_DCR_DBA_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7498 #define TIM_DCR_DBA_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 7499
Kojto 107:4f6c30876dfa 7500 #define TIM_DCR_DBL ((uint32_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 107:4f6c30876dfa 7501 #define TIM_DCR_DBL_0 ((uint32_t)0x0100) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7502 #define TIM_DCR_DBL_1 ((uint32_t)0x0200) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7503 #define TIM_DCR_DBL_2 ((uint32_t)0x0400) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7504 #define TIM_DCR_DBL_3 ((uint32_t)0x0800) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7505 #define TIM_DCR_DBL_4 ((uint32_t)0x1000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 7506
Kojto 107:4f6c30876dfa 7507 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 107:4f6c30876dfa 7508 #define TIM_DMAR_DMAB ((uint32_t)0xFFFF) /*!<DMA register for burst accesses */
Kojto 107:4f6c30876dfa 7509
Kojto 107:4f6c30876dfa 7510 /******************* Bit definition for TIM_OR register *********************/
Kojto 107:4f6c30876dfa 7511 #define TIM_OR_TI4_RMP ((uint32_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
Kojto 107:4f6c30876dfa 7512 #define TIM_OR_TI4_RMP_0 ((uint32_t)0x0040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7513 #define TIM_OR_TI4_RMP_1 ((uint32_t)0x0080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7514 #define TIM_OR_ITR1_RMP ((uint32_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
Kojto 107:4f6c30876dfa 7515 #define TIM_OR_ITR1_RMP_0 ((uint32_t)0x0400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7516 #define TIM_OR_ITR1_RMP_1 ((uint32_t)0x0800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7517
Kojto 107:4f6c30876dfa 7518 /****************** Bit definition for TIM_CCMR3 register *******************/
Kojto 107:4f6c30876dfa 7519 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
Kojto 107:4f6c30876dfa 7520 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
Kojto 107:4f6c30876dfa 7521
Kojto 107:4f6c30876dfa 7522 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
Kojto 107:4f6c30876dfa 7523 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7524 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7525 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7526 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7527
Kojto 107:4f6c30876dfa 7528 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
Kojto 107:4f6c30876dfa 7529
Kojto 107:4f6c30876dfa 7530 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 107:4f6c30876dfa 7531 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 107:4f6c30876dfa 7532
Kojto 107:4f6c30876dfa 7533 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 107:4f6c30876dfa 7534 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7535 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7536 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 7537 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 7538
Kojto 107:4f6c30876dfa 7539 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 107:4f6c30876dfa 7540
Kojto 107:4f6c30876dfa 7541 /******************* Bit definition for TIM_CCR5 register *******************/
Kojto 107:4f6c30876dfa 7542 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
Kojto 107:4f6c30876dfa 7543 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
Kojto 107:4f6c30876dfa 7544 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
Kojto 107:4f6c30876dfa 7545 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
Kojto 107:4f6c30876dfa 7546
Kojto 107:4f6c30876dfa 7547 /******************* Bit definition for TIM_CCR6 register *******************/
Kojto 107:4f6c30876dfa 7548 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
Kojto 107:4f6c30876dfa 7549
Kojto 116:c0f6e94411f5 7550
Kojto 107:4f6c30876dfa 7551 /******************************************************************************/
Kojto 107:4f6c30876dfa 7552 /* */
Kojto 107:4f6c30876dfa 7553 /* Low Power Timer (LPTIM) */
Kojto 107:4f6c30876dfa 7554 /* */
Kojto 107:4f6c30876dfa 7555 /******************************************************************************/
Kojto 107:4f6c30876dfa 7556 /****************** Bit definition for LPTIM_ISR register *******************/
Kojto 107:4f6c30876dfa 7557 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001) /*!< Compare match */
Kojto 107:4f6c30876dfa 7558 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002) /*!< Autoreload match */
Kojto 107:4f6c30876dfa 7559 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004) /*!< External trigger edge event */
Kojto 107:4f6c30876dfa 7560 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008) /*!< Compare register update OK */
Kojto 107:4f6c30876dfa 7561 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010) /*!< Autoreload register update OK */
Kojto 107:4f6c30876dfa 7562 #define LPTIM_ISR_UP ((uint32_t)0x00000020) /*!< Counter direction change down to up */
Kojto 107:4f6c30876dfa 7563 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040) /*!< Counter direction change up to down */
Kojto 107:4f6c30876dfa 7564
Kojto 107:4f6c30876dfa 7565 /****************** Bit definition for LPTIM_ICR register *******************/
Kojto 107:4f6c30876dfa 7566 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001) /*!< Compare match Clear Flag */
Kojto 107:4f6c30876dfa 7567 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002) /*!< Autoreload match Clear Flag */
Kojto 107:4f6c30876dfa 7568 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004) /*!< External trigger edge event Clear Flag */
Kojto 107:4f6c30876dfa 7569 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008) /*!< Compare register update OK Clear Flag */
Kojto 107:4f6c30876dfa 7570 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010) /*!< Autoreload register update OK Clear Flag */
Kojto 107:4f6c30876dfa 7571 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020) /*!< Counter direction change down to up Clear Flag */
Kojto 107:4f6c30876dfa 7572 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040) /*!< Counter direction change up to down Clear Flag */
Kojto 107:4f6c30876dfa 7573
Kojto 107:4f6c30876dfa 7574 /****************** Bit definition for LPTIM_IER register ********************/
Kojto 107:4f6c30876dfa 7575 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001) /*!< Compare match Interrupt Enable */
Kojto 107:4f6c30876dfa 7576 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002) /*!< Autoreload match Interrupt Enable */
Kojto 107:4f6c30876dfa 7577 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004) /*!< External trigger edge event Interrupt Enable */
Kojto 107:4f6c30876dfa 7578 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008) /*!< Compare register update OK Interrupt Enable */
Kojto 107:4f6c30876dfa 7579 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010) /*!< Autoreload register update OK Interrupt Enable */
Kojto 107:4f6c30876dfa 7580 #define LPTIM_IER_UPIE ((uint32_t)0x00000020) /*!< Counter direction change down to up Interrupt Enable */
Kojto 107:4f6c30876dfa 7581 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040) /*!< Counter direction change up to down Interrupt Enable */
Kojto 107:4f6c30876dfa 7582
Kojto 107:4f6c30876dfa 7583 /****************** Bit definition for LPTIM_CFGR register *******************/
Kojto 107:4f6c30876dfa 7584 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001) /*!< Clock selector */
Kojto 107:4f6c30876dfa 7585
Kojto 107:4f6c30876dfa 7586 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006) /*!< CKPOL[1:0] bits (Clock polarity) */
Kojto 107:4f6c30876dfa 7587 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7588 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7589
Kojto 107:4f6c30876dfa 7590 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
Kojto 107:4f6c30876dfa 7591 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7592 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7593
Kojto 107:4f6c30876dfa 7594 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
Kojto 107:4f6c30876dfa 7595 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7596 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7597
Kojto 107:4f6c30876dfa 7598 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00) /*!< PRESC[2:0] bits (Clock prescaler) */
Kojto 107:4f6c30876dfa 7599 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7600 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7601 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 7602
Kojto 107:4f6c30876dfa 7603 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
Kojto 107:4f6c30876dfa 7604 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7605 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7606 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 7607
Kojto 107:4f6c30876dfa 7608 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
Kojto 107:4f6c30876dfa 7609 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7610 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7611
Kojto 107:4f6c30876dfa 7612 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000) /*!< Timout enable */
Kojto 107:4f6c30876dfa 7613 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000) /*!< Waveform shape */
Kojto 107:4f6c30876dfa 7614 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000) /*!< Waveform shape polarity */
Kojto 107:4f6c30876dfa 7615 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000) /*!< Reg update mode */
Kojto 107:4f6c30876dfa 7616 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000) /*!< Counter mode enable */
Kojto 107:4f6c30876dfa 7617 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000) /*!< Encoder mode enable */
Kojto 107:4f6c30876dfa 7618
Kojto 107:4f6c30876dfa 7619 /****************** Bit definition for LPTIM_CR register ********************/
Kojto 107:4f6c30876dfa 7620 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001) /*!< LPTIMer enable */
Kojto 107:4f6c30876dfa 7621 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00080002) /*!< Timer start in single mode */
Kojto 107:4f6c30876dfa 7622 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004) /*!< Timer start in continuous mode */
Kojto 107:4f6c30876dfa 7623
Kojto 107:4f6c30876dfa 7624 /****************** Bit definition for LPTIM_CMP register *******************/
Kojto 107:4f6c30876dfa 7625 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFF) /*!< Compare register */
Kojto 107:4f6c30876dfa 7626
Kojto 107:4f6c30876dfa 7627 /****************** Bit definition for LPTIM_ARR register *******************/
Kojto 107:4f6c30876dfa 7628 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!< Auto reload register */
Kojto 107:4f6c30876dfa 7629
Kojto 107:4f6c30876dfa 7630 /****************** Bit definition for LPTIM_CNT register *******************/
Kojto 107:4f6c30876dfa 7631 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!< Counter register */
Kojto 107:4f6c30876dfa 7632 /******************************************************************************/
Kojto 107:4f6c30876dfa 7633 /* */
Kojto 107:4f6c30876dfa 7634 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 107:4f6c30876dfa 7635 /* */
Kojto 107:4f6c30876dfa 7636 /******************************************************************************/
Kojto 107:4f6c30876dfa 7637 /****************** Bit definition for USART_CR1 register *******************/
Kojto 107:4f6c30876dfa 7638 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Kojto 107:4f6c30876dfa 7639 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 107:4f6c30876dfa 7640 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 107:4f6c30876dfa 7641 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 107:4f6c30876dfa 7642 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 107:4f6c30876dfa 7643 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 107:4f6c30876dfa 7644 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Kojto 107:4f6c30876dfa 7645 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 107:4f6c30876dfa 7646 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 107:4f6c30876dfa 7647 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 107:4f6c30876dfa 7648 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Kojto 107:4f6c30876dfa 7649 #define USART_CR1_M ((uint32_t)0x10001000) /*!< Word length */
Kojto 107:4f6c30876dfa 7650 #define USART_CR1_M_0 ((uint32_t)0x00001000) /*!< Word length - Bit 0 */
Kojto 107:4f6c30876dfa 7651 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Kojto 107:4f6c30876dfa 7652 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Kojto 107:4f6c30876dfa 7653 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 107:4f6c30876dfa 7654 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 107:4f6c30876dfa 7655 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7656 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7657 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 7658 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 7659 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 7660 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 107:4f6c30876dfa 7661 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7662 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7663 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 7664 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Kojto 107:4f6c30876dfa 7665 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Kojto 107:4f6c30876dfa 7666 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Kojto 107:4f6c30876dfa 7667 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Kojto 107:4f6c30876dfa 7668 #define USART_CR1_M_1 ((uint32_t)0x10000000) /*!< Word length - Bit 1 */
Kojto 107:4f6c30876dfa 7669
Kojto 107:4f6c30876dfa 7670 /****************** Bit definition for USART_CR2 register *******************/
Kojto 107:4f6c30876dfa 7671 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Kojto 107:4f6c30876dfa 7672 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Kojto 107:4f6c30876dfa 7673 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Kojto 107:4f6c30876dfa 7674 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 107:4f6c30876dfa 7675 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 107:4f6c30876dfa 7676 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 107:4f6c30876dfa 7677 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 107:4f6c30876dfa 7678 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 107:4f6c30876dfa 7679 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7680 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7681 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Kojto 107:4f6c30876dfa 7682 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Kojto 107:4f6c30876dfa 7683 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Kojto 107:4f6c30876dfa 7684 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Kojto 107:4f6c30876dfa 7685 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Kojto 107:4f6c30876dfa 7686 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Kojto 107:4f6c30876dfa 7687 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable */
Kojto 107:4f6c30876dfa 7688 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 107:4f6c30876dfa 7689 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7690 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7691 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Kojto 107:4f6c30876dfa 7692 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Kojto 107:4f6c30876dfa 7693
Kojto 107:4f6c30876dfa 7694 /****************** Bit definition for USART_CR3 register *******************/
Kojto 107:4f6c30876dfa 7695 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 107:4f6c30876dfa 7696 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Kojto 107:4f6c30876dfa 7697 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Kojto 107:4f6c30876dfa 7698 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 107:4f6c30876dfa 7699 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
Kojto 107:4f6c30876dfa 7700 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
Kojto 107:4f6c30876dfa 7701 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 107:4f6c30876dfa 7702 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 107:4f6c30876dfa 7703 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 107:4f6c30876dfa 7704 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 107:4f6c30876dfa 7705 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 107:4f6c30876dfa 7706 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Kojto 107:4f6c30876dfa 7707 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Kojto 107:4f6c30876dfa 7708 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Kojto 107:4f6c30876dfa 7709 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Kojto 107:4f6c30876dfa 7710 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Kojto 107:4f6c30876dfa 7711 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 107:4f6c30876dfa 7712 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 107:4f6c30876dfa 7713 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 107:4f6c30876dfa 7714 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Kojto 107:4f6c30876dfa 7715
Kojto 116:c0f6e94411f5 7716
Kojto 107:4f6c30876dfa 7717 /****************** Bit definition for USART_BRR register *******************/
Kojto 107:4f6c30876dfa 7718 #define USART_BRR_DIV_FRACTION ((uint32_t)0x000F) /*!< Fraction of USARTDIV */
Kojto 107:4f6c30876dfa 7719 #define USART_BRR_DIV_MANTISSA ((uint32_t)0xFFF0) /*!< Mantissa of USARTDIV */
Kojto 107:4f6c30876dfa 7720
Kojto 107:4f6c30876dfa 7721 /****************** Bit definition for USART_GTPR register ******************/
Kojto 107:4f6c30876dfa 7722 #define USART_GTPR_PSC ((uint32_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 107:4f6c30876dfa 7723 #define USART_GTPR_GT ((uint32_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
Kojto 107:4f6c30876dfa 7724
Kojto 107:4f6c30876dfa 7725
Kojto 107:4f6c30876dfa 7726 /******************* Bit definition for USART_RTOR register *****************/
Kojto 107:4f6c30876dfa 7727 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Kojto 107:4f6c30876dfa 7728 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Kojto 107:4f6c30876dfa 7729
Kojto 107:4f6c30876dfa 7730 /******************* Bit definition for USART_RQR register ******************/
Kojto 107:4f6c30876dfa 7731 #define USART_RQR_ABRRQ ((uint32_t)0x0001) /*!< Auto-Baud Rate Request */
Kojto 107:4f6c30876dfa 7732 #define USART_RQR_SBKRQ ((uint32_t)0x0002) /*!< Send Break Request */
Kojto 107:4f6c30876dfa 7733 #define USART_RQR_MMRQ ((uint32_t)0x0004) /*!< Mute Mode Request */
Kojto 107:4f6c30876dfa 7734 #define USART_RQR_RXFRQ ((uint32_t)0x0008) /*!< Receive Data flush Request */
Kojto 107:4f6c30876dfa 7735 #define USART_RQR_TXFRQ ((uint32_t)0x0010) /*!< Transmit data flush Request */
Kojto 107:4f6c30876dfa 7736
Kojto 107:4f6c30876dfa 7737 /******************* Bit definition for USART_ISR register ******************/
Kojto 107:4f6c30876dfa 7738 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 107:4f6c30876dfa 7739 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 107:4f6c30876dfa 7740 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Kojto 107:4f6c30876dfa 7741 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 107:4f6c30876dfa 7742 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 107:4f6c30876dfa 7743 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 107:4f6c30876dfa 7744 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 107:4f6c30876dfa 7745 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 107:4f6c30876dfa 7746 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Kojto 107:4f6c30876dfa 7747 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Kojto 107:4f6c30876dfa 7748 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Kojto 107:4f6c30876dfa 7749 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Kojto 107:4f6c30876dfa 7750 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Kojto 107:4f6c30876dfa 7751 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Kojto 107:4f6c30876dfa 7752 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Kojto 107:4f6c30876dfa 7753 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Kojto 107:4f6c30876dfa 7754 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Kojto 107:4f6c30876dfa 7755 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Kojto 107:4f6c30876dfa 7756 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
Kojto 107:4f6c30876dfa 7757 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
Kojto 107:4f6c30876dfa 7758 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Kojto 107:4f6c30876dfa 7759 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Kojto 107:4f6c30876dfa 7760
Kojto 107:4f6c30876dfa 7761 /******************* Bit definition for USART_ICR register ******************/
Kojto 107:4f6c30876dfa 7762 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Kojto 107:4f6c30876dfa 7763 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Kojto 107:4f6c30876dfa 7764 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Kojto 107:4f6c30876dfa 7765 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Kojto 107:4f6c30876dfa 7766 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Kojto 107:4f6c30876dfa 7767 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Kojto 107:4f6c30876dfa 7768 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
Kojto 107:4f6c30876dfa 7769 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Kojto 107:4f6c30876dfa 7770 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Kojto 107:4f6c30876dfa 7771 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
Kojto 107:4f6c30876dfa 7772 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Kojto 107:4f6c30876dfa 7773 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
Kojto 107:4f6c30876dfa 7774
Kojto 107:4f6c30876dfa 7775 /******************* Bit definition for USART_RDR register ******************/
Kojto 107:4f6c30876dfa 7776 #define USART_RDR_RDR ((uint32_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 107:4f6c30876dfa 7777
Kojto 107:4f6c30876dfa 7778 /******************* Bit definition for USART_TDR register ******************/
Kojto 107:4f6c30876dfa 7779 #define USART_TDR_TDR ((uint32_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 107:4f6c30876dfa 7780
Kojto 107:4f6c30876dfa 7781 /******************************************************************************/
Kojto 107:4f6c30876dfa 7782 /* */
Kojto 107:4f6c30876dfa 7783 /* Window WATCHDOG */
Kojto 107:4f6c30876dfa 7784 /* */
Kojto 107:4f6c30876dfa 7785 /******************************************************************************/
Kojto 107:4f6c30876dfa 7786 /******************* Bit definition for WWDG_CR register ********************/
Kojto 116:c0f6e94411f5 7787 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 116:c0f6e94411f5 7788 #define WWDG_CR_T_0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 116:c0f6e94411f5 7789 #define WWDG_CR_T_1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 116:c0f6e94411f5 7790 #define WWDG_CR_T_2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 116:c0f6e94411f5 7791 #define WWDG_CR_T_3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 116:c0f6e94411f5 7792 #define WWDG_CR_T_4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 116:c0f6e94411f5 7793 #define WWDG_CR_T_5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 116:c0f6e94411f5 7794 #define WWDG_CR_T_6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 116:c0f6e94411f5 7795
Kojto 116:c0f6e94411f5 7796 /* Legacy defines */
Kojto 116:c0f6e94411f5 7797 #define WWDG_CR_T0 WWDG_CR_T_0 /*!<Bit 0 */
Kojto 116:c0f6e94411f5 7798 #define WWDG_CR_T1 WWDG_CR_T_1 /*!<Bit 1 */
Kojto 116:c0f6e94411f5 7799 #define WWDG_CR_T2 WWDG_CR_T_2 /*!<Bit 2 */
Kojto 116:c0f6e94411f5 7800 #define WWDG_CR_T3 WWDG_CR_T_3 /*!<Bit 3 */
Kojto 116:c0f6e94411f5 7801 #define WWDG_CR_T4 WWDG_CR_T_4 /*!<Bit 4 */
Kojto 116:c0f6e94411f5 7802 #define WWDG_CR_T5 WWDG_CR_T_5 /*!<Bit 5 */
Kojto 116:c0f6e94411f5 7803 #define WWDG_CR_T6 WWDG_CR_T_6 /*!<Bit 6 */
Kojto 116:c0f6e94411f5 7804
Kojto 116:c0f6e94411f5 7805 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 107:4f6c30876dfa 7806
Kojto 107:4f6c30876dfa 7807 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 116:c0f6e94411f5 7808 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 116:c0f6e94411f5 7809 #define WWDG_CFR_W_0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 116:c0f6e94411f5 7810 #define WWDG_CFR_W_1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 116:c0f6e94411f5 7811 #define WWDG_CFR_W_2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 116:c0f6e94411f5 7812 #define WWDG_CFR_W_3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 116:c0f6e94411f5 7813 #define WWDG_CFR_W_4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 116:c0f6e94411f5 7814 #define WWDG_CFR_W_5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 116:c0f6e94411f5 7815 #define WWDG_CFR_W_6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 116:c0f6e94411f5 7816
Kojto 116:c0f6e94411f5 7817 /* Legacy defines */
Kojto 116:c0f6e94411f5 7818 #define WWDG_CFR_W0 WWDG_CFR_W_0 /*!<Bit 0 */
Kojto 116:c0f6e94411f5 7819 #define WWDG_CFR_W1 WWDG_CFR_W_1 /*!<Bit 1 */
Kojto 116:c0f6e94411f5 7820 #define WWDG_CFR_W2 WWDG_CFR_W_2 /*!<Bit 2 */
Kojto 116:c0f6e94411f5 7821 #define WWDG_CFR_W3 WWDG_CFR_W_3 /*!<Bit 3 */
Kojto 116:c0f6e94411f5 7822 #define WWDG_CFR_W4 WWDG_CFR_W_4 /*!<Bit 4 */
Kojto 116:c0f6e94411f5 7823 #define WWDG_CFR_W5 WWDG_CFR_W_5 /*!<Bit 5 */
Kojto 116:c0f6e94411f5 7824 #define WWDG_CFR_W6 WWDG_CFR_W_6 /*!<Bit 6 */
Kojto 116:c0f6e94411f5 7825
Kojto 116:c0f6e94411f5 7826 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 116:c0f6e94411f5 7827 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 116:c0f6e94411f5 7828 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 116:c0f6e94411f5 7829
Kojto 116:c0f6e94411f5 7830 /* Legacy defines */
Kojto 116:c0f6e94411f5 7831 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /*!<Bit 0 */
Kojto 116:c0f6e94411f5 7832 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /*!<Bit 1 */
Kojto 116:c0f6e94411f5 7833
Kojto 116:c0f6e94411f5 7834 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 107:4f6c30876dfa 7835
Kojto 107:4f6c30876dfa 7836 /******************* Bit definition for WWDG_SR register ********************/
Kojto 116:c0f6e94411f5 7837 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 107:4f6c30876dfa 7838
Kojto 107:4f6c30876dfa 7839 /******************************************************************************/
Kojto 107:4f6c30876dfa 7840 /* */
Kojto 107:4f6c30876dfa 7841 /* DBG */
Kojto 107:4f6c30876dfa 7842 /* */
Kojto 107:4f6c30876dfa 7843 /******************************************************************************/
Kojto 107:4f6c30876dfa 7844 /******************** Bit definition for DBGMCU_IDCODE register *************/
Kojto 107:4f6c30876dfa 7845 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
Kojto 107:4f6c30876dfa 7846 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
Kojto 107:4f6c30876dfa 7847
Kojto 107:4f6c30876dfa 7848 /******************** Bit definition for DBGMCU_CR register *****************/
Kojto 107:4f6c30876dfa 7849 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 7850 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 7851 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 7852 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 7853
Kojto 107:4f6c30876dfa 7854 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
Kojto 107:4f6c30876dfa 7855 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 7856 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 7857
Kojto 107:4f6c30876dfa 7858 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
Kojto 107:4f6c30876dfa 7859 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 7860 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 7861 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
Kojto 107:4f6c30876dfa 7862 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 7863 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 7864 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 7865 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 7866 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 7867 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 7868 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 7869 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 7870 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 7871 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 7872 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 7873 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 7874 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 7875 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)
Kojto 107:4f6c30876dfa 7876
Kojto 107:4f6c30876dfa 7877 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
Kojto 107:4f6c30876dfa 7878 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 7879 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 7880 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 7881 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 7882 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 7883
Kojto 107:4f6c30876dfa 7884 /******************************************************************************/
Kojto 107:4f6c30876dfa 7885 /* */
Kojto 107:4f6c30876dfa 7886 /* Ethernet MAC Registers bits definitions */
Kojto 107:4f6c30876dfa 7887 /* */
Kojto 107:4f6c30876dfa 7888 /******************************************************************************/
Kojto 107:4f6c30876dfa 7889 /* Bit definition for Ethernet MAC Control Register register */
Kojto 107:4f6c30876dfa 7890 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
Kojto 107:4f6c30876dfa 7891 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
Kojto 107:4f6c30876dfa 7892 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
Kojto 107:4f6c30876dfa 7893 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
Kojto 107:4f6c30876dfa 7894 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
Kojto 107:4f6c30876dfa 7895 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
Kojto 107:4f6c30876dfa 7896 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
Kojto 107:4f6c30876dfa 7897 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
Kojto 107:4f6c30876dfa 7898 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
Kojto 107:4f6c30876dfa 7899 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
Kojto 107:4f6c30876dfa 7900 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
Kojto 107:4f6c30876dfa 7901 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
Kojto 107:4f6c30876dfa 7902 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
Kojto 107:4f6c30876dfa 7903 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
Kojto 107:4f6c30876dfa 7904 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
Kojto 107:4f6c30876dfa 7905 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
Kojto 107:4f6c30876dfa 7906 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
Kojto 107:4f6c30876dfa 7907 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
Kojto 107:4f6c30876dfa 7908 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
Kojto 107:4f6c30876dfa 7909 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Kojto 107:4f6c30876dfa 7910 a transmission attempt during retries after a collision: 0 =< r <2^k */
Kojto 107:4f6c30876dfa 7911 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
Kojto 107:4f6c30876dfa 7912 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
Kojto 107:4f6c30876dfa 7913 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
Kojto 107:4f6c30876dfa 7914 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
Kojto 107:4f6c30876dfa 7915 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
Kojto 107:4f6c30876dfa 7916 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
Kojto 107:4f6c30876dfa 7917 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
Kojto 107:4f6c30876dfa 7918
Kojto 107:4f6c30876dfa 7919 /* Bit definition for Ethernet MAC Frame Filter Register */
Kojto 107:4f6c30876dfa 7920 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
Kojto 107:4f6c30876dfa 7921 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
Kojto 107:4f6c30876dfa 7922 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
Kojto 107:4f6c30876dfa 7923 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
Kojto 107:4f6c30876dfa 7924 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
Kojto 107:4f6c30876dfa 7925 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
Kojto 107:4f6c30876dfa 7926 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
Kojto 107:4f6c30876dfa 7927 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
Kojto 107:4f6c30876dfa 7928 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
Kojto 107:4f6c30876dfa 7929 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
Kojto 107:4f6c30876dfa 7930 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
Kojto 107:4f6c30876dfa 7931 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
Kojto 107:4f6c30876dfa 7932 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
Kojto 107:4f6c30876dfa 7933 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
Kojto 107:4f6c30876dfa 7934
Kojto 107:4f6c30876dfa 7935 /* Bit definition for Ethernet MAC Hash Table High Register */
Kojto 107:4f6c30876dfa 7936 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
Kojto 107:4f6c30876dfa 7937
Kojto 107:4f6c30876dfa 7938 /* Bit definition for Ethernet MAC Hash Table Low Register */
Kojto 107:4f6c30876dfa 7939 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
Kojto 107:4f6c30876dfa 7940
Kojto 107:4f6c30876dfa 7941 /* Bit definition for Ethernet MAC MII Address Register */
Kojto 107:4f6c30876dfa 7942 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
Kojto 107:4f6c30876dfa 7943 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
Kojto 107:4f6c30876dfa 7944 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
Kojto 107:4f6c30876dfa 7945 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
Kojto 107:4f6c30876dfa 7946 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
Kojto 107:4f6c30876dfa 7947 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Kojto 107:4f6c30876dfa 7948 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Kojto 107:4f6c30876dfa 7949 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
Kojto 107:4f6c30876dfa 7950 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
Kojto 107:4f6c30876dfa 7951 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
Kojto 107:4f6c30876dfa 7952
Kojto 107:4f6c30876dfa 7953 /* Bit definition for Ethernet MAC MII Data Register */
Kojto 107:4f6c30876dfa 7954 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
Kojto 107:4f6c30876dfa 7955
Kojto 107:4f6c30876dfa 7956 /* Bit definition for Ethernet MAC Flow Control Register */
Kojto 107:4f6c30876dfa 7957 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
Kojto 107:4f6c30876dfa 7958 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
Kojto 107:4f6c30876dfa 7959 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
Kojto 107:4f6c30876dfa 7960 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
Kojto 107:4f6c30876dfa 7961 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
Kojto 107:4f6c30876dfa 7962 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
Kojto 107:4f6c30876dfa 7963 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
Kojto 107:4f6c30876dfa 7964 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
Kojto 107:4f6c30876dfa 7965 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
Kojto 107:4f6c30876dfa 7966 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
Kojto 107:4f6c30876dfa 7967 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
Kojto 107:4f6c30876dfa 7968
Kojto 107:4f6c30876dfa 7969 /* Bit definition for Ethernet MAC VLAN Tag Register */
Kojto 107:4f6c30876dfa 7970 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
Kojto 107:4f6c30876dfa 7971 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
Kojto 107:4f6c30876dfa 7972
Kojto 107:4f6c30876dfa 7973 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Kojto 107:4f6c30876dfa 7974 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
Kojto 107:4f6c30876dfa 7975 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Kojto 107:4f6c30876dfa 7976 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Kojto 107:4f6c30876dfa 7977 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Kojto 107:4f6c30876dfa 7978 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Kojto 107:4f6c30876dfa 7979 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Kojto 107:4f6c30876dfa 7980 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Kojto 107:4f6c30876dfa 7981 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Kojto 107:4f6c30876dfa 7982 RSVD - Filter1 Command - RSVD - Filter0 Command
Kojto 107:4f6c30876dfa 7983 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Kojto 107:4f6c30876dfa 7984 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Kojto 107:4f6c30876dfa 7985 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Kojto 107:4f6c30876dfa 7986
Kojto 107:4f6c30876dfa 7987 /* Bit definition for Ethernet MAC PMT Control and Status Register */
Kojto 107:4f6c30876dfa 7988 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
Kojto 107:4f6c30876dfa 7989 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
Kojto 107:4f6c30876dfa 7990 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
Kojto 107:4f6c30876dfa 7991 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
Kojto 107:4f6c30876dfa 7992 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
Kojto 107:4f6c30876dfa 7993 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
Kojto 107:4f6c30876dfa 7994 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
Kojto 107:4f6c30876dfa 7995
Kojto 107:4f6c30876dfa 7996 /* Bit definition for Ethernet MAC Status Register */
Kojto 107:4f6c30876dfa 7997 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
Kojto 107:4f6c30876dfa 7998 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
Kojto 107:4f6c30876dfa 7999 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
Kojto 107:4f6c30876dfa 8000 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
Kojto 107:4f6c30876dfa 8001 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
Kojto 107:4f6c30876dfa 8002
Kojto 107:4f6c30876dfa 8003 /* Bit definition for Ethernet MAC Interrupt Mask Register */
Kojto 107:4f6c30876dfa 8004 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
Kojto 107:4f6c30876dfa 8005 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
Kojto 107:4f6c30876dfa 8006
Kojto 107:4f6c30876dfa 8007 /* Bit definition for Ethernet MAC Address0 High Register */
Kojto 107:4f6c30876dfa 8008 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
Kojto 107:4f6c30876dfa 8009
Kojto 107:4f6c30876dfa 8010 /* Bit definition for Ethernet MAC Address0 Low Register */
Kojto 107:4f6c30876dfa 8011 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
Kojto 107:4f6c30876dfa 8012
Kojto 107:4f6c30876dfa 8013 /* Bit definition for Ethernet MAC Address1 High Register */
Kojto 107:4f6c30876dfa 8014 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto 107:4f6c30876dfa 8015 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto 107:4f6c30876dfa 8016 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Kojto 107:4f6c30876dfa 8017 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto 107:4f6c30876dfa 8018 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto 107:4f6c30876dfa 8019 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto 107:4f6c30876dfa 8020 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto 107:4f6c30876dfa 8021 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto 107:4f6c30876dfa 8022 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
Kojto 107:4f6c30876dfa 8023 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Kojto 107:4f6c30876dfa 8024
Kojto 107:4f6c30876dfa 8025 /* Bit definition for Ethernet MAC Address1 Low Register */
Kojto 107:4f6c30876dfa 8026 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
Kojto 107:4f6c30876dfa 8027
Kojto 107:4f6c30876dfa 8028 /* Bit definition for Ethernet MAC Address2 High Register */
Kojto 107:4f6c30876dfa 8029 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto 107:4f6c30876dfa 8030 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto 107:4f6c30876dfa 8031 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Kojto 107:4f6c30876dfa 8032 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto 107:4f6c30876dfa 8033 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto 107:4f6c30876dfa 8034 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto 107:4f6c30876dfa 8035 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto 107:4f6c30876dfa 8036 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto 107:4f6c30876dfa 8037 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Kojto 107:4f6c30876dfa 8038 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Kojto 107:4f6c30876dfa 8039
Kojto 107:4f6c30876dfa 8040 /* Bit definition for Ethernet MAC Address2 Low Register */
Kojto 107:4f6c30876dfa 8041 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
Kojto 107:4f6c30876dfa 8042
Kojto 107:4f6c30876dfa 8043 /* Bit definition for Ethernet MAC Address3 High Register */
Kojto 107:4f6c30876dfa 8044 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
Kojto 107:4f6c30876dfa 8045 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
Kojto 107:4f6c30876dfa 8046 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Kojto 107:4f6c30876dfa 8047 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Kojto 107:4f6c30876dfa 8048 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Kojto 107:4f6c30876dfa 8049 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Kojto 107:4f6c30876dfa 8050 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Kojto 107:4f6c30876dfa 8051 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Kojto 107:4f6c30876dfa 8052 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Kojto 107:4f6c30876dfa 8053 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
Kojto 107:4f6c30876dfa 8054
Kojto 107:4f6c30876dfa 8055 /* Bit definition for Ethernet MAC Address3 Low Register */
Kojto 107:4f6c30876dfa 8056 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
Kojto 107:4f6c30876dfa 8057
Kojto 107:4f6c30876dfa 8058 /******************************************************************************/
Kojto 107:4f6c30876dfa 8059 /* Ethernet MMC Registers bits definition */
Kojto 107:4f6c30876dfa 8060 /******************************************************************************/
Kojto 107:4f6c30876dfa 8061
Kojto 107:4f6c30876dfa 8062 /* Bit definition for Ethernet MMC Contol Register */
Kojto 107:4f6c30876dfa 8063 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */
Kojto 107:4f6c30876dfa 8064 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */
Kojto 107:4f6c30876dfa 8065 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
Kojto 107:4f6c30876dfa 8066 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
Kojto 107:4f6c30876dfa 8067 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
Kojto 107:4f6c30876dfa 8068 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
Kojto 107:4f6c30876dfa 8069
Kojto 107:4f6c30876dfa 8070 /* Bit definition for Ethernet MMC Receive Interrupt Register */
Kojto 107:4f6c30876dfa 8071 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8072 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8073 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8074
Kojto 107:4f6c30876dfa 8075 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
Kojto 107:4f6c30876dfa 8076 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8077 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8078 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8079
Kojto 107:4f6c30876dfa 8080 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Kojto 107:4f6c30876dfa 8081 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8082 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8083 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8084
Kojto 107:4f6c30876dfa 8085 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Kojto 107:4f6c30876dfa 8086 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8087 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8088 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Kojto 107:4f6c30876dfa 8089
Kojto 107:4f6c30876dfa 8090 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Kojto 107:4f6c30876dfa 8091 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Kojto 107:4f6c30876dfa 8092
Kojto 107:4f6c30876dfa 8093 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Kojto 107:4f6c30876dfa 8094 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Kojto 107:4f6c30876dfa 8095
Kojto 107:4f6c30876dfa 8096 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Kojto 107:4f6c30876dfa 8097 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
Kojto 107:4f6c30876dfa 8098
Kojto 107:4f6c30876dfa 8099 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Kojto 107:4f6c30876dfa 8100 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
Kojto 107:4f6c30876dfa 8101
Kojto 107:4f6c30876dfa 8102 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Kojto 107:4f6c30876dfa 8103 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
Kojto 107:4f6c30876dfa 8104
Kojto 107:4f6c30876dfa 8105 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Kojto 107:4f6c30876dfa 8106 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
Kojto 107:4f6c30876dfa 8107
Kojto 107:4f6c30876dfa 8108 /******************************************************************************/
Kojto 107:4f6c30876dfa 8109 /* Ethernet PTP Registers bits definition */
Kojto 107:4f6c30876dfa 8110 /******************************************************************************/
Kojto 107:4f6c30876dfa 8111
Kojto 107:4f6c30876dfa 8112 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
Kojto 107:4f6c30876dfa 8113 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */
Kojto 107:4f6c30876dfa 8114 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */
Kojto 107:4f6c30876dfa 8115 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */
Kojto 107:4f6c30876dfa 8116 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */
Kojto 107:4f6c30876dfa 8117 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */
Kojto 107:4f6c30876dfa 8118 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */
Kojto 107:4f6c30876dfa 8119 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */
Kojto 107:4f6c30876dfa 8120 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */
Kojto 107:4f6c30876dfa 8121 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */
Kojto 107:4f6c30876dfa 8122
Kojto 107:4f6c30876dfa 8123 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
Kojto 107:4f6c30876dfa 8124 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
Kojto 107:4f6c30876dfa 8125 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
Kojto 107:4f6c30876dfa 8126 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
Kojto 107:4f6c30876dfa 8127 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
Kojto 107:4f6c30876dfa 8128 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
Kojto 107:4f6c30876dfa 8129
Kojto 107:4f6c30876dfa 8130 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
Kojto 107:4f6c30876dfa 8131 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
Kojto 107:4f6c30876dfa 8132
Kojto 107:4f6c30876dfa 8133 /* Bit definition for Ethernet PTP Time Stamp High Register */
Kojto 107:4f6c30876dfa 8134 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
Kojto 107:4f6c30876dfa 8135
Kojto 107:4f6c30876dfa 8136 /* Bit definition for Ethernet PTP Time Stamp Low Register */
Kojto 107:4f6c30876dfa 8137 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
Kojto 107:4f6c30876dfa 8138 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
Kojto 107:4f6c30876dfa 8139
Kojto 107:4f6c30876dfa 8140 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
Kojto 107:4f6c30876dfa 8141 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
Kojto 107:4f6c30876dfa 8142
Kojto 107:4f6c30876dfa 8143 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Kojto 107:4f6c30876dfa 8144 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
Kojto 107:4f6c30876dfa 8145 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
Kojto 107:4f6c30876dfa 8146
Kojto 107:4f6c30876dfa 8147 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
Kojto 107:4f6c30876dfa 8148 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
Kojto 107:4f6c30876dfa 8149
Kojto 107:4f6c30876dfa 8150 /* Bit definition for Ethernet PTP Target Time High Register */
Kojto 107:4f6c30876dfa 8151 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
Kojto 107:4f6c30876dfa 8152
Kojto 107:4f6c30876dfa 8153 /* Bit definition for Ethernet PTP Target Time Low Register */
Kojto 107:4f6c30876dfa 8154 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
Kojto 107:4f6c30876dfa 8155
Kojto 107:4f6c30876dfa 8156 /* Bit definition for Ethernet PTP Time Stamp Status Register */
Kojto 107:4f6c30876dfa 8157 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */
Kojto 107:4f6c30876dfa 8158 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */
Kojto 107:4f6c30876dfa 8159
Kojto 107:4f6c30876dfa 8160 /******************************************************************************/
Kojto 107:4f6c30876dfa 8161 /* Ethernet DMA Registers bits definition */
Kojto 107:4f6c30876dfa 8162 /******************************************************************************/
Kojto 107:4f6c30876dfa 8163
Kojto 107:4f6c30876dfa 8164 /* Bit definition for Ethernet DMA Bus Mode Register */
Kojto 107:4f6c30876dfa 8165 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
Kojto 107:4f6c30876dfa 8166 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
Kojto 107:4f6c30876dfa 8167 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
Kojto 107:4f6c30876dfa 8168 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
Kojto 107:4f6c30876dfa 8169 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto 107:4f6c30876dfa 8170 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto 107:4f6c30876dfa 8171 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 107:4f6c30876dfa 8172 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 107:4f6c30876dfa 8173 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 107:4f6c30876dfa 8174 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 107:4f6c30876dfa 8175 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 107:4f6c30876dfa 8176 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 107:4f6c30876dfa 8177 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 107:4f6c30876dfa 8178 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 107:4f6c30876dfa 8179 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto 107:4f6c30876dfa 8180 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto 107:4f6c30876dfa 8181 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
Kojto 107:4f6c30876dfa 8182 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Kojto 107:4f6c30876dfa 8183 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
Kojto 107:4f6c30876dfa 8184 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
Kojto 107:4f6c30876dfa 8185 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
Kojto 107:4f6c30876dfa 8186 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Kojto 107:4f6c30876dfa 8187 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
Kojto 107:4f6c30876dfa 8188 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto 107:4f6c30876dfa 8189 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto 107:4f6c30876dfa 8190 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 107:4f6c30876dfa 8191 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 107:4f6c30876dfa 8192 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 107:4f6c30876dfa 8193 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 107:4f6c30876dfa 8194 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 107:4f6c30876dfa 8195 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 107:4f6c30876dfa 8196 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 107:4f6c30876dfa 8197 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 107:4f6c30876dfa 8198 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto 107:4f6c30876dfa 8199 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto 107:4f6c30876dfa 8200 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */
Kojto 107:4f6c30876dfa 8201 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
Kojto 107:4f6c30876dfa 8202 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
Kojto 107:4f6c30876dfa 8203 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
Kojto 107:4f6c30876dfa 8204
Kojto 107:4f6c30876dfa 8205 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Kojto 107:4f6c30876dfa 8206 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
Kojto 107:4f6c30876dfa 8207
Kojto 107:4f6c30876dfa 8208 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
Kojto 107:4f6c30876dfa 8209 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
Kojto 107:4f6c30876dfa 8210
Kojto 107:4f6c30876dfa 8211 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Kojto 107:4f6c30876dfa 8212 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
Kojto 107:4f6c30876dfa 8213
Kojto 107:4f6c30876dfa 8214 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Kojto 107:4f6c30876dfa 8215 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
Kojto 107:4f6c30876dfa 8216
Kojto 107:4f6c30876dfa 8217 /* Bit definition for Ethernet DMA Status Register */
Kojto 107:4f6c30876dfa 8218 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
Kojto 107:4f6c30876dfa 8219 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
Kojto 107:4f6c30876dfa 8220 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
Kojto 107:4f6c30876dfa 8221 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
Kojto 107:4f6c30876dfa 8222 /* combination with EBS[2:0] for GetFlagStatus function */
Kojto 107:4f6c30876dfa 8223 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
Kojto 107:4f6c30876dfa 8224 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
Kojto 107:4f6c30876dfa 8225 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
Kojto 107:4f6c30876dfa 8226 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
Kojto 107:4f6c30876dfa 8227 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
Kojto 107:4f6c30876dfa 8228 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
Kojto 107:4f6c30876dfa 8229 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
Kojto 107:4f6c30876dfa 8230 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
Kojto 107:4f6c30876dfa 8231 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
Kojto 107:4f6c30876dfa 8232 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
Kojto 107:4f6c30876dfa 8233 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
Kojto 107:4f6c30876dfa 8234 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
Kojto 107:4f6c30876dfa 8235 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
Kojto 107:4f6c30876dfa 8236 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
Kojto 107:4f6c30876dfa 8237 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
Kojto 107:4f6c30876dfa 8238 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
Kojto 107:4f6c30876dfa 8239 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
Kojto 107:4f6c30876dfa 8240 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
Kojto 107:4f6c30876dfa 8241 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
Kojto 107:4f6c30876dfa 8242 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
Kojto 107:4f6c30876dfa 8243 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
Kojto 107:4f6c30876dfa 8244 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
Kojto 107:4f6c30876dfa 8245 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
Kojto 107:4f6c30876dfa 8246 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
Kojto 107:4f6c30876dfa 8247 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
Kojto 107:4f6c30876dfa 8248 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
Kojto 107:4f6c30876dfa 8249 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
Kojto 107:4f6c30876dfa 8250 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
Kojto 107:4f6c30876dfa 8251 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
Kojto 107:4f6c30876dfa 8252 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
Kojto 107:4f6c30876dfa 8253 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
Kojto 107:4f6c30876dfa 8254 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
Kojto 107:4f6c30876dfa 8255
Kojto 107:4f6c30876dfa 8256 /* Bit definition for Ethernet DMA Operation Mode Register */
Kojto 107:4f6c30876dfa 8257 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
Kojto 107:4f6c30876dfa 8258 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
Kojto 107:4f6c30876dfa 8259 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
Kojto 107:4f6c30876dfa 8260 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
Kojto 107:4f6c30876dfa 8261 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
Kojto 107:4f6c30876dfa 8262 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
Kojto 107:4f6c30876dfa 8263 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto 107:4f6c30876dfa 8264 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto 107:4f6c30876dfa 8265 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto 107:4f6c30876dfa 8266 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto 107:4f6c30876dfa 8267 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto 107:4f6c30876dfa 8268 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto 107:4f6c30876dfa 8269 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto 107:4f6c30876dfa 8270 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto 107:4f6c30876dfa 8271 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
Kojto 107:4f6c30876dfa 8272 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
Kojto 107:4f6c30876dfa 8273 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
Kojto 107:4f6c30876dfa 8274 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
Kojto 107:4f6c30876dfa 8275 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto 107:4f6c30876dfa 8276 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto 107:4f6c30876dfa 8277 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto 107:4f6c30876dfa 8278 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto 107:4f6c30876dfa 8279 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
Kojto 107:4f6c30876dfa 8280 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
Kojto 107:4f6c30876dfa 8281
Kojto 107:4f6c30876dfa 8282 /* Bit definition for Ethernet DMA Interrupt Enable Register */
Kojto 107:4f6c30876dfa 8283 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
Kojto 107:4f6c30876dfa 8284 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
Kojto 107:4f6c30876dfa 8285 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
Kojto 107:4f6c30876dfa 8286 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
Kojto 107:4f6c30876dfa 8287 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
Kojto 107:4f6c30876dfa 8288 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
Kojto 107:4f6c30876dfa 8289 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
Kojto 107:4f6c30876dfa 8290 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
Kojto 107:4f6c30876dfa 8291 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
Kojto 107:4f6c30876dfa 8292 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
Kojto 107:4f6c30876dfa 8293 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
Kojto 107:4f6c30876dfa 8294 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
Kojto 107:4f6c30876dfa 8295 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
Kojto 107:4f6c30876dfa 8296 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
Kojto 107:4f6c30876dfa 8297 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
Kojto 107:4f6c30876dfa 8298
Kojto 107:4f6c30876dfa 8299 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Kojto 107:4f6c30876dfa 8300 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
Kojto 107:4f6c30876dfa 8301 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
Kojto 107:4f6c30876dfa 8302 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
Kojto 107:4f6c30876dfa 8303 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
Kojto 107:4f6c30876dfa 8304
Kojto 107:4f6c30876dfa 8305 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Kojto 107:4f6c30876dfa 8306 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
Kojto 107:4f6c30876dfa 8307
Kojto 107:4f6c30876dfa 8308 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Kojto 107:4f6c30876dfa 8309 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
Kojto 107:4f6c30876dfa 8310
Kojto 107:4f6c30876dfa 8311 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Kojto 107:4f6c30876dfa 8312 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
Kojto 107:4f6c30876dfa 8313
Kojto 107:4f6c30876dfa 8314 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Kojto 107:4f6c30876dfa 8315 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
Kojto 107:4f6c30876dfa 8316
Kojto 107:4f6c30876dfa 8317 /******************************************************************************/
Kojto 107:4f6c30876dfa 8318 /* */
Kojto 107:4f6c30876dfa 8319 /* USB_OTG */
Kojto 107:4f6c30876dfa 8320 /* */
Kojto 107:4f6c30876dfa 8321 /******************************************************************************/
Kojto 107:4f6c30876dfa 8322 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
Kojto 107:4f6c30876dfa 8323 #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */
Kojto 107:4f6c30876dfa 8324 #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */
Kojto 107:4f6c30876dfa 8325 #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */
Kojto 107:4f6c30876dfa 8326 #define USB_OTG_GOTGCTL_VBVALOVAL ((uint32_t)0x00000008) /*!< VBUS valid override value */
Kojto 107:4f6c30876dfa 8327 #define USB_OTG_GOTGCTL_AVALOEN ((uint32_t)0x00000010) /*!< A-peripheral session valid override enable */
Kojto 107:4f6c30876dfa 8328 #define USB_OTG_GOTGCTL_AVALOVAL ((uint32_t)0x00000020) /*!< A-peripheral session valid override value */
Kojto 107:4f6c30876dfa 8329 #define USB_OTG_GOTGCTL_BVALOEN ((uint32_t)0x00000040) /*!< B-peripheral session valid override enable */
Kojto 107:4f6c30876dfa 8330 #define USB_OTG_GOTGCTL_BVALOVAL ((uint32_t)0x00000080) /*!< B-peripheral session valid override value */
Kojto 107:4f6c30876dfa 8331 #define USB_OTG_GOTGCTL_HNGSCS ((uint32_t)0x00000100) /*!< Host set HNP enable */
Kojto 107:4f6c30876dfa 8332 #define USB_OTG_GOTGCTL_HNPRQ ((uint32_t)0x00000200) /*!< HNP request */
Kojto 107:4f6c30876dfa 8333 #define USB_OTG_GOTGCTL_HSHNPEN ((uint32_t)0x00000400) /*!< Host set HNP enable */
Kojto 107:4f6c30876dfa 8334 #define USB_OTG_GOTGCTL_DHNPEN ((uint32_t)0x00000800) /*!< Device HNP enabled */
Kojto 107:4f6c30876dfa 8335 #define USB_OTG_GOTGCTL_EHEN ((uint32_t)0x00001000) /*!< Embedded host enable */
Kojto 107:4f6c30876dfa 8336 #define USB_OTG_GOTGCTL_CIDSTS ((uint32_t)0x00010000) /*!< Connector ID status */
Kojto 107:4f6c30876dfa 8337 #define USB_OTG_GOTGCTL_DBCT ((uint32_t)0x00020000) /*!< Long/short debounce time */
Kojto 107:4f6c30876dfa 8338 #define USB_OTG_GOTGCTL_ASVLD ((uint32_t)0x00040000) /*!< A-session valid */
Kojto 107:4f6c30876dfa 8339 #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */
Kojto 107:4f6c30876dfa 8340 #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */
Kojto 107:4f6c30876dfa 8341
Kojto 107:4f6c30876dfa 8342 /******************** Bit definition for USB_OTG_HCFG register ********************/
Kojto 107:4f6c30876dfa 8343 #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */
Kojto 107:4f6c30876dfa 8344 #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8345 #define USB_OTG_HCFG_FSLSPCS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8346 #define USB_OTG_HCFG_FSLSS ((uint32_t)0x00000004) /*!< FS- and LS-only support */
Kojto 107:4f6c30876dfa 8347
Kojto 107:4f6c30876dfa 8348 /******************** Bit definition for USB_OTG_DCFG register ********************/
Kojto 107:4f6c30876dfa 8349 #define USB_OTG_DCFG_DSPD ((uint32_t)0x00000003) /*!< Device speed */
Kojto 107:4f6c30876dfa 8350 #define USB_OTG_DCFG_DSPD_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8351 #define USB_OTG_DCFG_DSPD_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8352 #define USB_OTG_DCFG_NZLSOHSK ((uint32_t)0x00000004) /*!< Nonzero-length status OUT handshake */
Kojto 107:4f6c30876dfa 8353
Kojto 107:4f6c30876dfa 8354 #define USB_OTG_DCFG_DAD ((uint32_t)0x000007F0) /*!< Device address */
Kojto 107:4f6c30876dfa 8355 #define USB_OTG_DCFG_DAD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8356 #define USB_OTG_DCFG_DAD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8357 #define USB_OTG_DCFG_DAD_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8358 #define USB_OTG_DCFG_DAD_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8359 #define USB_OTG_DCFG_DAD_4 ((uint32_t)0x00000100) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8360 #define USB_OTG_DCFG_DAD_5 ((uint32_t)0x00000200) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8361 #define USB_OTG_DCFG_DAD_6 ((uint32_t)0x00000400) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8362
Kojto 107:4f6c30876dfa 8363 #define USB_OTG_DCFG_PFIVL ((uint32_t)0x00001800) /*!< Periodic (micro)frame interval */
Kojto 107:4f6c30876dfa 8364 #define USB_OTG_DCFG_PFIVL_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8365 #define USB_OTG_DCFG_PFIVL_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8366
Kojto 107:4f6c30876dfa 8367 #define USB_OTG_DCFG_PERSCHIVL ((uint32_t)0x03000000) /*!< Periodic scheduling interval */
Kojto 107:4f6c30876dfa 8368 #define USB_OTG_DCFG_PERSCHIVL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8369 #define USB_OTG_DCFG_PERSCHIVL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8370
Kojto 107:4f6c30876dfa 8371 /******************** Bit definition for USB_OTG_PCGCR register ********************/
Kojto 107:4f6c30876dfa 8372 #define USB_OTG_PCGCR_STPPCLK ((uint32_t)0x00000001) /*!< Stop PHY clock */
Kojto 107:4f6c30876dfa 8373 #define USB_OTG_PCGCR_GATEHCLK ((uint32_t)0x00000002) /*!< Gate HCLK */
Kojto 107:4f6c30876dfa 8374 #define USB_OTG_PCGCR_PHYSUSP ((uint32_t)0x00000010) /*!< PHY suspended */
Kojto 107:4f6c30876dfa 8375
Kojto 107:4f6c30876dfa 8376 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
Kojto 107:4f6c30876dfa 8377 #define USB_OTG_GOTGINT_SEDET ((uint32_t)0x00000004) /*!< Session end detected */
Kojto 107:4f6c30876dfa 8378 #define USB_OTG_GOTGINT_SRSSCHG ((uint32_t)0x00000100) /*!< Session request success status change */
Kojto 107:4f6c30876dfa 8379 #define USB_OTG_GOTGINT_HNSSCHG ((uint32_t)0x00000200) /*!< Host negotiation success status change */
Kojto 107:4f6c30876dfa 8380 #define USB_OTG_GOTGINT_HNGDET ((uint32_t)0x00020000) /*!< Host negotiation detected */
Kojto 107:4f6c30876dfa 8381 #define USB_OTG_GOTGINT_ADTOCHG ((uint32_t)0x00040000) /*!< A-device timeout change */
Kojto 107:4f6c30876dfa 8382 #define USB_OTG_GOTGINT_DBCDNE ((uint32_t)0x00080000) /*!< Debounce done */
Kojto 107:4f6c30876dfa 8383 #define USB_OTG_GOTGINT_IDCHNG ((uint32_t)0x00100000) /*!< Change in ID pin input value */
Kojto 107:4f6c30876dfa 8384
Kojto 107:4f6c30876dfa 8385 /******************** Bit definition for USB_OTG_DCTL register ********************/
Kojto 107:4f6c30876dfa 8386 #define USB_OTG_DCTL_RWUSIG ((uint32_t)0x00000001) /*!< Remote wakeup signaling */
Kojto 107:4f6c30876dfa 8387 #define USB_OTG_DCTL_SDIS ((uint32_t)0x00000002) /*!< Soft disconnect */
Kojto 107:4f6c30876dfa 8388 #define USB_OTG_DCTL_GINSTS ((uint32_t)0x00000004) /*!< Global IN NAK status */
Kojto 107:4f6c30876dfa 8389 #define USB_OTG_DCTL_GONSTS ((uint32_t)0x00000008) /*!< Global OUT NAK status */
Kojto 107:4f6c30876dfa 8390
Kojto 107:4f6c30876dfa 8391 #define USB_OTG_DCTL_TCTL ((uint32_t)0x00000070) /*!< Test control */
Kojto 107:4f6c30876dfa 8392 #define USB_OTG_DCTL_TCTL_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8393 #define USB_OTG_DCTL_TCTL_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8394 #define USB_OTG_DCTL_TCTL_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8395 #define USB_OTG_DCTL_SGINAK ((uint32_t)0x00000080) /*!< Set global IN NAK */
Kojto 107:4f6c30876dfa 8396 #define USB_OTG_DCTL_CGINAK ((uint32_t)0x00000100) /*!< Clear global IN NAK */
Kojto 107:4f6c30876dfa 8397 #define USB_OTG_DCTL_SGONAK ((uint32_t)0x00000200) /*!< Set global OUT NAK */
Kojto 107:4f6c30876dfa 8398 #define USB_OTG_DCTL_CGONAK ((uint32_t)0x00000400) /*!< Clear global OUT NAK */
Kojto 107:4f6c30876dfa 8399 #define USB_OTG_DCTL_POPRGDNE ((uint32_t)0x00000800) /*!< Power-on programming done */
Kojto 107:4f6c30876dfa 8400
Kojto 107:4f6c30876dfa 8401 /******************** Bit definition for USB_OTG_HFIR register ********************/
Kojto 107:4f6c30876dfa 8402 #define USB_OTG_HFIR_FRIVL ((uint32_t)0x0000FFFF) /*!< Frame interval */
Kojto 107:4f6c30876dfa 8403
Kojto 107:4f6c30876dfa 8404 /******************** Bit definition for USB_OTG_HFNUM register ********************/
Kojto 107:4f6c30876dfa 8405 #define USB_OTG_HFNUM_FRNUM ((uint32_t)0x0000FFFF) /*!< Frame number */
Kojto 107:4f6c30876dfa 8406 #define USB_OTG_HFNUM_FTREM ((uint32_t)0xFFFF0000) /*!< Frame time remaining */
Kojto 107:4f6c30876dfa 8407
Kojto 107:4f6c30876dfa 8408 /******************** Bit definition for USB_OTG_DSTS register ********************/
Kojto 107:4f6c30876dfa 8409 #define USB_OTG_DSTS_SUSPSTS ((uint32_t)0x00000001) /*!< Suspend status */
Kojto 107:4f6c30876dfa 8410
Kojto 107:4f6c30876dfa 8411 #define USB_OTG_DSTS_ENUMSPD ((uint32_t)0x00000006) /*!< Enumerated speed */
Kojto 107:4f6c30876dfa 8412 #define USB_OTG_DSTS_ENUMSPD_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8413 #define USB_OTG_DSTS_ENUMSPD_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8414 #define USB_OTG_DSTS_EERR ((uint32_t)0x00000008) /*!< Erratic error */
Kojto 107:4f6c30876dfa 8415 #define USB_OTG_DSTS_FNSOF ((uint32_t)0x003FFF00) /*!< Frame number of the received SOF */
Kojto 107:4f6c30876dfa 8416
Kojto 107:4f6c30876dfa 8417 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
Kojto 107:4f6c30876dfa 8418 #define USB_OTG_GAHBCFG_GINT ((uint32_t)0x00000001) /*!< Global interrupt mask */
Kojto 107:4f6c30876dfa 8419 #define USB_OTG_GAHBCFG_HBSTLEN ((uint32_t)0x0000001E) /*!< Burst length/type */
Kojto 107:4f6c30876dfa 8420 #define USB_OTG_GAHBCFG_HBSTLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8421 #define USB_OTG_GAHBCFG_HBSTLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8422 #define USB_OTG_GAHBCFG_HBSTLEN_2 ((uint32_t)0x00000008) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8423 #define USB_OTG_GAHBCFG_HBSTLEN_3 ((uint32_t)0x00000010) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8424 #define USB_OTG_GAHBCFG_DMAEN ((uint32_t)0x00000020) /*!< DMA enable */
Kojto 107:4f6c30876dfa 8425 #define USB_OTG_GAHBCFG_TXFELVL ((uint32_t)0x00000080) /*!< TxFIFO empty level */
Kojto 107:4f6c30876dfa 8426 #define USB_OTG_GAHBCFG_PTXFELVL ((uint32_t)0x00000100) /*!< Periodic TxFIFO empty level */
Kojto 107:4f6c30876dfa 8427
Kojto 107:4f6c30876dfa 8428 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
Kojto 107:4f6c30876dfa 8429 #define USB_OTG_GUSBCFG_TOCAL ((uint32_t)0x00000007) /*!< FS timeout calibration */
Kojto 107:4f6c30876dfa 8430 #define USB_OTG_GUSBCFG_TOCAL_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8431 #define USB_OTG_GUSBCFG_TOCAL_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8432 #define USB_OTG_GUSBCFG_TOCAL_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8433 #define USB_OTG_GUSBCFG_PHYSEL ((uint32_t)0x00000040) /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
Kojto 107:4f6c30876dfa 8434 #define USB_OTG_GUSBCFG_SRPCAP ((uint32_t)0x00000100) /*!< SRP-capable */
Kojto 107:4f6c30876dfa 8435 #define USB_OTG_GUSBCFG_HNPCAP ((uint32_t)0x00000200) /*!< HNP-capable */
Kojto 107:4f6c30876dfa 8436 #define USB_OTG_GUSBCFG_TRDT ((uint32_t)0x00003C00) /*!< USB turnaround time */
Kojto 107:4f6c30876dfa 8437 #define USB_OTG_GUSBCFG_TRDT_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8438 #define USB_OTG_GUSBCFG_TRDT_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8439 #define USB_OTG_GUSBCFG_TRDT_2 ((uint32_t)0x00001000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8440 #define USB_OTG_GUSBCFG_TRDT_3 ((uint32_t)0x00002000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8441 #define USB_OTG_GUSBCFG_PHYLPCS ((uint32_t)0x00008000) /*!< PHY Low-power clock select */
Kojto 107:4f6c30876dfa 8442 #define USB_OTG_GUSBCFG_ULPIFSLS ((uint32_t)0x00020000) /*!< ULPI FS/LS select */
Kojto 107:4f6c30876dfa 8443 #define USB_OTG_GUSBCFG_ULPIAR ((uint32_t)0x00040000) /*!< ULPI Auto-resume */
Kojto 107:4f6c30876dfa 8444 #define USB_OTG_GUSBCFG_ULPICSM ((uint32_t)0x00080000) /*!< ULPI Clock SuspendM */
Kojto 107:4f6c30876dfa 8445 #define USB_OTG_GUSBCFG_ULPIEVBUSD ((uint32_t)0x00100000) /*!< ULPI External VBUS Drive */
Kojto 107:4f6c30876dfa 8446 #define USB_OTG_GUSBCFG_ULPIEVBUSI ((uint32_t)0x00200000) /*!< ULPI external VBUS indicator */
Kojto 107:4f6c30876dfa 8447 #define USB_OTG_GUSBCFG_TSDPS ((uint32_t)0x00400000) /*!< TermSel DLine pulsing selection */
Kojto 107:4f6c30876dfa 8448 #define USB_OTG_GUSBCFG_PCCI ((uint32_t)0x00800000) /*!< Indicator complement */
Kojto 107:4f6c30876dfa 8449 #define USB_OTG_GUSBCFG_PTCI ((uint32_t)0x01000000) /*!< Indicator pass through */
Kojto 107:4f6c30876dfa 8450 #define USB_OTG_GUSBCFG_ULPIIPD ((uint32_t)0x02000000) /*!< ULPI interface protect disable */
Kojto 107:4f6c30876dfa 8451 #define USB_OTG_GUSBCFG_FHMOD ((uint32_t)0x20000000) /*!< Forced host mode */
Kojto 107:4f6c30876dfa 8452 #define USB_OTG_GUSBCFG_FDMOD ((uint32_t)0x40000000) /*!< Forced peripheral mode */
Kojto 107:4f6c30876dfa 8453 #define USB_OTG_GUSBCFG_CTXPKT ((uint32_t)0x80000000) /*!< Corrupt Tx packet */
Kojto 107:4f6c30876dfa 8454
Kojto 107:4f6c30876dfa 8455 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
Kojto 107:4f6c30876dfa 8456 #define USB_OTG_GRSTCTL_CSRST ((uint32_t)0x00000001) /*!< Core soft reset */
Kojto 107:4f6c30876dfa 8457 #define USB_OTG_GRSTCTL_HSRST ((uint32_t)0x00000002) /*!< HCLK soft reset */
Kojto 107:4f6c30876dfa 8458 #define USB_OTG_GRSTCTL_FCRST ((uint32_t)0x00000004) /*!< Host frame counter reset */
Kojto 107:4f6c30876dfa 8459 #define USB_OTG_GRSTCTL_RXFFLSH ((uint32_t)0x00000010) /*!< RxFIFO flush */
Kojto 107:4f6c30876dfa 8460 #define USB_OTG_GRSTCTL_TXFFLSH ((uint32_t)0x00000020) /*!< TxFIFO flush */
Kojto 107:4f6c30876dfa 8461 #define USB_OTG_GRSTCTL_TXFNUM ((uint32_t)0x000007C0) /*!< TxFIFO number */
Kojto 107:4f6c30876dfa 8462 #define USB_OTG_GRSTCTL_TXFNUM_0 ((uint32_t)0x00000040) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8463 #define USB_OTG_GRSTCTL_TXFNUM_1 ((uint32_t)0x00000080) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8464 #define USB_OTG_GRSTCTL_TXFNUM_2 ((uint32_t)0x00000100) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8465 #define USB_OTG_GRSTCTL_TXFNUM_3 ((uint32_t)0x00000200) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8466 #define USB_OTG_GRSTCTL_TXFNUM_4 ((uint32_t)0x00000400) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8467 #define USB_OTG_GRSTCTL_DMAREQ ((uint32_t)0x40000000) /*!< DMA request signal */
Kojto 107:4f6c30876dfa 8468 #define USB_OTG_GRSTCTL_AHBIDL ((uint32_t)0x80000000) /*!< AHB master idle */
Kojto 107:4f6c30876dfa 8469
Kojto 107:4f6c30876dfa 8470 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
Kojto 107:4f6c30876dfa 8471 #define USB_OTG_DIEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 107:4f6c30876dfa 8472 #define USB_OTG_DIEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 107:4f6c30876dfa 8473 #define USB_OTG_DIEPMSK_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 107:4f6c30876dfa 8474 #define USB_OTG_DIEPMSK_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 107:4f6c30876dfa 8475 #define USB_OTG_DIEPMSK_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 107:4f6c30876dfa 8476 #define USB_OTG_DIEPMSK_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 107:4f6c30876dfa 8477 #define USB_OTG_DIEPMSK_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 107:4f6c30876dfa 8478 #define USB_OTG_DIEPMSK_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 107:4f6c30876dfa 8479
Kojto 107:4f6c30876dfa 8480 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
Kojto 107:4f6c30876dfa 8481 #define USB_OTG_HPTXSTS_PTXFSAVL ((uint32_t)0x0000FFFF) /*!< Periodic transmit data FIFO space available */
Kojto 107:4f6c30876dfa 8482 #define USB_OTG_HPTXSTS_PTXQSAV ((uint32_t)0x00FF0000) /*!< Periodic transmit request queue space available */
Kojto 107:4f6c30876dfa 8483 #define USB_OTG_HPTXSTS_PTXQSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8484 #define USB_OTG_HPTXSTS_PTXQSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8485 #define USB_OTG_HPTXSTS_PTXQSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8486 #define USB_OTG_HPTXSTS_PTXQSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8487 #define USB_OTG_HPTXSTS_PTXQSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8488 #define USB_OTG_HPTXSTS_PTXQSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8489 #define USB_OTG_HPTXSTS_PTXQSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8490 #define USB_OTG_HPTXSTS_PTXQSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 8491
Kojto 107:4f6c30876dfa 8492 #define USB_OTG_HPTXSTS_PTXQTOP ((uint32_t)0xFF000000) /*!< Top of the periodic transmit request queue */
Kojto 107:4f6c30876dfa 8493 #define USB_OTG_HPTXSTS_PTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8494 #define USB_OTG_HPTXSTS_PTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8495 #define USB_OTG_HPTXSTS_PTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8496 #define USB_OTG_HPTXSTS_PTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8497 #define USB_OTG_HPTXSTS_PTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8498 #define USB_OTG_HPTXSTS_PTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8499 #define USB_OTG_HPTXSTS_PTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8500 #define USB_OTG_HPTXSTS_PTXQTOP_7 ((uint32_t)0x80000000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 8501
Kojto 107:4f6c30876dfa 8502 /******************** Bit definition for USB_OTG_HAINT register ********************/
Kojto 107:4f6c30876dfa 8503 #define USB_OTG_HAINT_HAINT ((uint32_t)0x0000FFFF) /*!< Channel interrupts */
Kojto 107:4f6c30876dfa 8504
Kojto 107:4f6c30876dfa 8505 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
Kojto 107:4f6c30876dfa 8506 #define USB_OTG_DOEPMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 107:4f6c30876dfa 8507 #define USB_OTG_DOEPMSK_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 107:4f6c30876dfa 8508 #define USB_OTG_DOEPMSK_STUPM ((uint32_t)0x00000008) /*!< SETUP phase done mask */
Kojto 107:4f6c30876dfa 8509 #define USB_OTG_DOEPMSK_OTEPDM ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled mask */
Kojto 116:c0f6e94411f5 8510 #define USB_OTG_DOEPMSK_OTEPSPRM ((uint32_t)0x00000020) /*!< Status Phase Received mask */
Kojto 107:4f6c30876dfa 8511 #define USB_OTG_DOEPMSK_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received mask */
Kojto 107:4f6c30876dfa 8512 #define USB_OTG_DOEPMSK_OPEM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 107:4f6c30876dfa 8513 #define USB_OTG_DOEPMSK_BOIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 107:4f6c30876dfa 8514
Kojto 107:4f6c30876dfa 8515 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
Kojto 107:4f6c30876dfa 8516 #define USB_OTG_GINTSTS_CMOD ((uint32_t)0x00000001) /*!< Current mode of operation */
Kojto 107:4f6c30876dfa 8517 #define USB_OTG_GINTSTS_MMIS ((uint32_t)0x00000002) /*!< Mode mismatch interrupt */
Kojto 107:4f6c30876dfa 8518 #define USB_OTG_GINTSTS_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt */
Kojto 107:4f6c30876dfa 8519 #define USB_OTG_GINTSTS_SOF ((uint32_t)0x00000008) /*!< Start of frame */
Kojto 107:4f6c30876dfa 8520 #define USB_OTG_GINTSTS_RXFLVL ((uint32_t)0x00000010) /*!< RxFIFO nonempty */
Kojto 107:4f6c30876dfa 8521 #define USB_OTG_GINTSTS_NPTXFE ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty */
Kojto 107:4f6c30876dfa 8522 #define USB_OTG_GINTSTS_GINAKEFF ((uint32_t)0x00000040) /*!< Global IN nonperiodic NAK effective */
Kojto 107:4f6c30876dfa 8523 #define USB_OTG_GINTSTS_BOUTNAKEFF ((uint32_t)0x00000080) /*!< Global OUT NAK effective */
Kojto 107:4f6c30876dfa 8524 #define USB_OTG_GINTSTS_ESUSP ((uint32_t)0x00000400) /*!< Early suspend */
Kojto 107:4f6c30876dfa 8525 #define USB_OTG_GINTSTS_USBSUSP ((uint32_t)0x00000800) /*!< USB suspend */
Kojto 107:4f6c30876dfa 8526 #define USB_OTG_GINTSTS_USBRST ((uint32_t)0x00001000) /*!< USB reset */
Kojto 107:4f6c30876dfa 8527 #define USB_OTG_GINTSTS_ENUMDNE ((uint32_t)0x00002000) /*!< Enumeration done */
Kojto 107:4f6c30876dfa 8528 #define USB_OTG_GINTSTS_ISOODRP ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt */
Kojto 107:4f6c30876dfa 8529 #define USB_OTG_GINTSTS_EOPF ((uint32_t)0x00008000) /*!< End of periodic frame interrupt */
Kojto 107:4f6c30876dfa 8530 #define USB_OTG_GINTSTS_IEPINT ((uint32_t)0x00040000) /*!< IN endpoint interrupt */
Kojto 107:4f6c30876dfa 8531 #define USB_OTG_GINTSTS_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoint interrupt */
Kojto 107:4f6c30876dfa 8532 #define USB_OTG_GINTSTS_IISOIXFR ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer */
Kojto 107:4f6c30876dfa 8533 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT ((uint32_t)0x00200000) /*!< Incomplete periodic transfer */
Kojto 107:4f6c30876dfa 8534 #define USB_OTG_GINTSTS_DATAFSUSP ((uint32_t)0x00400000) /*!< Data fetch suspended */
Kojto 107:4f6c30876dfa 8535 #define USB_OTG_GINTSTS_RSTDET ((uint32_t)0x00800000) /*!< Reset detected interrupt */
Kojto 107:4f6c30876dfa 8536 #define USB_OTG_GINTSTS_HPRTINT ((uint32_t)0x01000000) /*!< Host port interrupt */
Kojto 107:4f6c30876dfa 8537 #define USB_OTG_GINTSTS_HCINT ((uint32_t)0x02000000) /*!< Host channels interrupt */
Kojto 107:4f6c30876dfa 8538 #define USB_OTG_GINTSTS_PTXFE ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty */
Kojto 107:4f6c30876dfa 8539 #define USB_OTG_GINTSTS_LPMINT ((uint32_t)0x08000000) /*!< LPM interrupt */
Kojto 107:4f6c30876dfa 8540 #define USB_OTG_GINTSTS_CIDSCHG ((uint32_t)0x10000000) /*!< Connector ID status change */
Kojto 107:4f6c30876dfa 8541 #define USB_OTG_GINTSTS_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt */
Kojto 107:4f6c30876dfa 8542 #define USB_OTG_GINTSTS_SRQINT ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt */
Kojto 107:4f6c30876dfa 8543 #define USB_OTG_GINTSTS_WKUINT ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt */
Kojto 107:4f6c30876dfa 8544
Kojto 107:4f6c30876dfa 8545 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
Kojto 107:4f6c30876dfa 8546 #define USB_OTG_GINTMSK_MMISM ((uint32_t)0x00000002) /*!< Mode mismatch interrupt mask */
Kojto 107:4f6c30876dfa 8547 #define USB_OTG_GINTMSK_OTGINT ((uint32_t)0x00000004) /*!< OTG interrupt mask */
Kojto 107:4f6c30876dfa 8548 #define USB_OTG_GINTMSK_SOFM ((uint32_t)0x00000008) /*!< Start of frame mask */
Kojto 107:4f6c30876dfa 8549 #define USB_OTG_GINTMSK_RXFLVLM ((uint32_t)0x00000010) /*!< Receive FIFO nonempty mask */
Kojto 107:4f6c30876dfa 8550 #define USB_OTG_GINTMSK_NPTXFEM ((uint32_t)0x00000020) /*!< Nonperiodic TxFIFO empty mask */
Kojto 107:4f6c30876dfa 8551 #define USB_OTG_GINTMSK_GINAKEFFM ((uint32_t)0x00000040) /*!< Global nonperiodic IN NAK effective mask */
Kojto 107:4f6c30876dfa 8552 #define USB_OTG_GINTMSK_GONAKEFFM ((uint32_t)0x00000080) /*!< Global OUT NAK effective mask */
Kojto 107:4f6c30876dfa 8553 #define USB_OTG_GINTMSK_ESUSPM ((uint32_t)0x00000400) /*!< Early suspend mask */
Kojto 107:4f6c30876dfa 8554 #define USB_OTG_GINTMSK_USBSUSPM ((uint32_t)0x00000800) /*!< USB suspend mask */
Kojto 107:4f6c30876dfa 8555 #define USB_OTG_GINTMSK_USBRST ((uint32_t)0x00001000) /*!< USB reset mask */
Kojto 107:4f6c30876dfa 8556 #define USB_OTG_GINTMSK_ENUMDNEM ((uint32_t)0x00002000) /*!< Enumeration done mask */
Kojto 107:4f6c30876dfa 8557 #define USB_OTG_GINTMSK_ISOODRPM ((uint32_t)0x00004000) /*!< Isochronous OUT packet dropped interrupt mask */
Kojto 107:4f6c30876dfa 8558 #define USB_OTG_GINTMSK_EOPFM ((uint32_t)0x00008000) /*!< End of periodic frame interrupt mask */
Kojto 107:4f6c30876dfa 8559 #define USB_OTG_GINTMSK_EPMISM ((uint32_t)0x00020000) /*!< Endpoint mismatch interrupt mask */
Kojto 107:4f6c30876dfa 8560 #define USB_OTG_GINTMSK_IEPINT ((uint32_t)0x00040000) /*!< IN endpoints interrupt mask */
Kojto 107:4f6c30876dfa 8561 #define USB_OTG_GINTMSK_OEPINT ((uint32_t)0x00080000) /*!< OUT endpoints interrupt mask */
Kojto 107:4f6c30876dfa 8562 #define USB_OTG_GINTMSK_IISOIXFRM ((uint32_t)0x00100000) /*!< Incomplete isochronous IN transfer mask */
Kojto 107:4f6c30876dfa 8563 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM ((uint32_t)0x00200000) /*!< Incomplete periodic transfer mask */
Kojto 107:4f6c30876dfa 8564 #define USB_OTG_GINTMSK_FSUSPM ((uint32_t)0x00400000) /*!< Data fetch suspended mask */
Kojto 107:4f6c30876dfa 8565 #define USB_OTG_GINTMSK_RSTDEM ((uint32_t)0x00800000) /*!< Reset detected interrupt mask */
Kojto 107:4f6c30876dfa 8566 #define USB_OTG_GINTMSK_PRTIM ((uint32_t)0x01000000) /*!< Host port interrupt mask */
Kojto 107:4f6c30876dfa 8567 #define USB_OTG_GINTMSK_HCIM ((uint32_t)0x02000000) /*!< Host channels interrupt mask */
Kojto 107:4f6c30876dfa 8568 #define USB_OTG_GINTMSK_PTXFEM ((uint32_t)0x04000000) /*!< Periodic TxFIFO empty mask */
Kojto 107:4f6c30876dfa 8569 #define USB_OTG_GINTMSK_LPMINTM ((uint32_t)0x08000000) /*!< LPM interrupt Mask */
Kojto 107:4f6c30876dfa 8570 #define USB_OTG_GINTMSK_CIDSCHGM ((uint32_t)0x10000000) /*!< Connector ID status change mask */
Kojto 107:4f6c30876dfa 8571 #define USB_OTG_GINTMSK_DISCINT ((uint32_t)0x20000000) /*!< Disconnect detected interrupt mask */
Kojto 107:4f6c30876dfa 8572 #define USB_OTG_GINTMSK_SRQIM ((uint32_t)0x40000000) /*!< Session request/new session detected interrupt mask */
Kojto 107:4f6c30876dfa 8573 #define USB_OTG_GINTMSK_WUIM ((uint32_t)0x80000000) /*!< Resume/remote wakeup detected interrupt mask */
Kojto 107:4f6c30876dfa 8574
Kojto 107:4f6c30876dfa 8575 /******************** Bit definition for USB_OTG_DAINT register ********************/
Kojto 107:4f6c30876dfa 8576 #define USB_OTG_DAINT_IEPINT ((uint32_t)0x0000FFFF) /*!< IN endpoint interrupt bits */
Kojto 107:4f6c30876dfa 8577 #define USB_OTG_DAINT_OEPINT ((uint32_t)0xFFFF0000) /*!< OUT endpoint interrupt bits */
Kojto 107:4f6c30876dfa 8578
Kojto 107:4f6c30876dfa 8579 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
Kojto 107:4f6c30876dfa 8580 #define USB_OTG_HAINTMSK_HAINTM ((uint32_t)0x0000FFFF) /*!< Channel interrupt mask */
Kojto 107:4f6c30876dfa 8581
Kojto 107:4f6c30876dfa 8582 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
Kojto 107:4f6c30876dfa 8583 #define USB_OTG_GRXSTSP_EPNUM ((uint32_t)0x0000000F) /*!< IN EP interrupt mask bits */
Kojto 107:4f6c30876dfa 8584 #define USB_OTG_GRXSTSP_BCNT ((uint32_t)0x00007FF0) /*!< OUT EP interrupt mask bits */
Kojto 107:4f6c30876dfa 8585 #define USB_OTG_GRXSTSP_DPID ((uint32_t)0x00018000) /*!< OUT EP interrupt mask bits */
Kojto 107:4f6c30876dfa 8586 #define USB_OTG_GRXSTSP_PKTSTS ((uint32_t)0x001E0000) /*!< OUT EP interrupt mask bits */
Kojto 107:4f6c30876dfa 8587
Kojto 107:4f6c30876dfa 8588 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
Kojto 107:4f6c30876dfa 8589 #define USB_OTG_DAINTMSK_IEPM ((uint32_t)0x0000FFFF) /*!< IN EP interrupt mask bits */
Kojto 107:4f6c30876dfa 8590 #define USB_OTG_DAINTMSK_OEPM ((uint32_t)0xFFFF0000) /*!< OUT EP interrupt mask bits */
Kojto 107:4f6c30876dfa 8591
Kojto 107:4f6c30876dfa 8592 /******************** Bit definition for OTG register ********************/
Kojto 107:4f6c30876dfa 8593
Kojto 107:4f6c30876dfa 8594 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 107:4f6c30876dfa 8595 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8596 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8597 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8598 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8599 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 107:4f6c30876dfa 8600
Kojto 107:4f6c30876dfa 8601 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 107:4f6c30876dfa 8602 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8603 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8604
Kojto 107:4f6c30876dfa 8605 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 107:4f6c30876dfa 8606 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8607 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8608 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8609 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8610
Kojto 107:4f6c30876dfa 8611 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 107:4f6c30876dfa 8612 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8613 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8614 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8615 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8616
Kojto 107:4f6c30876dfa 8617 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 107:4f6c30876dfa 8618 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8619 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8620 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8621 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8622
Kojto 107:4f6c30876dfa 8623 /******************** Bit definition for OTG register ********************/
Kojto 107:4f6c30876dfa 8624
Kojto 107:4f6c30876dfa 8625 #define USB_OTG_CHNUM ((uint32_t)0x0000000F) /*!< Channel number */
Kojto 107:4f6c30876dfa 8626 #define USB_OTG_CHNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8627 #define USB_OTG_CHNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8628 #define USB_OTG_CHNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8629 #define USB_OTG_CHNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8630 #define USB_OTG_BCNT ((uint32_t)0x00007FF0) /*!< Byte count */
Kojto 107:4f6c30876dfa 8631
Kojto 107:4f6c30876dfa 8632 #define USB_OTG_DPID ((uint32_t)0x00018000) /*!< Data PID */
Kojto 107:4f6c30876dfa 8633 #define USB_OTG_DPID_0 ((uint32_t)0x00008000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8634 #define USB_OTG_DPID_1 ((uint32_t)0x00010000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8635
Kojto 107:4f6c30876dfa 8636 #define USB_OTG_PKTSTS ((uint32_t)0x001E0000) /*!< Packet status */
Kojto 107:4f6c30876dfa 8637 #define USB_OTG_PKTSTS_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8638 #define USB_OTG_PKTSTS_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8639 #define USB_OTG_PKTSTS_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8640 #define USB_OTG_PKTSTS_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8641
Kojto 107:4f6c30876dfa 8642 #define USB_OTG_EPNUM ((uint32_t)0x0000000F) /*!< Endpoint number */
Kojto 107:4f6c30876dfa 8643 #define USB_OTG_EPNUM_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8644 #define USB_OTG_EPNUM_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8645 #define USB_OTG_EPNUM_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8646 #define USB_OTG_EPNUM_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8647
Kojto 107:4f6c30876dfa 8648 #define USB_OTG_FRMNUM ((uint32_t)0x01E00000) /*!< Frame number */
Kojto 107:4f6c30876dfa 8649 #define USB_OTG_FRMNUM_0 ((uint32_t)0x00200000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8650 #define USB_OTG_FRMNUM_1 ((uint32_t)0x00400000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8651 #define USB_OTG_FRMNUM_2 ((uint32_t)0x00800000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8652 #define USB_OTG_FRMNUM_3 ((uint32_t)0x01000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8653
Kojto 107:4f6c30876dfa 8654 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
Kojto 107:4f6c30876dfa 8655 #define USB_OTG_GRXFSIZ_RXFD ((uint32_t)0x0000FFFF) /*!< RxFIFO depth */
Kojto 107:4f6c30876dfa 8656
Kojto 107:4f6c30876dfa 8657 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
Kojto 107:4f6c30876dfa 8658 #define USB_OTG_DVBUSDIS_VBUSDT ((uint32_t)0x0000FFFF) /*!< Device VBUS discharge time */
Kojto 107:4f6c30876dfa 8659
Kojto 107:4f6c30876dfa 8660 /******************** Bit definition for OTG register ********************/
Kojto 107:4f6c30876dfa 8661 #define USB_OTG_NPTXFSA ((uint32_t)0x0000FFFF) /*!< Nonperiodic transmit RAM start address */
Kojto 107:4f6c30876dfa 8662 #define USB_OTG_NPTXFD ((uint32_t)0xFFFF0000) /*!< Nonperiodic TxFIFO depth */
Kojto 107:4f6c30876dfa 8663 #define USB_OTG_TX0FSA ((uint32_t)0x0000FFFF) /*!< Endpoint 0 transmit RAM start address */
Kojto 107:4f6c30876dfa 8664 #define USB_OTG_TX0FD ((uint32_t)0xFFFF0000) /*!< Endpoint 0 TxFIFO depth */
Kojto 107:4f6c30876dfa 8665
Kojto 107:4f6c30876dfa 8666 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
Kojto 107:4f6c30876dfa 8667 #define USB_OTG_DVBUSPULSE_DVBUSP ((uint32_t)0x00000FFF) /*!< Device VBUS pulsing time */
Kojto 107:4f6c30876dfa 8668
Kojto 107:4f6c30876dfa 8669 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
Kojto 107:4f6c30876dfa 8670 #define USB_OTG_GNPTXSTS_NPTXFSAV ((uint32_t)0x0000FFFF) /*!< Nonperiodic TxFIFO space available */
Kojto 107:4f6c30876dfa 8671
Kojto 107:4f6c30876dfa 8672 #define USB_OTG_GNPTXSTS_NPTQXSAV ((uint32_t)0x00FF0000) /*!< Nonperiodic transmit request queue space available */
Kojto 107:4f6c30876dfa 8673 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 ((uint32_t)0x00010000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8674 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 ((uint32_t)0x00020000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8675 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 ((uint32_t)0x00040000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8676 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 ((uint32_t)0x00080000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8677 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 ((uint32_t)0x00100000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8678 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 ((uint32_t)0x00200000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8679 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 ((uint32_t)0x00400000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8680 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 ((uint32_t)0x00800000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 8681
Kojto 107:4f6c30876dfa 8682 #define USB_OTG_GNPTXSTS_NPTXQTOP ((uint32_t)0x7F000000) /*!< Top of the nonperiodic transmit request queue */
Kojto 107:4f6c30876dfa 8683 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 ((uint32_t)0x01000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8684 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 ((uint32_t)0x02000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8685 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 ((uint32_t)0x04000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8686 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 ((uint32_t)0x08000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8687 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 ((uint32_t)0x10000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8688 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 ((uint32_t)0x20000000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8689 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 ((uint32_t)0x40000000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8690
Kojto 107:4f6c30876dfa 8691 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
Kojto 107:4f6c30876dfa 8692 #define USB_OTG_DTHRCTL_NONISOTHREN ((uint32_t)0x00000001) /*!< Nonisochronous IN endpoints threshold enable */
Kojto 107:4f6c30876dfa 8693 #define USB_OTG_DTHRCTL_ISOTHREN ((uint32_t)0x00000002) /*!< ISO IN endpoint threshold enable */
Kojto 107:4f6c30876dfa 8694
Kojto 107:4f6c30876dfa 8695 #define USB_OTG_DTHRCTL_TXTHRLEN ((uint32_t)0x000007FC) /*!< Transmit threshold length */
Kojto 107:4f6c30876dfa 8696 #define USB_OTG_DTHRCTL_TXTHRLEN_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8697 #define USB_OTG_DTHRCTL_TXTHRLEN_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8698 #define USB_OTG_DTHRCTL_TXTHRLEN_2 ((uint32_t)0x00000010) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8699 #define USB_OTG_DTHRCTL_TXTHRLEN_3 ((uint32_t)0x00000020) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8700 #define USB_OTG_DTHRCTL_TXTHRLEN_4 ((uint32_t)0x00000040) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8701 #define USB_OTG_DTHRCTL_TXTHRLEN_5 ((uint32_t)0x00000080) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8702 #define USB_OTG_DTHRCTL_TXTHRLEN_6 ((uint32_t)0x00000100) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8703 #define USB_OTG_DTHRCTL_TXTHRLEN_7 ((uint32_t)0x00000200) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 8704 #define USB_OTG_DTHRCTL_TXTHRLEN_8 ((uint32_t)0x00000400) /*!<Bit 8 */
Kojto 107:4f6c30876dfa 8705 #define USB_OTG_DTHRCTL_RXTHREN ((uint32_t)0x00010000) /*!< Receive threshold enable */
Kojto 107:4f6c30876dfa 8706
Kojto 107:4f6c30876dfa 8707 #define USB_OTG_DTHRCTL_RXTHRLEN ((uint32_t)0x03FE0000) /*!< Receive threshold length */
Kojto 107:4f6c30876dfa 8708 #define USB_OTG_DTHRCTL_RXTHRLEN_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8709 #define USB_OTG_DTHRCTL_RXTHRLEN_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8710 #define USB_OTG_DTHRCTL_RXTHRLEN_2 ((uint32_t)0x00080000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8711 #define USB_OTG_DTHRCTL_RXTHRLEN_3 ((uint32_t)0x00100000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8712 #define USB_OTG_DTHRCTL_RXTHRLEN_4 ((uint32_t)0x00200000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8713 #define USB_OTG_DTHRCTL_RXTHRLEN_5 ((uint32_t)0x00400000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8714 #define USB_OTG_DTHRCTL_RXTHRLEN_6 ((uint32_t)0x00800000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8715 #define USB_OTG_DTHRCTL_RXTHRLEN_7 ((uint32_t)0x01000000) /*!<Bit 7 */
Kojto 107:4f6c30876dfa 8716 #define USB_OTG_DTHRCTL_RXTHRLEN_8 ((uint32_t)0x02000000) /*!<Bit 8 */
Kojto 107:4f6c30876dfa 8717 #define USB_OTG_DTHRCTL_ARPEN ((uint32_t)0x08000000) /*!< Arbiter parking enable */
Kojto 107:4f6c30876dfa 8718
Kojto 107:4f6c30876dfa 8719 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
Kojto 107:4f6c30876dfa 8720 #define USB_OTG_DIEPEMPMSK_INEPTXFEM ((uint32_t)0x0000FFFF) /*!< IN EP Tx FIFO empty interrupt mask bits */
Kojto 107:4f6c30876dfa 8721
Kojto 107:4f6c30876dfa 8722 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
Kojto 107:4f6c30876dfa 8723 #define USB_OTG_DEACHINT_IEP1INT ((uint32_t)0x00000002) /*!< IN endpoint 1interrupt bit */
Kojto 107:4f6c30876dfa 8724 #define USB_OTG_DEACHINT_OEP1INT ((uint32_t)0x00020000) /*!< OUT endpoint 1 interrupt bit */
Kojto 107:4f6c30876dfa 8725
Kojto 107:4f6c30876dfa 8726 /******************** Bit definition for USB_OTG_GCCFG register ********************/
Kojto 107:4f6c30876dfa 8727 #define USB_OTG_GCCFG_PWRDWN ((uint32_t)0x00010000) /*!< Power down */
Kojto 107:4f6c30876dfa 8728 #define USB_OTG_GCCFG_VBDEN ((uint32_t)0x00200000) /*!< USB VBUS Detection Enable */
Kojto 107:4f6c30876dfa 8729
Kojto 107:4f6c30876dfa 8730 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
Kojto 107:4f6c30876dfa 8731 #define USB_OTG_GPWRDN_ADPMEN ((uint32_t)0x00000001) /*!< ADP module enable */
Kojto 107:4f6c30876dfa 8732 #define USB_OTG_GPWRDN_ADPIF ((uint32_t)0x00800000) /*!< ADP Interrupt flag */
Kojto 107:4f6c30876dfa 8733
Kojto 107:4f6c30876dfa 8734 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
Kojto 107:4f6c30876dfa 8735 #define USB_OTG_DEACHINTMSK_IEP1INTM ((uint32_t)0x00000002) /*!< IN Endpoint 1 interrupt mask bit */
Kojto 107:4f6c30876dfa 8736 #define USB_OTG_DEACHINTMSK_OEP1INTM ((uint32_t)0x00020000) /*!< OUT Endpoint 1 interrupt mask bit */
Kojto 107:4f6c30876dfa 8737
Kojto 107:4f6c30876dfa 8738 /******************** Bit definition for USB_OTG_CID register ********************/
Kojto 107:4f6c30876dfa 8739 #define USB_OTG_CID_PRODUCT_ID ((uint32_t)0xFFFFFFFF) /*!< Product ID field */
Kojto 107:4f6c30876dfa 8740
Kojto 107:4f6c30876dfa 8741 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
Kojto 107:4f6c30876dfa 8742 #define USB_OTG_GLPMCFG_LPMEN ((uint32_t)0x00000001) /*!< LPM support enable */
Kojto 107:4f6c30876dfa 8743 #define USB_OTG_GLPMCFG_LPMACK ((uint32_t)0x00000002) /*!< LPM Token acknowledge enable */
Kojto 107:4f6c30876dfa 8744 #define USB_OTG_GLPMCFG_BESL ((uint32_t)0x0000003C) /*!< BESL value received with last ACKed LPM Token */
Kojto 107:4f6c30876dfa 8745 #define USB_OTG_GLPMCFG_REMWAKE ((uint32_t)0x00000040) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 107:4f6c30876dfa 8746 #define USB_OTG_GLPMCFG_L1SSEN ((uint32_t)0x00000080) /*!< L1 shallow sleep enable */
Kojto 107:4f6c30876dfa 8747 #define USB_OTG_GLPMCFG_BESLTHRS ((uint32_t)0x00000F00) /*!< BESL threshold */
Kojto 107:4f6c30876dfa 8748 #define USB_OTG_GLPMCFG_L1DSEN ((uint32_t)0x00001000) /*!< L1 deep sleep enable */
Kojto 107:4f6c30876dfa 8749 #define USB_OTG_GLPMCFG_LPMRSP ((uint32_t)0x00006000) /*!< LPM response */
Kojto 107:4f6c30876dfa 8750 #define USB_OTG_GLPMCFG_SLPSTS ((uint32_t)0x00008000) /*!< Port sleep status */
Kojto 107:4f6c30876dfa 8751 #define USB_OTG_GLPMCFG_L1RSMOK ((uint32_t)0x00010000) /*!< Sleep State Resume OK */
Kojto 107:4f6c30876dfa 8752 #define USB_OTG_GLPMCFG_LPMCHIDX ((uint32_t)0x001E0000) /*!< LPM Channel Index */
Kojto 107:4f6c30876dfa 8753 #define USB_OTG_GLPMCFG_LPMRCNT ((uint32_t)0x00E00000) /*!< LPM retry count */
Kojto 107:4f6c30876dfa 8754 #define USB_OTG_GLPMCFG_SNDLPM ((uint32_t)0x01000000) /*!< Send LPM transaction */
Kojto 107:4f6c30876dfa 8755 #define USB_OTG_GLPMCFG_LPMRCNTSTS ((uint32_t)0x0E000000) /*!< LPM retry count status */
Kojto 107:4f6c30876dfa 8756 #define USB_OTG_GLPMCFG_ENBESL ((uint32_t)0x10000000) /*!< Enable best effort service latency */
Kojto 107:4f6c30876dfa 8757
Kojto 107:4f6c30876dfa 8758 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
Kojto 107:4f6c30876dfa 8759 #define USB_OTG_DIEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 107:4f6c30876dfa 8760 #define USB_OTG_DIEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 107:4f6c30876dfa 8761 #define USB_OTG_DIEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask (nonisochronous endpoints) */
Kojto 107:4f6c30876dfa 8762 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 107:4f6c30876dfa 8763 #define USB_OTG_DIEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 107:4f6c30876dfa 8764 #define USB_OTG_DIEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 107:4f6c30876dfa 8765 #define USB_OTG_DIEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< FIFO underrun mask */
Kojto 107:4f6c30876dfa 8766 #define USB_OTG_DIEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 107:4f6c30876dfa 8767 #define USB_OTG_DIEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 107:4f6c30876dfa 8768
Kojto 107:4f6c30876dfa 8769 /******************** Bit definition for USB_OTG_HPRT register ********************/
Kojto 107:4f6c30876dfa 8770 #define USB_OTG_HPRT_PCSTS ((uint32_t)0x00000001) /*!< Port connect status */
Kojto 107:4f6c30876dfa 8771 #define USB_OTG_HPRT_PCDET ((uint32_t)0x00000002) /*!< Port connect detected */
Kojto 107:4f6c30876dfa 8772 #define USB_OTG_HPRT_PENA ((uint32_t)0x00000004) /*!< Port enable */
Kojto 107:4f6c30876dfa 8773 #define USB_OTG_HPRT_PENCHNG ((uint32_t)0x00000008) /*!< Port enable/disable change */
Kojto 107:4f6c30876dfa 8774 #define USB_OTG_HPRT_POCA ((uint32_t)0x00000010) /*!< Port overcurrent active */
Kojto 107:4f6c30876dfa 8775 #define USB_OTG_HPRT_POCCHNG ((uint32_t)0x00000020) /*!< Port overcurrent change */
Kojto 107:4f6c30876dfa 8776 #define USB_OTG_HPRT_PRES ((uint32_t)0x00000040) /*!< Port resume */
Kojto 107:4f6c30876dfa 8777 #define USB_OTG_HPRT_PSUSP ((uint32_t)0x00000080) /*!< Port suspend */
Kojto 107:4f6c30876dfa 8778 #define USB_OTG_HPRT_PRST ((uint32_t)0x00000100) /*!< Port reset */
Kojto 107:4f6c30876dfa 8779
Kojto 107:4f6c30876dfa 8780 #define USB_OTG_HPRT_PLSTS ((uint32_t)0x00000C00) /*!< Port line status */
Kojto 107:4f6c30876dfa 8781 #define USB_OTG_HPRT_PLSTS_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8782 #define USB_OTG_HPRT_PLSTS_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8783 #define USB_OTG_HPRT_PPWR ((uint32_t)0x00001000) /*!< Port power */
Kojto 107:4f6c30876dfa 8784
Kojto 107:4f6c30876dfa 8785 #define USB_OTG_HPRT_PTCTL ((uint32_t)0x0001E000) /*!< Port test control */
Kojto 107:4f6c30876dfa 8786 #define USB_OTG_HPRT_PTCTL_0 ((uint32_t)0x00002000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8787 #define USB_OTG_HPRT_PTCTL_1 ((uint32_t)0x00004000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8788 #define USB_OTG_HPRT_PTCTL_2 ((uint32_t)0x00008000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8789 #define USB_OTG_HPRT_PTCTL_3 ((uint32_t)0x00010000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8790
Kojto 107:4f6c30876dfa 8791 #define USB_OTG_HPRT_PSPD ((uint32_t)0x00060000) /*!< Port speed */
Kojto 107:4f6c30876dfa 8792 #define USB_OTG_HPRT_PSPD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8793 #define USB_OTG_HPRT_PSPD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8794
Kojto 107:4f6c30876dfa 8795 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
Kojto 107:4f6c30876dfa 8796 #define USB_OTG_DOEPEACHMSK1_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed interrupt mask */
Kojto 107:4f6c30876dfa 8797 #define USB_OTG_DOEPEACHMSK1_EPDM ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt mask */
Kojto 107:4f6c30876dfa 8798 #define USB_OTG_DOEPEACHMSK1_TOM ((uint32_t)0x00000008) /*!< Timeout condition mask */
Kojto 107:4f6c30876dfa 8799 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK ((uint32_t)0x00000010) /*!< IN token received when TxFIFO empty mask */
Kojto 107:4f6c30876dfa 8800 #define USB_OTG_DOEPEACHMSK1_INEPNMM ((uint32_t)0x00000020) /*!< IN token received with EP mismatch mask */
Kojto 107:4f6c30876dfa 8801 #define USB_OTG_DOEPEACHMSK1_INEPNEM ((uint32_t)0x00000040) /*!< IN endpoint NAK effective mask */
Kojto 107:4f6c30876dfa 8802 #define USB_OTG_DOEPEACHMSK1_TXFURM ((uint32_t)0x00000100) /*!< OUT packet error mask */
Kojto 107:4f6c30876dfa 8803 #define USB_OTG_DOEPEACHMSK1_BIM ((uint32_t)0x00000200) /*!< BNA interrupt mask */
Kojto 107:4f6c30876dfa 8804 #define USB_OTG_DOEPEACHMSK1_BERRM ((uint32_t)0x00001000) /*!< Bubble error interrupt mask */
Kojto 107:4f6c30876dfa 8805 #define USB_OTG_DOEPEACHMSK1_NAKM ((uint32_t)0x00002000) /*!< NAK interrupt mask */
Kojto 107:4f6c30876dfa 8806 #define USB_OTG_DOEPEACHMSK1_NYETM ((uint32_t)0x00004000) /*!< NYET interrupt mask */
Kojto 107:4f6c30876dfa 8807
Kojto 107:4f6c30876dfa 8808 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
Kojto 107:4f6c30876dfa 8809 #define USB_OTG_HPTXFSIZ_PTXSA ((uint32_t)0x0000FFFF) /*!< Host periodic TxFIFO start address */
Kojto 107:4f6c30876dfa 8810 #define USB_OTG_HPTXFSIZ_PTXFD ((uint32_t)0xFFFF0000) /*!< Host periodic TxFIFO depth */
Kojto 107:4f6c30876dfa 8811
Kojto 107:4f6c30876dfa 8812 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
Kojto 107:4f6c30876dfa 8813 #define USB_OTG_DIEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 107:4f6c30876dfa 8814 #define USB_OTG_DIEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 107:4f6c30876dfa 8815 #define USB_OTG_DIEPCTL_EONUM_DPID ((uint32_t)0x00010000) /*!< Even/odd frame */
Kojto 107:4f6c30876dfa 8816 #define USB_OTG_DIEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 107:4f6c30876dfa 8817
Kojto 107:4f6c30876dfa 8818 #define USB_OTG_DIEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 107:4f6c30876dfa 8819 #define USB_OTG_DIEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8820 #define USB_OTG_DIEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8821 #define USB_OTG_DIEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 107:4f6c30876dfa 8822
Kojto 107:4f6c30876dfa 8823 #define USB_OTG_DIEPCTL_TXFNUM ((uint32_t)0x03C00000) /*!< TxFIFO number */
Kojto 107:4f6c30876dfa 8824 #define USB_OTG_DIEPCTL_TXFNUM_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8825 #define USB_OTG_DIEPCTL_TXFNUM_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8826 #define USB_OTG_DIEPCTL_TXFNUM_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8827 #define USB_OTG_DIEPCTL_TXFNUM_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8828 #define USB_OTG_DIEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 107:4f6c30876dfa 8829 #define USB_OTG_DIEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 107:4f6c30876dfa 8830 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 107:4f6c30876dfa 8831 #define USB_OTG_DIEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 107:4f6c30876dfa 8832 #define USB_OTG_DIEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 107:4f6c30876dfa 8833 #define USB_OTG_DIEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 107:4f6c30876dfa 8834
Kojto 107:4f6c30876dfa 8835 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
Kojto 107:4f6c30876dfa 8836 #define USB_OTG_HCCHAR_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */
Kojto 107:4f6c30876dfa 8837
Kojto 107:4f6c30876dfa 8838 #define USB_OTG_HCCHAR_EPNUM ((uint32_t)0x00007800) /*!< Endpoint number */
Kojto 107:4f6c30876dfa 8839 #define USB_OTG_HCCHAR_EPNUM_0 ((uint32_t)0x00000800) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8840 #define USB_OTG_HCCHAR_EPNUM_1 ((uint32_t)0x00001000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8841 #define USB_OTG_HCCHAR_EPNUM_2 ((uint32_t)0x00002000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8842 #define USB_OTG_HCCHAR_EPNUM_3 ((uint32_t)0x00004000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8843 #define USB_OTG_HCCHAR_EPDIR ((uint32_t)0x00008000) /*!< Endpoint direction */
Kojto 107:4f6c30876dfa 8844 #define USB_OTG_HCCHAR_LSDEV ((uint32_t)0x00020000) /*!< Low-speed device */
Kojto 107:4f6c30876dfa 8845
Kojto 107:4f6c30876dfa 8846 #define USB_OTG_HCCHAR_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 107:4f6c30876dfa 8847 #define USB_OTG_HCCHAR_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8848 #define USB_OTG_HCCHAR_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8849
Kojto 107:4f6c30876dfa 8850 #define USB_OTG_HCCHAR_MC ((uint32_t)0x00300000) /*!< Multi Count (MC) / Error Count (EC) */
Kojto 107:4f6c30876dfa 8851 #define USB_OTG_HCCHAR_MC_0 ((uint32_t)0x00100000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8852 #define USB_OTG_HCCHAR_MC_1 ((uint32_t)0x00200000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8853
Kojto 107:4f6c30876dfa 8854 #define USB_OTG_HCCHAR_DAD ((uint32_t)0x1FC00000) /*!< Device address */
Kojto 107:4f6c30876dfa 8855 #define USB_OTG_HCCHAR_DAD_0 ((uint32_t)0x00400000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8856 #define USB_OTG_HCCHAR_DAD_1 ((uint32_t)0x00800000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8857 #define USB_OTG_HCCHAR_DAD_2 ((uint32_t)0x01000000) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8858 #define USB_OTG_HCCHAR_DAD_3 ((uint32_t)0x02000000) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8859 #define USB_OTG_HCCHAR_DAD_4 ((uint32_t)0x04000000) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8860 #define USB_OTG_HCCHAR_DAD_5 ((uint32_t)0x08000000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8861 #define USB_OTG_HCCHAR_DAD_6 ((uint32_t)0x10000000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8862 #define USB_OTG_HCCHAR_ODDFRM ((uint32_t)0x20000000) /*!< Odd frame */
Kojto 107:4f6c30876dfa 8863 #define USB_OTG_HCCHAR_CHDIS ((uint32_t)0x40000000) /*!< Channel disable */
Kojto 107:4f6c30876dfa 8864 #define USB_OTG_HCCHAR_CHENA ((uint32_t)0x80000000) /*!< Channel enable */
Kojto 107:4f6c30876dfa 8865
Kojto 107:4f6c30876dfa 8866 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
Kojto 107:4f6c30876dfa 8867
Kojto 107:4f6c30876dfa 8868 #define USB_OTG_HCSPLT_PRTADDR ((uint32_t)0x0000007F) /*!< Port address */
Kojto 107:4f6c30876dfa 8869 #define USB_OTG_HCSPLT_PRTADDR_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8870 #define USB_OTG_HCSPLT_PRTADDR_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8871 #define USB_OTG_HCSPLT_PRTADDR_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8872 #define USB_OTG_HCSPLT_PRTADDR_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8873 #define USB_OTG_HCSPLT_PRTADDR_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8874 #define USB_OTG_HCSPLT_PRTADDR_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8875 #define USB_OTG_HCSPLT_PRTADDR_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8876
Kojto 107:4f6c30876dfa 8877 #define USB_OTG_HCSPLT_HUBADDR ((uint32_t)0x00003F80) /*!< Hub address */
Kojto 107:4f6c30876dfa 8878 #define USB_OTG_HCSPLT_HUBADDR_0 ((uint32_t)0x00000080) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8879 #define USB_OTG_HCSPLT_HUBADDR_1 ((uint32_t)0x00000100) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8880 #define USB_OTG_HCSPLT_HUBADDR_2 ((uint32_t)0x00000200) /*!<Bit 2 */
Kojto 107:4f6c30876dfa 8881 #define USB_OTG_HCSPLT_HUBADDR_3 ((uint32_t)0x00000400) /*!<Bit 3 */
Kojto 107:4f6c30876dfa 8882 #define USB_OTG_HCSPLT_HUBADDR_4 ((uint32_t)0x00000800) /*!<Bit 4 */
Kojto 107:4f6c30876dfa 8883 #define USB_OTG_HCSPLT_HUBADDR_5 ((uint32_t)0x00001000) /*!<Bit 5 */
Kojto 107:4f6c30876dfa 8884 #define USB_OTG_HCSPLT_HUBADDR_6 ((uint32_t)0x00002000) /*!<Bit 6 */
Kojto 107:4f6c30876dfa 8885
Kojto 107:4f6c30876dfa 8886 #define USB_OTG_HCSPLT_XACTPOS ((uint32_t)0x0000C000) /*!< XACTPOS */
Kojto 107:4f6c30876dfa 8887 #define USB_OTG_HCSPLT_XACTPOS_0 ((uint32_t)0x00004000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8888 #define USB_OTG_HCSPLT_XACTPOS_1 ((uint32_t)0x00008000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8889 #define USB_OTG_HCSPLT_COMPLSPLT ((uint32_t)0x00010000) /*!< Do complete split */
Kojto 107:4f6c30876dfa 8890 #define USB_OTG_HCSPLT_SPLITEN ((uint32_t)0x80000000) /*!< Split enable */
Kojto 107:4f6c30876dfa 8891
Kojto 107:4f6c30876dfa 8892 /******************** Bit definition for USB_OTG_HCINT register ********************/
Kojto 107:4f6c30876dfa 8893 #define USB_OTG_HCINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed */
Kojto 107:4f6c30876dfa 8894 #define USB_OTG_HCINT_CHH ((uint32_t)0x00000002) /*!< Channel halted */
Kojto 107:4f6c30876dfa 8895 #define USB_OTG_HCINT_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 107:4f6c30876dfa 8896 #define USB_OTG_HCINT_STALL ((uint32_t)0x00000008) /*!< STALL response received interrupt */
Kojto 107:4f6c30876dfa 8897 #define USB_OTG_HCINT_NAK ((uint32_t)0x00000010) /*!< NAK response received interrupt */
Kojto 107:4f6c30876dfa 8898 #define USB_OTG_HCINT_ACK ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt */
Kojto 107:4f6c30876dfa 8899 #define USB_OTG_HCINT_NYET ((uint32_t)0x00000040) /*!< Response received interrupt */
Kojto 107:4f6c30876dfa 8900 #define USB_OTG_HCINT_TXERR ((uint32_t)0x00000080) /*!< Transaction error */
Kojto 107:4f6c30876dfa 8901 #define USB_OTG_HCINT_BBERR ((uint32_t)0x00000100) /*!< Babble error */
Kojto 107:4f6c30876dfa 8902 #define USB_OTG_HCINT_FRMOR ((uint32_t)0x00000200) /*!< Frame overrun */
Kojto 107:4f6c30876dfa 8903 #define USB_OTG_HCINT_DTERR ((uint32_t)0x00000400) /*!< Data toggle error */
Kojto 107:4f6c30876dfa 8904
Kojto 107:4f6c30876dfa 8905 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
Kojto 107:4f6c30876dfa 8906 #define USB_OTG_DIEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 107:4f6c30876dfa 8907 #define USB_OTG_DIEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 107:4f6c30876dfa 8908 #define USB_OTG_DIEPINT_TOC ((uint32_t)0x00000008) /*!< Timeout condition */
Kojto 107:4f6c30876dfa 8909 #define USB_OTG_DIEPINT_ITTXFE ((uint32_t)0x00000010) /*!< IN token received when TxFIFO is empty */
Kojto 107:4f6c30876dfa 8910 #define USB_OTG_DIEPINT_INEPNE ((uint32_t)0x00000040) /*!< IN endpoint NAK effective */
Kojto 107:4f6c30876dfa 8911 #define USB_OTG_DIEPINT_TXFE ((uint32_t)0x00000080) /*!< Transmit FIFO empty */
Kojto 107:4f6c30876dfa 8912 #define USB_OTG_DIEPINT_TXFIFOUDRN ((uint32_t)0x00000100) /*!< Transmit Fifo Underrun */
Kojto 107:4f6c30876dfa 8913 #define USB_OTG_DIEPINT_BNA ((uint32_t)0x00000200) /*!< Buffer not available interrupt */
Kojto 107:4f6c30876dfa 8914 #define USB_OTG_DIEPINT_PKTDRPSTS ((uint32_t)0x00000800) /*!< Packet dropped status */
Kojto 107:4f6c30876dfa 8915 #define USB_OTG_DIEPINT_BERR ((uint32_t)0x00001000) /*!< Babble error interrupt */
Kojto 107:4f6c30876dfa 8916 #define USB_OTG_DIEPINT_NAK ((uint32_t)0x00002000) /*!< NAK interrupt */
Kojto 107:4f6c30876dfa 8917
Kojto 107:4f6c30876dfa 8918 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
Kojto 107:4f6c30876dfa 8919 #define USB_OTG_HCINTMSK_XFRCM ((uint32_t)0x00000001) /*!< Transfer completed mask */
Kojto 107:4f6c30876dfa 8920 #define USB_OTG_HCINTMSK_CHHM ((uint32_t)0x00000002) /*!< Channel halted mask */
Kojto 107:4f6c30876dfa 8921 #define USB_OTG_HCINTMSK_AHBERR ((uint32_t)0x00000004) /*!< AHB error */
Kojto 107:4f6c30876dfa 8922 #define USB_OTG_HCINTMSK_STALLM ((uint32_t)0x00000008) /*!< STALL response received interrupt mask */
Kojto 107:4f6c30876dfa 8923 #define USB_OTG_HCINTMSK_NAKM ((uint32_t)0x00000010) /*!< NAK response received interrupt mask */
Kojto 107:4f6c30876dfa 8924 #define USB_OTG_HCINTMSK_ACKM ((uint32_t)0x00000020) /*!< ACK response received/transmitted interrupt mask */
Kojto 107:4f6c30876dfa 8925 #define USB_OTG_HCINTMSK_NYET ((uint32_t)0x00000040) /*!< response received interrupt mask */
Kojto 107:4f6c30876dfa 8926 #define USB_OTG_HCINTMSK_TXERRM ((uint32_t)0x00000080) /*!< Transaction error mask */
Kojto 107:4f6c30876dfa 8927 #define USB_OTG_HCINTMSK_BBERRM ((uint32_t)0x00000100) /*!< Babble error mask */
Kojto 107:4f6c30876dfa 8928 #define USB_OTG_HCINTMSK_FRMORM ((uint32_t)0x00000200) /*!< Frame overrun mask */
Kojto 107:4f6c30876dfa 8929 #define USB_OTG_HCINTMSK_DTERRM ((uint32_t)0x00000400) /*!< Data toggle error mask */
Kojto 107:4f6c30876dfa 8930
Kojto 107:4f6c30876dfa 8931 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
Kojto 107:4f6c30876dfa 8932
Kojto 107:4f6c30876dfa 8933 #define USB_OTG_DIEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 107:4f6c30876dfa 8934 #define USB_OTG_DIEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 107:4f6c30876dfa 8935 #define USB_OTG_DIEPTSIZ_MULCNT ((uint32_t)0x60000000) /*!< Packet count */
Kojto 107:4f6c30876dfa 8936 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
Kojto 107:4f6c30876dfa 8937 #define USB_OTG_HCTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 107:4f6c30876dfa 8938 #define USB_OTG_HCTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 107:4f6c30876dfa 8939 #define USB_OTG_HCTSIZ_DOPING ((uint32_t)0x80000000) /*!< Do PING */
Kojto 107:4f6c30876dfa 8940 #define USB_OTG_HCTSIZ_DPID ((uint32_t)0x60000000) /*!< Data PID */
Kojto 107:4f6c30876dfa 8941 #define USB_OTG_HCTSIZ_DPID_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8942 #define USB_OTG_HCTSIZ_DPID_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8943
Kojto 107:4f6c30876dfa 8944 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
Kojto 107:4f6c30876dfa 8945 #define USB_OTG_DIEPDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 107:4f6c30876dfa 8946
Kojto 107:4f6c30876dfa 8947 /******************** Bit definition for USB_OTG_HCDMA register ********************/
Kojto 107:4f6c30876dfa 8948 #define USB_OTG_HCDMA_DMAADDR ((uint32_t)0xFFFFFFFF) /*!< DMA address */
Kojto 107:4f6c30876dfa 8949
Kojto 107:4f6c30876dfa 8950 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
Kojto 107:4f6c30876dfa 8951 #define USB_OTG_DTXFSTS_INEPTFSAV ((uint32_t)0x0000FFFF) /*!< IN endpoint TxFIFO space available */
Kojto 107:4f6c30876dfa 8952
Kojto 107:4f6c30876dfa 8953 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
Kojto 107:4f6c30876dfa 8954 #define USB_OTG_DIEPTXF_INEPTXSA ((uint32_t)0x0000FFFF) /*!< IN endpoint FIFOx transmit RAM start address */
Kojto 107:4f6c30876dfa 8955 #define USB_OTG_DIEPTXF_INEPTXFD ((uint32_t)0xFFFF0000) /*!< IN endpoint TxFIFO depth */
Kojto 107:4f6c30876dfa 8956
Kojto 107:4f6c30876dfa 8957 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
Kojto 107:4f6c30876dfa 8958 #define USB_OTG_DOEPCTL_MPSIZ ((uint32_t)0x000007FF) /*!< Maximum packet size */ /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8959 #define USB_OTG_DOEPCTL_USBAEP ((uint32_t)0x00008000) /*!< USB active endpoint */
Kojto 107:4f6c30876dfa 8960 #define USB_OTG_DOEPCTL_NAKSTS ((uint32_t)0x00020000) /*!< NAK status */
Kojto 107:4f6c30876dfa 8961 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM ((uint32_t)0x10000000) /*!< Set DATA0 PID */
Kojto 107:4f6c30876dfa 8962 #define USB_OTG_DOEPCTL_SODDFRM ((uint32_t)0x20000000) /*!< Set odd frame */
Kojto 107:4f6c30876dfa 8963 #define USB_OTG_DOEPCTL_EPTYP ((uint32_t)0x000C0000) /*!< Endpoint type */
Kojto 107:4f6c30876dfa 8964 #define USB_OTG_DOEPCTL_EPTYP_0 ((uint32_t)0x00040000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8965 #define USB_OTG_DOEPCTL_EPTYP_1 ((uint32_t)0x00080000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8966 #define USB_OTG_DOEPCTL_SNPM ((uint32_t)0x00100000) /*!< Snoop mode */
Kojto 107:4f6c30876dfa 8967 #define USB_OTG_DOEPCTL_STALL ((uint32_t)0x00200000) /*!< STALL handshake */
Kojto 107:4f6c30876dfa 8968 #define USB_OTG_DOEPCTL_CNAK ((uint32_t)0x04000000) /*!< Clear NAK */
Kojto 107:4f6c30876dfa 8969 #define USB_OTG_DOEPCTL_SNAK ((uint32_t)0x08000000) /*!< Set NAK */
Kojto 107:4f6c30876dfa 8970 #define USB_OTG_DOEPCTL_EPDIS ((uint32_t)0x40000000) /*!< Endpoint disable */
Kojto 107:4f6c30876dfa 8971 #define USB_OTG_DOEPCTL_EPENA ((uint32_t)0x80000000) /*!< Endpoint enable */
Kojto 107:4f6c30876dfa 8972
Kojto 107:4f6c30876dfa 8973 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
Kojto 107:4f6c30876dfa 8974 #define USB_OTG_DOEPINT_XFRC ((uint32_t)0x00000001) /*!< Transfer completed interrupt */
Kojto 107:4f6c30876dfa 8975 #define USB_OTG_DOEPINT_EPDISD ((uint32_t)0x00000002) /*!< Endpoint disabled interrupt */
Kojto 107:4f6c30876dfa 8976 #define USB_OTG_DOEPINT_STUP ((uint32_t)0x00000008) /*!< SETUP phase done */
Kojto 107:4f6c30876dfa 8977 #define USB_OTG_DOEPINT_OTEPDIS ((uint32_t)0x00000010) /*!< OUT token received when endpoint disabled */
Kojto 116:c0f6e94411f5 8978 #define USB_OTG_DOEPINT_OTEPSPR ((uint32_t)0x00000020) /*!< Status Phase Received For Control Write */
Kojto 107:4f6c30876dfa 8979 #define USB_OTG_DOEPINT_B2BSTUP ((uint32_t)0x00000040) /*!< Back-to-back SETUP packets received */
Kojto 107:4f6c30876dfa 8980 #define USB_OTG_DOEPINT_NYET ((uint32_t)0x00004000) /*!< NYET interrupt */
Kojto 107:4f6c30876dfa 8981
Kojto 107:4f6c30876dfa 8982 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
Kojto 107:4f6c30876dfa 8983 #define USB_OTG_DOEPTSIZ_XFRSIZ ((uint32_t)0x0007FFFF) /*!< Transfer size */
Kojto 107:4f6c30876dfa 8984 #define USB_OTG_DOEPTSIZ_PKTCNT ((uint32_t)0x1FF80000) /*!< Packet count */
Kojto 107:4f6c30876dfa 8985
Kojto 107:4f6c30876dfa 8986 #define USB_OTG_DOEPTSIZ_STUPCNT ((uint32_t)0x60000000) /*!< SETUP packet count */
Kojto 107:4f6c30876dfa 8987 #define USB_OTG_DOEPTSIZ_STUPCNT_0 ((uint32_t)0x20000000) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8988 #define USB_OTG_DOEPTSIZ_STUPCNT_1 ((uint32_t)0x40000000) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8989
Kojto 107:4f6c30876dfa 8990 /******************** Bit definition for PCGCCTL register ********************/
Kojto 107:4f6c30876dfa 8991 #define USB_OTG_PCGCCTL_STOPCLK ((uint32_t)0x00000001) /*!< SETUP packet count */
Kojto 107:4f6c30876dfa 8992 #define USB_OTG_PCGCCTL_GATECLK ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 107:4f6c30876dfa 8993 #define USB_OTG_PCGCCTL_PHYSUSP ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 107:4f6c30876dfa 8994
Kojto 107:4f6c30876dfa 8995 /**
Kojto 107:4f6c30876dfa 8996 * @}
Kojto 107:4f6c30876dfa 8997 */
Kojto 107:4f6c30876dfa 8998
Kojto 107:4f6c30876dfa 8999 /**
Kojto 107:4f6c30876dfa 9000 * @}
Kojto 107:4f6c30876dfa 9001 */
Kojto 107:4f6c30876dfa 9002
Kojto 107:4f6c30876dfa 9003 /** @addtogroup Exported_macros
Kojto 107:4f6c30876dfa 9004 * @{
Kojto 107:4f6c30876dfa 9005 */
Kojto 107:4f6c30876dfa 9006
Kojto 107:4f6c30876dfa 9007 /******************************* ADC Instances ********************************/
Kojto 107:4f6c30876dfa 9008 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
Kojto 107:4f6c30876dfa 9009 ((__INSTANCE__) == ADC2) || \
Kojto 107:4f6c30876dfa 9010 ((__INSTANCE__) == ADC3))
Kojto 107:4f6c30876dfa 9011
Kojto 107:4f6c30876dfa 9012 /******************************* CAN Instances ********************************/
Kojto 107:4f6c30876dfa 9013 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
Kojto 107:4f6c30876dfa 9014 ((__INSTANCE__) == CAN2))
Kojto 107:4f6c30876dfa 9015
Kojto 107:4f6c30876dfa 9016 /******************************* CRC Instances ********************************/
Kojto 107:4f6c30876dfa 9017 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
Kojto 107:4f6c30876dfa 9018
Kojto 107:4f6c30876dfa 9019 /******************************* DAC Instances ********************************/
Kojto 107:4f6c30876dfa 9020 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
Kojto 107:4f6c30876dfa 9021
Kojto 107:4f6c30876dfa 9022 /******************************* DCMI Instances *******************************/
Kojto 107:4f6c30876dfa 9023 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
Kojto 107:4f6c30876dfa 9024
Kojto 116:c0f6e94411f5 9025
Kojto 107:4f6c30876dfa 9026 /******************************* DMA2D Instances *******************************/
Kojto 107:4f6c30876dfa 9027 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
Kojto 107:4f6c30876dfa 9028
Kojto 107:4f6c30876dfa 9029 /******************************** DMA Instances *******************************/
Kojto 107:4f6c30876dfa 9030 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
Kojto 107:4f6c30876dfa 9031 ((__INSTANCE__) == DMA1_Stream1) || \
Kojto 107:4f6c30876dfa 9032 ((__INSTANCE__) == DMA1_Stream2) || \
Kojto 107:4f6c30876dfa 9033 ((__INSTANCE__) == DMA1_Stream3) || \
Kojto 107:4f6c30876dfa 9034 ((__INSTANCE__) == DMA1_Stream4) || \
Kojto 107:4f6c30876dfa 9035 ((__INSTANCE__) == DMA1_Stream5) || \
Kojto 107:4f6c30876dfa 9036 ((__INSTANCE__) == DMA1_Stream6) || \
Kojto 107:4f6c30876dfa 9037 ((__INSTANCE__) == DMA1_Stream7) || \
Kojto 107:4f6c30876dfa 9038 ((__INSTANCE__) == DMA2_Stream0) || \
Kojto 107:4f6c30876dfa 9039 ((__INSTANCE__) == DMA2_Stream1) || \
Kojto 107:4f6c30876dfa 9040 ((__INSTANCE__) == DMA2_Stream2) || \
Kojto 107:4f6c30876dfa 9041 ((__INSTANCE__) == DMA2_Stream3) || \
Kojto 107:4f6c30876dfa 9042 ((__INSTANCE__) == DMA2_Stream4) || \
Kojto 107:4f6c30876dfa 9043 ((__INSTANCE__) == DMA2_Stream5) || \
Kojto 107:4f6c30876dfa 9044 ((__INSTANCE__) == DMA2_Stream6) || \
Kojto 107:4f6c30876dfa 9045 ((__INSTANCE__) == DMA2_Stream7))
Kojto 107:4f6c30876dfa 9046
Kojto 107:4f6c30876dfa 9047 /******************************* GPIO Instances *******************************/
Kojto 107:4f6c30876dfa 9048 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
Kojto 107:4f6c30876dfa 9049 ((__INSTANCE__) == GPIOB) || \
Kojto 107:4f6c30876dfa 9050 ((__INSTANCE__) == GPIOC) || \
Kojto 107:4f6c30876dfa 9051 ((__INSTANCE__) == GPIOD) || \
Kojto 107:4f6c30876dfa 9052 ((__INSTANCE__) == GPIOE) || \
Kojto 107:4f6c30876dfa 9053 ((__INSTANCE__) == GPIOF) || \
Kojto 107:4f6c30876dfa 9054 ((__INSTANCE__) == GPIOG) || \
Kojto 107:4f6c30876dfa 9055 ((__INSTANCE__) == GPIOH) || \
Kojto 107:4f6c30876dfa 9056 ((__INSTANCE__) == GPIOI) || \
Kojto 107:4f6c30876dfa 9057 ((__INSTANCE__) == GPIOJ) || \
Kojto 107:4f6c30876dfa 9058 ((__INSTANCE__) == GPIOK))
Kojto 107:4f6c30876dfa 9059
Kojto 107:4f6c30876dfa 9060 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
Kojto 107:4f6c30876dfa 9061 ((__INSTANCE__) == GPIOB) || \
Kojto 107:4f6c30876dfa 9062 ((__INSTANCE__) == GPIOC) || \
Kojto 107:4f6c30876dfa 9063 ((__INSTANCE__) == GPIOD) || \
Kojto 107:4f6c30876dfa 9064 ((__INSTANCE__) == GPIOE) || \
Kojto 107:4f6c30876dfa 9065 ((__INSTANCE__) == GPIOF) || \
Kojto 107:4f6c30876dfa 9066 ((__INSTANCE__) == GPIOG) || \
Kojto 107:4f6c30876dfa 9067 ((__INSTANCE__) == GPIOH) || \
Kojto 107:4f6c30876dfa 9068 ((__INSTANCE__) == GPIOI) || \
Kojto 107:4f6c30876dfa 9069 ((__INSTANCE__) == GPIOJ) || \
Kojto 107:4f6c30876dfa 9070 ((__INSTANCE__) == GPIOK))
Kojto 107:4f6c30876dfa 9071
Kojto 107:4f6c30876dfa 9072 /****************************** CEC Instances *********************************/
Kojto 107:4f6c30876dfa 9073 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
Kojto 107:4f6c30876dfa 9074
Kojto 107:4f6c30876dfa 9075 /****************************** QSPI Instances *********************************/
Kojto 107:4f6c30876dfa 9076 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto 107:4f6c30876dfa 9077
Kojto 107:4f6c30876dfa 9078
Kojto 107:4f6c30876dfa 9079 /******************************** I2C Instances *******************************/
Kojto 107:4f6c30876dfa 9080 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
Kojto 107:4f6c30876dfa 9081 ((__INSTANCE__) == I2C2) || \
Kojto 107:4f6c30876dfa 9082 ((__INSTANCE__) == I2C3) || \
Kojto 107:4f6c30876dfa 9083 ((__INSTANCE__) == I2C4))
Kojto 107:4f6c30876dfa 9084
Kojto 107:4f6c30876dfa 9085 /******************************** I2S Instances *******************************/
Kojto 107:4f6c30876dfa 9086 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
Kojto 107:4f6c30876dfa 9087 ((__INSTANCE__) == SPI2) || \
Kojto 107:4f6c30876dfa 9088 ((__INSTANCE__) == SPI3))
Kojto 107:4f6c30876dfa 9089
Kojto 107:4f6c30876dfa 9090 /******************************* LPTIM Instances ********************************/
Kojto 107:4f6c30876dfa 9091 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
Kojto 107:4f6c30876dfa 9092
Kojto 107:4f6c30876dfa 9093 /****************************** LTDC Instances ********************************/
Kojto 107:4f6c30876dfa 9094 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
Kojto 107:4f6c30876dfa 9095
Kojto 116:c0f6e94411f5 9096
Kojto 107:4f6c30876dfa 9097 /******************************* RNG Instances ********************************/
Kojto 107:4f6c30876dfa 9098 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
Kojto 107:4f6c30876dfa 9099
Kojto 107:4f6c30876dfa 9100 /****************************** RTC Instances *********************************/
Kojto 107:4f6c30876dfa 9101 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
Kojto 107:4f6c30876dfa 9102
Kojto 107:4f6c30876dfa 9103 /******************************* SAI Instances ********************************/
Kojto 107:4f6c30876dfa 9104 #define IS_SAI_BLOCK_PERIPH(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
Kojto 107:4f6c30876dfa 9105 ((__PERIPH__) == SAI1_Block_B) || \
Kojto 107:4f6c30876dfa 9106 ((__PERIPH__) == SAI2_Block_A) || \
Kojto 107:4f6c30876dfa 9107 ((__PERIPH__) == SAI2_Block_B))
Kojto 107:4f6c30876dfa 9108
Kojto 107:4f6c30876dfa 9109
Kojto 107:4f6c30876dfa 9110 /******************************** SDMMC Instances *******************************/
Kojto 107:4f6c30876dfa 9111 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
Kojto 107:4f6c30876dfa 9112
Kojto 107:4f6c30876dfa 9113 /****************************** SPDIFRX Instances *********************************/
Kojto 107:4f6c30876dfa 9114 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
Kojto 107:4f6c30876dfa 9115
Kojto 107:4f6c30876dfa 9116 /******************************** SPI Instances *******************************/
Kojto 107:4f6c30876dfa 9117 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
Kojto 107:4f6c30876dfa 9118 ((__INSTANCE__) == SPI2) || \
Kojto 107:4f6c30876dfa 9119 ((__INSTANCE__) == SPI3) || \
Kojto 107:4f6c30876dfa 9120 ((__INSTANCE__) == SPI4) || \
Kojto 107:4f6c30876dfa 9121 ((__INSTANCE__) == SPI5) || \
Kojto 107:4f6c30876dfa 9122 ((__INSTANCE__) == SPI6))
Kojto 107:4f6c30876dfa 9123
Kojto 107:4f6c30876dfa 9124 /****************** TIM Instances : All supported instances *******************/
Kojto 107:4f6c30876dfa 9125 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9126 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9127 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9128 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9129 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9130 ((__INSTANCE__) == TIM6) || \
Kojto 107:4f6c30876dfa 9131 ((__INSTANCE__) == TIM7) || \
Kojto 107:4f6c30876dfa 9132 ((__INSTANCE__) == TIM8) || \
Kojto 107:4f6c30876dfa 9133 ((__INSTANCE__) == TIM9) || \
Kojto 107:4f6c30876dfa 9134 ((__INSTANCE__) == TIM10) || \
Kojto 107:4f6c30876dfa 9135 ((__INSTANCE__) == TIM11) || \
Kojto 107:4f6c30876dfa 9136 ((__INSTANCE__) == TIM12) || \
Kojto 107:4f6c30876dfa 9137 ((__INSTANCE__) == TIM13) || \
Kojto 107:4f6c30876dfa 9138 ((__INSTANCE__) == TIM14))
Kojto 107:4f6c30876dfa 9139
Kojto 107:4f6c30876dfa 9140 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 107:4f6c30876dfa 9141 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9142 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9143 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9144 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9145 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9146 ((__INSTANCE__) == TIM8) || \
Kojto 107:4f6c30876dfa 9147 ((__INSTANCE__) == TIM9) || \
Kojto 107:4f6c30876dfa 9148 ((__INSTANCE__) == TIM10) || \
Kojto 107:4f6c30876dfa 9149 ((__INSTANCE__) == TIM11) || \
Kojto 107:4f6c30876dfa 9150 ((__INSTANCE__) == TIM12) || \
Kojto 107:4f6c30876dfa 9151 ((__INSTANCE__) == TIM13) || \
Kojto 107:4f6c30876dfa 9152 ((__INSTANCE__) == TIM14))
Kojto 107:4f6c30876dfa 9153
Kojto 107:4f6c30876dfa 9154 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 107:4f6c30876dfa 9155 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9156 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9157 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9158 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9159 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9160 ((__INSTANCE__) == TIM8) || \
Kojto 107:4f6c30876dfa 9161 ((__INSTANCE__) == TIM9) || \
Kojto 107:4f6c30876dfa 9162 ((__INSTANCE__) == TIM12))
Kojto 107:4f6c30876dfa 9163
Kojto 107:4f6c30876dfa 9164 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 107:4f6c30876dfa 9165 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9166 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9167 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9168 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9169 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9170 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9171
Kojto 107:4f6c30876dfa 9172 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 107:4f6c30876dfa 9173 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9174 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9175 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9176 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9177 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9178 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9179
Kojto 107:4f6c30876dfa 9180 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
Kojto 107:4f6c30876dfa 9181 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
Kojto 107:4f6c30876dfa 9182 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9183 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9184
Kojto 107:4f6c30876dfa 9185 /****************** TIM Instances : supporting OCxREF clear *******************/
Kojto 107:4f6c30876dfa 9186 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9187 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9188 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9189 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9190 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9191 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9192
Kojto 107:4f6c30876dfa 9193 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto 107:4f6c30876dfa 9194 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9195 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9196 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9197 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9198 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9199 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9200 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9201
Kojto 107:4f6c30876dfa 9202 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
Kojto 107:4f6c30876dfa 9203 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9204 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9205 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9206 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9207 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9208 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9209 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9210 /****************** TIM Instances : at least 5 capture/compare channels *******/
Kojto 107:4f6c30876dfa 9211 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9212 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9213 ((__INSTANCE__) == TIM8) )
Kojto 107:4f6c30876dfa 9214
Kojto 107:4f6c30876dfa 9215 /****************** TIM Instances : at least 6 capture/compare channels *******/
Kojto 107:4f6c30876dfa 9216 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9217 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9218 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9219
Kojto 107:4f6c30876dfa 9220
Kojto 107:4f6c30876dfa 9221 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 107:4f6c30876dfa 9222 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9223 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9224
Kojto 107:4f6c30876dfa 9225 /****************** TIM Instances : supporting 2 break inputs *****************/
Kojto 107:4f6c30876dfa 9226 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9227 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9228 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9229
Kojto 107:4f6c30876dfa 9230 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 107:4f6c30876dfa 9231 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9232 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9233 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9234 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9235 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9236 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9237
Kojto 107:4f6c30876dfa 9238 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 107:4f6c30876dfa 9239 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9240 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9241 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9242 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9243 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9244 ((__INSTANCE__) == TIM6) || \
Kojto 107:4f6c30876dfa 9245 ((__INSTANCE__) == TIM7) || \
Kojto 107:4f6c30876dfa 9246 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9247
Kojto 107:4f6c30876dfa 9248 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 107:4f6c30876dfa 9249 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9250 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9251 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9252 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9253 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9254 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9255
Kojto 107:4f6c30876dfa 9256 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 107:4f6c30876dfa 9257 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9258 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9259 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9260 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9261 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9262 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9263
Kojto 107:4f6c30876dfa 9264 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 107:4f6c30876dfa 9265 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9266 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9267 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9268 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9269 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9270 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9271
Kojto 107:4f6c30876dfa 9272 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 107:4f6c30876dfa 9273 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9274 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9275 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9276 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9277 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9278 ((__INSTANCE__) == TIM6) || \
Kojto 107:4f6c30876dfa 9279 ((__INSTANCE__) == TIM7) || \
Kojto 107:4f6c30876dfa 9280 ((__INSTANCE__) == TIM8) || \
Kojto 107:4f6c30876dfa 9281 ((__INSTANCE__) == TIM13) || \
Kojto 107:4f6c30876dfa 9282 ((__INSTANCE__) == TIM14))
Kojto 107:4f6c30876dfa 9283
Kojto 107:4f6c30876dfa 9284 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 107:4f6c30876dfa 9285 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9286 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9287 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9288 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9289 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9290 ((__INSTANCE__) == TIM8) || \
Kojto 107:4f6c30876dfa 9291 ((__INSTANCE__) == TIM9) || \
Kojto 107:4f6c30876dfa 9292 ((__INSTANCE__) == TIM12))
Kojto 107:4f6c30876dfa 9293
Kojto 107:4f6c30876dfa 9294 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 107:4f6c30876dfa 9295 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9296 ((__INSTANCE__) == TIM5))
Kojto 107:4f6c30876dfa 9297
Kojto 107:4f6c30876dfa 9298 /***************** TIM Instances : external trigger input available ************/
Kojto 107:4f6c30876dfa 9299 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9300 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9301 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9302 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9303 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9304 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9305
Kojto 107:4f6c30876dfa 9306 /****************** TIM Instances : remapping capability **********************/
Kojto 107:4f6c30876dfa 9307 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9308 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9309 ((__INSTANCE__) == TIM11))
Kojto 107:4f6c30876dfa 9310
Kojto 107:4f6c30876dfa 9311 /******************* TIM Instances : output(s) available **********************/
Kojto 107:4f6c30876dfa 9312 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto 107:4f6c30876dfa 9313 ((((__INSTANCE__) == TIM1) && \
Kojto 107:4f6c30876dfa 9314 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9315 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9316 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 107:4f6c30876dfa 9317 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 107:4f6c30876dfa 9318 || \
Kojto 107:4f6c30876dfa 9319 (((__INSTANCE__) == TIM2) && \
Kojto 107:4f6c30876dfa 9320 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9321 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9322 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 107:4f6c30876dfa 9323 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 107:4f6c30876dfa 9324 || \
Kojto 107:4f6c30876dfa 9325 (((__INSTANCE__) == TIM3) && \
Kojto 107:4f6c30876dfa 9326 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9327 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9328 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 107:4f6c30876dfa 9329 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 107:4f6c30876dfa 9330 || \
Kojto 107:4f6c30876dfa 9331 (((__INSTANCE__) == TIM4) && \
Kojto 107:4f6c30876dfa 9332 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9333 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9334 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 107:4f6c30876dfa 9335 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 107:4f6c30876dfa 9336 || \
Kojto 107:4f6c30876dfa 9337 (((__INSTANCE__) == TIM5) && \
Kojto 107:4f6c30876dfa 9338 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9339 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9340 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 107:4f6c30876dfa 9341 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 107:4f6c30876dfa 9342 || \
Kojto 107:4f6c30876dfa 9343 (((__INSTANCE__) == TIM8) && \
Kojto 107:4f6c30876dfa 9344 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9345 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9346 ((__CHANNEL__) == TIM_CHANNEL_3) || \
Kojto 107:4f6c30876dfa 9347 ((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto 107:4f6c30876dfa 9348 || \
Kojto 107:4f6c30876dfa 9349 (((__INSTANCE__) == TIM9) && \
Kojto 107:4f6c30876dfa 9350 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9351 ((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto 107:4f6c30876dfa 9352 || \
Kojto 107:4f6c30876dfa 9353 (((__INSTANCE__) == TIM10) && \
Kojto 107:4f6c30876dfa 9354 (((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto 107:4f6c30876dfa 9355 || \
Kojto 107:4f6c30876dfa 9356 (((__INSTANCE__) == TIM11) && \
Kojto 107:4f6c30876dfa 9357 (((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto 107:4f6c30876dfa 9358 || \
Kojto 107:4f6c30876dfa 9359 (((__INSTANCE__) == TIM12) && \
Kojto 107:4f6c30876dfa 9360 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9361 ((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto 107:4f6c30876dfa 9362 || \
Kojto 107:4f6c30876dfa 9363 (((__INSTANCE__) == TIM13) && \
Kojto 107:4f6c30876dfa 9364 (((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto 107:4f6c30876dfa 9365 || \
Kojto 107:4f6c30876dfa 9366 (((__INSTANCE__) == TIM14) && \
Kojto 107:4f6c30876dfa 9367 (((__CHANNEL__) == TIM_CHANNEL_1))))
Kojto 107:4f6c30876dfa 9368
Kojto 107:4f6c30876dfa 9369 /************ TIM Instances : complementary output(s) available ***************/
Kojto 107:4f6c30876dfa 9370 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto 107:4f6c30876dfa 9371 ((((__INSTANCE__) == TIM1) && \
Kojto 107:4f6c30876dfa 9372 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9373 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9374 ((__CHANNEL__) == TIM_CHANNEL_3))) \
Kojto 107:4f6c30876dfa 9375 || \
Kojto 107:4f6c30876dfa 9376 (((__INSTANCE__) == TIM8) && \
Kojto 107:4f6c30876dfa 9377 (((__CHANNEL__) == TIM_CHANNEL_1) || \
Kojto 107:4f6c30876dfa 9378 ((__CHANNEL__) == TIM_CHANNEL_2) || \
Kojto 107:4f6c30876dfa 9379 ((__CHANNEL__) == TIM_CHANNEL_3))))
Kojto 107:4f6c30876dfa 9380
Kojto 107:4f6c30876dfa 9381 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
Kojto 107:4f6c30876dfa 9382 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9383 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9384 ((__INSTANCE__) == TIM8) )
Kojto 107:4f6c30876dfa 9385
Kojto 107:4f6c30876dfa 9386 /****************** TIM Instances : supporting synchronization ****************/
Kojto 107:4f6c30876dfa 9387 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
Kojto 107:4f6c30876dfa 9388 (((__INSTANCE__) == TIM1) || \
Kojto 107:4f6c30876dfa 9389 ((__INSTANCE__) == TIM2) || \
Kojto 107:4f6c30876dfa 9390 ((__INSTANCE__) == TIM3) || \
Kojto 107:4f6c30876dfa 9391 ((__INSTANCE__) == TIM4) || \
Kojto 107:4f6c30876dfa 9392 ((__INSTANCE__) == TIM5) || \
Kojto 107:4f6c30876dfa 9393 ((__INSTANCE__) == TIM6) || \
Kojto 107:4f6c30876dfa 9394 ((__INSTANCE__) == TIM7) || \
Kojto 107:4f6c30876dfa 9395 ((__INSTANCE__) == TIM8))
Kojto 107:4f6c30876dfa 9396
Kojto 107:4f6c30876dfa 9397 /******************** USART Instances : Synchronous mode **********************/
Kojto 107:4f6c30876dfa 9398 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 107:4f6c30876dfa 9399 ((__INSTANCE__) == USART2) || \
Kojto 107:4f6c30876dfa 9400 ((__INSTANCE__) == USART3) || \
Kojto 107:4f6c30876dfa 9401 ((__INSTANCE__) == USART6))
Kojto 107:4f6c30876dfa 9402
Kojto 107:4f6c30876dfa 9403 /******************** UART Instances : Asynchronous mode **********************/
Kojto 107:4f6c30876dfa 9404 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 107:4f6c30876dfa 9405 ((__INSTANCE__) == USART2) || \
Kojto 107:4f6c30876dfa 9406 ((__INSTANCE__) == USART3) || \
Kojto 107:4f6c30876dfa 9407 ((__INSTANCE__) == UART4) || \
Kojto 107:4f6c30876dfa 9408 ((__INSTANCE__) == UART5) || \
Kojto 107:4f6c30876dfa 9409 ((__INSTANCE__) == USART6) || \
Kojto 107:4f6c30876dfa 9410 ((__INSTANCE__) == UART7) || \
Kojto 107:4f6c30876dfa 9411 ((__INSTANCE__) == UART8))
Kojto 107:4f6c30876dfa 9412
Kojto 107:4f6c30876dfa 9413 /****************** UART Instances : Hardware Flow control ********************/
Kojto 107:4f6c30876dfa 9414 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 107:4f6c30876dfa 9415 ((__INSTANCE__) == USART2) || \
Kojto 107:4f6c30876dfa 9416 ((__INSTANCE__) == USART3) || \
Kojto 107:4f6c30876dfa 9417 ((__INSTANCE__) == UART4) || \
Kojto 107:4f6c30876dfa 9418 ((__INSTANCE__) == UART5) || \
Kojto 107:4f6c30876dfa 9419 ((__INSTANCE__) == USART6) || \
Kojto 107:4f6c30876dfa 9420 ((__INSTANCE__) == UART7) || \
Kojto 107:4f6c30876dfa 9421 ((__INSTANCE__) == UART8))
Kojto 107:4f6c30876dfa 9422
Kojto 107:4f6c30876dfa 9423 /********************* UART Instances : Smart card mode ***********************/
Kojto 107:4f6c30876dfa 9424 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 107:4f6c30876dfa 9425 ((__INSTANCE__) == USART2) || \
Kojto 107:4f6c30876dfa 9426 ((__INSTANCE__) == USART3) || \
Kojto 107:4f6c30876dfa 9427 ((__INSTANCE__) == USART6))
Kojto 107:4f6c30876dfa 9428
Kojto 107:4f6c30876dfa 9429 /*********************** UART Instances : IRDA mode ***************************/
Kojto 107:4f6c30876dfa 9430 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
Kojto 107:4f6c30876dfa 9431 ((__INSTANCE__) == USART2) || \
Kojto 107:4f6c30876dfa 9432 ((__INSTANCE__) == USART3) || \
Kojto 107:4f6c30876dfa 9433 ((__INSTANCE__) == UART4) || \
Kojto 107:4f6c30876dfa 9434 ((__INSTANCE__) == UART5) || \
Kojto 107:4f6c30876dfa 9435 ((__INSTANCE__) == USART6) || \
Kojto 107:4f6c30876dfa 9436 ((__INSTANCE__) == UART7) || \
Kojto 107:4f6c30876dfa 9437 ((__INSTANCE__) == UART8))
Kojto 107:4f6c30876dfa 9438
Kojto 107:4f6c30876dfa 9439 /****************************** IWDG Instances ********************************/
Kojto 107:4f6c30876dfa 9440 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
Kojto 107:4f6c30876dfa 9441
Kojto 107:4f6c30876dfa 9442 /****************************** WWDG Instances ********************************/
Kojto 107:4f6c30876dfa 9443 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
Kojto 107:4f6c30876dfa 9444
Kojto 107:4f6c30876dfa 9445
Kojto 107:4f6c30876dfa 9446 /******************************************************************************/
Kojto 107:4f6c30876dfa 9447 /* For a painless codes migration between the STM32F7xx device product */
Kojto 107:4f6c30876dfa 9448 /* lines, the aliases defined below are put in place to overcome the */
Kojto 107:4f6c30876dfa 9449 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 107:4f6c30876dfa 9450 /* No need to update developed interrupt code when moving across */
Kojto 107:4f6c30876dfa 9451 /* product lines within the same STM32F7 Family */
Kojto 107:4f6c30876dfa 9452 /******************************************************************************/
Kojto 107:4f6c30876dfa 9453
Kojto 107:4f6c30876dfa 9454 /* Aliases for __IRQn */
Kojto 107:4f6c30876dfa 9455 #define HASH_RNG_IRQn RNG_IRQn
Kojto 107:4f6c30876dfa 9456
Kojto 107:4f6c30876dfa 9457 /* Aliases for __IRQHandler */
Kojto 107:4f6c30876dfa 9458 #define HASH_RNG_IRQHandler RNG_IRQHandler
Kojto 107:4f6c30876dfa 9459
Kojto 107:4f6c30876dfa 9460 /**
Kojto 107:4f6c30876dfa 9461 * @}
Kojto 107:4f6c30876dfa 9462 */
Kojto 107:4f6c30876dfa 9463
Kojto 107:4f6c30876dfa 9464 /**
Kojto 107:4f6c30876dfa 9465 * @}
Kojto 107:4f6c30876dfa 9466 */
Kojto 107:4f6c30876dfa 9467
Kojto 107:4f6c30876dfa 9468 /**
Kojto 107:4f6c30876dfa 9469 * @}
Kojto 107:4f6c30876dfa 9470 */
Kojto 107:4f6c30876dfa 9471
Kojto 107:4f6c30876dfa 9472 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 9473 }
Kojto 107:4f6c30876dfa 9474 #endif /* __cplusplus */
Kojto 107:4f6c30876dfa 9475
Kojto 107:4f6c30876dfa 9476 #endif /* __STM32F746xx_H */
Kojto 107:4f6c30876dfa 9477
Kojto 107:4f6c30876dfa 9478
Kojto 107:4f6c30876dfa 9479 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/