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TARGET_DISCO_F334C8/stm32f3xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 100:cbbeb26dbd92

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	100:cbbeb26dbd92	1	/**
Kojto	100:cbbeb26dbd92	2	******************************************************************************
Kojto	100:cbbeb26dbd92	3	* @file stm32f3xx_hal_rcc_ex.h
Kojto	100:cbbeb26dbd92	4	* @author MCD Application Team
Kojto	100:cbbeb26dbd92	5	* @version V1.1.0
Kojto	100:cbbeb26dbd92	6	* @date 12-Sept-2014
Kojto	100:cbbeb26dbd92	7	* @brief Header file of RCC HAL Extended module.
Kojto	100:cbbeb26dbd92	8	******************************************************************************
Kojto	100:cbbeb26dbd92	9	* @attention
Kojto	100:cbbeb26dbd92	10	*
Kojto	100:cbbeb26dbd92	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	100:cbbeb26dbd92	12	*
Kojto	100:cbbeb26dbd92	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	100:cbbeb26dbd92	14	* are permitted provided that the following conditions are met:
Kojto	100:cbbeb26dbd92	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	100:cbbeb26dbd92	16	* this list of conditions and the following disclaimer.
Kojto	100:cbbeb26dbd92	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	100:cbbeb26dbd92	18	* this list of conditions and the following disclaimer in the documentation
Kojto	100:cbbeb26dbd92	19	* and/or other materials provided with the distribution.
Kojto	100:cbbeb26dbd92	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	100:cbbeb26dbd92	21	* may be used to endorse or promote products derived from this software
Kojto	100:cbbeb26dbd92	22	* without specific prior written permission.
Kojto	100:cbbeb26dbd92	23	*
Kojto	100:cbbeb26dbd92	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	100:cbbeb26dbd92	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	100:cbbeb26dbd92	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	100:cbbeb26dbd92	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	100:cbbeb26dbd92	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	100:cbbeb26dbd92	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	100:cbbeb26dbd92	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	100:cbbeb26dbd92	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	100:cbbeb26dbd92	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	100:cbbeb26dbd92	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	100:cbbeb26dbd92	34	*
Kojto	100:cbbeb26dbd92	35	******************************************************************************
Kojto	100:cbbeb26dbd92	36	*/
Kojto	100:cbbeb26dbd92	37
Kojto	100:cbbeb26dbd92	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	100:cbbeb26dbd92	39	#ifndef __STM32F3xx_HAL_RCC_EX_H
Kojto	100:cbbeb26dbd92	40	#define __STM32F3xx_HAL_RCC_EX_H
Kojto	100:cbbeb26dbd92	41
Kojto	100:cbbeb26dbd92	42	#ifdef __cplusplus
Kojto	100:cbbeb26dbd92	43	extern "C" {
Kojto	100:cbbeb26dbd92	44	#endif
Kojto	100:cbbeb26dbd92	45
Kojto	100:cbbeb26dbd92	46	/* Includes ------------------------------------------------------------------*/
Kojto	100:cbbeb26dbd92	47	#include "stm32f3xx_hal_def.h"
Kojto	100:cbbeb26dbd92	48
Kojto	100:cbbeb26dbd92	49	/** @addtogroup STM32F3xx_HAL_Driver
Kojto	100:cbbeb26dbd92	50	* @{
Kojto	100:cbbeb26dbd92	51	*/
Kojto	100:cbbeb26dbd92	52
Kojto	100:cbbeb26dbd92	53	/** @addtogroup RCCEx
Kojto	100:cbbeb26dbd92	54	* @{
Kojto	100:cbbeb26dbd92	55	*/
Kojto	100:cbbeb26dbd92	56
Kojto	100:cbbeb26dbd92	57	/* Exported types ------------------------------------------------------------*/
Kojto	100:cbbeb26dbd92	58
Kojto	100:cbbeb26dbd92	59	/** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
Kojto	100:cbbeb26dbd92	60	* @{
Kojto	100:cbbeb26dbd92	61	*/
Kojto	100:cbbeb26dbd92	62	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	63	/**
Kojto	100:cbbeb26dbd92	64	* @brief RCC PLL configuration structure definition
Kojto	100:cbbeb26dbd92	65	*/
Kojto	100:cbbeb26dbd92	66	typedef struct
Kojto	100:cbbeb26dbd92	67	{
Kojto	100:cbbeb26dbd92	68	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto	100:cbbeb26dbd92	69	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	100:cbbeb26dbd92	70
Kojto	100:cbbeb26dbd92	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	100:cbbeb26dbd92	72	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
Kojto	100:cbbeb26dbd92	73
Kojto	100:cbbeb26dbd92	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	100:cbbeb26dbd92	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	100:cbbeb26dbd92	76
Kojto	100:cbbeb26dbd92	77	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto	100:cbbeb26dbd92	78	This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
Kojto	100:cbbeb26dbd92	79
Kojto	100:cbbeb26dbd92	80	}RCC_PLLInitTypeDef;
Kojto	100:cbbeb26dbd92	81
Kojto	100:cbbeb26dbd92	82	/**
Kojto	100:cbbeb26dbd92	83	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	100:cbbeb26dbd92	84	*/
Kojto	100:cbbeb26dbd92	85	typedef struct
Kojto	100:cbbeb26dbd92	86	{
Kojto	100:cbbeb26dbd92	87	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	100:cbbeb26dbd92	88	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	100:cbbeb26dbd92	89
Kojto	100:cbbeb26dbd92	90	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	100:cbbeb26dbd92	91	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	100:cbbeb26dbd92	92
Kojto	100:cbbeb26dbd92	93	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	100:cbbeb26dbd92	94	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	100:cbbeb26dbd92	95
Kojto	100:cbbeb26dbd92	96	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	100:cbbeb26dbd92	97	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	100:cbbeb26dbd92	98
Kojto	100:cbbeb26dbd92	99	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	100:cbbeb26dbd92	100	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	100:cbbeb26dbd92	101
Kojto	100:cbbeb26dbd92	102	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	100:cbbeb26dbd92	103	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	100:cbbeb26dbd92	104
Kojto	100:cbbeb26dbd92	105	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	100:cbbeb26dbd92	106
Kojto	100:cbbeb26dbd92	107	}RCC_OscInitTypeDef;
Kojto	100:cbbeb26dbd92	108
Kojto	100:cbbeb26dbd92	109	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	110
Kojto	100:cbbeb26dbd92	111	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	112	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	113	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	100:cbbeb26dbd92	114	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	115	/**
Kojto	100:cbbeb26dbd92	116	* @brief RCC PLL configuration structure definition
Kojto	100:cbbeb26dbd92	117	*/
Kojto	100:cbbeb26dbd92	118	typedef struct
Kojto	100:cbbeb26dbd92	119	{
Kojto	100:cbbeb26dbd92	120	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto	100:cbbeb26dbd92	121	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	100:cbbeb26dbd92	122
Kojto	100:cbbeb26dbd92	123	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	100:cbbeb26dbd92	124	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
Kojto	100:cbbeb26dbd92	125
Kojto	100:cbbeb26dbd92	126	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	100:cbbeb26dbd92	127	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	100:cbbeb26dbd92	128
Kojto	100:cbbeb26dbd92	129	}RCC_PLLInitTypeDef;
Kojto	100:cbbeb26dbd92	130
Kojto	100:cbbeb26dbd92	131	/**
Kojto	100:cbbeb26dbd92	132	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	100:cbbeb26dbd92	133	*/
Kojto	100:cbbeb26dbd92	134	typedef struct
Kojto	100:cbbeb26dbd92	135	{
Kojto	100:cbbeb26dbd92	136	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	100:cbbeb26dbd92	137	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	100:cbbeb26dbd92	138
Kojto	100:cbbeb26dbd92	139	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	100:cbbeb26dbd92	140	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	100:cbbeb26dbd92	141
Kojto	100:cbbeb26dbd92	142	uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
Kojto	100:cbbeb26dbd92	143	This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
Kojto	100:cbbeb26dbd92	144
Kojto	100:cbbeb26dbd92	145	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	100:cbbeb26dbd92	146	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	100:cbbeb26dbd92	147
Kojto	100:cbbeb26dbd92	148	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	100:cbbeb26dbd92	149	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	100:cbbeb26dbd92	150
Kojto	100:cbbeb26dbd92	151	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	100:cbbeb26dbd92	152	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	100:cbbeb26dbd92	153
Kojto	100:cbbeb26dbd92	154	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	100:cbbeb26dbd92	155	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	100:cbbeb26dbd92	156
Kojto	100:cbbeb26dbd92	157	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	100:cbbeb26dbd92	158
Kojto	100:cbbeb26dbd92	159	}RCC_OscInitTypeDef;
Kojto	100:cbbeb26dbd92	160	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	161	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	162	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	163	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	164
Kojto	100:cbbeb26dbd92	165	/**
Kojto	100:cbbeb26dbd92	166	* @brief RCC extended clocks structure definition
Kojto	100:cbbeb26dbd92	167	*/
Kojto	100:cbbeb26dbd92	168	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	169	typedef struct
Kojto	100:cbbeb26dbd92	170	{
Kojto	100:cbbeb26dbd92	171	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	172	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	173
Kojto	100:cbbeb26dbd92	174	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	175	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	176
Kojto	100:cbbeb26dbd92	177	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	178	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	179
Kojto	100:cbbeb26dbd92	180	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	181	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	182
Kojto	100:cbbeb26dbd92	183	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	184	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	185
Kojto	100:cbbeb26dbd92	186	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	187	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	188
Kojto	100:cbbeb26dbd92	189	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	190	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	191
Kojto	100:cbbeb26dbd92	192	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	100:cbbeb26dbd92	193	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	100:cbbeb26dbd92	194
Kojto	100:cbbeb26dbd92	195	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	100:cbbeb26dbd92	196	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	100:cbbeb26dbd92	197
Kojto	100:cbbeb26dbd92	198	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	199	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	200
Kojto	100:cbbeb26dbd92	201	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	202	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	203
Kojto	100:cbbeb26dbd92	204	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	100:cbbeb26dbd92	205	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	100:cbbeb26dbd92	206
Kojto	100:cbbeb26dbd92	207	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	100:cbbeb26dbd92	208	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	100:cbbeb26dbd92	209
Kojto	100:cbbeb26dbd92	210	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	100:cbbeb26dbd92	211	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	100:cbbeb26dbd92	212	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	213	#endif /* STM32F301x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	214
Kojto	100:cbbeb26dbd92	215	#if defined(STM32F302x8)
Kojto	100:cbbeb26dbd92	216	typedef struct
Kojto	100:cbbeb26dbd92	217	{
Kojto	100:cbbeb26dbd92	218	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	219	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	220
Kojto	100:cbbeb26dbd92	221	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	222	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	223
Kojto	100:cbbeb26dbd92	224	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	225	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	226
Kojto	100:cbbeb26dbd92	227	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	228	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	229
Kojto	100:cbbeb26dbd92	230	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	231	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	232
Kojto	100:cbbeb26dbd92	233	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	234	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	235
Kojto	100:cbbeb26dbd92	236	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	237	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	238
Kojto	100:cbbeb26dbd92	239	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	100:cbbeb26dbd92	240	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	100:cbbeb26dbd92	241
Kojto	100:cbbeb26dbd92	242	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	100:cbbeb26dbd92	243	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	100:cbbeb26dbd92	244
Kojto	100:cbbeb26dbd92	245	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	246	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	247
Kojto	100:cbbeb26dbd92	248	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	249	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	250
Kojto	100:cbbeb26dbd92	251	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	100:cbbeb26dbd92	252	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	100:cbbeb26dbd92	253
Kojto	100:cbbeb26dbd92	254	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	100:cbbeb26dbd92	255	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	100:cbbeb26dbd92	256
Kojto	100:cbbeb26dbd92	257	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	100:cbbeb26dbd92	258	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	100:cbbeb26dbd92	259
Kojto	100:cbbeb26dbd92	260	uint32_t USBClockSelection; /*!< USB clock source
Kojto	100:cbbeb26dbd92	261	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	100:cbbeb26dbd92	262
Kojto	100:cbbeb26dbd92	263	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	264	#endif /* STM32F302x8 */
Kojto	100:cbbeb26dbd92	265
Kojto	100:cbbeb26dbd92	266	#if defined(STM32F302xC)
Kojto	100:cbbeb26dbd92	267	typedef struct
Kojto	100:cbbeb26dbd92	268	{
Kojto	100:cbbeb26dbd92	269	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	270	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	271
Kojto	100:cbbeb26dbd92	272	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	273	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	274
Kojto	100:cbbeb26dbd92	275	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	276	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	277
Kojto	100:cbbeb26dbd92	278	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	279	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	280
Kojto	100:cbbeb26dbd92	281	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	282	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	283
Kojto	100:cbbeb26dbd92	284	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	100:cbbeb26dbd92	285	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	100:cbbeb26dbd92	286
Kojto	100:cbbeb26dbd92	287	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	100:cbbeb26dbd92	288	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	100:cbbeb26dbd92	289
Kojto	100:cbbeb26dbd92	290	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	291	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	292
Kojto	100:cbbeb26dbd92	293	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	294	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	295
Kojto	100:cbbeb26dbd92	296	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	297	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	298
Kojto	100:cbbeb26dbd92	299	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	300	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	301
Kojto	100:cbbeb26dbd92	302	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	303	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	304
Kojto	100:cbbeb26dbd92	305	uint32_t USBClockSelection; /*!< USB clock source
Kojto	100:cbbeb26dbd92	306	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	100:cbbeb26dbd92	307
Kojto	100:cbbeb26dbd92	308	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	309	#endif /* STM32F302xC */
Kojto	100:cbbeb26dbd92	310
Kojto	100:cbbeb26dbd92	311	#if defined(STM32F303xC)
Kojto	100:cbbeb26dbd92	312	typedef struct
Kojto	100:cbbeb26dbd92	313	{
Kojto	100:cbbeb26dbd92	314	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	315	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	316
Kojto	100:cbbeb26dbd92	317	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	318	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	319
Kojto	100:cbbeb26dbd92	320	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	321	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	322
Kojto	100:cbbeb26dbd92	323	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	324	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	325
Kojto	100:cbbeb26dbd92	326	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	327	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	328
Kojto	100:cbbeb26dbd92	329	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	100:cbbeb26dbd92	330	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	100:cbbeb26dbd92	331
Kojto	100:cbbeb26dbd92	332	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	100:cbbeb26dbd92	333	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	100:cbbeb26dbd92	334
Kojto	100:cbbeb26dbd92	335	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	336	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	337
Kojto	100:cbbeb26dbd92	338	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	339	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	340
Kojto	100:cbbeb26dbd92	341	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	342	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	343
Kojto	100:cbbeb26dbd92	344	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	100:cbbeb26dbd92	345	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	100:cbbeb26dbd92	346
Kojto	100:cbbeb26dbd92	347	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	348	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	349
Kojto	100:cbbeb26dbd92	350	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	351	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	352
Kojto	100:cbbeb26dbd92	353	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	100:cbbeb26dbd92	354	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	100:cbbeb26dbd92	355
Kojto	100:cbbeb26dbd92	356	uint32_t USBClockSelection; /*!< USB clock source
Kojto	100:cbbeb26dbd92	357	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	100:cbbeb26dbd92	358
Kojto	100:cbbeb26dbd92	359	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	360	#endif /* STM32F303xC */
Kojto	100:cbbeb26dbd92	361
Kojto	100:cbbeb26dbd92	362	#if defined(STM32F302xE)
Kojto	100:cbbeb26dbd92	363	typedef struct
Kojto	100:cbbeb26dbd92	364	{
Kojto	100:cbbeb26dbd92	365	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	366	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	367
Kojto	100:cbbeb26dbd92	368	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	369	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	370
Kojto	100:cbbeb26dbd92	371	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	372	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	373
Kojto	100:cbbeb26dbd92	374	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	375	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	376
Kojto	100:cbbeb26dbd92	377	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	378	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	379
Kojto	100:cbbeb26dbd92	380	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	100:cbbeb26dbd92	381	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	100:cbbeb26dbd92	382
Kojto	100:cbbeb26dbd92	383	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	100:cbbeb26dbd92	384	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	100:cbbeb26dbd92	385
Kojto	100:cbbeb26dbd92	386	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	387	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	388
Kojto	100:cbbeb26dbd92	389	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	390	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	391
Kojto	100:cbbeb26dbd92	392	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	100:cbbeb26dbd92	393	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	100:cbbeb26dbd92	394
Kojto	100:cbbeb26dbd92	395	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	396	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	397
Kojto	100:cbbeb26dbd92	398	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	399	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	400
Kojto	100:cbbeb26dbd92	401	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	402	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	403
Kojto	100:cbbeb26dbd92	404	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto	100:cbbeb26dbd92	405	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto	100:cbbeb26dbd92	406
Kojto	100:cbbeb26dbd92	407	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto	100:cbbeb26dbd92	408	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto	100:cbbeb26dbd92	409
Kojto	100:cbbeb26dbd92	410	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	100:cbbeb26dbd92	411	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	100:cbbeb26dbd92	412
Kojto	100:cbbeb26dbd92	413	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	100:cbbeb26dbd92	414	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	100:cbbeb26dbd92	415
Kojto	100:cbbeb26dbd92	416	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	100:cbbeb26dbd92	417	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	100:cbbeb26dbd92	418
Kojto	100:cbbeb26dbd92	419	uint32_t USBClockSelection; /*!< USB clock source
Kojto	100:cbbeb26dbd92	420	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	100:cbbeb26dbd92	421
Kojto	100:cbbeb26dbd92	422	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	423	#endif /* STM32F302xE */
Kojto	100:cbbeb26dbd92	424
Kojto	100:cbbeb26dbd92	425	#if defined(STM32F303xE)
Kojto	100:cbbeb26dbd92	426	typedef struct
Kojto	100:cbbeb26dbd92	427	{
Kojto	100:cbbeb26dbd92	428	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	429	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	430
Kojto	100:cbbeb26dbd92	431	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	432	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	433
Kojto	100:cbbeb26dbd92	434	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	435	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	436
Kojto	100:cbbeb26dbd92	437	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	438	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	439
Kojto	100:cbbeb26dbd92	440	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	441	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	442
Kojto	100:cbbeb26dbd92	443	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	100:cbbeb26dbd92	444	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	100:cbbeb26dbd92	445
Kojto	100:cbbeb26dbd92	446	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	100:cbbeb26dbd92	447	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	100:cbbeb26dbd92	448
Kojto	100:cbbeb26dbd92	449	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	450	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	451
Kojto	100:cbbeb26dbd92	452	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	453	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	454
Kojto	100:cbbeb26dbd92	455	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	100:cbbeb26dbd92	456	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	100:cbbeb26dbd92	457
Kojto	100:cbbeb26dbd92	458	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	459	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	460
Kojto	100:cbbeb26dbd92	461	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	100:cbbeb26dbd92	462	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	100:cbbeb26dbd92	463
Kojto	100:cbbeb26dbd92	464	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	465	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	466
Kojto	100:cbbeb26dbd92	467	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	468	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	469
Kojto	100:cbbeb26dbd92	470	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto	100:cbbeb26dbd92	471	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto	100:cbbeb26dbd92	472
Kojto	100:cbbeb26dbd92	473	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto	100:cbbeb26dbd92	474	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto	100:cbbeb26dbd92	475
Kojto	100:cbbeb26dbd92	476	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	100:cbbeb26dbd92	477	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	100:cbbeb26dbd92	478
Kojto	100:cbbeb26dbd92	479	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	100:cbbeb26dbd92	480	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	100:cbbeb26dbd92	481
Kojto	100:cbbeb26dbd92	482	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	100:cbbeb26dbd92	483	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	100:cbbeb26dbd92	484
Kojto	100:cbbeb26dbd92	485	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	100:cbbeb26dbd92	486	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	100:cbbeb26dbd92	487
Kojto	100:cbbeb26dbd92	488	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
Kojto	100:cbbeb26dbd92	489	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
Kojto	100:cbbeb26dbd92	490
Kojto	100:cbbeb26dbd92	491	uint32_t USBClockSelection; /*!< USB clock source
Kojto	100:cbbeb26dbd92	492	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	100:cbbeb26dbd92	493
Kojto	100:cbbeb26dbd92	494	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	495	#endif /* STM32F303xE */
Kojto	100:cbbeb26dbd92	496
Kojto	100:cbbeb26dbd92	497	#if defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	498	typedef struct
Kojto	100:cbbeb26dbd92	499	{
Kojto	100:cbbeb26dbd92	500	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	501	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	502
Kojto	100:cbbeb26dbd92	503	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	504	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	505
Kojto	100:cbbeb26dbd92	506	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	507	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	508
Kojto	100:cbbeb26dbd92	509	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	510	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	511
Kojto	100:cbbeb26dbd92	512	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	513	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	514
Kojto	100:cbbeb26dbd92	515	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	100:cbbeb26dbd92	516	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	100:cbbeb26dbd92	517
Kojto	100:cbbeb26dbd92	518	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	100:cbbeb26dbd92	519	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	100:cbbeb26dbd92	520
Kojto	100:cbbeb26dbd92	521	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	522	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	523
Kojto	100:cbbeb26dbd92	524	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	525	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	526
Kojto	100:cbbeb26dbd92	527	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	100:cbbeb26dbd92	528	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	100:cbbeb26dbd92	529
Kojto	100:cbbeb26dbd92	530	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	531	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	532
Kojto	100:cbbeb26dbd92	533	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	100:cbbeb26dbd92	534	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	100:cbbeb26dbd92	535
Kojto	100:cbbeb26dbd92	536	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	537	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	538
Kojto	100:cbbeb26dbd92	539	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	540	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	541
Kojto	100:cbbeb26dbd92	542	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto	100:cbbeb26dbd92	543	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto	100:cbbeb26dbd92	544
Kojto	100:cbbeb26dbd92	545	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto	100:cbbeb26dbd92	546	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto	100:cbbeb26dbd92	547
Kojto	100:cbbeb26dbd92	548	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	100:cbbeb26dbd92	549	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	100:cbbeb26dbd92	550
Kojto	100:cbbeb26dbd92	551	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	100:cbbeb26dbd92	552	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	100:cbbeb26dbd92	553
Kojto	100:cbbeb26dbd92	554	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	100:cbbeb26dbd92	555	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	100:cbbeb26dbd92	556
Kojto	100:cbbeb26dbd92	557	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	100:cbbeb26dbd92	558	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	100:cbbeb26dbd92	559
Kojto	100:cbbeb26dbd92	560	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
Kojto	100:cbbeb26dbd92	561	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
Kojto	100:cbbeb26dbd92	562
Kojto	100:cbbeb26dbd92	563	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	564	#endif /* STM32F398xx */
Kojto	100:cbbeb26dbd92	565
Kojto	100:cbbeb26dbd92	566	#if defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	567	typedef struct
Kojto	100:cbbeb26dbd92	568	{
Kojto	100:cbbeb26dbd92	569	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	570	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	571
Kojto	100:cbbeb26dbd92	572	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	573	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	574
Kojto	100:cbbeb26dbd92	575	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	576	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	577
Kojto	100:cbbeb26dbd92	578	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	579	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	580
Kojto	100:cbbeb26dbd92	581	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	582	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	583
Kojto	100:cbbeb26dbd92	584	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	100:cbbeb26dbd92	585	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	100:cbbeb26dbd92	586
Kojto	100:cbbeb26dbd92	587	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	100:cbbeb26dbd92	588	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	100:cbbeb26dbd92	589
Kojto	100:cbbeb26dbd92	590	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	591	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	592
Kojto	100:cbbeb26dbd92	593	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	594	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	595
Kojto	100:cbbeb26dbd92	596	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	597	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	598
Kojto	100:cbbeb26dbd92	599	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	100:cbbeb26dbd92	600	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	100:cbbeb26dbd92	601
Kojto	100:cbbeb26dbd92	602	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	100:cbbeb26dbd92	603	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	100:cbbeb26dbd92	604
Kojto	100:cbbeb26dbd92	605	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	606	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	607
Kojto	100:cbbeb26dbd92	608	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	100:cbbeb26dbd92	609	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	100:cbbeb26dbd92	610
Kojto	100:cbbeb26dbd92	611	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	612	#endif /* STM32F358xx */
Kojto	100:cbbeb26dbd92	613
Kojto	100:cbbeb26dbd92	614	#if defined(STM32F303x8)
Kojto	100:cbbeb26dbd92	615	typedef struct
Kojto	100:cbbeb26dbd92	616	{
Kojto	100:cbbeb26dbd92	617	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	618	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	619
Kojto	100:cbbeb26dbd92	620	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	621	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	622
Kojto	100:cbbeb26dbd92	623	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	624	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	625
Kojto	100:cbbeb26dbd92	626	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	627	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	628
Kojto	100:cbbeb26dbd92	629	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	630	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	631
Kojto	100:cbbeb26dbd92	632	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	633	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	634
Kojto	100:cbbeb26dbd92	635	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	636	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	637
Kojto	100:cbbeb26dbd92	638	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	639	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	640
Kojto	100:cbbeb26dbd92	641	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	642	#endif /* STM32F303x8 */
Kojto	100:cbbeb26dbd92	643
Kojto	100:cbbeb26dbd92	644	#if defined(STM32F334x8)
Kojto	100:cbbeb26dbd92	645	typedef struct
Kojto	100:cbbeb26dbd92	646	{
Kojto	100:cbbeb26dbd92	647	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	648	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	649
Kojto	100:cbbeb26dbd92	650	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	651	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	652
Kojto	100:cbbeb26dbd92	653	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	654	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	655
Kojto	100:cbbeb26dbd92	656	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	657	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	658
Kojto	100:cbbeb26dbd92	659	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	660	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	661
Kojto	100:cbbeb26dbd92	662	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	663	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	664
Kojto	100:cbbeb26dbd92	665	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	666	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	667
Kojto	100:cbbeb26dbd92	668	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	669	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	670
Kojto	100:cbbeb26dbd92	671	uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
Kojto	100:cbbeb26dbd92	672	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	673
Kojto	100:cbbeb26dbd92	674	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	675	#endif /* STM32F334x8 */
Kojto	100:cbbeb26dbd92	676
Kojto	100:cbbeb26dbd92	677	#if defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	678	typedef struct
Kojto	100:cbbeb26dbd92	679	{
Kojto	100:cbbeb26dbd92	680	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	681	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	682
Kojto	100:cbbeb26dbd92	683	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	684	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	685
Kojto	100:cbbeb26dbd92	686	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	687	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	688
Kojto	100:cbbeb26dbd92	689	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	690	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	691
Kojto	100:cbbeb26dbd92	692	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	693	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	694
Kojto	100:cbbeb26dbd92	695	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	696	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	697
Kojto	100:cbbeb26dbd92	698	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	100:cbbeb26dbd92	699	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	100:cbbeb26dbd92	700
Kojto	100:cbbeb26dbd92	701	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	100:cbbeb26dbd92	702	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	100:cbbeb26dbd92	703
Kojto	100:cbbeb26dbd92	704	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	705	#endif /* STM32F328xx */
Kojto	100:cbbeb26dbd92	706
Kojto	100:cbbeb26dbd92	707	#if defined(STM32F373xC)
Kojto	100:cbbeb26dbd92	708	typedef struct
Kojto	100:cbbeb26dbd92	709	{
Kojto	100:cbbeb26dbd92	710	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	711	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	712
Kojto	100:cbbeb26dbd92	713	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	714	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	715
Kojto	100:cbbeb26dbd92	716	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	717	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	718
Kojto	100:cbbeb26dbd92	719	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	720	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	721
Kojto	100:cbbeb26dbd92	722	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	723	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	724
Kojto	100:cbbeb26dbd92	725	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	726	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	727
Kojto	100:cbbeb26dbd92	728	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	729	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	730
Kojto	100:cbbeb26dbd92	731	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	100:cbbeb26dbd92	732	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	100:cbbeb26dbd92	733
Kojto	100:cbbeb26dbd92	734	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
Kojto	100:cbbeb26dbd92	735	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
Kojto	100:cbbeb26dbd92	736
Kojto	100:cbbeb26dbd92	737	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	100:cbbeb26dbd92	738	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	100:cbbeb26dbd92	739
Kojto	100:cbbeb26dbd92	740	uint32_t USBClockSelection; /*!< USB clock source
Kojto	100:cbbeb26dbd92	741	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	100:cbbeb26dbd92	742
Kojto	100:cbbeb26dbd92	743	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	744	#endif /* STM32F373xC */
Kojto	100:cbbeb26dbd92	745
Kojto	100:cbbeb26dbd92	746	#if defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	747	typedef struct
Kojto	100:cbbeb26dbd92	748	{
Kojto	100:cbbeb26dbd92	749	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	100:cbbeb26dbd92	750	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	100:cbbeb26dbd92	751
Kojto	100:cbbeb26dbd92	752	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	100:cbbeb26dbd92	753	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	100:cbbeb26dbd92	754
Kojto	100:cbbeb26dbd92	755	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	100:cbbeb26dbd92	756	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	100:cbbeb26dbd92	757
Kojto	100:cbbeb26dbd92	758	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	100:cbbeb26dbd92	759	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	100:cbbeb26dbd92	760
Kojto	100:cbbeb26dbd92	761	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	100:cbbeb26dbd92	762	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	100:cbbeb26dbd92	763
Kojto	100:cbbeb26dbd92	764	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	100:cbbeb26dbd92	765	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	100:cbbeb26dbd92	766
Kojto	100:cbbeb26dbd92	767	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	100:cbbeb26dbd92	768	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	100:cbbeb26dbd92	769
Kojto	100:cbbeb26dbd92	770	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	100:cbbeb26dbd92	771	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	100:cbbeb26dbd92	772
Kojto	100:cbbeb26dbd92	773	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
Kojto	100:cbbeb26dbd92	774	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
Kojto	100:cbbeb26dbd92	775
Kojto	100:cbbeb26dbd92	776	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	100:cbbeb26dbd92	777	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	100:cbbeb26dbd92	778
Kojto	100:cbbeb26dbd92	779	}RCC_PeriphCLKInitTypeDef;
Kojto	100:cbbeb26dbd92	780	#endif /* STM32F378xx */
Kojto	100:cbbeb26dbd92	781
Kojto	100:cbbeb26dbd92	782	/**
Kojto	100:cbbeb26dbd92	783	* @}
Kojto	100:cbbeb26dbd92	784	*/
Kojto	100:cbbeb26dbd92	785
Kojto	100:cbbeb26dbd92	786	/* Exported constants --------------------------------------------------------*/
Kojto	100:cbbeb26dbd92	787	/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
Kojto	100:cbbeb26dbd92	788	* @{
Kojto	100:cbbeb26dbd92	789	*/
Kojto	100:cbbeb26dbd92	790	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	791	defined(STM32F334x8) \|\| \
Kojto	100:cbbeb26dbd92	792	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	793	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
Kojto	100:cbbeb26dbd92	794	* @{
Kojto	100:cbbeb26dbd92	795	*/
Kojto	100:cbbeb26dbd92	796	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto	100:cbbeb26dbd92	797	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	100:cbbeb26dbd92	798	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	100:cbbeb26dbd92	799	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	100:cbbeb26dbd92	800	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	100:cbbeb26dbd92	801	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	100:cbbeb26dbd92	802	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto	100:cbbeb26dbd92	803
Kojto	100:cbbeb26dbd92	804	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	100:cbbeb26dbd92	805	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	100:cbbeb26dbd92	806	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	807	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	808	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	809	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	100:cbbeb26dbd92	810	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
Kojto	100:cbbeb26dbd92	811	/**
Kojto	100:cbbeb26dbd92	812	* @}
Kojto	100:cbbeb26dbd92	813	*/
Kojto	100:cbbeb26dbd92	814	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	815	/* STM32F334x8 */
Kojto	100:cbbeb26dbd92	816	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	817
Kojto	100:cbbeb26dbd92	818	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	819	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	820	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	821	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
Kojto	100:cbbeb26dbd92	822	* @{
Kojto	100:cbbeb26dbd92	823	*/
Kojto	100:cbbeb26dbd92	824	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto	100:cbbeb26dbd92	825	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	100:cbbeb26dbd92	826	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	100:cbbeb26dbd92	827	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	100:cbbeb26dbd92	828	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	100:cbbeb26dbd92	829	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	100:cbbeb26dbd92	830	#define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV \| RCC_CFGR_MCO_PLL)
Kojto	100:cbbeb26dbd92	831	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto	100:cbbeb26dbd92	832
Kojto	100:cbbeb26dbd92	833	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	100:cbbeb26dbd92	834	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	100:cbbeb26dbd92	835	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	836	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	837	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	838	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	100:cbbeb26dbd92	839	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	840	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
Kojto	100:cbbeb26dbd92	841	/**
Kojto	100:cbbeb26dbd92	842	* @}
Kojto	100:cbbeb26dbd92	843	*/
Kojto	100:cbbeb26dbd92	844	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	845	/* STM32F303x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	846	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	847
Kojto	100:cbbeb26dbd92	848	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	849	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
Kojto	100:cbbeb26dbd92	850	* @{
Kojto	100:cbbeb26dbd92	851	*/
Kojto	100:cbbeb26dbd92	852	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	100:cbbeb26dbd92	853	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto	100:cbbeb26dbd92	854
Kojto	100:cbbeb26dbd92	855	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	856	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	100:cbbeb26dbd92	857	/**
Kojto	100:cbbeb26dbd92	858	* @}
Kojto	100:cbbeb26dbd92	859	*/
Kojto	100:cbbeb26dbd92	860
Kojto	100:cbbeb26dbd92	861	/** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
Kojto	100:cbbeb26dbd92	862	* @{
Kojto	100:cbbeb26dbd92	863	*/
Kojto	100:cbbeb26dbd92	864	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	100:cbbeb26dbd92	865	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	100:cbbeb26dbd92	866	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	100:cbbeb26dbd92	867	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	100:cbbeb26dbd92	868	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	100:cbbeb26dbd92	869	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	100:cbbeb26dbd92	870	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	100:cbbeb26dbd92	871	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	100:cbbeb26dbd92	872	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	100:cbbeb26dbd92	873	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	100:cbbeb26dbd92	874	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	100:cbbeb26dbd92	875	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	100:cbbeb26dbd92	876	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	100:cbbeb26dbd92	877	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	100:cbbeb26dbd92	878	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	100:cbbeb26dbd92	879	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	100:cbbeb26dbd92	880
Kojto	100:cbbeb26dbd92	881	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
Kojto	100:cbbeb26dbd92	882	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	883	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
Kojto	100:cbbeb26dbd92	884	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	885	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
Kojto	100:cbbeb26dbd92	886	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	887	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
Kojto	100:cbbeb26dbd92	888	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
Kojto	100:cbbeb26dbd92	889	/**
Kojto	100:cbbeb26dbd92	890	* @}
Kojto	100:cbbeb26dbd92	891	*/
Kojto	100:cbbeb26dbd92	892	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	893
Kojto	100:cbbeb26dbd92	894	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	895	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	896	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	100:cbbeb26dbd92	897	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	898	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
Kojto	100:cbbeb26dbd92	899	* @{
Kojto	100:cbbeb26dbd92	900	*/
Kojto	100:cbbeb26dbd92	901	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	100:cbbeb26dbd92	902	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto	100:cbbeb26dbd92	903
Kojto	100:cbbeb26dbd92	904	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	905	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	100:cbbeb26dbd92	906	/**
Kojto	100:cbbeb26dbd92	907	* @}
Kojto	100:cbbeb26dbd92	908	*/
Kojto	100:cbbeb26dbd92	909
Kojto	100:cbbeb26dbd92	910	/** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
Kojto	100:cbbeb26dbd92	911	* @{
Kojto	100:cbbeb26dbd92	912	*/
Kojto	100:cbbeb26dbd92	913
Kojto	100:cbbeb26dbd92	914	#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	100:cbbeb26dbd92	915	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	100:cbbeb26dbd92	916	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	100:cbbeb26dbd92	917	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	100:cbbeb26dbd92	918	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	100:cbbeb26dbd92	919	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	100:cbbeb26dbd92	920	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	100:cbbeb26dbd92	921	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	100:cbbeb26dbd92	922	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	100:cbbeb26dbd92	923	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	100:cbbeb26dbd92	924	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	100:cbbeb26dbd92	925	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	100:cbbeb26dbd92	926	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	100:cbbeb26dbd92	927	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	100:cbbeb26dbd92	928	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	100:cbbeb26dbd92	929	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	100:cbbeb26dbd92	930
Kojto	100:cbbeb26dbd92	931	#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) \|\| ((DIV) == RCC_HSE_PREDIV_DIV2) \|\| \
Kojto	100:cbbeb26dbd92	932	((DIV) == RCC_HSE_PREDIV_DIV3) \|\| ((DIV) == RCC_HSE_PREDIV_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	933	((DIV) == RCC_HSE_PREDIV_DIV5) \|\| ((DIV) == RCC_HSE_PREDIV_DIV6) \|\| \
Kojto	100:cbbeb26dbd92	934	((DIV) == RCC_HSE_PREDIV_DIV7) \|\| ((DIV) == RCC_HSE_PREDIV_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	935	((DIV) == RCC_HSE_PREDIV_DIV9) \|\| ((DIV) == RCC_HSE_PREDIV_DIV10) \|\| \
Kojto	100:cbbeb26dbd92	936	((DIV) == RCC_HSE_PREDIV_DIV11) \|\| ((DIV) == RCC_HSE_PREDIV_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	937	((DIV) == RCC_HSE_PREDIV_DIV13) \|\| ((DIV) == RCC_HSE_PREDIV_DIV14) \|\| \
Kojto	100:cbbeb26dbd92	938	((DIV) == RCC_HSE_PREDIV_DIV15) \|\| ((DIV) == RCC_HSE_PREDIV_DIV16))
Kojto	100:cbbeb26dbd92	939	/**
Kojto	100:cbbeb26dbd92	940	* @}
Kojto	100:cbbeb26dbd92	941	*/
Kojto	100:cbbeb26dbd92	942	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	943	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	944	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	945	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	946
Kojto	100:cbbeb26dbd92	947	/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
Kojto	100:cbbeb26dbd92	948	* @{
Kojto	100:cbbeb26dbd92	949	*/
Kojto	100:cbbeb26dbd92	950	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	951	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	952	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	953	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	954	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	955	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	956	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	957	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	958	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	959	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
Kojto	100:cbbeb26dbd92	960	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	961	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
Kojto	100:cbbeb26dbd92	962	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
Kojto	100:cbbeb26dbd92	963	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
Kojto	100:cbbeb26dbd92	964
Kojto	100:cbbeb26dbd92	965	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	966	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	967	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
Kojto	100:cbbeb26dbd92	968	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
Kojto	100:cbbeb26dbd92	969	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	100:cbbeb26dbd92	970	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_RTC))
Kojto	100:cbbeb26dbd92	971	#endif /* STM32F301x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	972
Kojto	100:cbbeb26dbd92	973	#if defined(STM32F302x8)
Kojto	100:cbbeb26dbd92	974	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	975	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	976	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	977	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	978	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	979	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	980	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	981	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	982	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
Kojto	100:cbbeb26dbd92	983	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	984	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	100:cbbeb26dbd92	985	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
Kojto	100:cbbeb26dbd92	986	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
Kojto	100:cbbeb26dbd92	987	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
Kojto	100:cbbeb26dbd92	988
Kojto	100:cbbeb26dbd92	989	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	990	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	991	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
Kojto	100:cbbeb26dbd92	992	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
Kojto	100:cbbeb26dbd92	993	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB \| \
Kojto	100:cbbeb26dbd92	994	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	100:cbbeb26dbd92	995	RCC_PERIPHCLK_TIM17))
Kojto	100:cbbeb26dbd92	996	#endif /* STM32F302x8 */
Kojto	100:cbbeb26dbd92	997
Kojto	100:cbbeb26dbd92	998	#if defined(STM32F302xC)
Kojto	100:cbbeb26dbd92	999	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1000	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1001	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1002	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	100:cbbeb26dbd92	1003	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	100:cbbeb26dbd92	1004	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1005	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1006	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1007	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	1008	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1009	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1010	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	100:cbbeb26dbd92	1011
Kojto	100:cbbeb26dbd92	1012	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1013	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	100:cbbeb26dbd92	1014	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1015	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
Kojto	100:cbbeb26dbd92	1016	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
Kojto	100:cbbeb26dbd92	1017	RCC_PERIPHCLK_USB))
Kojto	100:cbbeb26dbd92	1018	#endif /* STM32F302xC */
Kojto	100:cbbeb26dbd92	1019
Kojto	100:cbbeb26dbd92	1020	#if defined(STM32F303xC)
Kojto	100:cbbeb26dbd92	1021	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1022	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1023	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1024	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	100:cbbeb26dbd92	1025	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	100:cbbeb26dbd92	1026	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1027	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1028	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1029	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	100:cbbeb26dbd92	1030	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	1031	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1032	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	100:cbbeb26dbd92	1033	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1034	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	100:cbbeb26dbd92	1035
Kojto	100:cbbeb26dbd92	1036	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1037	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	100:cbbeb26dbd92	1038	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1039	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	100:cbbeb26dbd92	1040	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	100:cbbeb26dbd92	1041	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
Kojto	100:cbbeb26dbd92	1042	RCC_PERIPHCLK_USB))
Kojto	100:cbbeb26dbd92	1043	#endif /* STM32F303xC */
Kojto	100:cbbeb26dbd92	1044
Kojto	100:cbbeb26dbd92	1045	#if defined(STM32F302xE)
Kojto	100:cbbeb26dbd92	1046	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1047	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1048	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1049	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	100:cbbeb26dbd92	1050	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	100:cbbeb26dbd92	1051	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1052	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1053	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1054	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	1055	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1056	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1057	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	100:cbbeb26dbd92	1058	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto	100:cbbeb26dbd92	1059	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto	100:cbbeb26dbd92	1060	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto	100:cbbeb26dbd92	1061	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto	100:cbbeb26dbd92	1062	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto	100:cbbeb26dbd92	1063	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto	100:cbbeb26dbd92	1064
Kojto	100:cbbeb26dbd92	1065	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1066	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	100:cbbeb26dbd92	1067	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1068	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
Kojto	100:cbbeb26dbd92	1069	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
Kojto	100:cbbeb26dbd92	1070	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
Kojto	100:cbbeb26dbd92	1071	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
Kojto	100:cbbeb26dbd92	1072	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	100:cbbeb26dbd92	1073	RCC_PERIPHCLK_TIM17))
Kojto	100:cbbeb26dbd92	1074	#endif /* STM32F302xE */
Kojto	100:cbbeb26dbd92	1075
Kojto	100:cbbeb26dbd92	1076	#if defined(STM32F303xE)
Kojto	100:cbbeb26dbd92	1077	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1078	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1079	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1080	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	100:cbbeb26dbd92	1081	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	100:cbbeb26dbd92	1082	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1083	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1084	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1085	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	100:cbbeb26dbd92	1086	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	1087	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1088	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	100:cbbeb26dbd92	1089	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1090	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	100:cbbeb26dbd92	1091	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto	100:cbbeb26dbd92	1092	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto	100:cbbeb26dbd92	1093	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto	100:cbbeb26dbd92	1094	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto	100:cbbeb26dbd92	1095	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto	100:cbbeb26dbd92	1096	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto	100:cbbeb26dbd92	1097	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
Kojto	100:cbbeb26dbd92	1098
Kojto	100:cbbeb26dbd92	1099	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1100	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	100:cbbeb26dbd92	1101	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1102	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	100:cbbeb26dbd92	1103	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	100:cbbeb26dbd92	1104	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
Kojto	100:cbbeb26dbd92	1105	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
Kojto	100:cbbeb26dbd92	1106	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
Kojto	100:cbbeb26dbd92	1107	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	100:cbbeb26dbd92	1108	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_TIM20))
Kojto	100:cbbeb26dbd92	1109	#endif /* STM32F303xE */
Kojto	100:cbbeb26dbd92	1110
Kojto	100:cbbeb26dbd92	1111	#if defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	1112	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1113	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1114	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1115	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	100:cbbeb26dbd92	1116	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	100:cbbeb26dbd92	1117	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1118	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1119	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1120	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	100:cbbeb26dbd92	1121	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	1122	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1123	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	100:cbbeb26dbd92	1124	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1125	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto	100:cbbeb26dbd92	1126	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto	100:cbbeb26dbd92	1127	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto	100:cbbeb26dbd92	1128	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto	100:cbbeb26dbd92	1129	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto	100:cbbeb26dbd92	1130	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto	100:cbbeb26dbd92	1131	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
Kojto	100:cbbeb26dbd92	1132
Kojto	100:cbbeb26dbd92	1133	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1134	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	100:cbbeb26dbd92	1135	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1136	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	100:cbbeb26dbd92	1137	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	100:cbbeb26dbd92	1138	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
Kojto	100:cbbeb26dbd92	1139	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM2 \| \
Kojto	100:cbbeb26dbd92	1140	RCC_PERIPHCLK_TIM34 \| RCC_PERIPHCLK_TIM15 \| \
Kojto	100:cbbeb26dbd92	1141	RCC_PERIPHCLK_TIM16 \| RCC_PERIPHCLK_TIM17 \| \
Kojto	100:cbbeb26dbd92	1142	RCC_PERIPHCLK_TIM20))
Kojto	100:cbbeb26dbd92	1143	#endif /* STM32F398xx */
Kojto	100:cbbeb26dbd92	1144
Kojto	100:cbbeb26dbd92	1145	#if defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	1146	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1147	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1148	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1149	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	100:cbbeb26dbd92	1150	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	100:cbbeb26dbd92	1151	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1152	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1153	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1154	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	100:cbbeb26dbd92	1155	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	100:cbbeb26dbd92	1156	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1157	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	100:cbbeb26dbd92	1158	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1159
Kojto	100:cbbeb26dbd92	1160	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1161	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	100:cbbeb26dbd92	1162	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1163	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	100:cbbeb26dbd92	1164	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	100:cbbeb26dbd92	1165	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC))
Kojto	100:cbbeb26dbd92	1166	#endif /* STM32F358xx */
Kojto	100:cbbeb26dbd92	1167
Kojto	100:cbbeb26dbd92	1168	#if defined(STM32F303x8)
Kojto	100:cbbeb26dbd92	1169	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1170	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1171	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1172	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1173	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1174	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1175	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1176
Kojto	100:cbbeb26dbd92	1177	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1178	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
Kojto	100:cbbeb26dbd92	1179	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
Kojto	100:cbbeb26dbd92	1180	#endif /* STM32F303x8 */
Kojto	100:cbbeb26dbd92	1181
Kojto	100:cbbeb26dbd92	1182	#if defined(STM32F334x8)
Kojto	100:cbbeb26dbd92	1183	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1184	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1185	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1186	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1187	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1188	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1189	#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
Kojto	100:cbbeb26dbd92	1190	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1191
Kojto	100:cbbeb26dbd92	1192	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1193	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
Kojto	100:cbbeb26dbd92	1194	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_HRTIM1 \| \
Kojto	100:cbbeb26dbd92	1195	RCC_PERIPHCLK_RTC))
Kojto	100:cbbeb26dbd92	1196	#endif /* STM32F334x8 */
Kojto	100:cbbeb26dbd92	1197
Kojto	100:cbbeb26dbd92	1198	#if defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	1199	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1200	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1201	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1202	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1203	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1204	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	100:cbbeb26dbd92	1205	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1206
Kojto	100:cbbeb26dbd92	1207	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1208	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
Kojto	100:cbbeb26dbd92	1209	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
Kojto	100:cbbeb26dbd92	1210	#endif /* STM32F328xx */
Kojto	100:cbbeb26dbd92	1211
Kojto	100:cbbeb26dbd92	1212	#if defined(STM32F373xC)
Kojto	100:cbbeb26dbd92	1213	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1214	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1215	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1216	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1217	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1218	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1219	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	100:cbbeb26dbd92	1220	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
Kojto	100:cbbeb26dbd92	1221	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1222	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	100:cbbeb26dbd92	1223
Kojto	100:cbbeb26dbd92	1224	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1225	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1226	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
Kojto	100:cbbeb26dbd92	1227	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
Kojto	100:cbbeb26dbd92	1228	RCC_PERIPHCLK_USB))
Kojto	100:cbbeb26dbd92	1229	#endif /* STM32F373xC */
Kojto	100:cbbeb26dbd92	1230
Kojto	100:cbbeb26dbd92	1231	#if defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	1232	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	100:cbbeb26dbd92	1233	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	100:cbbeb26dbd92	1234	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	100:cbbeb26dbd92	1235	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	100:cbbeb26dbd92	1236	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	100:cbbeb26dbd92	1237	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	100:cbbeb26dbd92	1238	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	100:cbbeb26dbd92	1239	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
Kojto	100:cbbeb26dbd92	1240	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	100:cbbeb26dbd92	1241
Kojto	100:cbbeb26dbd92	1242	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	100:cbbeb26dbd92	1243	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	100:cbbeb26dbd92	1244	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
Kojto	100:cbbeb26dbd92	1245	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
Kojto	100:cbbeb26dbd92	1246	#endif /* STM32F378xx */
Kojto	100:cbbeb26dbd92	1247	/**
Kojto	100:cbbeb26dbd92	1248	* @}
Kojto	100:cbbeb26dbd92	1249	*/
Kojto	100:cbbeb26dbd92	1250
Kojto	100:cbbeb26dbd92	1251	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	1252
Kojto	100:cbbeb26dbd92	1253	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	100:cbbeb26dbd92	1254	* @{
Kojto	100:cbbeb26dbd92	1255	*/
Kojto	100:cbbeb26dbd92	1256	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	100:cbbeb26dbd92	1257	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	100:cbbeb26dbd92	1258	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	100:cbbeb26dbd92	1259	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	100:cbbeb26dbd92	1260
Kojto	100:cbbeb26dbd92	1261	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	100:cbbeb26dbd92	1262	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1263	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1264	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1265	/**
Kojto	100:cbbeb26dbd92	1266	* @}
Kojto	100:cbbeb26dbd92	1267	*/
Kojto	100:cbbeb26dbd92	1268
Kojto	100:cbbeb26dbd92	1269	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	100:cbbeb26dbd92	1270	* @{
Kojto	100:cbbeb26dbd92	1271	*/
Kojto	100:cbbeb26dbd92	1272	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	100:cbbeb26dbd92	1273	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	100:cbbeb26dbd92	1274
Kojto	100:cbbeb26dbd92	1275	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1276	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	100:cbbeb26dbd92	1277	/**
Kojto	100:cbbeb26dbd92	1278	* @}
Kojto	100:cbbeb26dbd92	1279	*/
Kojto	100:cbbeb26dbd92	1280
Kojto	100:cbbeb26dbd92	1281	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
Kojto	100:cbbeb26dbd92	1282	* @{
Kojto	100:cbbeb26dbd92	1283	*/
Kojto	100:cbbeb26dbd92	1284	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
Kojto	100:cbbeb26dbd92	1285	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
Kojto	100:cbbeb26dbd92	1286
Kojto	100:cbbeb26dbd92	1287	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1288	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto	100:cbbeb26dbd92	1289	/**
Kojto	100:cbbeb26dbd92	1290	* @}
Kojto	100:cbbeb26dbd92	1291	*/
Kojto	100:cbbeb26dbd92	1292
Kojto	100:cbbeb26dbd92	1293	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
Kojto	100:cbbeb26dbd92	1294	* @{
Kojto	100:cbbeb26dbd92	1295	*/
Kojto	100:cbbeb26dbd92	1296	#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
Kojto	100:cbbeb26dbd92	1297	#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
Kojto	100:cbbeb26dbd92	1298	#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
Kojto	100:cbbeb26dbd92	1299	#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
Kojto	100:cbbeb26dbd92	1300	#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
Kojto	100:cbbeb26dbd92	1301	#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
Kojto	100:cbbeb26dbd92	1302	#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
Kojto	100:cbbeb26dbd92	1303	#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
Kojto	100:cbbeb26dbd92	1304	#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
Kojto	100:cbbeb26dbd92	1305	#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
Kojto	100:cbbeb26dbd92	1306	#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
Kojto	100:cbbeb26dbd92	1307	#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
Kojto	100:cbbeb26dbd92	1308	#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
Kojto	100:cbbeb26dbd92	1309
Kojto	100:cbbeb26dbd92	1310	#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	1311	((ADCCLK) == RCC_ADC1PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	1312	((ADCCLK) == RCC_ADC1PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	1313	((ADCCLK) == RCC_ADC1PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	1314	((ADCCLK) == RCC_ADC1PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) \|\| \
Kojto	100:cbbeb26dbd92	1315	((ADCCLK) == RCC_ADC1PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) \|\| \
Kojto	100:cbbeb26dbd92	1316	((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
Kojto	100:cbbeb26dbd92	1317	/**
Kojto	100:cbbeb26dbd92	1318	* @}
Kojto	100:cbbeb26dbd92	1319	*/
Kojto	100:cbbeb26dbd92	1320
Kojto	100:cbbeb26dbd92	1321	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto	100:cbbeb26dbd92	1322	* @{
Kojto	100:cbbeb26dbd92	1323	*/
Kojto	100:cbbeb26dbd92	1324	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto	100:cbbeb26dbd92	1325	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto	100:cbbeb26dbd92	1326
Kojto	100:cbbeb26dbd92	1327	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1328	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	100:cbbeb26dbd92	1329	/**
Kojto	100:cbbeb26dbd92	1330	* @}
Kojto	100:cbbeb26dbd92	1331	*/
Kojto	100:cbbeb26dbd92	1332
Kojto	100:cbbeb26dbd92	1333	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	100:cbbeb26dbd92	1334	* @{
Kojto	100:cbbeb26dbd92	1335	*/
Kojto	100:cbbeb26dbd92	1336	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	100:cbbeb26dbd92	1337	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	100:cbbeb26dbd92	1338
Kojto	100:cbbeb26dbd92	1339	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1340	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1341	/**
Kojto	100:cbbeb26dbd92	1342	* @}
Kojto	100:cbbeb26dbd92	1343	*/
Kojto	100:cbbeb26dbd92	1344
Kojto	100:cbbeb26dbd92	1345	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
Kojto	100:cbbeb26dbd92	1346	* @{
Kojto	100:cbbeb26dbd92	1347	*/
Kojto	100:cbbeb26dbd92	1348	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
Kojto	100:cbbeb26dbd92	1349	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
Kojto	100:cbbeb26dbd92	1350
Kojto	100:cbbeb26dbd92	1351	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1352	((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1353	/**
Kojto	100:cbbeb26dbd92	1354	* @}
Kojto	100:cbbeb26dbd92	1355	*/
Kojto	100:cbbeb26dbd92	1356
Kojto	100:cbbeb26dbd92	1357	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
Kojto	100:cbbeb26dbd92	1358	* @{
Kojto	100:cbbeb26dbd92	1359	*/
Kojto	100:cbbeb26dbd92	1360	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
Kojto	100:cbbeb26dbd92	1361	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
Kojto	100:cbbeb26dbd92	1362
Kojto	100:cbbeb26dbd92	1363	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1364	((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1365	/**
Kojto	100:cbbeb26dbd92	1366	* @}
Kojto	100:cbbeb26dbd92	1367	*/
Kojto	100:cbbeb26dbd92	1368
Kojto	100:cbbeb26dbd92	1369	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
Kojto	100:cbbeb26dbd92	1370	* @{
Kojto	100:cbbeb26dbd92	1371	*/
Kojto	100:cbbeb26dbd92	1372	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
Kojto	100:cbbeb26dbd92	1373	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
Kojto	100:cbbeb26dbd92	1374
Kojto	100:cbbeb26dbd92	1375	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1376	((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1377	/**
Kojto	100:cbbeb26dbd92	1378	* @}
Kojto	100:cbbeb26dbd92	1379	*/
Kojto	100:cbbeb26dbd92	1380
Kojto	100:cbbeb26dbd92	1381	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	1382
Kojto	100:cbbeb26dbd92	1383	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	1384
Kojto	100:cbbeb26dbd92	1385	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	100:cbbeb26dbd92	1386	* @{
Kojto	100:cbbeb26dbd92	1387	*/
Kojto	100:cbbeb26dbd92	1388	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	100:cbbeb26dbd92	1389	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	100:cbbeb26dbd92	1390	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	100:cbbeb26dbd92	1391	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	100:cbbeb26dbd92	1392
Kojto	100:cbbeb26dbd92	1393	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	100:cbbeb26dbd92	1394	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1395	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1396	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1397	/**
Kojto	100:cbbeb26dbd92	1398	* @}
Kojto	100:cbbeb26dbd92	1399	*/
Kojto	100:cbbeb26dbd92	1400
Kojto	100:cbbeb26dbd92	1401	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	100:cbbeb26dbd92	1402	* @{
Kojto	100:cbbeb26dbd92	1403	*/
Kojto	100:cbbeb26dbd92	1404	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	100:cbbeb26dbd92	1405	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	100:cbbeb26dbd92	1406
Kojto	100:cbbeb26dbd92	1407	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1408	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	100:cbbeb26dbd92	1409	/**
Kojto	100:cbbeb26dbd92	1410	* @}
Kojto	100:cbbeb26dbd92	1411	*/
Kojto	100:cbbeb26dbd92	1412
Kojto	100:cbbeb26dbd92	1413	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto	100:cbbeb26dbd92	1414	* @{
Kojto	100:cbbeb26dbd92	1415	*/
Kojto	100:cbbeb26dbd92	1416
Kojto	100:cbbeb26dbd92	1417	/* ADC1 & ADC2 */
Kojto	100:cbbeb26dbd92	1418	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto	100:cbbeb26dbd92	1419	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto	100:cbbeb26dbd92	1420	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto	100:cbbeb26dbd92	1421	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto	100:cbbeb26dbd92	1422	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto	100:cbbeb26dbd92	1423	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto	100:cbbeb26dbd92	1424	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto	100:cbbeb26dbd92	1425	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto	100:cbbeb26dbd92	1426	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto	100:cbbeb26dbd92	1427	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto	100:cbbeb26dbd92	1428	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto	100:cbbeb26dbd92	1429	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto	100:cbbeb26dbd92	1430	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto	100:cbbeb26dbd92	1431
Kojto	100:cbbeb26dbd92	1432	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	1433	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	1434	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	1435	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	1436	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
Kojto	100:cbbeb26dbd92	1437	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
Kojto	100:cbbeb26dbd92	1438	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto	100:cbbeb26dbd92	1439	/**
Kojto	100:cbbeb26dbd92	1440	* @}
Kojto	100:cbbeb26dbd92	1441	*/
Kojto	100:cbbeb26dbd92	1442
Kojto	100:cbbeb26dbd92	1443	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto	100:cbbeb26dbd92	1444	* @{
Kojto	100:cbbeb26dbd92	1445	*/
Kojto	100:cbbeb26dbd92	1446	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto	100:cbbeb26dbd92	1447	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto	100:cbbeb26dbd92	1448
Kojto	100:cbbeb26dbd92	1449	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1450	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	100:cbbeb26dbd92	1451	/**
Kojto	100:cbbeb26dbd92	1452	* @}
Kojto	100:cbbeb26dbd92	1453	*/
Kojto	100:cbbeb26dbd92	1454	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	100:cbbeb26dbd92	1455	* @{
Kojto	100:cbbeb26dbd92	1456	*/
Kojto	100:cbbeb26dbd92	1457	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	100:cbbeb26dbd92	1458	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	100:cbbeb26dbd92	1459
Kojto	100:cbbeb26dbd92	1460	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1461	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1462	/**
Kojto	100:cbbeb26dbd92	1463	* @}
Kojto	100:cbbeb26dbd92	1464	*/
Kojto	100:cbbeb26dbd92	1465
Kojto	100:cbbeb26dbd92	1466	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
Kojto	100:cbbeb26dbd92	1467	* @{
Kojto	100:cbbeb26dbd92	1468	*/
Kojto	100:cbbeb26dbd92	1469	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
Kojto	100:cbbeb26dbd92	1470	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
Kojto	100:cbbeb26dbd92	1471	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
Kojto	100:cbbeb26dbd92	1472	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
Kojto	100:cbbeb26dbd92	1473
Kojto	100:cbbeb26dbd92	1474	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
Kojto	100:cbbeb26dbd92	1475	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1476	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1477	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1478	/**
Kojto	100:cbbeb26dbd92	1479	* @}
Kojto	100:cbbeb26dbd92	1480	*/
Kojto	100:cbbeb26dbd92	1481
Kojto	100:cbbeb26dbd92	1482	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
Kojto	100:cbbeb26dbd92	1483	* @{
Kojto	100:cbbeb26dbd92	1484	*/
Kojto	100:cbbeb26dbd92	1485	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
Kojto	100:cbbeb26dbd92	1486	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
Kojto	100:cbbeb26dbd92	1487	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
Kojto	100:cbbeb26dbd92	1488	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
Kojto	100:cbbeb26dbd92	1489
Kojto	100:cbbeb26dbd92	1490	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
Kojto	100:cbbeb26dbd92	1491	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1492	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1493	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1494	/**
Kojto	100:cbbeb26dbd92	1495	* @}
Kojto	100:cbbeb26dbd92	1496	*/
Kojto	100:cbbeb26dbd92	1497
Kojto	100:cbbeb26dbd92	1498	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	1499
Kojto	100:cbbeb26dbd92	1500	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	1501
Kojto	100:cbbeb26dbd92	1502	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	100:cbbeb26dbd92	1503	* @{
Kojto	100:cbbeb26dbd92	1504	*/
Kojto	100:cbbeb26dbd92	1505	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	100:cbbeb26dbd92	1506	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	100:cbbeb26dbd92	1507	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	100:cbbeb26dbd92	1508	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	100:cbbeb26dbd92	1509
Kojto	100:cbbeb26dbd92	1510	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	100:cbbeb26dbd92	1511	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1512	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1513	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1514	/**
Kojto	100:cbbeb26dbd92	1515	* @}
Kojto	100:cbbeb26dbd92	1516	*/
Kojto	100:cbbeb26dbd92	1517
Kojto	100:cbbeb26dbd92	1518	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	100:cbbeb26dbd92	1519	* @{
Kojto	100:cbbeb26dbd92	1520	*/
Kojto	100:cbbeb26dbd92	1521	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	100:cbbeb26dbd92	1522	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	100:cbbeb26dbd92	1523
Kojto	100:cbbeb26dbd92	1524	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1525	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	100:cbbeb26dbd92	1526	/**
Kojto	100:cbbeb26dbd92	1527	* @}
Kojto	100:cbbeb26dbd92	1528	*/
Kojto	100:cbbeb26dbd92	1529
Kojto	100:cbbeb26dbd92	1530	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
Kojto	100:cbbeb26dbd92	1531	* @{
Kojto	100:cbbeb26dbd92	1532	*/
Kojto	100:cbbeb26dbd92	1533	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
Kojto	100:cbbeb26dbd92	1534	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
Kojto	100:cbbeb26dbd92	1535
Kojto	100:cbbeb26dbd92	1536	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1537	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto	100:cbbeb26dbd92	1538	/**
Kojto	100:cbbeb26dbd92	1539	* @}
Kojto	100:cbbeb26dbd92	1540	*/
Kojto	100:cbbeb26dbd92	1541
Kojto	100:cbbeb26dbd92	1542	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto	100:cbbeb26dbd92	1543	* @{
Kojto	100:cbbeb26dbd92	1544	*/
Kojto	100:cbbeb26dbd92	1545
Kojto	100:cbbeb26dbd92	1546	/* ADC1 & ADC2 */
Kojto	100:cbbeb26dbd92	1547	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto	100:cbbeb26dbd92	1548	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto	100:cbbeb26dbd92	1549	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto	100:cbbeb26dbd92	1550	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto	100:cbbeb26dbd92	1551	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto	100:cbbeb26dbd92	1552	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto	100:cbbeb26dbd92	1553	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto	100:cbbeb26dbd92	1554	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto	100:cbbeb26dbd92	1555	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto	100:cbbeb26dbd92	1556	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto	100:cbbeb26dbd92	1557	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto	100:cbbeb26dbd92	1558	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto	100:cbbeb26dbd92	1559	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto	100:cbbeb26dbd92	1560
Kojto	100:cbbeb26dbd92	1561	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	1562	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	1563	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	1564	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	1565	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
Kojto	100:cbbeb26dbd92	1566	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
Kojto	100:cbbeb26dbd92	1567	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto	100:cbbeb26dbd92	1568	/**
Kojto	100:cbbeb26dbd92	1569	* @}
Kojto	100:cbbeb26dbd92	1570	*/
Kojto	100:cbbeb26dbd92	1571
Kojto	100:cbbeb26dbd92	1572	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto	100:cbbeb26dbd92	1573	* @{
Kojto	100:cbbeb26dbd92	1574	*/
Kojto	100:cbbeb26dbd92	1575	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto	100:cbbeb26dbd92	1576	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto	100:cbbeb26dbd92	1577
Kojto	100:cbbeb26dbd92	1578	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1579	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	100:cbbeb26dbd92	1580	/**
Kojto	100:cbbeb26dbd92	1581	* @}
Kojto	100:cbbeb26dbd92	1582	*/
Kojto	100:cbbeb26dbd92	1583
Kojto	100:cbbeb26dbd92	1584	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	100:cbbeb26dbd92	1585	* @{
Kojto	100:cbbeb26dbd92	1586	*/
Kojto	100:cbbeb26dbd92	1587	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	100:cbbeb26dbd92	1588	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	100:cbbeb26dbd92	1589
Kojto	100:cbbeb26dbd92	1590	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1591	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1592	/**
Kojto	100:cbbeb26dbd92	1593	* @}
Kojto	100:cbbeb26dbd92	1594	*/
Kojto	100:cbbeb26dbd92	1595
Kojto	100:cbbeb26dbd92	1596	/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
Kojto	100:cbbeb26dbd92	1597	* @{
Kojto	100:cbbeb26dbd92	1598	*/
Kojto	100:cbbeb26dbd92	1599	#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
Kojto	100:cbbeb26dbd92	1600	#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
Kojto	100:cbbeb26dbd92	1601
Kojto	100:cbbeb26dbd92	1602	#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1603	((SOURCE) == RCC_TIM2CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1604	/**
Kojto	100:cbbeb26dbd92	1605	* @}
Kojto	100:cbbeb26dbd92	1606	*/
Kojto	100:cbbeb26dbd92	1607
Kojto	100:cbbeb26dbd92	1608	/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
Kojto	100:cbbeb26dbd92	1609	* @{
Kojto	100:cbbeb26dbd92	1610	*/
Kojto	100:cbbeb26dbd92	1611	#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
Kojto	100:cbbeb26dbd92	1612	#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
Kojto	100:cbbeb26dbd92	1613
Kojto	100:cbbeb26dbd92	1614	#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1615	((SOURCE) == RCC_TIM34CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1616	/**
Kojto	100:cbbeb26dbd92	1617	* @}
Kojto	100:cbbeb26dbd92	1618	*/
Kojto	100:cbbeb26dbd92	1619
Kojto	100:cbbeb26dbd92	1620	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
Kojto	100:cbbeb26dbd92	1621	* @{
Kojto	100:cbbeb26dbd92	1622	*/
Kojto	100:cbbeb26dbd92	1623	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
Kojto	100:cbbeb26dbd92	1624	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
Kojto	100:cbbeb26dbd92	1625
Kojto	100:cbbeb26dbd92	1626	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1627	((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1628	/**
Kojto	100:cbbeb26dbd92	1629	* @}
Kojto	100:cbbeb26dbd92	1630	*/
Kojto	100:cbbeb26dbd92	1631
Kojto	100:cbbeb26dbd92	1632	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
Kojto	100:cbbeb26dbd92	1633	* @{
Kojto	100:cbbeb26dbd92	1634	*/
Kojto	100:cbbeb26dbd92	1635	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
Kojto	100:cbbeb26dbd92	1636	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
Kojto	100:cbbeb26dbd92	1637
Kojto	100:cbbeb26dbd92	1638	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1639	((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1640	/**
Kojto	100:cbbeb26dbd92	1641	* @}
Kojto	100:cbbeb26dbd92	1642	*/
Kojto	100:cbbeb26dbd92	1643
Kojto	100:cbbeb26dbd92	1644	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
Kojto	100:cbbeb26dbd92	1645	* @{
Kojto	100:cbbeb26dbd92	1646	*/
Kojto	100:cbbeb26dbd92	1647	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
Kojto	100:cbbeb26dbd92	1648	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
Kojto	100:cbbeb26dbd92	1649
Kojto	100:cbbeb26dbd92	1650	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1651	((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1652	/**
Kojto	100:cbbeb26dbd92	1653	* @}
Kojto	100:cbbeb26dbd92	1654	*/
Kojto	100:cbbeb26dbd92	1655
Kojto	100:cbbeb26dbd92	1656	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
Kojto	100:cbbeb26dbd92	1657	* @{
Kojto	100:cbbeb26dbd92	1658	*/
Kojto	100:cbbeb26dbd92	1659	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
Kojto	100:cbbeb26dbd92	1660	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
Kojto	100:cbbeb26dbd92	1661	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
Kojto	100:cbbeb26dbd92	1662	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
Kojto	100:cbbeb26dbd92	1663
Kojto	100:cbbeb26dbd92	1664	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
Kojto	100:cbbeb26dbd92	1665	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1666	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1667	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1668	/**
Kojto	100:cbbeb26dbd92	1669	* @}
Kojto	100:cbbeb26dbd92	1670	*/
Kojto	100:cbbeb26dbd92	1671
Kojto	100:cbbeb26dbd92	1672	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
Kojto	100:cbbeb26dbd92	1673	* @{
Kojto	100:cbbeb26dbd92	1674	*/
Kojto	100:cbbeb26dbd92	1675	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
Kojto	100:cbbeb26dbd92	1676	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
Kojto	100:cbbeb26dbd92	1677	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
Kojto	100:cbbeb26dbd92	1678	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
Kojto	100:cbbeb26dbd92	1679
Kojto	100:cbbeb26dbd92	1680	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
Kojto	100:cbbeb26dbd92	1681	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1682	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1683	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1684	/**
Kojto	100:cbbeb26dbd92	1685	* @}
Kojto	100:cbbeb26dbd92	1686	*/
Kojto	100:cbbeb26dbd92	1687
Kojto	100:cbbeb26dbd92	1688	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	1689
Kojto	100:cbbeb26dbd92	1690	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	1691	/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
Kojto	100:cbbeb26dbd92	1692	* @{
Kojto	100:cbbeb26dbd92	1693	*/
Kojto	100:cbbeb26dbd92	1694	#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
Kojto	100:cbbeb26dbd92	1695	#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
Kojto	100:cbbeb26dbd92	1696
Kojto	100:cbbeb26dbd92	1697	#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1698	((SOURCE) == RCC_TIM20CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1699	/**
Kojto	100:cbbeb26dbd92	1700	* @}
Kojto	100:cbbeb26dbd92	1701	*/
Kojto	100:cbbeb26dbd92	1702	#endif /* STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	1703
Kojto	100:cbbeb26dbd92	1704	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	1705	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	1706
Kojto	100:cbbeb26dbd92	1707	/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
Kojto	100:cbbeb26dbd92	1708	* @{
Kojto	100:cbbeb26dbd92	1709	*/
Kojto	100:cbbeb26dbd92	1710
Kojto	100:cbbeb26dbd92	1711	/* ADC3 & ADC4 */
Kojto	100:cbbeb26dbd92	1712	#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
Kojto	100:cbbeb26dbd92	1713	#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
Kojto	100:cbbeb26dbd92	1714	#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
Kojto	100:cbbeb26dbd92	1715	#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
Kojto	100:cbbeb26dbd92	1716	#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
Kojto	100:cbbeb26dbd92	1717	#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
Kojto	100:cbbeb26dbd92	1718	#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
Kojto	100:cbbeb26dbd92	1719	#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
Kojto	100:cbbeb26dbd92	1720	#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
Kojto	100:cbbeb26dbd92	1721	#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
Kojto	100:cbbeb26dbd92	1722	#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
Kojto	100:cbbeb26dbd92	1723	#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
Kojto	100:cbbeb26dbd92	1724	#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
Kojto	100:cbbeb26dbd92	1725
Kojto	100:cbbeb26dbd92	1726	#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	1727	((ADCCLK) == RCC_ADC34PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	1728	((ADCCLK) == RCC_ADC34PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	1729	((ADCCLK) == RCC_ADC34PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	1730	((ADCCLK) == RCC_ADC34PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) \|\| \
Kojto	100:cbbeb26dbd92	1731	((ADCCLK) == RCC_ADC34PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) \|\| \
Kojto	100:cbbeb26dbd92	1732	((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
Kojto	100:cbbeb26dbd92	1733	/**
Kojto	100:cbbeb26dbd92	1734	* @}
Kojto	100:cbbeb26dbd92	1735	*/
Kojto	100:cbbeb26dbd92	1736
Kojto	100:cbbeb26dbd92	1737	/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
Kojto	100:cbbeb26dbd92	1738	* @{
Kojto	100:cbbeb26dbd92	1739	*/
Kojto	100:cbbeb26dbd92	1740	#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
Kojto	100:cbbeb26dbd92	1741	#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
Kojto	100:cbbeb26dbd92	1742
Kojto	100:cbbeb26dbd92	1743	#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1744	((SOURCE) == RCC_TIM8CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1745	/**
Kojto	100:cbbeb26dbd92	1746	* @}
Kojto	100:cbbeb26dbd92	1747	*/
Kojto	100:cbbeb26dbd92	1748
Kojto	100:cbbeb26dbd92	1749	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	1750
Kojto	100:cbbeb26dbd92	1751	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	1752
Kojto	100:cbbeb26dbd92	1753	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	100:cbbeb26dbd92	1754	* @{
Kojto	100:cbbeb26dbd92	1755	*/
Kojto	100:cbbeb26dbd92	1756	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
Kojto	100:cbbeb26dbd92	1757	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	100:cbbeb26dbd92	1758	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	100:cbbeb26dbd92	1759	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	100:cbbeb26dbd92	1760
Kojto	100:cbbeb26dbd92	1761	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
Kojto	100:cbbeb26dbd92	1762	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1763	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1764	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1765	/**
Kojto	100:cbbeb26dbd92	1766	* @}
Kojto	100:cbbeb26dbd92	1767	*/
Kojto	100:cbbeb26dbd92	1768
Kojto	100:cbbeb26dbd92	1769	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto	100:cbbeb26dbd92	1770	* @{
Kojto	100:cbbeb26dbd92	1771	*/
Kojto	100:cbbeb26dbd92	1772	/* ADC1 & ADC2 */
Kojto	100:cbbeb26dbd92	1773	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto	100:cbbeb26dbd92	1774	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto	100:cbbeb26dbd92	1775	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto	100:cbbeb26dbd92	1776	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto	100:cbbeb26dbd92	1777	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto	100:cbbeb26dbd92	1778	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto	100:cbbeb26dbd92	1779	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto	100:cbbeb26dbd92	1780	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto	100:cbbeb26dbd92	1781	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto	100:cbbeb26dbd92	1782	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto	100:cbbeb26dbd92	1783	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto	100:cbbeb26dbd92	1784	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto	100:cbbeb26dbd92	1785	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto	100:cbbeb26dbd92	1786
Kojto	100:cbbeb26dbd92	1787	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	1788	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	1789	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	1790	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
Kojto	100:cbbeb26dbd92	1791	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
Kojto	100:cbbeb26dbd92	1792	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
Kojto	100:cbbeb26dbd92	1793	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto	100:cbbeb26dbd92	1794	/**
Kojto	100:cbbeb26dbd92	1795	* @}
Kojto	100:cbbeb26dbd92	1796	*/
Kojto	100:cbbeb26dbd92	1797
Kojto	100:cbbeb26dbd92	1798	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	100:cbbeb26dbd92	1799	* @{
Kojto	100:cbbeb26dbd92	1800	*/
Kojto	100:cbbeb26dbd92	1801	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	100:cbbeb26dbd92	1802	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	100:cbbeb26dbd92	1803
Kojto	100:cbbeb26dbd92	1804	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1805	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1806	/**
Kojto	100:cbbeb26dbd92	1807	* @}
Kojto	100:cbbeb26dbd92	1808	*/
Kojto	100:cbbeb26dbd92	1809
Kojto	100:cbbeb26dbd92	1810	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	1811
Kojto	100:cbbeb26dbd92	1812	#if defined(STM32F334x8)
Kojto	100:cbbeb26dbd92	1813
Kojto	100:cbbeb26dbd92	1814	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
Kojto	100:cbbeb26dbd92	1815	* @{
Kojto	100:cbbeb26dbd92	1816	*/
Kojto	100:cbbeb26dbd92	1817	#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
Kojto	100:cbbeb26dbd92	1818	#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
Kojto	100:cbbeb26dbd92	1819
Kojto	100:cbbeb26dbd92	1820	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) \|\| \
Kojto	100:cbbeb26dbd92	1821	((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
Kojto	100:cbbeb26dbd92	1822	/**
Kojto	100:cbbeb26dbd92	1823	* @}
Kojto	100:cbbeb26dbd92	1824	*/
Kojto	100:cbbeb26dbd92	1825
Kojto	100:cbbeb26dbd92	1826	#endif /* STM32F334x8 */
Kojto	100:cbbeb26dbd92	1827
Kojto	100:cbbeb26dbd92	1828	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	1829
Kojto	100:cbbeb26dbd92	1830	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	100:cbbeb26dbd92	1831	* @{
Kojto	100:cbbeb26dbd92	1832	*/
Kojto	100:cbbeb26dbd92	1833	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	100:cbbeb26dbd92	1834	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	100:cbbeb26dbd92	1835	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	100:cbbeb26dbd92	1836	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	100:cbbeb26dbd92	1837
Kojto	100:cbbeb26dbd92	1838	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	100:cbbeb26dbd92	1839	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	100:cbbeb26dbd92	1840	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	100:cbbeb26dbd92	1841	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	100:cbbeb26dbd92	1842	/**
Kojto	100:cbbeb26dbd92	1843	* @}
Kojto	100:cbbeb26dbd92	1844	*/
Kojto	100:cbbeb26dbd92	1845
Kojto	100:cbbeb26dbd92	1846	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	100:cbbeb26dbd92	1847	* @{
Kojto	100:cbbeb26dbd92	1848	*/
Kojto	100:cbbeb26dbd92	1849	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	100:cbbeb26dbd92	1850	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	100:cbbeb26dbd92	1851
Kojto	100:cbbeb26dbd92	1852	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1853	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	100:cbbeb26dbd92	1854	/**
Kojto	100:cbbeb26dbd92	1855	* @}
Kojto	100:cbbeb26dbd92	1856	*/
Kojto	100:cbbeb26dbd92	1857
Kojto	100:cbbeb26dbd92	1858	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
Kojto	100:cbbeb26dbd92	1859	* @{
Kojto	100:cbbeb26dbd92	1860	*/
Kojto	100:cbbeb26dbd92	1861
Kojto	100:cbbeb26dbd92	1862	/* ADC1 */
Kojto	100:cbbeb26dbd92	1863	#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
Kojto	100:cbbeb26dbd92	1864	#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
Kojto	100:cbbeb26dbd92	1865	#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
Kojto	100:cbbeb26dbd92	1866	#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
Kojto	100:cbbeb26dbd92	1867
Kojto	100:cbbeb26dbd92	1868	#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV4) \|\| \
Kojto	100:cbbeb26dbd92	1869	((ADCCLK) == RCC_ADC1PCLK2_DIV6) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
Kojto	100:cbbeb26dbd92	1870	/**
Kojto	100:cbbeb26dbd92	1871	* @}
Kojto	100:cbbeb26dbd92	1872	*/
Kojto	100:cbbeb26dbd92	1873
Kojto	100:cbbeb26dbd92	1874	/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
Kojto	100:cbbeb26dbd92	1875	* @{
Kojto	100:cbbeb26dbd92	1876	*/
Kojto	100:cbbeb26dbd92	1877	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto	100:cbbeb26dbd92	1878	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto	100:cbbeb26dbd92	1879
Kojto	100:cbbeb26dbd92	1880	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	100:cbbeb26dbd92	1881	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	100:cbbeb26dbd92	1882	/**
Kojto	100:cbbeb26dbd92	1883	* @}
Kojto	100:cbbeb26dbd92	1884	*/
Kojto	100:cbbeb26dbd92	1885
Kojto	100:cbbeb26dbd92	1886	/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
Kojto	100:cbbeb26dbd92	1887	* @{
Kojto	100:cbbeb26dbd92	1888	*/
Kojto	100:cbbeb26dbd92	1889	#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
Kojto	100:cbbeb26dbd92	1890	#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
Kojto	100:cbbeb26dbd92	1891	#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
Kojto	100:cbbeb26dbd92	1892	#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
Kojto	100:cbbeb26dbd92	1893	#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
Kojto	100:cbbeb26dbd92	1894	#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
Kojto	100:cbbeb26dbd92	1895	#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
Kojto	100:cbbeb26dbd92	1896	#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
Kojto	100:cbbeb26dbd92	1897	#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
Kojto	100:cbbeb26dbd92	1898	#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
Kojto	100:cbbeb26dbd92	1899	#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
Kojto	100:cbbeb26dbd92	1900	#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
Kojto	100:cbbeb26dbd92	1901	#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
Kojto	100:cbbeb26dbd92	1902	#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
Kojto	100:cbbeb26dbd92	1903	#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
Kojto	100:cbbeb26dbd92	1904	#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
Kojto	100:cbbeb26dbd92	1905	#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
Kojto	100:cbbeb26dbd92	1906
Kojto	100:cbbeb26dbd92	1907	#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV2) \|\| \
Kojto	100:cbbeb26dbd92	1908	((DIV) == RCC_SDADCSYSCLK_DIV4) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV6) \|\| \
Kojto	100:cbbeb26dbd92	1909	((DIV) == RCC_SDADCSYSCLK_DIV8) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV10) \|\| \
Kojto	100:cbbeb26dbd92	1910	((DIV) == RCC_SDADCSYSCLK_DIV12) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV14) \|\| \
Kojto	100:cbbeb26dbd92	1911	((DIV) == RCC_SDADCSYSCLK_DIV16) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV20) \|\| \
Kojto	100:cbbeb26dbd92	1912	((DIV) == RCC_SDADCSYSCLK_DIV24) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV28) \|\| \
Kojto	100:cbbeb26dbd92	1913	((DIV) == RCC_SDADCSYSCLK_DIV32) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV36) \|\| \
Kojto	100:cbbeb26dbd92	1914	((DIV) == RCC_SDADCSYSCLK_DIV40) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV44) \|\| \
Kojto	100:cbbeb26dbd92	1915	((DIV) == RCC_SDADCSYSCLK_DIV48))
Kojto	100:cbbeb26dbd92	1916	/**
Kojto	100:cbbeb26dbd92	1917	* @}
Kojto	100:cbbeb26dbd92	1918	*/
Kojto	100:cbbeb26dbd92	1919
Kojto	100:cbbeb26dbd92	1920	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	1921
Kojto	100:cbbeb26dbd92	1922	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	100:cbbeb26dbd92	1923	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	100:cbbeb26dbd92	1924	defined(STM32F302x8) \|\| \
Kojto	100:cbbeb26dbd92	1925	defined(STM32F373xC)
Kojto	100:cbbeb26dbd92	1926	/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
Kojto	100:cbbeb26dbd92	1927	* @{
Kojto	100:cbbeb26dbd92	1928	*/
Kojto	100:cbbeb26dbd92	1929	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
Kojto	100:cbbeb26dbd92	1930	#define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
Kojto	100:cbbeb26dbd92	1931
Kojto	100:cbbeb26dbd92	1932	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) \|\| \
Kojto	100:cbbeb26dbd92	1933	((SOURCE) == RCC_USBPLLCLK_DIV1_5))
Kojto	100:cbbeb26dbd92	1934	/**
Kojto	100:cbbeb26dbd92	1935	* @}
Kojto	100:cbbeb26dbd92	1936	*/
Kojto	100:cbbeb26dbd92	1937
Kojto	100:cbbeb26dbd92	1938	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	100:cbbeb26dbd92	1939	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	100:cbbeb26dbd92	1940	/* STM32F302x8 \|\| */
Kojto	100:cbbeb26dbd92	1941	/* STM32F373xC */
Kojto	100:cbbeb26dbd92	1942
Kojto	100:cbbeb26dbd92	1943	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	1944	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	1945	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
Kojto	100:cbbeb26dbd92	1946	* @{
Kojto	100:cbbeb26dbd92	1947	*/
Kojto	100:cbbeb26dbd92	1948	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
Kojto	100:cbbeb26dbd92	1949
Kojto	100:cbbeb26dbd92	1950	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
Kojto	100:cbbeb26dbd92	1951	/**
Kojto	100:cbbeb26dbd92	1952	* @}
Kojto	100:cbbeb26dbd92	1953	*/
Kojto	100:cbbeb26dbd92	1954	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	1955	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	1956
Kojto	100:cbbeb26dbd92	1957	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	1958	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	1959	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	1960
Kojto	100:cbbeb26dbd92	1961	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
Kojto	100:cbbeb26dbd92	1962	* @{
Kojto	100:cbbeb26dbd92	1963	*/
Kojto	100:cbbeb26dbd92	1964	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto	100:cbbeb26dbd92	1965	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto	100:cbbeb26dbd92	1966	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto	100:cbbeb26dbd92	1967	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto	100:cbbeb26dbd92	1968	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto	100:cbbeb26dbd92	1969	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto	100:cbbeb26dbd92	1970	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto	100:cbbeb26dbd92	1971	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto	100:cbbeb26dbd92	1972
Kojto	100:cbbeb26dbd92	1973	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
Kojto	100:cbbeb26dbd92	1974	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
Kojto	100:cbbeb26dbd92	1975	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
Kojto	100:cbbeb26dbd92	1976	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
Kojto	100:cbbeb26dbd92	1977	/**
Kojto	100:cbbeb26dbd92	1978	* @}
Kojto	100:cbbeb26dbd92	1979	*/
Kojto	100:cbbeb26dbd92	1980
Kojto	100:cbbeb26dbd92	1981	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	1982	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	1983	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	1984
Kojto	100:cbbeb26dbd92	1985	/**
Kojto	100:cbbeb26dbd92	1986	* @}
Kojto	100:cbbeb26dbd92	1987	*/
Kojto	100:cbbeb26dbd92	1988
Kojto	100:cbbeb26dbd92	1989	/* Exported macro ------------------------------------------------------------*/
Kojto	100:cbbeb26dbd92	1990	/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
Kojto	100:cbbeb26dbd92	1991	* @{
Kojto	100:cbbeb26dbd92	1992	*/
Kojto	100:cbbeb26dbd92	1993
Kojto	100:cbbeb26dbd92	1994	/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
Kojto	100:cbbeb26dbd92	1995	* @{
Kojto	100:cbbeb26dbd92	1996	*/
Kojto	100:cbbeb26dbd92	1997	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	1998	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto	100:cbbeb26dbd92	1999	* @note This macro must be used only when the PLL is disabled.
Kojto	100:cbbeb26dbd92	2000	*
Kojto	100:cbbeb26dbd92	2001	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	100:cbbeb26dbd92	2002	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2003	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	100:cbbeb26dbd92	2004	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	100:cbbeb26dbd92	2005	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto	100:cbbeb26dbd92	2006	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto	100:cbbeb26dbd92	2007	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto	100:cbbeb26dbd92	2008	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto	100:cbbeb26dbd92	2009	*
Kojto	100:cbbeb26dbd92	2010	*/
Kojto	100:cbbeb26dbd92	2011	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
Kojto	100:cbbeb26dbd92	2012	do { \
Kojto	100:cbbeb26dbd92	2013	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto	100:cbbeb26dbd92	2014	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
Kojto	100:cbbeb26dbd92	2015	} while(0)
Kojto	100:cbbeb26dbd92	2016	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2017
Kojto	100:cbbeb26dbd92	2018	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	2019	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	2020	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	100:cbbeb26dbd92	2021	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2022	/** @brief Macro to configure the PLL clock source and multiplication factor.
Kojto	100:cbbeb26dbd92	2023	* @note This macro must be used only when the PLL is disabled.
Kojto	100:cbbeb26dbd92	2024	*
Kojto	100:cbbeb26dbd92	2025	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	100:cbbeb26dbd92	2026	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2027	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	100:cbbeb26dbd92	2028	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	100:cbbeb26dbd92	2029	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto	100:cbbeb26dbd92	2030	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto	100:cbbeb26dbd92	2031	*
Kojto	100:cbbeb26dbd92	2032	*/
Kojto	100:cbbeb26dbd92	2033	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
Kojto	100:cbbeb26dbd92	2034	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__)))
Kojto	100:cbbeb26dbd92	2035	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	2036	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	2037	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2038	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2039	/**
Kojto	100:cbbeb26dbd92	2040	* @}
Kojto	100:cbbeb26dbd92	2041	*/
Kojto	100:cbbeb26dbd92	2042
Kojto	100:cbbeb26dbd92	2043	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	2044	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	2045	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	100:cbbeb26dbd92	2046	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2047	/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
Kojto	100:cbbeb26dbd92	2048	* @{
Kojto	100:cbbeb26dbd92	2049	*/
Kojto	100:cbbeb26dbd92	2050
Kojto	100:cbbeb26dbd92	2051	/**
Kojto	100:cbbeb26dbd92	2052	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto	100:cbbeb26dbd92	2053	* @note Predivision factor can not be changed if PLL is used as system clock
Kojto	100:cbbeb26dbd92	2054	* In this case, you have to select another source of the system clock, disable the PLL and
Kojto	100:cbbeb26dbd92	2055	* then change the HSE predivision factor.
Kojto	100:cbbeb26dbd92	2056	* @param __HSEPredivValue__: specifies the division value applied to HSE.
Kojto	100:cbbeb26dbd92	2057	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto	100:cbbeb26dbd92	2058	*/
Kojto	100:cbbeb26dbd92	2059	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
Kojto	100:cbbeb26dbd92	2060	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
Kojto	100:cbbeb26dbd92	2061	/**
Kojto	100:cbbeb26dbd92	2062	* @}
Kojto	100:cbbeb26dbd92	2063	*/
Kojto	100:cbbeb26dbd92	2064	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	2065	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	2066	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2067	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2068
Kojto	100:cbbeb26dbd92	2069	/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
Kojto	100:cbbeb26dbd92	2070	* @brief Enable or disable the AHB peripheral clock.
Kojto	100:cbbeb26dbd92	2071	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	100:cbbeb26dbd92	2072	* is disabled and the application software has to enable this clock before
Kojto	100:cbbeb26dbd92	2073	* using it.
Kojto	100:cbbeb26dbd92	2074	* @{
Kojto	100:cbbeb26dbd92	2075	*/
Kojto	100:cbbeb26dbd92	2076	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2077	#define __ADC1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC1EN))
Kojto	100:cbbeb26dbd92	2078
Kojto	100:cbbeb26dbd92	2079	#define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
Kojto	100:cbbeb26dbd92	2080	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2081
Kojto	100:cbbeb26dbd92	2082	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2083	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2084	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
Kojto	100:cbbeb26dbd92	2085	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
Kojto	100:cbbeb26dbd92	2086	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
Kojto	100:cbbeb26dbd92	2087	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2088	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	100:cbbeb26dbd92	2089	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	100:cbbeb26dbd92	2090
Kojto	100:cbbeb26dbd92	2091	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto	100:cbbeb26dbd92	2092	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto	100:cbbeb26dbd92	2093	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
Kojto	100:cbbeb26dbd92	2094	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2095	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	100:cbbeb26dbd92	2096	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	100:cbbeb26dbd92	2097	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2098	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2099
Kojto	100:cbbeb26dbd92	2100	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2101	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2102	#define __ADC34_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC34EN))
Kojto	100:cbbeb26dbd92	2103
Kojto	100:cbbeb26dbd92	2104	#define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
Kojto	100:cbbeb26dbd92	2105	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2106	/* STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2107
Kojto	100:cbbeb26dbd92	2108	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	2109	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
Kojto	100:cbbeb26dbd92	2110	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2111	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	100:cbbeb26dbd92	2112	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	100:cbbeb26dbd92	2113
Kojto	100:cbbeb26dbd92	2114	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
Kojto	100:cbbeb26dbd92	2115	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2116	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	100:cbbeb26dbd92	2117	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	100:cbbeb26dbd92	2118	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	2119
Kojto	100:cbbeb26dbd92	2120	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2121	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
Kojto	100:cbbeb26dbd92	2122	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
Kojto	100:cbbeb26dbd92	2123
Kojto	100:cbbeb26dbd92	2124	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto	100:cbbeb26dbd92	2125	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto	100:cbbeb26dbd92	2126	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2127
Kojto	100:cbbeb26dbd92	2128	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2129	#define __FMC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FMCEN))
Kojto	100:cbbeb26dbd92	2130	#define __GPIOG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOGEN))
Kojto	100:cbbeb26dbd92	2131	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
Kojto	100:cbbeb26dbd92	2132
Kojto	100:cbbeb26dbd92	2133	#define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
Kojto	100:cbbeb26dbd92	2134	#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
Kojto	100:cbbeb26dbd92	2135	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
Kojto	100:cbbeb26dbd92	2136	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2137	/**
Kojto	100:cbbeb26dbd92	2138	* @}
Kojto	100:cbbeb26dbd92	2139	*/
Kojto	100:cbbeb26dbd92	2140
Kojto	100:cbbeb26dbd92	2141	/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
Kojto	100:cbbeb26dbd92	2142	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	100:cbbeb26dbd92	2143	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	100:cbbeb26dbd92	2144	* is disabled and the application software has to enable this clock before
Kojto	100:cbbeb26dbd92	2145	* using it.
Kojto	100:cbbeb26dbd92	2146	* @{
Kojto	100:cbbeb26dbd92	2147	*/
Kojto	100:cbbeb26dbd92	2148	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2149	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	100:cbbeb26dbd92	2150	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
Kojto	100:cbbeb26dbd92	2151	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	100:cbbeb26dbd92	2152	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
Kojto	100:cbbeb26dbd92	2153
Kojto	100:cbbeb26dbd92	2154	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	100:cbbeb26dbd92	2155	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	100:cbbeb26dbd92	2156	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	100:cbbeb26dbd92	2157	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	100:cbbeb26dbd92	2158	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2159
Kojto	100:cbbeb26dbd92	2160	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2161	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2162	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	100:cbbeb26dbd92	2163	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
Kojto	100:cbbeb26dbd92	2164	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	100:cbbeb26dbd92	2165	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
Kojto	100:cbbeb26dbd92	2166	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
Kojto	100:cbbeb26dbd92	2167	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
Kojto	100:cbbeb26dbd92	2168	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	100:cbbeb26dbd92	2169
Kojto	100:cbbeb26dbd92	2170	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	100:cbbeb26dbd92	2171	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	100:cbbeb26dbd92	2172	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	100:cbbeb26dbd92	2173	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	100:cbbeb26dbd92	2174	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	100:cbbeb26dbd92	2175	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	100:cbbeb26dbd92	2176	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	100:cbbeb26dbd92	2177	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2178	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2179
Kojto	100:cbbeb26dbd92	2180	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	2181	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	100:cbbeb26dbd92	2182	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
Kojto	100:cbbeb26dbd92	2183
Kojto	100:cbbeb26dbd92	2184	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	100:cbbeb26dbd92	2185	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto	100:cbbeb26dbd92	2186	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	2187
Kojto	100:cbbeb26dbd92	2188	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2189	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	100:cbbeb26dbd92	2190	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
Kojto	100:cbbeb26dbd92	2191	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
Kojto	100:cbbeb26dbd92	2192	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
Kojto	100:cbbeb26dbd92	2193	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
Kojto	100:cbbeb26dbd92	2194	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
Kojto	100:cbbeb26dbd92	2195	#define __TIM18_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM18EN))
Kojto	100:cbbeb26dbd92	2196	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	100:cbbeb26dbd92	2197	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
Kojto	100:cbbeb26dbd92	2198	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	100:cbbeb26dbd92	2199	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
Kojto	100:cbbeb26dbd92	2200	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
Kojto	100:cbbeb26dbd92	2201
Kojto	100:cbbeb26dbd92	2202	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	100:cbbeb26dbd92	2203	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	100:cbbeb26dbd92	2204	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto	100:cbbeb26dbd92	2205	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	100:cbbeb26dbd92	2206	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	100:cbbeb26dbd92	2207	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	100:cbbeb26dbd92	2208	#define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
Kojto	100:cbbeb26dbd92	2209	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	100:cbbeb26dbd92	2210	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	100:cbbeb26dbd92	2211	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	100:cbbeb26dbd92	2212	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto	100:cbbeb26dbd92	2213	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	100:cbbeb26dbd92	2214	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2215
Kojto	100:cbbeb26dbd92	2216	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2217	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	2218	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	2219	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2220	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
Kojto	100:cbbeb26dbd92	2221
Kojto	100:cbbeb26dbd92	2222	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	100:cbbeb26dbd92	2223	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2224	/* STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	2225	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	2226	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2227
Kojto	100:cbbeb26dbd92	2228	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	100:cbbeb26dbd92	2229	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	100:cbbeb26dbd92	2230	defined(STM32F302x8) \|\| \
Kojto	100:cbbeb26dbd92	2231	defined(STM32F373xC)
Kojto	100:cbbeb26dbd92	2232	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
Kojto	100:cbbeb26dbd92	2233
Kojto	100:cbbeb26dbd92	2234	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto	100:cbbeb26dbd92	2235	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	100:cbbeb26dbd92	2236	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	100:cbbeb26dbd92	2237	/* STM32F302x8 \|\| */
Kojto	100:cbbeb26dbd92	2238	/* STM32F373xC */
Kojto	100:cbbeb26dbd92	2239
Kojto	100:cbbeb26dbd92	2240	#if !defined(STM32F301x8)
Kojto	100:cbbeb26dbd92	2241	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
Kojto	100:cbbeb26dbd92	2242
Kojto	100:cbbeb26dbd92	2243	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto	100:cbbeb26dbd92	2244	#endif /* STM32F301x8*/
Kojto	100:cbbeb26dbd92	2245
Kojto	100:cbbeb26dbd92	2246	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2247	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
Kojto	100:cbbeb26dbd92	2248
Kojto	100:cbbeb26dbd92	2249	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	100:cbbeb26dbd92	2250	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2251	/**
Kojto	100:cbbeb26dbd92	2252	* @}
Kojto	100:cbbeb26dbd92	2253	*/
Kojto	100:cbbeb26dbd92	2254
Kojto	100:cbbeb26dbd92	2255	/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
Kojto	100:cbbeb26dbd92	2256	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	100:cbbeb26dbd92	2257	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	100:cbbeb26dbd92	2258	* is disabled and the application software has to enable this clock before
Kojto	100:cbbeb26dbd92	2259	* using it.
Kojto	100:cbbeb26dbd92	2260	* @{
Kojto	100:cbbeb26dbd92	2261	*/
Kojto	100:cbbeb26dbd92	2262	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2263	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2264	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	100:cbbeb26dbd92	2265
Kojto	100:cbbeb26dbd92	2266	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	100:cbbeb26dbd92	2267	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2268	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2269
Kojto	100:cbbeb26dbd92	2270	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2271	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2272	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
Kojto	100:cbbeb26dbd92	2273
Kojto	100:cbbeb26dbd92	2274	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	100:cbbeb26dbd92	2275	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2276	/* STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2277
Kojto	100:cbbeb26dbd92	2278	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	2279	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	100:cbbeb26dbd92	2280
Kojto	100:cbbeb26dbd92	2281	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	100:cbbeb26dbd92	2282	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	2283
Kojto	100:cbbeb26dbd92	2284	#if defined(STM32F334x8)
Kojto	100:cbbeb26dbd92	2285	#define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_HRTIM1EN))
Kojto	100:cbbeb26dbd92	2286
Kojto	100:cbbeb26dbd92	2287	#define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
Kojto	100:cbbeb26dbd92	2288	#endif /* STM32F334x8 */
Kojto	100:cbbeb26dbd92	2289
Kojto	100:cbbeb26dbd92	2290	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2291	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
Kojto	100:cbbeb26dbd92	2292	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	100:cbbeb26dbd92	2293	#define __TIM19_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM19EN))
Kojto	100:cbbeb26dbd92	2294	#define __SDADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC1EN))
Kojto	100:cbbeb26dbd92	2295	#define __SDADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC2EN))
Kojto	100:cbbeb26dbd92	2296	#define __SDADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC3EN))
Kojto	100:cbbeb26dbd92	2297
Kojto	100:cbbeb26dbd92	2298	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	100:cbbeb26dbd92	2299	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	100:cbbeb26dbd92	2300	#define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
Kojto	100:cbbeb26dbd92	2301	#define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
Kojto	100:cbbeb26dbd92	2302	#define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
Kojto	100:cbbeb26dbd92	2303	#define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
Kojto	100:cbbeb26dbd92	2304	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2305
Kojto	100:cbbeb26dbd92	2306	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2307	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	2308	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	2309	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2310	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
Kojto	100:cbbeb26dbd92	2311
Kojto	100:cbbeb26dbd92	2312	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	100:cbbeb26dbd92	2313	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2314	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	2315	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	2316	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2317
Kojto	100:cbbeb26dbd92	2318	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2319	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
Kojto	100:cbbeb26dbd92	2320
Kojto	100:cbbeb26dbd92	2321	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	100:cbbeb26dbd92	2322	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2323
Kojto	100:cbbeb26dbd92	2324	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2325	#define __TIM20_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM20EN))
Kojto	100:cbbeb26dbd92	2326
Kojto	100:cbbeb26dbd92	2327	#define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
Kojto	100:cbbeb26dbd92	2328	#endif /* STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2329
Kojto	100:cbbeb26dbd92	2330	/**
Kojto	100:cbbeb26dbd92	2331	* @}
Kojto	100:cbbeb26dbd92	2332	*/
Kojto	100:cbbeb26dbd92	2333
Kojto	100:cbbeb26dbd92	2334	/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
Kojto	100:cbbeb26dbd92	2335	* @brief Force or release AHB peripheral reset.
Kojto	100:cbbeb26dbd92	2336	* @{
Kojto	100:cbbeb26dbd92	2337	*/
Kojto	100:cbbeb26dbd92	2338	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2339	#define __ADC1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC1RST))
Kojto	100:cbbeb26dbd92	2340
Kojto	100:cbbeb26dbd92	2341	#define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
Kojto	100:cbbeb26dbd92	2342	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2343
Kojto	100:cbbeb26dbd92	2344	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2345	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2346	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
Kojto	100:cbbeb26dbd92	2347	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
Kojto	100:cbbeb26dbd92	2348	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2349	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	100:cbbeb26dbd92	2350	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	100:cbbeb26dbd92	2351
Kojto	100:cbbeb26dbd92	2352	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto	100:cbbeb26dbd92	2353	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
Kojto	100:cbbeb26dbd92	2354	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2355	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	100:cbbeb26dbd92	2356	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	100:cbbeb26dbd92	2357	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2358	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2359
Kojto	100:cbbeb26dbd92	2360	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2361	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2362	#define __ADC34_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC34RST))
Kojto	100:cbbeb26dbd92	2363
Kojto	100:cbbeb26dbd92	2364	#define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
Kojto	100:cbbeb26dbd92	2365	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2366	/* STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2367
Kojto	100:cbbeb26dbd92	2368	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	2369	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
Kojto	100:cbbeb26dbd92	2370	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2371	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	100:cbbeb26dbd92	2372	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	100:cbbeb26dbd92	2373
Kojto	100:cbbeb26dbd92	2374	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
Kojto	100:cbbeb26dbd92	2375	/* Aliases for STM32 F3 compatibility */
Kojto	100:cbbeb26dbd92	2376	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	100:cbbeb26dbd92	2377	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	100:cbbeb26dbd92	2378	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	2379
Kojto	100:cbbeb26dbd92	2380	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2381	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
Kojto	100:cbbeb26dbd92	2382
Kojto	100:cbbeb26dbd92	2383	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto	100:cbbeb26dbd92	2384	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2385
Kojto	100:cbbeb26dbd92	2386	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2387	#define __FMC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FMCRST))
Kojto	100:cbbeb26dbd92	2388	#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOGRST))
Kojto	100:cbbeb26dbd92	2389	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
Kojto	100:cbbeb26dbd92	2390
Kojto	100:cbbeb26dbd92	2391	#define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
Kojto	100:cbbeb26dbd92	2392	#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
Kojto	100:cbbeb26dbd92	2393	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
Kojto	100:cbbeb26dbd92	2394	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2395	/**
Kojto	100:cbbeb26dbd92	2396	* @}
Kojto	100:cbbeb26dbd92	2397	*/
Kojto	100:cbbeb26dbd92	2398
Kojto	100:cbbeb26dbd92	2399	/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
Kojto	100:cbbeb26dbd92	2400	* @brief Force or release APB1 peripheral reset.
Kojto	100:cbbeb26dbd92	2401	* @{
Kojto	100:cbbeb26dbd92	2402	*/
Kojto	100:cbbeb26dbd92	2403	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2404	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	100:cbbeb26dbd92	2405	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	100:cbbeb26dbd92	2406	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	100:cbbeb26dbd92	2407	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	100:cbbeb26dbd92	2408
Kojto	100:cbbeb26dbd92	2409	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	100:cbbeb26dbd92	2410	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	100:cbbeb26dbd92	2411	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	100:cbbeb26dbd92	2412	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	100:cbbeb26dbd92	2413	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2414
Kojto	100:cbbeb26dbd92	2415	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2416	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2417	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	100:cbbeb26dbd92	2418	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	100:cbbeb26dbd92	2419	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	100:cbbeb26dbd92	2420	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	100:cbbeb26dbd92	2421	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	100:cbbeb26dbd92	2422	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	100:cbbeb26dbd92	2423	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	100:cbbeb26dbd92	2424
Kojto	100:cbbeb26dbd92	2425	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	100:cbbeb26dbd92	2426	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	100:cbbeb26dbd92	2427	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	100:cbbeb26dbd92	2428	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	100:cbbeb26dbd92	2429	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	100:cbbeb26dbd92	2430	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	100:cbbeb26dbd92	2431	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	100:cbbeb26dbd92	2432	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2433	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2434
Kojto	100:cbbeb26dbd92	2435	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	2436	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	100:cbbeb26dbd92	2437	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
Kojto	100:cbbeb26dbd92	2438
Kojto	100:cbbeb26dbd92	2439	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	100:cbbeb26dbd92	2440	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto	100:cbbeb26dbd92	2441	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	2442
Kojto	100:cbbeb26dbd92	2443	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2444	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	100:cbbeb26dbd92	2445	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	100:cbbeb26dbd92	2446	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
Kojto	100:cbbeb26dbd92	2447	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	100:cbbeb26dbd92	2448	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	100:cbbeb26dbd92	2449	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	100:cbbeb26dbd92	2450	#define __TIM18_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM18RST))
Kojto	100:cbbeb26dbd92	2451	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	100:cbbeb26dbd92	2452	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	100:cbbeb26dbd92	2453	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	100:cbbeb26dbd92	2454	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
Kojto	100:cbbeb26dbd92	2455	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	100:cbbeb26dbd92	2456
Kojto	100:cbbeb26dbd92	2457	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	100:cbbeb26dbd92	2458	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	100:cbbeb26dbd92	2459	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto	100:cbbeb26dbd92	2460	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	100:cbbeb26dbd92	2461	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	100:cbbeb26dbd92	2462	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	100:cbbeb26dbd92	2463	#define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
Kojto	100:cbbeb26dbd92	2464	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	100:cbbeb26dbd92	2465	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	100:cbbeb26dbd92	2466	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	100:cbbeb26dbd92	2467	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto	100:cbbeb26dbd92	2468	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	100:cbbeb26dbd92	2469	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2470
Kojto	100:cbbeb26dbd92	2471	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2472	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	2473	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	2474	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2475	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	100:cbbeb26dbd92	2476
Kojto	100:cbbeb26dbd92	2477	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	100:cbbeb26dbd92	2478	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2479	/* STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	2480	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	2481	/* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2482
Kojto	100:cbbeb26dbd92	2483	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	100:cbbeb26dbd92	2484	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	100:cbbeb26dbd92	2485	defined(STM32F302x8) \|\| \
Kojto	100:cbbeb26dbd92	2486	defined(STM32F373xC)
Kojto	100:cbbeb26dbd92	2487	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	100:cbbeb26dbd92	2488
Kojto	100:cbbeb26dbd92	2489	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto	100:cbbeb26dbd92	2490	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	100:cbbeb26dbd92	2491	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	100:cbbeb26dbd92	2492	/* STM32F302x8 \|\| */
Kojto	100:cbbeb26dbd92	2493	/* STM32F373xC */
Kojto	100:cbbeb26dbd92	2494
Kojto	100:cbbeb26dbd92	2495	#if !defined(STM32F301x8)
Kojto	100:cbbeb26dbd92	2496	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
Kojto	100:cbbeb26dbd92	2497
Kojto	100:cbbeb26dbd92	2498	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto	100:cbbeb26dbd92	2499	#endif /* STM32F301x8*/
Kojto	100:cbbeb26dbd92	2500
Kojto	100:cbbeb26dbd92	2501	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2502	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	100:cbbeb26dbd92	2503
Kojto	100:cbbeb26dbd92	2504	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	100:cbbeb26dbd92	2505	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2506	/**
Kojto	100:cbbeb26dbd92	2507	* @}
Kojto	100:cbbeb26dbd92	2508	*/
Kojto	100:cbbeb26dbd92	2509
Kojto	100:cbbeb26dbd92	2510	/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
Kojto	100:cbbeb26dbd92	2511	* @brief Force or release APB2 peripheral reset.
Kojto	100:cbbeb26dbd92	2512	* @{
Kojto	100:cbbeb26dbd92	2513	*/
Kojto	100:cbbeb26dbd92	2514	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2515	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2516	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	100:cbbeb26dbd92	2517
Kojto	100:cbbeb26dbd92	2518	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	100:cbbeb26dbd92	2519	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2520	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2521
Kojto	100:cbbeb26dbd92	2522	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2523	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2524	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	100:cbbeb26dbd92	2525
Kojto	100:cbbeb26dbd92	2526	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	100:cbbeb26dbd92	2527	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2528	/* STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2529
Kojto	100:cbbeb26dbd92	2530	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	2531	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	100:cbbeb26dbd92	2532
Kojto	100:cbbeb26dbd92	2533	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	100:cbbeb26dbd92	2534	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	2535
Kojto	100:cbbeb26dbd92	2536	#if defined(STM32F334x8)
Kojto	100:cbbeb26dbd92	2537	#define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_HRTIM1RST))
Kojto	100:cbbeb26dbd92	2538
Kojto	100:cbbeb26dbd92	2539	#define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
Kojto	100:cbbeb26dbd92	2540	#endif /* STM32F334x8 */
Kojto	100:cbbeb26dbd92	2541
Kojto	100:cbbeb26dbd92	2542	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	2543	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	100:cbbeb26dbd92	2544	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	100:cbbeb26dbd92	2545	#define __TIM19_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM19RST))
Kojto	100:cbbeb26dbd92	2546	#define __SDADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC1RST))
Kojto	100:cbbeb26dbd92	2547	#define __SDADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC2RST))
Kojto	100:cbbeb26dbd92	2548	#define __SDADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC3RST))
Kojto	100:cbbeb26dbd92	2549
Kojto	100:cbbeb26dbd92	2550	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	100:cbbeb26dbd92	2551	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	100:cbbeb26dbd92	2552	#define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
Kojto	100:cbbeb26dbd92	2553	#define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
Kojto	100:cbbeb26dbd92	2554	#define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
Kojto	100:cbbeb26dbd92	2555	#define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
Kojto	100:cbbeb26dbd92	2556	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	2557
Kojto	100:cbbeb26dbd92	2558	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2559	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	100:cbbeb26dbd92	2560	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	2561	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2562	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	100:cbbeb26dbd92	2563
Kojto	100:cbbeb26dbd92	2564	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	100:cbbeb26dbd92	2565	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2566	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	100:cbbeb26dbd92	2567	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	2568	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2569
Kojto	100:cbbeb26dbd92	2570	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2571	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	100:cbbeb26dbd92	2572
Kojto	100:cbbeb26dbd92	2573	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	100:cbbeb26dbd92	2574	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2575
Kojto	100:cbbeb26dbd92	2576	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	2577	#define __TIM20_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM20RST))
Kojto	100:cbbeb26dbd92	2578
Kojto	100:cbbeb26dbd92	2579	#define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
Kojto	100:cbbeb26dbd92	2580	#endif /* STM32F303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	2581
Kojto	100:cbbeb26dbd92	2582	/**
Kojto	100:cbbeb26dbd92	2583	* @}
Kojto	100:cbbeb26dbd92	2584	*/
Kojto	100:cbbeb26dbd92	2585
Kojto	100:cbbeb26dbd92	2586	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	2587	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	100:cbbeb26dbd92	2588	* @{
Kojto	100:cbbeb26dbd92	2589	*/
Kojto	100:cbbeb26dbd92	2590
Kojto	100:cbbeb26dbd92	2591	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	100:cbbeb26dbd92	2592	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto	100:cbbeb26dbd92	2593	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2594	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2595	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2596	*/
Kojto	100:cbbeb26dbd92	2597	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto	100:cbbeb26dbd92	2598	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto	100:cbbeb26dbd92	2599
Kojto	100:cbbeb26dbd92	2600	/** @brief Macro to get the I2C2 clock source.
Kojto	100:cbbeb26dbd92	2601	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2602	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2603	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2604	*/
Kojto	100:cbbeb26dbd92	2605	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto	100:cbbeb26dbd92	2606
Kojto	100:cbbeb26dbd92	2607	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto	100:cbbeb26dbd92	2608	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto	100:cbbeb26dbd92	2609	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2610	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	100:cbbeb26dbd92	2611	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	100:cbbeb26dbd92	2612	*/
Kojto	100:cbbeb26dbd92	2613	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto	100:cbbeb26dbd92	2614	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
Kojto	100:cbbeb26dbd92	2615
Kojto	100:cbbeb26dbd92	2616	/** @brief Macro to get the I2C3 clock source.
Kojto	100:cbbeb26dbd92	2617	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2618	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	100:cbbeb26dbd92	2619	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	100:cbbeb26dbd92	2620	*/
Kojto	100:cbbeb26dbd92	2621	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
Kojto	100:cbbeb26dbd92	2622
Kojto	100:cbbeb26dbd92	2623	/**
Kojto	100:cbbeb26dbd92	2624	* @}
Kojto	100:cbbeb26dbd92	2625	*/
Kojto	100:cbbeb26dbd92	2626
Kojto	100:cbbeb26dbd92	2627	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	100:cbbeb26dbd92	2628	* @{
Kojto	100:cbbeb26dbd92	2629	*/
Kojto	100:cbbeb26dbd92	2630	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto	100:cbbeb26dbd92	2631	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto	100:cbbeb26dbd92	2632	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2633	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2634	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2635	*/
Kojto	100:cbbeb26dbd92	2636	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto	100:cbbeb26dbd92	2637	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto	100:cbbeb26dbd92	2638
Kojto	100:cbbeb26dbd92	2639	/** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto	100:cbbeb26dbd92	2640	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2641	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2642	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2643	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2644	*/
Kojto	100:cbbeb26dbd92	2645	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto	100:cbbeb26dbd92	2646
Kojto	100:cbbeb26dbd92	2647	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto	100:cbbeb26dbd92	2648	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
Kojto	100:cbbeb26dbd92	2649	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2650	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
Kojto	100:cbbeb26dbd92	2651	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
Kojto	100:cbbeb26dbd92	2652	*/
Kojto	100:cbbeb26dbd92	2653	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
Kojto	100:cbbeb26dbd92	2654	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
Kojto	100:cbbeb26dbd92	2655
Kojto	100:cbbeb26dbd92	2656	/** @brief Macro to get the TIM15 clock (TIM15CLK).
Kojto	100:cbbeb26dbd92	2657	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2658	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2659	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
Kojto	100:cbbeb26dbd92	2660	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
Kojto	100:cbbeb26dbd92	2661	*/
Kojto	100:cbbeb26dbd92	2662	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
Kojto	100:cbbeb26dbd92	2663
Kojto	100:cbbeb26dbd92	2664	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto	100:cbbeb26dbd92	2665	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
Kojto	100:cbbeb26dbd92	2666	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2667	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
Kojto	100:cbbeb26dbd92	2668	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
Kojto	100:cbbeb26dbd92	2669	*/
Kojto	100:cbbeb26dbd92	2670	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
Kojto	100:cbbeb26dbd92	2671	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
Kojto	100:cbbeb26dbd92	2672
Kojto	100:cbbeb26dbd92	2673	/** @brief Macro to get the TIM16 clock (TIM16CLK).
Kojto	100:cbbeb26dbd92	2674	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2675	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2676	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
Kojto	100:cbbeb26dbd92	2677	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
Kojto	100:cbbeb26dbd92	2678	*/
Kojto	100:cbbeb26dbd92	2679	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
Kojto	100:cbbeb26dbd92	2680
Kojto	100:cbbeb26dbd92	2681	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto	100:cbbeb26dbd92	2682	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
Kojto	100:cbbeb26dbd92	2683	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2684	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
Kojto	100:cbbeb26dbd92	2685	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
Kojto	100:cbbeb26dbd92	2686	*/
Kojto	100:cbbeb26dbd92	2687	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
Kojto	100:cbbeb26dbd92	2688	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
Kojto	100:cbbeb26dbd92	2689
Kojto	100:cbbeb26dbd92	2690	/** @brief Macro to get the TIM17 clock (TIM17CLK).
Kojto	100:cbbeb26dbd92	2691	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2692	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2693	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
Kojto	100:cbbeb26dbd92	2694	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
Kojto	100:cbbeb26dbd92	2695	*/
Kojto	100:cbbeb26dbd92	2696	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
Kojto	100:cbbeb26dbd92	2697
Kojto	100:cbbeb26dbd92	2698	/**
Kojto	100:cbbeb26dbd92	2699	* @}
Kojto	100:cbbeb26dbd92	2700	*/
Kojto	100:cbbeb26dbd92	2701
Kojto	100:cbbeb26dbd92	2702	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
Kojto	100:cbbeb26dbd92	2703	* @{
Kojto	100:cbbeb26dbd92	2704	*/
Kojto	100:cbbeb26dbd92	2705	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	100:cbbeb26dbd92	2706	* @note This function must be called before enabling the I2S APB clock.
Kojto	100:cbbeb26dbd92	2707	* @param __I2SCLKSource__: specifies the I2S clock source.
Kojto	100:cbbeb26dbd92	2708	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2709	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	100:cbbeb26dbd92	2710	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	100:cbbeb26dbd92	2711	* used as I2S clock source
Kojto	100:cbbeb26dbd92	2712	*/
Kojto	100:cbbeb26dbd92	2713	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
Kojto	100:cbbeb26dbd92	2714	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
Kojto	100:cbbeb26dbd92	2715
Kojto	100:cbbeb26dbd92	2716	/** @brief Macro to get the I2S clock source (I2SCLK).
Kojto	100:cbbeb26dbd92	2717	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2718	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	100:cbbeb26dbd92	2719	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	100:cbbeb26dbd92	2720	* used as I2S clock source
Kojto	100:cbbeb26dbd92	2721	*/
Kojto	100:cbbeb26dbd92	2722	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto	100:cbbeb26dbd92	2723	/**
Kojto	100:cbbeb26dbd92	2724	* @}
Kojto	100:cbbeb26dbd92	2725	*/
Kojto	100:cbbeb26dbd92	2726
Kojto	100:cbbeb26dbd92	2727	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	100:cbbeb26dbd92	2728	* @{
Kojto	100:cbbeb26dbd92	2729	*/
Kojto	100:cbbeb26dbd92	2730
Kojto	100:cbbeb26dbd92	2731	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto	100:cbbeb26dbd92	2732	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
Kojto	100:cbbeb26dbd92	2733	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2734	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto	100:cbbeb26dbd92	2735	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2736	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2737	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2738	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2739	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2740	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2741	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2742	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2743	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2744	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2745	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2746	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2747	*/
Kojto	100:cbbeb26dbd92	2748	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
Kojto	100:cbbeb26dbd92	2749	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
Kojto	100:cbbeb26dbd92	2750
Kojto	100:cbbeb26dbd92	2751	/** @brief Macro to get the ADC1 clock
Kojto	100:cbbeb26dbd92	2752	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2753	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto	100:cbbeb26dbd92	2754	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2755	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2756	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2757	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2758	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2759	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2760	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2761	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2762	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2763	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2764	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2765	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	2766	*/
Kojto	100:cbbeb26dbd92	2767	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
Kojto	100:cbbeb26dbd92	2768	/**
Kojto	100:cbbeb26dbd92	2769	* @}
Kojto	100:cbbeb26dbd92	2770	*/
Kojto	100:cbbeb26dbd92	2771
Kojto	100:cbbeb26dbd92	2772	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	2773
Kojto	100:cbbeb26dbd92	2774	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2775	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2776	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	100:cbbeb26dbd92	2777	* @{
Kojto	100:cbbeb26dbd92	2778	*/
Kojto	100:cbbeb26dbd92	2779
Kojto	100:cbbeb26dbd92	2780	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	100:cbbeb26dbd92	2781	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto	100:cbbeb26dbd92	2782	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2783	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2784	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2785	*/
Kojto	100:cbbeb26dbd92	2786	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto	100:cbbeb26dbd92	2787	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto	100:cbbeb26dbd92	2788
Kojto	100:cbbeb26dbd92	2789	/** @brief Macro to get the I2C2 clock source.
Kojto	100:cbbeb26dbd92	2790	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2791	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2792	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	100:cbbeb26dbd92	2793	*/
Kojto	100:cbbeb26dbd92	2794	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto	100:cbbeb26dbd92	2795	/**
Kojto	100:cbbeb26dbd92	2796	* @}
Kojto	100:cbbeb26dbd92	2797	*/
Kojto	100:cbbeb26dbd92	2798
Kojto	100:cbbeb26dbd92	2799	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	100:cbbeb26dbd92	2800	* @{
Kojto	100:cbbeb26dbd92	2801	*/
Kojto	100:cbbeb26dbd92	2802
Kojto	100:cbbeb26dbd92	2803	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto	100:cbbeb26dbd92	2804	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
Kojto	100:cbbeb26dbd92	2805	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2806	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	100:cbbeb26dbd92	2807	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2808	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2809	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2810	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2811	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2812	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2813	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2814	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2815	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2816	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2817	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2818	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2819	*/
Kojto	100:cbbeb26dbd92	2820	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
Kojto	100:cbbeb26dbd92	2821	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
Kojto	100:cbbeb26dbd92	2822
Kojto	100:cbbeb26dbd92	2823	/** @brief Macro to get the ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2824	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2825	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	100:cbbeb26dbd92	2826	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2827	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2828	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2829	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2830	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2831	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2832	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2833	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2834	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2835	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2836	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2837	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	2838	*/
Kojto	100:cbbeb26dbd92	2839	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
Kojto	100:cbbeb26dbd92	2840	/**
Kojto	100:cbbeb26dbd92	2841	* @}
Kojto	100:cbbeb26dbd92	2842	*/
Kojto	100:cbbeb26dbd92	2843
Kojto	100:cbbeb26dbd92	2844	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	100:cbbeb26dbd92	2845	* @{
Kojto	100:cbbeb26dbd92	2846	*/
Kojto	100:cbbeb26dbd92	2847
Kojto	100:cbbeb26dbd92	2848	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto	100:cbbeb26dbd92	2849	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto	100:cbbeb26dbd92	2850	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2851	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2852	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2853	*/
Kojto	100:cbbeb26dbd92	2854	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto	100:cbbeb26dbd92	2855	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto	100:cbbeb26dbd92	2856
Kojto	100:cbbeb26dbd92	2857	/** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto	100:cbbeb26dbd92	2858	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2859	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2860	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2861	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	100:cbbeb26dbd92	2862	*/
Kojto	100:cbbeb26dbd92	2863	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto	100:cbbeb26dbd92	2864	/**
Kojto	100:cbbeb26dbd92	2865	* @}
Kojto	100:cbbeb26dbd92	2866	*/
Kojto	100:cbbeb26dbd92	2867
Kojto	100:cbbeb26dbd92	2868	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
Kojto	100:cbbeb26dbd92	2869	* @{
Kojto	100:cbbeb26dbd92	2870	*/
Kojto	100:cbbeb26dbd92	2871
Kojto	100:cbbeb26dbd92	2872	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	100:cbbeb26dbd92	2873	* @note This function must be called before enabling the I2S APB clock.
Kojto	100:cbbeb26dbd92	2874	* @param __I2SCLKSource__: specifies the I2S clock source.
Kojto	100:cbbeb26dbd92	2875	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2876	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	100:cbbeb26dbd92	2877	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	100:cbbeb26dbd92	2878	* used as I2S clock source
Kojto	100:cbbeb26dbd92	2879	*/
Kojto	100:cbbeb26dbd92	2880	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
Kojto	100:cbbeb26dbd92	2881	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
Kojto	100:cbbeb26dbd92	2882
Kojto	100:cbbeb26dbd92	2883	/** @brief Macro to get the I2S clock source (I2SCLK).
Kojto	100:cbbeb26dbd92	2884	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2885	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	100:cbbeb26dbd92	2886	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	100:cbbeb26dbd92	2887	* used as I2S clock source
Kojto	100:cbbeb26dbd92	2888	*/
Kojto	100:cbbeb26dbd92	2889	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto	100:cbbeb26dbd92	2890	/**
Kojto	100:cbbeb26dbd92	2891	* @}
Kojto	100:cbbeb26dbd92	2892	*/
Kojto	100:cbbeb26dbd92	2893
Kojto	100:cbbeb26dbd92	2894	/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
Kojto	100:cbbeb26dbd92	2895	* @{
Kojto	100:cbbeb26dbd92	2896	*/
Kojto	100:cbbeb26dbd92	2897
Kojto	100:cbbeb26dbd92	2898	/** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto	100:cbbeb26dbd92	2899	* @param __UART4CLKSource__: specifies the UART4 clock source.
Kojto	100:cbbeb26dbd92	2900	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2901	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto	100:cbbeb26dbd92	2902	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto	100:cbbeb26dbd92	2903	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto	100:cbbeb26dbd92	2904	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto	100:cbbeb26dbd92	2905	*/
Kojto	100:cbbeb26dbd92	2906	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
Kojto	100:cbbeb26dbd92	2907	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
Kojto	100:cbbeb26dbd92	2908
Kojto	100:cbbeb26dbd92	2909	/** @brief Macro to get the UART4 clock source.
Kojto	100:cbbeb26dbd92	2910	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2911	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto	100:cbbeb26dbd92	2912	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto	100:cbbeb26dbd92	2913	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto	100:cbbeb26dbd92	2914	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto	100:cbbeb26dbd92	2915	*/
Kojto	100:cbbeb26dbd92	2916	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
Kojto	100:cbbeb26dbd92	2917
Kojto	100:cbbeb26dbd92	2918	/** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto	100:cbbeb26dbd92	2919	* @param __UART5CLKSource__: specifies the UART5 clock source.
Kojto	100:cbbeb26dbd92	2920	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2921	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto	100:cbbeb26dbd92	2922	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto	100:cbbeb26dbd92	2923	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto	100:cbbeb26dbd92	2924	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto	100:cbbeb26dbd92	2925	*/
Kojto	100:cbbeb26dbd92	2926	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
Kojto	100:cbbeb26dbd92	2927	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
Kojto	100:cbbeb26dbd92	2928
Kojto	100:cbbeb26dbd92	2929	/** @brief Macro to get the UART5 clock source.
Kojto	100:cbbeb26dbd92	2930	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2931	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto	100:cbbeb26dbd92	2932	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto	100:cbbeb26dbd92	2933	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto	100:cbbeb26dbd92	2934	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto	100:cbbeb26dbd92	2935	*/
Kojto	100:cbbeb26dbd92	2936	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
Kojto	100:cbbeb26dbd92	2937	/**
Kojto	100:cbbeb26dbd92	2938	* @}
Kojto	100:cbbeb26dbd92	2939	*/
Kojto	100:cbbeb26dbd92	2940	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	2941	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	2942
Kojto	100:cbbeb26dbd92	2943	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	2944	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	100:cbbeb26dbd92	2945	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	100:cbbeb26dbd92	2946	* @{
Kojto	100:cbbeb26dbd92	2947	*/
Kojto	100:cbbeb26dbd92	2948
Kojto	100:cbbeb26dbd92	2949	/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
Kojto	100:cbbeb26dbd92	2950	* @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
Kojto	100:cbbeb26dbd92	2951	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2952	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto	100:cbbeb26dbd92	2953	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2954	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2955	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2956	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2957	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2958	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2959	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2960	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2961	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2962	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2963	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2964	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2965	*/
Kojto	100:cbbeb26dbd92	2966	#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
Kojto	100:cbbeb26dbd92	2967	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
Kojto	100:cbbeb26dbd92	2968
Kojto	100:cbbeb26dbd92	2969	/** @brief Macro to get the ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2970	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	2971	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto	100:cbbeb26dbd92	2972	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2973	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2974	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2975	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2976	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2977	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2978	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2979	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2980	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2981	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2982	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2983	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
Kojto	100:cbbeb26dbd92	2984	*/
Kojto	100:cbbeb26dbd92	2985	#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
Kojto	100:cbbeb26dbd92	2986	/**
Kojto	100:cbbeb26dbd92	2987	* @}
Kojto	100:cbbeb26dbd92	2988	*/
Kojto	100:cbbeb26dbd92	2989
Kojto	100:cbbeb26dbd92	2990	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	100:cbbeb26dbd92	2991	* @{
Kojto	100:cbbeb26dbd92	2992	*/
Kojto	100:cbbeb26dbd92	2993
Kojto	100:cbbeb26dbd92	2994	/** @brief Macro to configure the TIM8 clock (TIM8CLK).
Kojto	100:cbbeb26dbd92	2995	* @param __TIM8CLKSource__: specifies the TIM8 clock source.
Kojto	100:cbbeb26dbd92	2996	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	2997	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
Kojto	100:cbbeb26dbd92	2998	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
Kojto	100:cbbeb26dbd92	2999	*/
Kojto	100:cbbeb26dbd92	3000	#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
Kojto	100:cbbeb26dbd92	3001	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
Kojto	100:cbbeb26dbd92	3002
Kojto	100:cbbeb26dbd92	3003	/** @brief Macro to get the TIM8 clock (TIM8CLK).
Kojto	100:cbbeb26dbd92	3004	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3005	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3006	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
Kojto	100:cbbeb26dbd92	3007	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
Kojto	100:cbbeb26dbd92	3008	*/
Kojto	100:cbbeb26dbd92	3009	#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
Kojto	100:cbbeb26dbd92	3010
Kojto	100:cbbeb26dbd92	3011	/**
Kojto	100:cbbeb26dbd92	3012	* @}
Kojto	100:cbbeb26dbd92	3013	*/
Kojto	100:cbbeb26dbd92	3014	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	3015	/* STM32F303xC \|\| STM32F358xx */
Kojto	100:cbbeb26dbd92	3016
Kojto	100:cbbeb26dbd92	3017	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	100:cbbeb26dbd92	3018	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	100:cbbeb26dbd92	3019	* @{
Kojto	100:cbbeb26dbd92	3020	*/
Kojto	100:cbbeb26dbd92	3021
Kojto	100:cbbeb26dbd92	3022	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto	100:cbbeb26dbd92	3023	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
Kojto	100:cbbeb26dbd92	3024	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3025	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	100:cbbeb26dbd92	3026	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3027	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3028	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3029	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3030	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3031	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3032	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3033	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3034	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3035	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3036	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3037	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3038	*/
Kojto	100:cbbeb26dbd92	3039	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
Kojto	100:cbbeb26dbd92	3040	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
Kojto	100:cbbeb26dbd92	3041
Kojto	100:cbbeb26dbd92	3042	/** @brief Macro to get the ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3043	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3044	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	100:cbbeb26dbd92	3045	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3046	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3047	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3048	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3049	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3050	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3051	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3052	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3053	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3054	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3055	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3056	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	100:cbbeb26dbd92	3057	*/
Kojto	100:cbbeb26dbd92	3058	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
Kojto	100:cbbeb26dbd92	3059	/**
Kojto	100:cbbeb26dbd92	3060	* @}
Kojto	100:cbbeb26dbd92	3061	*/
Kojto	100:cbbeb26dbd92	3062
Kojto	100:cbbeb26dbd92	3063	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	100:cbbeb26dbd92	3064	* @{
Kojto	100:cbbeb26dbd92	3065	*/
Kojto	100:cbbeb26dbd92	3066	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto	100:cbbeb26dbd92	3067	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto	100:cbbeb26dbd92	3068	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3069	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	100:cbbeb26dbd92	3070	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	100:cbbeb26dbd92	3071	*/
Kojto	100:cbbeb26dbd92	3072	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto	100:cbbeb26dbd92	3073	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto	100:cbbeb26dbd92	3074
Kojto	100:cbbeb26dbd92	3075	/** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto	100:cbbeb26dbd92	3076	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3077	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3078	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	100:cbbeb26dbd92	3079	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	100:cbbeb26dbd92	3080	*/
Kojto	100:cbbeb26dbd92	3081	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto	100:cbbeb26dbd92	3082	/**
Kojto	100:cbbeb26dbd92	3083	* @}
Kojto	100:cbbeb26dbd92	3084	*/
Kojto	100:cbbeb26dbd92	3085	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	100:cbbeb26dbd92	3086
Kojto	100:cbbeb26dbd92	3087	#if defined(STM32F334x8)
Kojto	100:cbbeb26dbd92	3088	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
Kojto	100:cbbeb26dbd92	3089	* @{
Kojto	100:cbbeb26dbd92	3090	*/
Kojto	100:cbbeb26dbd92	3091	/** @brief Macro to configure the HRTIM1 clock.
Kojto	100:cbbeb26dbd92	3092	* @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
Kojto	100:cbbeb26dbd92	3093	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3094	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
Kojto	100:cbbeb26dbd92	3095	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
Kojto	100:cbbeb26dbd92	3096	*/
Kojto	100:cbbeb26dbd92	3097	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
Kojto	100:cbbeb26dbd92	3098	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
Kojto	100:cbbeb26dbd92	3099
Kojto	100:cbbeb26dbd92	3100	/** @brief Macro to get the HRTIM1 clock source.
Kojto	100:cbbeb26dbd92	3101	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3102	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
Kojto	100:cbbeb26dbd92	3103	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
Kojto	100:cbbeb26dbd92	3104	*/
Kojto	100:cbbeb26dbd92	3105	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
Kojto	100:cbbeb26dbd92	3106	/**
Kojto	100:cbbeb26dbd92	3107	* @}
Kojto	100:cbbeb26dbd92	3108	*/
Kojto	100:cbbeb26dbd92	3109	#endif /* STM32F334x8 */
Kojto	100:cbbeb26dbd92	3110
Kojto	100:cbbeb26dbd92	3111	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	100:cbbeb26dbd92	3112	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	100:cbbeb26dbd92	3113	* @{
Kojto	100:cbbeb26dbd92	3114	*/
Kojto	100:cbbeb26dbd92	3115	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	100:cbbeb26dbd92	3116	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto	100:cbbeb26dbd92	3117	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3118	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	100:cbbeb26dbd92	3119	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	100:cbbeb26dbd92	3120	*/
Kojto	100:cbbeb26dbd92	3121	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto	100:cbbeb26dbd92	3122	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto	100:cbbeb26dbd92	3123
Kojto	100:cbbeb26dbd92	3124	/** @brief Macro to get the I2C2 clock source.
Kojto	100:cbbeb26dbd92	3125	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3126	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	100:cbbeb26dbd92	3127	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	100:cbbeb26dbd92	3128	*/
Kojto	100:cbbeb26dbd92	3129	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto	100:cbbeb26dbd92	3130	/**
Kojto	100:cbbeb26dbd92	3131	* @}
Kojto	100:cbbeb26dbd92	3132	*/
Kojto	100:cbbeb26dbd92	3133
Kojto	100:cbbeb26dbd92	3134	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	100:cbbeb26dbd92	3135	* @{
Kojto	100:cbbeb26dbd92	3136	*/
Kojto	100:cbbeb26dbd92	3137	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto	100:cbbeb26dbd92	3138	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
Kojto	100:cbbeb26dbd92	3139	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3140	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3141	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3142	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3143	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3144	*/
Kojto	100:cbbeb26dbd92	3145	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
Kojto	100:cbbeb26dbd92	3146	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
Kojto	100:cbbeb26dbd92	3147
Kojto	100:cbbeb26dbd92	3148	/** @brief Macro to get the ADC1 clock (ADC1CLK).
Kojto	100:cbbeb26dbd92	3149	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3150	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3151	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3152	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3153	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
Kojto	100:cbbeb26dbd92	3154	*/
Kojto	100:cbbeb26dbd92	3155	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Kojto	100:cbbeb26dbd92	3156	/**
Kojto	100:cbbeb26dbd92	3157	* @}
Kojto	100:cbbeb26dbd92	3158	*/
Kojto	100:cbbeb26dbd92	3159
Kojto	100:cbbeb26dbd92	3160	/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
Kojto	100:cbbeb26dbd92	3161	* @{
Kojto	100:cbbeb26dbd92	3162	*/
Kojto	100:cbbeb26dbd92	3163	/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
Kojto	100:cbbeb26dbd92	3164	* @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
Kojto	100:cbbeb26dbd92	3165	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3166	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3167	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3168	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3169	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3170	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3171	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3172	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3173	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3174	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3175	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3176	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3177	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3178	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3179	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3180	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3181	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3182	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3183	*/
Kojto	100:cbbeb26dbd92	3184	#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
Kojto	100:cbbeb26dbd92	3185	MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
Kojto	100:cbbeb26dbd92	3186
Kojto	100:cbbeb26dbd92	3187	/** @brief Macro to get the SDADCx clock prescaler.
Kojto	100:cbbeb26dbd92	3188	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3189	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3190	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3191	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3192	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3193	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3194	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3195	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3196	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3197	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3198	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3199	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3200	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3201	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3202	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3203	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3204	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3205	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
Kojto	100:cbbeb26dbd92	3206	*/
Kojto	100:cbbeb26dbd92	3207	#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
Kojto	100:cbbeb26dbd92	3208	/**
Kojto	100:cbbeb26dbd92	3209	* @}
Kojto	100:cbbeb26dbd92	3210	*/
Kojto	100:cbbeb26dbd92	3211
Kojto	100:cbbeb26dbd92	3212	/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
Kojto	100:cbbeb26dbd92	3213	* @{
Kojto	100:cbbeb26dbd92	3214	*/
Kojto	100:cbbeb26dbd92	3215	/** @brief Macro to configure the CEC clock.
Kojto	100:cbbeb26dbd92	3216	* @param __CECCLKSource__: specifies the CEC clock source.
Kojto	100:cbbeb26dbd92	3217	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3218	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	100:cbbeb26dbd92	3219	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	100:cbbeb26dbd92	3220	*/
Kojto	100:cbbeb26dbd92	3221	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto	100:cbbeb26dbd92	3222	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto	100:cbbeb26dbd92	3223
Kojto	100:cbbeb26dbd92	3224	/** @brief Macro to get the HDMI CEC clock source.
Kojto	100:cbbeb26dbd92	3225	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3226	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	100:cbbeb26dbd92	3227	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	100:cbbeb26dbd92	3228	*/
Kojto	100:cbbeb26dbd92	3229	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto	100:cbbeb26dbd92	3230	/**
Kojto	100:cbbeb26dbd92	3231	* @}
Kojto	100:cbbeb26dbd92	3232	*/
Kojto	100:cbbeb26dbd92	3233
Kojto	100:cbbeb26dbd92	3234	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	100:cbbeb26dbd92	3235
Kojto	100:cbbeb26dbd92	3236	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	100:cbbeb26dbd92	3237	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	100:cbbeb26dbd92	3238	defined(STM32F302x8) \|\| \
Kojto	100:cbbeb26dbd92	3239	defined(STM32F373xC)
Kojto	100:cbbeb26dbd92	3240
Kojto	100:cbbeb26dbd92	3241	/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
Kojto	100:cbbeb26dbd92	3242	* @{
Kojto	100:cbbeb26dbd92	3243	*/
Kojto	100:cbbeb26dbd92	3244	/** @brief Macro to configure the USB clock (USBCLK).
Kojto	100:cbbeb26dbd92	3245	* @param __USBCLKSource__: specifies the USB clock source.
Kojto	100:cbbeb26dbd92	3246	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3247	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
Kojto	100:cbbeb26dbd92	3248	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
Kojto	100:cbbeb26dbd92	3249	*/
Kojto	100:cbbeb26dbd92	3250	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto	100:cbbeb26dbd92	3251	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
Kojto	100:cbbeb26dbd92	3252
Kojto	100:cbbeb26dbd92	3253	/** @brief Macro to get the USB clock source.
Kojto	100:cbbeb26dbd92	3254	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3255	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
Kojto	100:cbbeb26dbd92	3256	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
Kojto	100:cbbeb26dbd92	3257	*/
Kojto	100:cbbeb26dbd92	3258	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Kojto	100:cbbeb26dbd92	3259	/**
Kojto	100:cbbeb26dbd92	3260	* @}
Kojto	100:cbbeb26dbd92	3261	*/
Kojto	100:cbbeb26dbd92	3262
Kojto	100:cbbeb26dbd92	3263	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	100:cbbeb26dbd92	3264	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	100:cbbeb26dbd92	3265	/* STM32F302x8 \|\| */
Kojto	100:cbbeb26dbd92	3266	/* STM32F373xC */
Kojto	100:cbbeb26dbd92	3267
Kojto	100:cbbeb26dbd92	3268	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	100:cbbeb26dbd92	3269	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	100:cbbeb26dbd92	3270	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	100:cbbeb26dbd92	3271
Kojto	100:cbbeb26dbd92	3272	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	100:cbbeb26dbd92	3273	* @{
Kojto	100:cbbeb26dbd92	3274	*/
Kojto	100:cbbeb26dbd92	3275	/** @brief macro to configure the MCO clock.
Kojto	100:cbbeb26dbd92	3276	* @param __MCOCLKSource__: specifies the MCO clock source.
Kojto	100:cbbeb26dbd92	3277	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3278	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto	100:cbbeb26dbd92	3279	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto	100:cbbeb26dbd92	3280	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto	100:cbbeb26dbd92	3281	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto	100:cbbeb26dbd92	3282	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto	100:cbbeb26dbd92	3283	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto	100:cbbeb26dbd92	3284	* @param __MCODiv__: specifies the MCO clock prescaler.
Kojto	100:cbbeb26dbd92	3285	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3286	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
Kojto	100:cbbeb26dbd92	3287	*/
Kojto	100:cbbeb26dbd92	3288	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	100:cbbeb26dbd92	3289	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
Kojto	100:cbbeb26dbd92	3290	/**
Kojto	100:cbbeb26dbd92	3291	* @}
Kojto	100:cbbeb26dbd92	3292	*/
Kojto	100:cbbeb26dbd92	3293	#else
Kojto	100:cbbeb26dbd92	3294	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	100:cbbeb26dbd92	3295	* @{
Kojto	100:cbbeb26dbd92	3296	*/
Kojto	100:cbbeb26dbd92	3297
Kojto	100:cbbeb26dbd92	3298	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	100:cbbeb26dbd92	3299	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
Kojto	100:cbbeb26dbd92	3300	/**
Kojto	100:cbbeb26dbd92	3301	* @}
Kojto	100:cbbeb26dbd92	3302	*/
Kojto	100:cbbeb26dbd92	3303
Kojto	100:cbbeb26dbd92	3304	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	100:cbbeb26dbd92	3305	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	100:cbbeb26dbd92	3306	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	100:cbbeb26dbd92	3307
Kojto	100:cbbeb26dbd92	3308	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	3309
Kojto	100:cbbeb26dbd92	3310	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	100:cbbeb26dbd92	3311	* @{
Kojto	100:cbbeb26dbd92	3312	*/
Kojto	100:cbbeb26dbd92	3313	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto	100:cbbeb26dbd92	3314	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto	100:cbbeb26dbd92	3315	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3316	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	100:cbbeb26dbd92	3317	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	100:cbbeb26dbd92	3318	*/
Kojto	100:cbbeb26dbd92	3319	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto	100:cbbeb26dbd92	3320	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
Kojto	100:cbbeb26dbd92	3321
Kojto	100:cbbeb26dbd92	3322	/** @brief Macro to get the I2C3 clock source.
Kojto	100:cbbeb26dbd92	3323	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3324	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	100:cbbeb26dbd92	3325	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	100:cbbeb26dbd92	3326	*/
Kojto	100:cbbeb26dbd92	3327	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
Kojto	100:cbbeb26dbd92	3328	/**
Kojto	100:cbbeb26dbd92	3329	* @}
Kojto	100:cbbeb26dbd92	3330	*/
Kojto	100:cbbeb26dbd92	3331
Kojto	100:cbbeb26dbd92	3332	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	100:cbbeb26dbd92	3333	* @{
Kojto	100:cbbeb26dbd92	3334	*/
Kojto	100:cbbeb26dbd92	3335	/** @brief Macro to configure the TIM2 clock (TIM2CLK).
Kojto	100:cbbeb26dbd92	3336	* @param __TIM2CLKSource__: specifies the TIM2 clock source.
Kojto	100:cbbeb26dbd92	3337	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3338	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
Kojto	100:cbbeb26dbd92	3339	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
Kojto	100:cbbeb26dbd92	3340	*/
Kojto	100:cbbeb26dbd92	3341	#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
Kojto	100:cbbeb26dbd92	3342	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
Kojto	100:cbbeb26dbd92	3343
Kojto	100:cbbeb26dbd92	3344	/** @brief Macro to get the TIM2 clock (TIM2CLK).
Kojto	100:cbbeb26dbd92	3345	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3346	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3347	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
Kojto	100:cbbeb26dbd92	3348	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
Kojto	100:cbbeb26dbd92	3349	*/
Kojto	100:cbbeb26dbd92	3350	#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
Kojto	100:cbbeb26dbd92	3351
Kojto	100:cbbeb26dbd92	3352	/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
Kojto	100:cbbeb26dbd92	3353	* @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
Kojto	100:cbbeb26dbd92	3354	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3355	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
Kojto	100:cbbeb26dbd92	3356	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
Kojto	100:cbbeb26dbd92	3357	*/
Kojto	100:cbbeb26dbd92	3358	#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
Kojto	100:cbbeb26dbd92	3359	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
Kojto	100:cbbeb26dbd92	3360
Kojto	100:cbbeb26dbd92	3361	/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
Kojto	100:cbbeb26dbd92	3362	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3363	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3364	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
Kojto	100:cbbeb26dbd92	3365	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
Kojto	100:cbbeb26dbd92	3366	*/
Kojto	100:cbbeb26dbd92	3367	#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
Kojto	100:cbbeb26dbd92	3368
Kojto	100:cbbeb26dbd92	3369	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto	100:cbbeb26dbd92	3370	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
Kojto	100:cbbeb26dbd92	3371	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3372	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
Kojto	100:cbbeb26dbd92	3373	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
Kojto	100:cbbeb26dbd92	3374	*/
Kojto	100:cbbeb26dbd92	3375	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
Kojto	100:cbbeb26dbd92	3376	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
Kojto	100:cbbeb26dbd92	3377
Kojto	100:cbbeb26dbd92	3378	/** @brief Macro to get the TIM15 clock (TIM15CLK).
Kojto	100:cbbeb26dbd92	3379	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3380	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3381	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
Kojto	100:cbbeb26dbd92	3382	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
Kojto	100:cbbeb26dbd92	3383	*/
Kojto	100:cbbeb26dbd92	3384	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
Kojto	100:cbbeb26dbd92	3385
Kojto	100:cbbeb26dbd92	3386	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto	100:cbbeb26dbd92	3387	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
Kojto	100:cbbeb26dbd92	3388	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3389	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
Kojto	100:cbbeb26dbd92	3390	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
Kojto	100:cbbeb26dbd92	3391	*/
Kojto	100:cbbeb26dbd92	3392	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
Kojto	100:cbbeb26dbd92	3393	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
Kojto	100:cbbeb26dbd92	3394
Kojto	100:cbbeb26dbd92	3395	/** @brief Macro to get the TIM16 clock (TIM16CLK).
Kojto	100:cbbeb26dbd92	3396	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3397	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3398	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
Kojto	100:cbbeb26dbd92	3399	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
Kojto	100:cbbeb26dbd92	3400	*/
Kojto	100:cbbeb26dbd92	3401	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
Kojto	100:cbbeb26dbd92	3402
Kojto	100:cbbeb26dbd92	3403	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto	100:cbbeb26dbd92	3404	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
Kojto	100:cbbeb26dbd92	3405	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3406	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
Kojto	100:cbbeb26dbd92	3407	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
Kojto	100:cbbeb26dbd92	3408	*/
Kojto	100:cbbeb26dbd92	3409	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
Kojto	100:cbbeb26dbd92	3410	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
Kojto	100:cbbeb26dbd92	3411
Kojto	100:cbbeb26dbd92	3412	/** @brief Macro to get the TIM17 clock (TIM17CLK).
Kojto	100:cbbeb26dbd92	3413	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3414	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3415	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
Kojto	100:cbbeb26dbd92	3416	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
Kojto	100:cbbeb26dbd92	3417	*/
Kojto	100:cbbeb26dbd92	3418	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
Kojto	100:cbbeb26dbd92	3419
Kojto	100:cbbeb26dbd92	3420	/**
Kojto	100:cbbeb26dbd92	3421	* @}
Kojto	100:cbbeb26dbd92	3422	*/
Kojto	100:cbbeb26dbd92	3423
Kojto	100:cbbeb26dbd92	3424	#endif /* STM32f302xE \|\| STM32f303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	3425
Kojto	100:cbbeb26dbd92	3426	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	100:cbbeb26dbd92	3427	/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	100:cbbeb26dbd92	3428	* @{
Kojto	100:cbbeb26dbd92	3429	*/
Kojto	100:cbbeb26dbd92	3430	/** @brief Macro to configure the TIM20 clock (TIM20CLK).
Kojto	100:cbbeb26dbd92	3431	* @param __TIM20CLKSource__: specifies the TIM20 clock source.
Kojto	100:cbbeb26dbd92	3432	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3433	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
Kojto	100:cbbeb26dbd92	3434	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
Kojto	100:cbbeb26dbd92	3435	*/
Kojto	100:cbbeb26dbd92	3436	#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
Kojto	100:cbbeb26dbd92	3437	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
Kojto	100:cbbeb26dbd92	3438
Kojto	100:cbbeb26dbd92	3439	/** @brief Macro to get the TIM20 clock (TIM20CLK).
Kojto	100:cbbeb26dbd92	3440	* @retval The clock source can be one of the following values:
Kojto	100:cbbeb26dbd92	3441	* This parameter can be one of the following values:
Kojto	100:cbbeb26dbd92	3442	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
Kojto	100:cbbeb26dbd92	3443	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
Kojto	100:cbbeb26dbd92	3444	*/
Kojto	100:cbbeb26dbd92	3445	#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
Kojto	100:cbbeb26dbd92	3446
Kojto	100:cbbeb26dbd92	3447	/**
Kojto	100:cbbeb26dbd92	3448	* @}
Kojto	100:cbbeb26dbd92	3449	*/
Kojto	100:cbbeb26dbd92	3450	#endif /* STM32f303xE \|\| STM32F398xx */
Kojto	100:cbbeb26dbd92	3451
Kojto	100:cbbeb26dbd92	3452
Kojto	100:cbbeb26dbd92	3453	/**
Kojto	100:cbbeb26dbd92	3454	* @}
Kojto	100:cbbeb26dbd92	3455	*/
Kojto	100:cbbeb26dbd92	3456
Kojto	100:cbbeb26dbd92	3457	/* Exported functions --------------------------------------------------------*/
Kojto	100:cbbeb26dbd92	3458	/** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
Kojto	100:cbbeb26dbd92	3459	* @{
Kojto	100:cbbeb26dbd92	3460	*/
Kojto	100:cbbeb26dbd92	3461
Kojto	100:cbbeb26dbd92	3462	/** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
Kojto	100:cbbeb26dbd92	3463	* @{
Kojto	100:cbbeb26dbd92	3464	*/
Kojto	100:cbbeb26dbd92	3465	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	100:cbbeb26dbd92	3466	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	100:cbbeb26dbd92	3467	/**
Kojto	100:cbbeb26dbd92	3468	* @}
Kojto	100:cbbeb26dbd92	3469	*/
Kojto	100:cbbeb26dbd92	3470
Kojto	100:cbbeb26dbd92	3471	/**
Kojto	100:cbbeb26dbd92	3472	* @}
Kojto	100:cbbeb26dbd92	3473	*/
Kojto	100:cbbeb26dbd92	3474
Kojto	100:cbbeb26dbd92	3475	/**
Kojto	100:cbbeb26dbd92	3476	* @}
Kojto	100:cbbeb26dbd92	3477	*/
Kojto	100:cbbeb26dbd92	3478
Kojto	100:cbbeb26dbd92	3479	/**
Kojto	100:cbbeb26dbd92	3480	* @}
Kojto	100:cbbeb26dbd92	3481	*/
Kojto	100:cbbeb26dbd92	3482	#ifdef __cplusplus
Kojto	100:cbbeb26dbd92	3483	}
Kojto	100:cbbeb26dbd92	3484	#endif
Kojto	100:cbbeb26dbd92	3485
Kojto	100:cbbeb26dbd92	3486	#endif /* __STM32F3xx_HAL_RCC_EX_H */
Kojto	100:cbbeb26dbd92	3487
Kojto	100:cbbeb26dbd92	3488	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_DISCO_F334C8/stm32f3xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

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