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TARGET_B96B_F446VE/stm32f4xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 112:6f327212ef96

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	112:6f327212ef96	1	/**
Kojto	112:6f327212ef96	2	******************************************************************************
Kojto	112:6f327212ef96	3	* @file stm32f4xx_hal_rcc_ex.h
Kojto	112:6f327212ef96	4	* @author MCD Application Team
Kojto	112:6f327212ef96	5	* @version V1.4.1
Kojto	112:6f327212ef96	6	* @date 09-October-2015
Kojto	112:6f327212ef96	7	* @brief Header file of RCC HAL Extension module.
Kojto	112:6f327212ef96	8	******************************************************************************
Kojto	112:6f327212ef96	9	* @attention
Kojto	112:6f327212ef96	10	*
Kojto	112:6f327212ef96	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	112:6f327212ef96	12	*
Kojto	112:6f327212ef96	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	112:6f327212ef96	14	* are permitted provided that the following conditions are met:
Kojto	112:6f327212ef96	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	112:6f327212ef96	16	* this list of conditions and the following disclaimer.
Kojto	112:6f327212ef96	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	112:6f327212ef96	18	* this list of conditions and the following disclaimer in the documentation
Kojto	112:6f327212ef96	19	* and/or other materials provided with the distribution.
Kojto	112:6f327212ef96	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	112:6f327212ef96	21	* may be used to endorse or promote products derived from this software
Kojto	112:6f327212ef96	22	* without specific prior written permission.
Kojto	112:6f327212ef96	23	*
Kojto	112:6f327212ef96	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	112:6f327212ef96	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	112:6f327212ef96	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	112:6f327212ef96	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	112:6f327212ef96	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	112:6f327212ef96	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	112:6f327212ef96	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	112:6f327212ef96	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	112:6f327212ef96	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	112:6f327212ef96	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	112:6f327212ef96	34	*
Kojto	112:6f327212ef96	35	******************************************************************************
Kojto	112:6f327212ef96	36	*/
Kojto	112:6f327212ef96	37
Kojto	112:6f327212ef96	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	112:6f327212ef96	39	#ifndef __STM32F4xx_HAL_RCC_EX_H
Kojto	112:6f327212ef96	40	#define __STM32F4xx_HAL_RCC_EX_H
Kojto	112:6f327212ef96	41
Kojto	112:6f327212ef96	42	#ifdef __cplusplus
Kojto	112:6f327212ef96	43	extern "C" {
Kojto	112:6f327212ef96	44	#endif
Kojto	112:6f327212ef96	45
Kojto	112:6f327212ef96	46	/* Includes ------------------------------------------------------------------*/
Kojto	112:6f327212ef96	47	#include "stm32f4xx_hal_def.h"
Kojto	112:6f327212ef96	48
Kojto	112:6f327212ef96	49	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	112:6f327212ef96	50	* @{
Kojto	112:6f327212ef96	51	*/
Kojto	112:6f327212ef96	52
Kojto	112:6f327212ef96	53	/** @addtogroup RCCEx
Kojto	112:6f327212ef96	54	* @{
Kojto	112:6f327212ef96	55	*/
Kojto	112:6f327212ef96	56
Kojto	112:6f327212ef96	57	/* Exported types ------------------------------------------------------------*/
Kojto	112:6f327212ef96	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	112:6f327212ef96	59	* @{
Kojto	112:6f327212ef96	60	*/
Kojto	112:6f327212ef96	61
Kojto	112:6f327212ef96	62	/**
Kojto	112:6f327212ef96	63	* @brief RCC PLL configuration structure definition
Kojto	112:6f327212ef96	64	*/
Kojto	112:6f327212ef96	65	typedef struct
Kojto	112:6f327212ef96	66	{
Kojto	112:6f327212ef96	67	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	112:6f327212ef96	68	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	112:6f327212ef96	69
Kojto	112:6f327212ef96	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto	112:6f327212ef96	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	112:6f327212ef96	72
Kojto	112:6f327212ef96	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto	112:6f327212ef96	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto	112:6f327212ef96	75
Kojto	112:6f327212ef96	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto	112:6f327212ef96	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	112:6f327212ef96	78
Kojto	112:6f327212ef96	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto	112:6f327212ef96	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto	112:6f327212ef96	81
Kojto	112:6f327212ef96	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto	112:6f327212ef96	83	This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
Kojto	112:6f327212ef96	84	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	112:6f327212ef96	85	defined(STM32F479xx)
Kojto	112:6f327212ef96	86	uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	112:6f327212ef96	87	This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx and STM32F479xx
Kojto	112:6f327212ef96	88	devices.
Kojto	112:6f327212ef96	89	This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto	112:6f327212ef96	90	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	91	}RCC_PLLInitTypeDef;
Kojto	112:6f327212ef96	92
Kojto	112:6f327212ef96	93	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	94	/**
Kojto	112:6f327212ef96	95	* @brief PLLI2S Clock structure definition
Kojto	112:6f327212ef96	96	*/
Kojto	112:6f327212ef96	97	typedef struct
Kojto	112:6f327212ef96	98	{
Kojto	112:6f327212ef96	99	uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto	112:6f327212ef96	100	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	112:6f327212ef96	101
Kojto	112:6f327212ef96	102	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	112:6f327212ef96	103	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	112:6f327212ef96	104
Kojto	112:6f327212ef96	105	uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto	112:6f327212ef96	106	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto	112:6f327212ef96	107
Kojto	112:6f327212ef96	108	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto	112:6f327212ef96	109	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	110	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	112:6f327212ef96	111
Kojto	112:6f327212ef96	112	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	112:6f327212ef96	113	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	114	This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto	112:6f327212ef96	115	}RCC_PLLI2SInitTypeDef;
Kojto	112:6f327212ef96	116
Kojto	112:6f327212ef96	117	/**
Kojto	112:6f327212ef96	118	* @brief PLLSAI Clock structure definition
Kojto	112:6f327212ef96	119	*/
Kojto	112:6f327212ef96	120	typedef struct
Kojto	112:6f327212ef96	121	{
Kojto	112:6f327212ef96	122	uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto	112:6f327212ef96	123	This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto	112:6f327212ef96	124
Kojto	112:6f327212ef96	125	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	112:6f327212ef96	126	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto	112:6f327212ef96	127
Kojto	112:6f327212ef96	128	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	112:6f327212ef96	129	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	112:6f327212ef96	130
Kojto	112:6f327212ef96	131	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto	112:6f327212ef96	132	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	133	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	112:6f327212ef96	134	}RCC_PLLSAIInitTypeDef;
Kojto	112:6f327212ef96	135	/**
Kojto	112:6f327212ef96	136	* @brief RCC extended clocks structure definition
Kojto	112:6f327212ef96	137	*/
Kojto	112:6f327212ef96	138	typedef struct
Kojto	112:6f327212ef96	139	{
Kojto	112:6f327212ef96	140	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	112:6f327212ef96	141	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	112:6f327212ef96	142
Kojto	112:6f327212ef96	143	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	112:6f327212ef96	144	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	145
Kojto	112:6f327212ef96	146	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	112:6f327212ef96	147	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	112:6f327212ef96	148
Kojto	112:6f327212ef96	149	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	112:6f327212ef96	150	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	112:6f327212ef96	151	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	112:6f327212ef96	152
Kojto	112:6f327212ef96	153	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	112:6f327212ef96	154	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	112:6f327212ef96	155	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	112:6f327212ef96	156
Kojto	112:6f327212ef96	157	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto	112:6f327212ef96	158	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	112:6f327212ef96	159
Kojto	112:6f327212ef96	160	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto	112:6f327212ef96	161	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	112:6f327212ef96	162
Kojto	112:6f327212ef96	163	uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto	112:6f327212ef96	164	This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto	112:6f327212ef96	165
Kojto	112:6f327212ef96	166	uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto	112:6f327212ef96	167	This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto	112:6f327212ef96	168
Kojto	112:6f327212ef96	169	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	112:6f327212ef96	170	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	112:6f327212ef96	171
Kojto	112:6f327212ef96	172	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	112:6f327212ef96	173	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	112:6f327212ef96	174
Kojto	112:6f327212ef96	175	uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto	112:6f327212ef96	176	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	112:6f327212ef96	177
Kojto	112:6f327212ef96	178	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	112:6f327212ef96	179	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	112:6f327212ef96	180
Kojto	112:6f327212ef96	181	uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto	112:6f327212ef96	182	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto	112:6f327212ef96	183
Kojto	112:6f327212ef96	184	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	112:6f327212ef96	185	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto	112:6f327212ef96	186
Kojto	112:6f327212ef96	187	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	112:6f327212ef96	188	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	112:6f327212ef96	189	}RCC_PeriphCLKInitTypeDef;
Kojto	112:6f327212ef96	190	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	191
Kojto	112:6f327212ef96	192	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	193	/**
Kojto	112:6f327212ef96	194	* @brief RCC extended clocks structure definition
Kojto	112:6f327212ef96	195	*/
Kojto	112:6f327212ef96	196	typedef struct
Kojto	112:6f327212ef96	197	{
Kojto	112:6f327212ef96	198	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	112:6f327212ef96	199	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	112:6f327212ef96	200
Kojto	112:6f327212ef96	201	uint32_t I2SClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	112:6f327212ef96	202	This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
Kojto	112:6f327212ef96	203
Kojto	112:6f327212ef96	204	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto	112:6f327212ef96	205	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	112:6f327212ef96	206
Kojto	112:6f327212ef96	207	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 Clock Source Selection.
Kojto	112:6f327212ef96	208	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto	112:6f327212ef96	209
Kojto	112:6f327212ef96	210	uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto	112:6f327212ef96	211	This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto	112:6f327212ef96	212	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto	112:6f327212ef96	213	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	112:6f327212ef96	214	}RCC_PeriphCLKInitTypeDef;
Kojto	112:6f327212ef96	215	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	216
Kojto	112:6f327212ef96	217	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	218
Kojto	112:6f327212ef96	219	/**
Kojto	112:6f327212ef96	220	* @brief PLLI2S Clock structure definition
Kojto	112:6f327212ef96	221	*/
Kojto	112:6f327212ef96	222	typedef struct
Kojto	112:6f327212ef96	223	{
Kojto	112:6f327212ef96	224	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	112:6f327212ef96	225	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	226	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	227
Kojto	112:6f327212ef96	228	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	112:6f327212ef96	229	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	230	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	231
Kojto	112:6f327212ef96	232	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto	112:6f327212ef96	233	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	234	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	112:6f327212ef96	235	}RCC_PLLI2SInitTypeDef;
Kojto	112:6f327212ef96	236
Kojto	112:6f327212ef96	237	/**
Kojto	112:6f327212ef96	238	* @brief PLLSAI Clock structure definition
Kojto	112:6f327212ef96	239	*/
Kojto	112:6f327212ef96	240	typedef struct
Kojto	112:6f327212ef96	241	{
Kojto	112:6f327212ef96	242	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	112:6f327212ef96	243	This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	244	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	112:6f327212ef96	245	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	246	uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS and SDIO clocks.
Kojto	112:6f327212ef96	247	This parameter is only available in STM32F469xx/STM32F479xx devices.
Kojto	112:6f327212ef96	248	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto	112:6f327212ef96	249	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	250
Kojto	112:6f327212ef96	251	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto	112:6f327212ef96	252	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	253	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	112:6f327212ef96	254
Kojto	112:6f327212ef96	255	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto	112:6f327212ef96	256	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	257	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto	112:6f327212ef96	258
Kojto	112:6f327212ef96	259	}RCC_PLLSAIInitTypeDef;
Kojto	112:6f327212ef96	260	/**
Kojto	112:6f327212ef96	261	* @brief RCC extended clocks structure definition
Kojto	112:6f327212ef96	262	*/
Kojto	112:6f327212ef96	263	typedef struct
Kojto	112:6f327212ef96	264	{
Kojto	112:6f327212ef96	265	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	112:6f327212ef96	266	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	112:6f327212ef96	267
Kojto	112:6f327212ef96	268	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	112:6f327212ef96	269	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	270
Kojto	112:6f327212ef96	271	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	112:6f327212ef96	272	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	112:6f327212ef96	273
Kojto	112:6f327212ef96	274	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	112:6f327212ef96	275	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	112:6f327212ef96	276	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	112:6f327212ef96	277
Kojto	112:6f327212ef96	278	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	112:6f327212ef96	279	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	112:6f327212ef96	280	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	112:6f327212ef96	281
Kojto	112:6f327212ef96	282	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto	112:6f327212ef96	283	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto	112:6f327212ef96	284
Kojto	112:6f327212ef96	285	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	112:6f327212ef96	286	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	112:6f327212ef96	287
Kojto	112:6f327212ef96	288	uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto	112:6f327212ef96	289	This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto	112:6f327212ef96	290	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	291	uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto	112:6f327212ef96	292	This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto	112:6f327212ef96	293
Kojto	112:6f327212ef96	294	uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto	112:6f327212ef96	295	This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto	112:6f327212ef96	296	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	297	}RCC_PeriphCLKInitTypeDef;
Kojto	112:6f327212ef96	298	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	299
Kojto	112:6f327212ef96	300	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	112:6f327212ef96	301	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	112:6f327212ef96	302	/**
Kojto	112:6f327212ef96	303	* @brief PLLI2S Clock structure definition
Kojto	112:6f327212ef96	304	*/
Kojto	112:6f327212ef96	305	typedef struct
Kojto	112:6f327212ef96	306	{
Kojto	112:6f327212ef96	307	#if defined(STM32F411xE)
Kojto	112:6f327212ef96	308	uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto	112:6f327212ef96	309	This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto	112:6f327212ef96	310	#endif /* STM32F411xE */
Kojto	112:6f327212ef96	311
Kojto	112:6f327212ef96	312	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	112:6f327212ef96	313	This parameter must be a number between Min_Data = 192 and Max_Data = 432
Kojto	112:6f327212ef96	314	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	315
Kojto	112:6f327212ef96	316	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	112:6f327212ef96	317	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	318	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	319
Kojto	112:6f327212ef96	320	}RCC_PLLI2SInitTypeDef;
Kojto	112:6f327212ef96	321
Kojto	112:6f327212ef96	322
Kojto	112:6f327212ef96	323	/**
Kojto	112:6f327212ef96	324	* @brief RCC extended clocks structure definition
Kojto	112:6f327212ef96	325	*/
Kojto	112:6f327212ef96	326	typedef struct
Kojto	112:6f327212ef96	327	{
Kojto	112:6f327212ef96	328	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	112:6f327212ef96	329	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	112:6f327212ef96	330
Kojto	112:6f327212ef96	331	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	112:6f327212ef96	332	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	112:6f327212ef96	333
Kojto	112:6f327212ef96	334	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto	112:6f327212ef96	335	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	112:6f327212ef96	336
Kojto	112:6f327212ef96	337	}RCC_PeriphCLKInitTypeDef;
Kojto	112:6f327212ef96	338	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	112:6f327212ef96	339	/**
Kojto	112:6f327212ef96	340	* @}
Kojto	112:6f327212ef96	341	*/
Kojto	112:6f327212ef96	342
Kojto	112:6f327212ef96	343	/* Exported constants --------------------------------------------------------*/
Kojto	112:6f327212ef96	344	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto	112:6f327212ef96	345	* @{
Kojto	112:6f327212ef96	346	*/
Kojto	112:6f327212ef96	347
Kojto	112:6f327212ef96	348	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
Kojto	112:6f327212ef96	349	* @{
Kojto	112:6f327212ef96	350	*/
Kojto	112:6f327212ef96	351	/------------------- Peripheral Clock source for STM32F410xx ----------------/
Kojto	112:6f327212ef96	352	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	353	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	354	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	355	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	356	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	357	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	358	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	359	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	360
Kojto	112:6f327212ef96	361	/------------------- Peripheral Clock source for STM32F446xx ----------------/
Kojto	112:6f327212ef96	362	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	363	#define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	364	#define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	365	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	366	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	367	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	368	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	369	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	370	#define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	371	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	372	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	373	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
Kojto	112:6f327212ef96	374	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
Kojto	112:6f327212ef96	375	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	376	/-----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	377
Kojto	112:6f327212ef96	378	/----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------/
Kojto	112:6f327212ef96	379	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	380	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	381	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	382	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	383	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	384	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	385	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	386	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	387	#define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000080)
Kojto	112:6f327212ef96	388	#define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	389	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	390	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	391
Kojto	112:6f327212ef96	392	/-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------/
Kojto	112:6f327212ef96	393	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	112:6f327212ef96	394	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	395	#define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	396	#define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	397	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	398	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	112:6f327212ef96	399	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	112:6f327212ef96	400	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
Kojto	112:6f327212ef96	401	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	112:6f327212ef96	402	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	403
Kojto	112:6f327212ef96	404	/-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------/
Kojto	112:6f327212ef96	405	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	112:6f327212ef96	406	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	112:6f327212ef96	407	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	408	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	409	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	410	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	112:6f327212ef96	411	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	412	/**
Kojto	112:6f327212ef96	413	* @}
Kojto	112:6f327212ef96	414	*/
Kojto	112:6f327212ef96	415	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	112:6f327212ef96	416	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	112:6f327212ef96	417	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	112:6f327212ef96	418	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	419	/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
Kojto	112:6f327212ef96	420	* @{
Kojto	112:6f327212ef96	421	*/
Kojto	112:6f327212ef96	422	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	423	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	424	/**
Kojto	112:6f327212ef96	425	* @}
Kojto	112:6f327212ef96	426	*/
Kojto	112:6f327212ef96	427	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	112:6f327212ef96	428	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	429
Kojto	112:6f327212ef96	430	/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
Kojto	112:6f327212ef96	431	* @{
Kojto	112:6f327212ef96	432	*/
Kojto	112:6f327212ef96	433	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	112:6f327212ef96	434	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	435	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	436	#define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
Kojto	112:6f327212ef96	437	#define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
Kojto	112:6f327212ef96	438	#define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
Kojto	112:6f327212ef96	439	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	440	/**
Kojto	112:6f327212ef96	441	* @}
Kojto	112:6f327212ef96	442	*/
Kojto	112:6f327212ef96	443
Kojto	112:6f327212ef96	444	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
Kojto	112:6f327212ef96	445	* @{
Kojto	112:6f327212ef96	446	*/
Kojto	112:6f327212ef96	447	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	448	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	449	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	450	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
Kojto	112:6f327212ef96	451	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	452	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	453	/**
Kojto	112:6f327212ef96	454	* @}
Kojto	112:6f327212ef96	455	*/
Kojto	112:6f327212ef96	456
Kojto	112:6f327212ef96	457	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
Kojto	112:6f327212ef96	458	* @{
Kojto	112:6f327212ef96	459	*/
Kojto	112:6f327212ef96	460	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	461	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	462	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	463	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
Kojto	112:6f327212ef96	464	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	465	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	466	/**
Kojto	112:6f327212ef96	467	* @}
Kojto	112:6f327212ef96	468	*/
Kojto	112:6f327212ef96	469
Kojto	112:6f327212ef96	470	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	471	/** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
Kojto	112:6f327212ef96	472	* @{
Kojto	112:6f327212ef96	473	*/
Kojto	112:6f327212ef96	474	#define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	475	#define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
Kojto	112:6f327212ef96	476	#define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
Kojto	112:6f327212ef96	477	/**
Kojto	112:6f327212ef96	478	* @}
Kojto	112:6f327212ef96	479	*/
Kojto	112:6f327212ef96	480
Kojto	112:6f327212ef96	481	/** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
Kojto	112:6f327212ef96	482	* @{
Kojto	112:6f327212ef96	483	*/
Kojto	112:6f327212ef96	484	#define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	485	#define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
Kojto	112:6f327212ef96	486	#define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
Kojto	112:6f327212ef96	487	/**
Kojto	112:6f327212ef96	488	* @}
Kojto	112:6f327212ef96	489	*/
Kojto	112:6f327212ef96	490	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	491
Kojto	112:6f327212ef96	492	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	493	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto	112:6f327212ef96	494	* @{
Kojto	112:6f327212ef96	495	*/
Kojto	112:6f327212ef96	496	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	497	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR_CK48MSEL)
Kojto	112:6f327212ef96	498	/**
Kojto	112:6f327212ef96	499	* @}
Kojto	112:6f327212ef96	500	*/
Kojto	112:6f327212ef96	501
Kojto	112:6f327212ef96	502	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	112:6f327212ef96	503	* @{
Kojto	112:6f327212ef96	504	*/
Kojto	112:6f327212ef96	505	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	506	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR_SDIOSEL)
Kojto	112:6f327212ef96	507	/**
Kojto	112:6f327212ef96	508	* @}
Kojto	112:6f327212ef96	509	*/
Kojto	112:6f327212ef96	510
Kojto	112:6f327212ef96	511	/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
Kojto	112:6f327212ef96	512	* @{
Kojto	112:6f327212ef96	513	*/
Kojto	112:6f327212ef96	514	#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	515	#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_DSISEL)
Kojto	112:6f327212ef96	516	/**
Kojto	112:6f327212ef96	517	* @}
Kojto	112:6f327212ef96	518	*/
Kojto	112:6f327212ef96	519	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	520
Kojto	112:6f327212ef96	521	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	522	/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto	112:6f327212ef96	523	* @{
Kojto	112:6f327212ef96	524	*/
Kojto	112:6f327212ef96	525	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	526	#define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto	112:6f327212ef96	527	#define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto	112:6f327212ef96	528	#define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto	112:6f327212ef96	529	/**
Kojto	112:6f327212ef96	530	* @}
Kojto	112:6f327212ef96	531	*/
Kojto	112:6f327212ef96	532
Kojto	112:6f327212ef96	533	/** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto	112:6f327212ef96	534	* @{
Kojto	112:6f327212ef96	535	*/
Kojto	112:6f327212ef96	536	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	537	#define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto	112:6f327212ef96	538	#define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto	112:6f327212ef96	539	#define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto	112:6f327212ef96	540	/**
Kojto	112:6f327212ef96	541	* @}
Kojto	112:6f327212ef96	542	*/
Kojto	112:6f327212ef96	543
Kojto	112:6f327212ef96	544	/** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto	112:6f327212ef96	545	* @{
Kojto	112:6f327212ef96	546	*/
Kojto	112:6f327212ef96	547	#define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	548	#define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto	112:6f327212ef96	549	#define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto	112:6f327212ef96	550	#define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto	112:6f327212ef96	551	/**
Kojto	112:6f327212ef96	552	* @}
Kojto	112:6f327212ef96	553	*/
Kojto	112:6f327212ef96	554
Kojto	112:6f327212ef96	555	/** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto	112:6f327212ef96	556	* @{
Kojto	112:6f327212ef96	557	*/
Kojto	112:6f327212ef96	558	#define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	559	#define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto	112:6f327212ef96	560	#define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto	112:6f327212ef96	561	#define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto	112:6f327212ef96	562	/**
Kojto	112:6f327212ef96	563	* @}
Kojto	112:6f327212ef96	564	*/
Kojto	112:6f327212ef96	565
Kojto	112:6f327212ef96	566	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	112:6f327212ef96	567	* @{
Kojto	112:6f327212ef96	568	*/
Kojto	112:6f327212ef96	569	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	570	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	112:6f327212ef96	571	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	112:6f327212ef96	572	/**
Kojto	112:6f327212ef96	573	* @}
Kojto	112:6f327212ef96	574	*/
Kojto	112:6f327212ef96	575
Kojto	112:6f327212ef96	576	/** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto	112:6f327212ef96	577	* @{
Kojto	112:6f327212ef96	578	*/
Kojto	112:6f327212ef96	579	#define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	580	#define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto	112:6f327212ef96	581	/**
Kojto	112:6f327212ef96	582	* @}
Kojto	112:6f327212ef96	583	*/
Kojto	112:6f327212ef96	584
Kojto	112:6f327212ef96	585	/** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto	112:6f327212ef96	586	* @{
Kojto	112:6f327212ef96	587	*/
Kojto	112:6f327212ef96	588	#define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	589	#define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto	112:6f327212ef96	590	/**
Kojto	112:6f327212ef96	591	* @}
Kojto	112:6f327212ef96	592	*/
Kojto	112:6f327212ef96	593
Kojto	112:6f327212ef96	594	/** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto	112:6f327212ef96	595	* @{
Kojto	112:6f327212ef96	596	*/
Kojto	112:6f327212ef96	597	#define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	598	#define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto	112:6f327212ef96	599	/**
Kojto	112:6f327212ef96	600	* @}
Kojto	112:6f327212ef96	601	*/
Kojto	112:6f327212ef96	602
Kojto	112:6f327212ef96	603	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto	112:6f327212ef96	604	* @{
Kojto	112:6f327212ef96	605	*/
Kojto	112:6f327212ef96	606	#define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	607	#define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto	112:6f327212ef96	608	/**
Kojto	112:6f327212ef96	609	* @}
Kojto	112:6f327212ef96	610	*/
Kojto	112:6f327212ef96	611
Kojto	112:6f327212ef96	612	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	613
Kojto	112:6f327212ef96	614	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	615
Kojto	112:6f327212ef96	616	/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
Kojto	112:6f327212ef96	617	* @{
Kojto	112:6f327212ef96	618	*/
Kojto	112:6f327212ef96	619	#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	620	#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
Kojto	112:6f327212ef96	621	#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
Kojto	112:6f327212ef96	622	/**
Kojto	112:6f327212ef96	623	* @}
Kojto	112:6f327212ef96	624	*/
Kojto	112:6f327212ef96	625
Kojto	112:6f327212ef96	626	/** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto	112:6f327212ef96	627	* @{
Kojto	112:6f327212ef96	628	*/
Kojto	112:6f327212ef96	629	#define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	630	#define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto	112:6f327212ef96	631	#define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto	112:6f327212ef96	632	/**
Kojto	112:6f327212ef96	633	* @}
Kojto	112:6f327212ef96	634	*/
Kojto	112:6f327212ef96	635
Kojto	112:6f327212ef96	636	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
Kojto	112:6f327212ef96	637	* @{
Kojto	112:6f327212ef96	638	*/
Kojto	112:6f327212ef96	639	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	640	#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
Kojto	112:6f327212ef96	641	#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	112:6f327212ef96	642	#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 \| RCC_DCKCFGR2_LPTIM1SEL_1)
Kojto	112:6f327212ef96	643	/**
Kojto	112:6f327212ef96	644	* @}
Kojto	112:6f327212ef96	645	*/
Kojto	112:6f327212ef96	646
Kojto	112:6f327212ef96	647	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto	112:6f327212ef96	648	* @{
Kojto	112:6f327212ef96	649	*/
Kojto	112:6f327212ef96	650	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto	112:6f327212ef96	651	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto	112:6f327212ef96	652	/**
Kojto	112:6f327212ef96	653	* @}
Kojto	112:6f327212ef96	654	*/
Kojto	112:6f327212ef96	655	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	656
Kojto	112:6f327212ef96	657	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	112:6f327212ef96	658	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\|\
Kojto	112:6f327212ef96	659	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	660	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto	112:6f327212ef96	661	* @{
Kojto	112:6f327212ef96	662	*/
Kojto	112:6f327212ef96	663	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto	112:6f327212ef96	664	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto	112:6f327212ef96	665	/**
Kojto	112:6f327212ef96	666	* @}
Kojto	112:6f327212ef96	667	*/
Kojto	112:6f327212ef96	668	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F401xC \|\| STM32F401xE \|\|\
Kojto	112:6f327212ef96	669	STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	670
Kojto	112:6f327212ef96	671	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	112:6f327212ef96	672	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	673	/** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
Kojto	112:6f327212ef96	674	* @{
Kojto	112:6f327212ef96	675	*/
Kojto	112:6f327212ef96	676	#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto	112:6f327212ef96	677	#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto	112:6f327212ef96	678	/**
Kojto	112:6f327212ef96	679	* @}
Kojto	112:6f327212ef96	680	*/
Kojto	112:6f327212ef96	681	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	682
Kojto	112:6f327212ef96	683
Kojto	112:6f327212ef96	684	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	112:6f327212ef96	685	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	112:6f327212ef96	686	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	112:6f327212ef96	687	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	688	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	112:6f327212ef96	689	* @{
Kojto	112:6f327212ef96	690	*/
Kojto	112:6f327212ef96	691	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	692	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
Kojto	112:6f327212ef96	693	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	112:6f327212ef96	694	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	112:6f327212ef96	695	/**
Kojto	112:6f327212ef96	696	* @}
Kojto	112:6f327212ef96	697	*/
Kojto	112:6f327212ef96	698	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	112:6f327212ef96	699	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	700
Kojto	112:6f327212ef96	701	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	702	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
Kojto	112:6f327212ef96	703	* @{
Kojto	112:6f327212ef96	704	*/
Kojto	112:6f327212ef96	705	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	706	#define RCC_MCO2SOURCE_I2SCLK RCC_CFGR_MCO2_0
Kojto	112:6f327212ef96	707	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
Kojto	112:6f327212ef96	708	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
Kojto	112:6f327212ef96	709	/**
Kojto	112:6f327212ef96	710	* @}
Kojto	112:6f327212ef96	711	*/
Kojto	112:6f327212ef96	712	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	713
Kojto	112:6f327212ef96	714	/**
Kojto	112:6f327212ef96	715	* @}
Kojto	112:6f327212ef96	716	*/
Kojto	112:6f327212ef96	717
Kojto	112:6f327212ef96	718	/* Exported macro ------------------------------------------------------------*/
Kojto	112:6f327212ef96	719	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	112:6f327212ef96	720	* @{
Kojto	112:6f327212ef96	721	*/
Kojto	112:6f327212ef96	722	/------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------/
Kojto	112:6f327212ef96	723	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	724	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	725	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	112:6f327212ef96	726	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	727	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	728	* using it.
Kojto	112:6f327212ef96	729	*/
Kojto	112:6f327212ef96	730	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	731	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	732	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	733	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	734	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	735	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	736	} while(0)
Kojto	112:6f327212ef96	737	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	738	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	739	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	740	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	741	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	742	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	743	} while(0)
Kojto	112:6f327212ef96	744	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	745	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	746	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	747	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	748	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	749	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	750	} while(0)
Kojto	112:6f327212ef96	751	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	752	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	753	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	754	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	755	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	756	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	757	} while(0)
Kojto	112:6f327212ef96	758	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	759	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	760	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	761	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	762	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	763	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	764	} while(0)
Kojto	112:6f327212ef96	765	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	766	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	767	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	112:6f327212ef96	768	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	769	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	112:6f327212ef96	770	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	771	} while(0)
Kojto	112:6f327212ef96	772	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	773	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	774	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	112:6f327212ef96	775	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	776	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	112:6f327212ef96	777	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	778	} while(0)
Kojto	112:6f327212ef96	779	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	780	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	781	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	112:6f327212ef96	782	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	783	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	112:6f327212ef96	784	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	785	} while(0)
Kojto	112:6f327212ef96	786	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	787	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	788	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	112:6f327212ef96	789	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	790	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	112:6f327212ef96	791	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	792	} while(0)
Kojto	112:6f327212ef96	793	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	794	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	795	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	112:6f327212ef96	796	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	797	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	112:6f327212ef96	798	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	799	} while(0)
Kojto	112:6f327212ef96	800	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	801	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	802	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	112:6f327212ef96	803	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	804	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	112:6f327212ef96	805	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	806	} while(0)
Kojto	112:6f327212ef96	807	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	808	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	809	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	112:6f327212ef96	810	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	811	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	112:6f327212ef96	812	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	813	} while(0)
Kojto	112:6f327212ef96	814	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	815	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	816	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	112:6f327212ef96	817	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	818	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	112:6f327212ef96	819	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	820	} while(0)
Kojto	112:6f327212ef96	821	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	822	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	823	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	112:6f327212ef96	824	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	825	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	112:6f327212ef96	826	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	827	} while(0)
Kojto	112:6f327212ef96	828	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	829	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	830	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	112:6f327212ef96	831	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	832	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	112:6f327212ef96	833	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	834	} while(0)
Kojto	112:6f327212ef96	835	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	836	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	837	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	112:6f327212ef96	838	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	839	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	112:6f327212ef96	840	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	841	} while(0)
Kojto	112:6f327212ef96	842	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	843	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	844	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	112:6f327212ef96	845	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	846	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	112:6f327212ef96	847	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	848	} while(0)
Kojto	112:6f327212ef96	849	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	112:6f327212ef96	850	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	112:6f327212ef96	851	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	112:6f327212ef96	852	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	112:6f327212ef96	853	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	112:6f327212ef96	854	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	112:6f327212ef96	855	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	112:6f327212ef96	856	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	112:6f327212ef96	857	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	112:6f327212ef96	858	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	112:6f327212ef96	859	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	112:6f327212ef96	860	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	112:6f327212ef96	861	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	112:6f327212ef96	862	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	112:6f327212ef96	863	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	112:6f327212ef96	864	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	112:6f327212ef96	865	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	112:6f327212ef96	866
Kojto	112:6f327212ef96	867	/**
Kojto	112:6f327212ef96	868	* @brief Enable ETHERNET clock.
Kojto	112:6f327212ef96	869	*/
Kojto	112:6f327212ef96	870	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	871	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	112:6f327212ef96	872	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	112:6f327212ef96	873	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	112:6f327212ef96	874	} while(0)
Kojto	112:6f327212ef96	875	/**
Kojto	112:6f327212ef96	876	* @brief Disable ETHERNET clock.
Kojto	112:6f327212ef96	877	*/
Kojto	112:6f327212ef96	878	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	112:6f327212ef96	879	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	112:6f327212ef96	880	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	112:6f327212ef96	881	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	112:6f327212ef96	882	} while(0)
Kojto	112:6f327212ef96	883	/**
Kojto	112:6f327212ef96	884	* @}
Kojto	112:6f327212ef96	885	*/
Kojto	112:6f327212ef96	886
Kojto	112:6f327212ef96	887	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	888	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	112:6f327212ef96	889	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	890	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	891	* using it.
Kojto	112:6f327212ef96	892	*/
Kojto	112:6f327212ef96	893	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	894	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	895	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	112:6f327212ef96	896	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	897	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	112:6f327212ef96	898	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	899	} while(0)
Kojto	112:6f327212ef96	900	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	112:6f327212ef96	901
Kojto	112:6f327212ef96	902	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	903	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	904	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	905	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	112:6f327212ef96	906	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	907	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	112:6f327212ef96	908	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	909	} while(0)
Kojto	112:6f327212ef96	910	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	911	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	912	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	112:6f327212ef96	913	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	914	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	112:6f327212ef96	915	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	916	} while(0)
Kojto	112:6f327212ef96	917
Kojto	112:6f327212ef96	918	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	112:6f327212ef96	919	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	112:6f327212ef96	920	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	921	/**
Kojto	112:6f327212ef96	922	* @}
Kojto	112:6f327212ef96	923	*/
Kojto	112:6f327212ef96	924
Kojto	112:6f327212ef96	925	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	926	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	112:6f327212ef96	927	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	928	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	929	* using it.
Kojto	112:6f327212ef96	930	* @{
Kojto	112:6f327212ef96	931	*/
Kojto	112:6f327212ef96	932	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	933	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	112:6f327212ef96	934	}while(0)
Kojto	112:6f327212ef96	935
Kojto	112:6f327212ef96	936	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	937	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	112:6f327212ef96	938	}while(0)
Kojto	112:6f327212ef96	939
Kojto	112:6f327212ef96	940	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	941	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	942	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	112:6f327212ef96	943	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	944	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	112:6f327212ef96	945	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	946	} while(0)
Kojto	112:6f327212ef96	947	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	112:6f327212ef96	948	/**
Kojto	112:6f327212ef96	949	* @}
Kojto	112:6f327212ef96	950	*/
Kojto	112:6f327212ef96	951
Kojto	112:6f327212ef96	952	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	953	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	112:6f327212ef96	954	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	955	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	956	* using it.
Kojto	112:6f327212ef96	957	*/
Kojto	112:6f327212ef96	958	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	959	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	960	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	112:6f327212ef96	961	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	962	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	112:6f327212ef96	963	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	964	} while(0)
Kojto	112:6f327212ef96	965	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	112:6f327212ef96	966	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	967	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	968	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	969	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	112:6f327212ef96	970	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	971	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	112:6f327212ef96	972	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	973	} while(0)
Kojto	112:6f327212ef96	974	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	112:6f327212ef96	975	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	976	/**
Kojto	112:6f327212ef96	977	* @}
Kojto	112:6f327212ef96	978	*/
Kojto	112:6f327212ef96	979
Kojto	112:6f327212ef96	980	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	981	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	982	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	983	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	984	* using it.
Kojto	112:6f327212ef96	985	*/
Kojto	112:6f327212ef96	986	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	987	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	988	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	989	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	990	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	991	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	992	} while(0)
Kojto	112:6f327212ef96	993	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	994	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	995	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	112:6f327212ef96	996	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	997	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	112:6f327212ef96	998	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	999	} while(0)
Kojto	112:6f327212ef96	1000	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1001	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1002	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	112:6f327212ef96	1003	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1004	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	112:6f327212ef96	1005	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1006	} while(0)
Kojto	112:6f327212ef96	1007	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1008	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1009	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	112:6f327212ef96	1010	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1011	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	112:6f327212ef96	1012	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1013	} while(0)
Kojto	112:6f327212ef96	1014	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1015	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1016	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	1017	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1018	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	1019	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1020	} while(0)
Kojto	112:6f327212ef96	1021	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1022	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1023	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	1024	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1025	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	1026	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1027	} while(0)
Kojto	112:6f327212ef96	1028	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1029	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1030	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	112:6f327212ef96	1031	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1032	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	112:6f327212ef96	1033	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1034	} while(0)
Kojto	112:6f327212ef96	1035	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1036	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	112:6f327212ef96	1038	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	112:6f327212ef96	1040	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1041	} while(0)
Kojto	112:6f327212ef96	1042	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1043	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1044	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	112:6f327212ef96	1045	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1046	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	112:6f327212ef96	1047	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1048	} while(0)
Kojto	112:6f327212ef96	1049	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1050	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1051	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	112:6f327212ef96	1052	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1053	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	112:6f327212ef96	1054	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1055	} while(0)
Kojto	112:6f327212ef96	1056	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1057	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1058	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	112:6f327212ef96	1059	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1060	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	112:6f327212ef96	1061	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1062	} while(0)
Kojto	112:6f327212ef96	1063	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1064	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1065	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	1066	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1067	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	1068	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1069	} while(0)
Kojto	112:6f327212ef96	1070	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1071	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1072	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	112:6f327212ef96	1073	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1074	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	112:6f327212ef96	1075	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1076	} while(0)
Kojto	112:6f327212ef96	1077	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1078	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1079	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	112:6f327212ef96	1080	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1081	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	112:6f327212ef96	1082	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1083	} while(0)
Kojto	112:6f327212ef96	1084	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1085	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1086	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	1087	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1088	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	1089	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1090	} while(0)
Kojto	112:6f327212ef96	1091	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1092	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1093	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	1094	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1095	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	1096	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1097	} while(0)
Kojto	112:6f327212ef96	1098	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1099	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1100	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	1101	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1102	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	1103	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1104	} while(0)
Kojto	112:6f327212ef96	1105	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1106	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1107	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	1108	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1109	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	1110	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1111	} while(0)
Kojto	112:6f327212ef96	1112	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1113	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1114	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	1115	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1116	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	1117	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1118	} while(0)
Kojto	112:6f327212ef96	1119	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	1120	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	1121	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	1122	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	112:6f327212ef96	1123	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	112:6f327212ef96	1124	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	112:6f327212ef96	1125	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	112:6f327212ef96	1126	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	112:6f327212ef96	1127	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	112:6f327212ef96	1128	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	112:6f327212ef96	1129	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	112:6f327212ef96	1130	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	112:6f327212ef96	1131	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	112:6f327212ef96	1132	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	112:6f327212ef96	1133	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	112:6f327212ef96	1134	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	112:6f327212ef96	1135	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	112:6f327212ef96	1136	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	112:6f327212ef96	1137	/**
Kojto	112:6f327212ef96	1138	* @}
Kojto	112:6f327212ef96	1139	*/
Kojto	112:6f327212ef96	1140
Kojto	112:6f327212ef96	1141	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	1142	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	1143	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	1144	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	1145	* using it.
Kojto	112:6f327212ef96	1146	*/
Kojto	112:6f327212ef96	1147	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1148	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1149	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	112:6f327212ef96	1150	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1151	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	112:6f327212ef96	1152	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1153	} while(0)
Kojto	112:6f327212ef96	1154	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1155	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1156	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	112:6f327212ef96	1157	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1158	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	112:6f327212ef96	1159	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1160	} while(0)
Kojto	112:6f327212ef96	1161	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1162	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1163	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	112:6f327212ef96	1164	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1165	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	112:6f327212ef96	1166	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1167	} while(0)
Kojto	112:6f327212ef96	1168	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1169	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1170	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	112:6f327212ef96	1171	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1172	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	112:6f327212ef96	1173	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1174	} while(0)
Kojto	112:6f327212ef96	1175	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1176	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1177	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	112:6f327212ef96	1178	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1179	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	112:6f327212ef96	1180	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1181	} while(0)
Kojto	112:6f327212ef96	1182	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1183	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1184	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	112:6f327212ef96	1185	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1186	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	112:6f327212ef96	1187	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1188	} while(0)
Kojto	112:6f327212ef96	1189	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1190	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1191	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	1192	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1193	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	1194	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1195	} while(0)
Kojto	112:6f327212ef96	1196	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1197	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1198	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	1199	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1200	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	1201	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1202	} while(0)
Kojto	112:6f327212ef96	1203	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1204	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1205	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	1206	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1207	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	1208	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1209	} while(0)
Kojto	112:6f327212ef96	1210	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	112:6f327212ef96	1211	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	112:6f327212ef96	1212	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	1213	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	112:6f327212ef96	1214	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	112:6f327212ef96	1215	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	112:6f327212ef96	1216	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	112:6f327212ef96	1217	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	112:6f327212ef96	1218	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	112:6f327212ef96	1219
Kojto	112:6f327212ef96	1220	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1221	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1222	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1223	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	112:6f327212ef96	1224	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1225	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	112:6f327212ef96	1226	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1227	} while(0)
Kojto	112:6f327212ef96	1228
Kojto	112:6f327212ef96	1229	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	112:6f327212ef96	1230	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1231
Kojto	112:6f327212ef96	1232	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1233	#define __HAL_RCC_DSI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1234	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1235	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	112:6f327212ef96	1236	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1237	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto	112:6f327212ef96	1238	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1239	} while(0)
Kojto	112:6f327212ef96	1240
Kojto	112:6f327212ef96	1241	#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
Kojto	112:6f327212ef96	1242	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1243	/**
Kojto	112:6f327212ef96	1244	* @}
Kojto	112:6f327212ef96	1245	*/
Kojto	112:6f327212ef96	1246
Kojto	112:6f327212ef96	1247	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	1248	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	1249	*/
Kojto	112:6f327212ef96	1250	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	1251	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	1252	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	112:6f327212ef96	1253	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	112:6f327212ef96	1254	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	112:6f327212ef96	1255	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	112:6f327212ef96	1256	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	112:6f327212ef96	1257	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	112:6f327212ef96	1258	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	112:6f327212ef96	1259	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	112:6f327212ef96	1260	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	1261
Kojto	112:6f327212ef96	1262	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	1263	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	1264	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	112:6f327212ef96	1265	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	112:6f327212ef96	1266	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	112:6f327212ef96	1267	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	112:6f327212ef96	1268	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	112:6f327212ef96	1269	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	112:6f327212ef96	1270	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	112:6f327212ef96	1271	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	112:6f327212ef96	1272	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	1273	/**
Kojto	112:6f327212ef96	1274	* @}
Kojto	112:6f327212ef96	1275	*/
Kojto	112:6f327212ef96	1276
Kojto	112:6f327212ef96	1277	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	112:6f327212ef96	1278	* @brief Force or release AHB2 peripheral reset.
Kojto	112:6f327212ef96	1279	* @{
Kojto	112:6f327212ef96	1280	*/
Kojto	112:6f327212ef96	1281	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	1282	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	1283	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	112:6f327212ef96	1284	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	112:6f327212ef96	1285
Kojto	112:6f327212ef96	1286	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	112:6f327212ef96	1287	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	1288	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	112:6f327212ef96	1289	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	112:6f327212ef96	1290
Kojto	112:6f327212ef96	1291	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1292	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	112:6f327212ef96	1293	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	112:6f327212ef96	1294
Kojto	112:6f327212ef96	1295	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	112:6f327212ef96	1296	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	112:6f327212ef96	1297	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1298	/**
Kojto	112:6f327212ef96	1299	* @}
Kojto	112:6f327212ef96	1300	*/
Kojto	112:6f327212ef96	1301
Kojto	112:6f327212ef96	1302	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	112:6f327212ef96	1303	* @brief Force or release AHB3 peripheral reset.
Kojto	112:6f327212ef96	1304	* @{
Kojto	112:6f327212ef96	1305	*/
Kojto	112:6f327212ef96	1306	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	1307	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	112:6f327212ef96	1308	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	112:6f327212ef96	1309	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	112:6f327212ef96	1310
Kojto	112:6f327212ef96	1311	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1312	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	112:6f327212ef96	1313	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	112:6f327212ef96	1314	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1315	/**
Kojto	112:6f327212ef96	1316	* @}
Kojto	112:6f327212ef96	1317	*/
Kojto	112:6f327212ef96	1318
Kojto	112:6f327212ef96	1319	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	1320	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	1321	*/
Kojto	112:6f327212ef96	1322	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	1323	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	1324	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	112:6f327212ef96	1325	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	112:6f327212ef96	1326	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	112:6f327212ef96	1327	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	1328	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	112:6f327212ef96	1329	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	112:6f327212ef96	1330	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	112:6f327212ef96	1331	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	112:6f327212ef96	1332	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	1333	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	112:6f327212ef96	1334	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	112:6f327212ef96	1335	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	1336	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	1337	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	1338	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	1339	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	1340
Kojto	112:6f327212ef96	1341	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	1342	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	1343	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	1344	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	1345	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	1346	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	1347	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	1348	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	112:6f327212ef96	1349	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	112:6f327212ef96	1350	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	112:6f327212ef96	1351	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	1352	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	112:6f327212ef96	1353	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	112:6f327212ef96	1354	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	112:6f327212ef96	1355	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	112:6f327212ef96	1356	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	1357	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	112:6f327212ef96	1358	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	112:6f327212ef96	1359	/**
Kojto	112:6f327212ef96	1360	* @}
Kojto	112:6f327212ef96	1361	*/
Kojto	112:6f327212ef96	1362
Kojto	112:6f327212ef96	1363	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	1364	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	1365	*/
Kojto	112:6f327212ef96	1366	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	112:6f327212ef96	1367	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	112:6f327212ef96	1368	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	112:6f327212ef96	1369	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	112:6f327212ef96	1370	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	1371	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	1372	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	1373
Kojto	112:6f327212ef96	1374	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	1375	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	1376	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	1377	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	112:6f327212ef96	1378	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	112:6f327212ef96	1379	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	112:6f327212ef96	1380	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	112:6f327212ef96	1381
Kojto	112:6f327212ef96	1382	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1383	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	112:6f327212ef96	1384	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	112:6f327212ef96	1385	#endif /* STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1386
Kojto	112:6f327212ef96	1387	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1388	#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DSIRST))
Kojto	112:6f327212ef96	1389	#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
Kojto	112:6f327212ef96	1390	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1391	/**
Kojto	112:6f327212ef96	1392	* @}
Kojto	112:6f327212ef96	1393	*/
Kojto	112:6f327212ef96	1394
Kojto	112:6f327212ef96	1395	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	1396	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	1397	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	1398	* power consumption.
Kojto	112:6f327212ef96	1399	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	1400	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	1401	*/
Kojto	112:6f327212ef96	1402	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	1403	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	1404	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	112:6f327212ef96	1405	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	112:6f327212ef96	1406	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	112:6f327212ef96	1407	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	112:6f327212ef96	1408	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	112:6f327212ef96	1409	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	112:6f327212ef96	1410	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	112:6f327212ef96	1411	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	112:6f327212ef96	1412	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	112:6f327212ef96	1413	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	112:6f327212ef96	1414	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	112:6f327212ef96	1415	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	112:6f327212ef96	1416	#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto	112:6f327212ef96	1417	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	112:6f327212ef96	1418	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	1419	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	1420	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	1421	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	1422
Kojto	112:6f327212ef96	1423	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	1424	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	1425	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	112:6f327212ef96	1426	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	112:6f327212ef96	1427	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	112:6f327212ef96	1428	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	112:6f327212ef96	1429	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	112:6f327212ef96	1430	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	112:6f327212ef96	1431	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	112:6f327212ef96	1432	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	112:6f327212ef96	1433	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	112:6f327212ef96	1434	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	112:6f327212ef96	1435	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	112:6f327212ef96	1436	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	112:6f327212ef96	1437	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	112:6f327212ef96	1438	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	1439	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	1440	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	1441	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	1442	/**
Kojto	112:6f327212ef96	1443	* @}
Kojto	112:6f327212ef96	1444	*/
Kojto	112:6f327212ef96	1445
Kojto	112:6f327212ef96	1446	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	1447	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	1448	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	1449	* power consumption.
Kojto	112:6f327212ef96	1450	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	1451	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	1452	* @{
Kojto	112:6f327212ef96	1453	*/
Kojto	112:6f327212ef96	1454	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	1455	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	1456
Kojto	112:6f327212ef96	1457	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	112:6f327212ef96	1458	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	112:6f327212ef96	1459
Kojto	112:6f327212ef96	1460	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	112:6f327212ef96	1461	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	112:6f327212ef96	1462
Kojto	112:6f327212ef96	1463	#if defined(STM32F437xx)\|\| defined(STM32F439xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1464	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	112:6f327212ef96	1465	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	112:6f327212ef96	1466
Kojto	112:6f327212ef96	1467	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	112:6f327212ef96	1468	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	112:6f327212ef96	1469	#endif /* STM32F437xx \|\| STM32F439xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1470	/**
Kojto	112:6f327212ef96	1471	* @}
Kojto	112:6f327212ef96	1472	*/
Kojto	112:6f327212ef96	1473
Kojto	112:6f327212ef96	1474	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	1475	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	1476	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	1477	* power consumption.
Kojto	112:6f327212ef96	1478	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	1479	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	1480	*/
Kojto	112:6f327212ef96	1481	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	112:6f327212ef96	1482	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	112:6f327212ef96	1483
Kojto	112:6f327212ef96	1484	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1485	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	112:6f327212ef96	1486	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	112:6f327212ef96	1487	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1488	/**
Kojto	112:6f327212ef96	1489	* @}
Kojto	112:6f327212ef96	1490	*/
Kojto	112:6f327212ef96	1491
Kojto	112:6f327212ef96	1492	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	1493	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	1494	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	1495	* power consumption.
Kojto	112:6f327212ef96	1496	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	1497	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	1498	*/
Kojto	112:6f327212ef96	1499	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	1500	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	1501	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	112:6f327212ef96	1502	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	112:6f327212ef96	1503	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	112:6f327212ef96	1504	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	1505	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	112:6f327212ef96	1506	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	112:6f327212ef96	1507	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	112:6f327212ef96	1508	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	112:6f327212ef96	1509	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	1510	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	112:6f327212ef96	1511	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	112:6f327212ef96	1512	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	1513	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	1514	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	1515	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	1516	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	1517
Kojto	112:6f327212ef96	1518	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	1519	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	1520	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	1521	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	1522	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	1523	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	1524	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	1525	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	112:6f327212ef96	1526	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	112:6f327212ef96	1527	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	112:6f327212ef96	1528	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	1529	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	112:6f327212ef96	1530	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	112:6f327212ef96	1531	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	112:6f327212ef96	1532	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	112:6f327212ef96	1533	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	1534	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	112:6f327212ef96	1535	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	112:6f327212ef96	1536	/**
Kojto	112:6f327212ef96	1537	* @}
Kojto	112:6f327212ef96	1538	*/
Kojto	112:6f327212ef96	1539
Kojto	112:6f327212ef96	1540	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	1541	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	1542	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	1543	* power consumption.
Kojto	112:6f327212ef96	1544	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	1545	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	1546	*/
Kojto	112:6f327212ef96	1547	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	112:6f327212ef96	1548	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	112:6f327212ef96	1549	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	112:6f327212ef96	1550	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	112:6f327212ef96	1551	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	112:6f327212ef96	1552	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	112:6f327212ef96	1553	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	1554	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	1555	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	1556
Kojto	112:6f327212ef96	1557	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	1558	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	1559	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	1560	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	112:6f327212ef96	1561	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	112:6f327212ef96	1562	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	112:6f327212ef96	1563	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	112:6f327212ef96	1564	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	112:6f327212ef96	1565	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	112:6f327212ef96	1566
Kojto	112:6f327212ef96	1567	#if defined(STM32F429xx)\|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1568	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
Kojto	112:6f327212ef96	1569
Kojto	112:6f327212ef96	1570	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	112:6f327212ef96	1571	#endif /* STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1572
Kojto	112:6f327212ef96	1573	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	1574	#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_DSILPEN))
Kojto	112:6f327212ef96	1575	#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
Kojto	112:6f327212ef96	1576	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1577	/**
Kojto	112:6f327212ef96	1578	* @}
Kojto	112:6f327212ef96	1579	*/
Kojto	112:6f327212ef96	1580	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx\|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	1581	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	1582
Kojto	112:6f327212ef96	1583	/----------------------------------- STM32F40xxx/STM32F41xxx-----------------/
Kojto	112:6f327212ef96	1584	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	1585	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	1586	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	112:6f327212ef96	1587	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	1588	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	1589	* using it.
Kojto	112:6f327212ef96	1590	*/
Kojto	112:6f327212ef96	1591	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1592	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1593	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	1594	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1595	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	1596	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1597	} while(0)
Kojto	112:6f327212ef96	1598	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1599	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1600	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	1601	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1602	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	1603	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1604	} while(0)
Kojto	112:6f327212ef96	1605	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1606	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1607	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	1608	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1609	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	1610	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1611	} while(0)
Kojto	112:6f327212ef96	1612	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1613	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1614	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	1615	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1616	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	1617	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1618	} while(0)
Kojto	112:6f327212ef96	1619	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1620	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1621	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	1622	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1623	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	1624	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1625	} while(0)
Kojto	112:6f327212ef96	1626	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1627	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1628	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	112:6f327212ef96	1629	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1630	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	112:6f327212ef96	1631	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1632	} while(0)
Kojto	112:6f327212ef96	1633	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1634	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1635	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	112:6f327212ef96	1636	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1637	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	112:6f327212ef96	1638	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1639	} while(0)
Kojto	112:6f327212ef96	1640	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1641	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1642	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	112:6f327212ef96	1643	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1644	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	112:6f327212ef96	1645	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1646	} while(0)
Kojto	112:6f327212ef96	1647	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1648	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1649	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	112:6f327212ef96	1650	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1651	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	112:6f327212ef96	1652	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1653	} while(0)
Kojto	112:6f327212ef96	1654	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1655	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1656	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	112:6f327212ef96	1657	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1658	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	112:6f327212ef96	1659	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1660	} while(0)
Kojto	112:6f327212ef96	1661	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	112:6f327212ef96	1662	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	112:6f327212ef96	1663	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	112:6f327212ef96	1664	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	112:6f327212ef96	1665	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	112:6f327212ef96	1666	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	112:6f327212ef96	1667	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	112:6f327212ef96	1668	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	112:6f327212ef96	1669	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	112:6f327212ef96	1670	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	112:6f327212ef96	1671	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	1672	/**
Kojto	112:6f327212ef96	1673	* @brief Enable ETHERNET clock.
Kojto	112:6f327212ef96	1674	*/
Kojto	112:6f327212ef96	1675	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1676	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1677	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	112:6f327212ef96	1678	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1679	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	112:6f327212ef96	1680	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1681	} while(0)
Kojto	112:6f327212ef96	1682	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1683	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1684	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	112:6f327212ef96	1685	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1686	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	112:6f327212ef96	1687	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1688	} while(0)
Kojto	112:6f327212ef96	1689	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1690	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1691	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	112:6f327212ef96	1692	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1693	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	112:6f327212ef96	1694	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1695	} while(0)
Kojto	112:6f327212ef96	1696	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1697	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1698	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	112:6f327212ef96	1699	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1700	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	112:6f327212ef96	1701	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1702	} while(0)
Kojto	112:6f327212ef96	1703	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1704	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	112:6f327212ef96	1705	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	112:6f327212ef96	1706	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	112:6f327212ef96	1707	} while(0)
Kojto	112:6f327212ef96	1708
Kojto	112:6f327212ef96	1709	/**
Kojto	112:6f327212ef96	1710	* @brief Disable ETHERNET clock.
Kojto	112:6f327212ef96	1711	*/
Kojto	112:6f327212ef96	1712	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	112:6f327212ef96	1713	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	112:6f327212ef96	1714	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	112:6f327212ef96	1715	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	112:6f327212ef96	1716	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	112:6f327212ef96	1717	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	112:6f327212ef96	1718	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	112:6f327212ef96	1719	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	112:6f327212ef96	1720	} while(0)
Kojto	112:6f327212ef96	1721	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	1722	/**
Kojto	112:6f327212ef96	1723	* @}
Kojto	112:6f327212ef96	1724	*/
Kojto	112:6f327212ef96	1725
Kojto	112:6f327212ef96	1726	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	1727	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	112:6f327212ef96	1728	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	1729	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	1730	* using it.
Kojto	112:6f327212ef96	1731	*/
Kojto	112:6f327212ef96	1732	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	1733	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	112:6f327212ef96	1734	}while(0)
Kojto	112:6f327212ef96	1735
Kojto	112:6f327212ef96	1736	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	1737	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	112:6f327212ef96	1738	}while(0)
Kojto	112:6f327212ef96	1739
Kojto	112:6f327212ef96	1740	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1741	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1742	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	112:6f327212ef96	1743	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1744	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	112:6f327212ef96	1745	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1746	} while(0)
Kojto	112:6f327212ef96	1747	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	112:6f327212ef96	1748
Kojto	112:6f327212ef96	1749	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	1750	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1751	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1752	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	112:6f327212ef96	1753	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1754	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	112:6f327212ef96	1755	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1756	} while(0)
Kojto	112:6f327212ef96	1757	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	112:6f327212ef96	1758	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	1759
Kojto	112:6f327212ef96	1760	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	1761	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1762	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1763	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	112:6f327212ef96	1764	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1765	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	112:6f327212ef96	1766	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1767	} while(0)
Kojto	112:6f327212ef96	1768	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1769	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1770	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	112:6f327212ef96	1771	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1772	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	112:6f327212ef96	1773	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1774	} while(0)
Kojto	112:6f327212ef96	1775	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	112:6f327212ef96	1776	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	112:6f327212ef96	1777	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	1778	/**
Kojto	112:6f327212ef96	1779	* @}
Kojto	112:6f327212ef96	1780	*/
Kojto	112:6f327212ef96	1781
Kojto	112:6f327212ef96	1782	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	1783	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	112:6f327212ef96	1784	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	1785	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	1786	* using it.
Kojto	112:6f327212ef96	1787	*/
Kojto	112:6f327212ef96	1788	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1789	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1790	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	112:6f327212ef96	1791	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1792	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto	112:6f327212ef96	1793	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1794	} while(0)
Kojto	112:6f327212ef96	1795	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto	112:6f327212ef96	1796	/**
Kojto	112:6f327212ef96	1797	* @}
Kojto	112:6f327212ef96	1798	*/
Kojto	112:6f327212ef96	1799
Kojto	112:6f327212ef96	1800	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	1801	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	1802	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	1803	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	1804	* using it.
Kojto	112:6f327212ef96	1805	*/
Kojto	112:6f327212ef96	1806	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1807	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	1809	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	1811	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1812	} while(0)
Kojto	112:6f327212ef96	1813	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1814	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1815	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	112:6f327212ef96	1816	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1817	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	112:6f327212ef96	1818	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1819	} while(0)
Kojto	112:6f327212ef96	1820	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1821	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1822	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	112:6f327212ef96	1823	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1824	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	112:6f327212ef96	1825	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1826	} while(0)
Kojto	112:6f327212ef96	1827	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1828	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1829	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	112:6f327212ef96	1830	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1831	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	112:6f327212ef96	1832	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1833	} while(0)
Kojto	112:6f327212ef96	1834	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1835	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1836	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	1837	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1838	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	1839	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1840	} while(0)
Kojto	112:6f327212ef96	1841	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1842	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1843	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	112:6f327212ef96	1844	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1845	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	112:6f327212ef96	1846	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1847	} while(0)
Kojto	112:6f327212ef96	1848	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1849	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1850	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	112:6f327212ef96	1851	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1852	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	112:6f327212ef96	1853	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1854	} while(0)
Kojto	112:6f327212ef96	1855	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1856	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1857	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	112:6f327212ef96	1858	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1859	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	112:6f327212ef96	1860	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1861	} while(0)
Kojto	112:6f327212ef96	1862	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1863	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1864	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	112:6f327212ef96	1865	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1866	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	112:6f327212ef96	1867	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1868	} while(0)
Kojto	112:6f327212ef96	1869	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1870	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1871	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	112:6f327212ef96	1872	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1873	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	112:6f327212ef96	1874	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1875	} while(0)
Kojto	112:6f327212ef96	1876	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1877	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1878	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	1879	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1880	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	1881	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1882	} while(0)
Kojto	112:6f327212ef96	1883	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1884	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1885	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	1886	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1887	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	1888	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1889	} while(0)
Kojto	112:6f327212ef96	1890	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1891	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1892	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	1893	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1894	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	1895	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1896	} while(0)
Kojto	112:6f327212ef96	1897	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1898	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1899	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	1900	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1901	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	1902	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1903	} while(0)
Kojto	112:6f327212ef96	1904	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1905	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1906	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	1907	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1908	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	1909	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1910	} while(0)
Kojto	112:6f327212ef96	1911	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1912	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1913	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	1914	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1915	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	1916	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1917	} while(0)
Kojto	112:6f327212ef96	1918	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	1919	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	1920	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	1921	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	112:6f327212ef96	1922	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	112:6f327212ef96	1923	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	112:6f327212ef96	1924	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	112:6f327212ef96	1925	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	112:6f327212ef96	1926	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	112:6f327212ef96	1927	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	112:6f327212ef96	1928	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	112:6f327212ef96	1929	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	112:6f327212ef96	1930	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	112:6f327212ef96	1931	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	112:6f327212ef96	1932	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	112:6f327212ef96	1933	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	112:6f327212ef96	1934	/**
Kojto	112:6f327212ef96	1935	* @}
Kojto	112:6f327212ef96	1936	*/
Kojto	112:6f327212ef96	1937
Kojto	112:6f327212ef96	1938	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	1939	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	1940	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	1941	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	1942	* using it.
Kojto	112:6f327212ef96	1943	*/
Kojto	112:6f327212ef96	1944	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1945	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1946	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	112:6f327212ef96	1947	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1948	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	112:6f327212ef96	1949	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1950	} while(0)
Kojto	112:6f327212ef96	1951	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1952	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1953	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	112:6f327212ef96	1954	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1955	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	112:6f327212ef96	1956	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1957	} while(0)
Kojto	112:6f327212ef96	1958	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1959	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1960	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	112:6f327212ef96	1961	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1962	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	112:6f327212ef96	1963	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1964	} while(0)
Kojto	112:6f327212ef96	1965	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1966	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1967	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	1968	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1969	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	1970	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1971	} while(0)
Kojto	112:6f327212ef96	1972	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1973	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1974	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	1975	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1976	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	1977	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1978	} while(0)
Kojto	112:6f327212ef96	1979	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	1980	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	1981	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	1982	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	1983	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	1984	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	1985	} while(0)
Kojto	112:6f327212ef96	1986
Kojto	112:6f327212ef96	1987	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	112:6f327212ef96	1988	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	112:6f327212ef96	1989	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	1990	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	112:6f327212ef96	1991	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	112:6f327212ef96	1992	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	112:6f327212ef96	1993	/**
Kojto	112:6f327212ef96	1994	* @}
Kojto	112:6f327212ef96	1995	*/
Kojto	112:6f327212ef96	1996
Kojto	112:6f327212ef96	1997	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	1998	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	1999	*/
Kojto	112:6f327212ef96	2000	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	2001	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	2002	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	112:6f327212ef96	2003	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	112:6f327212ef96	2004	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	112:6f327212ef96	2005	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	112:6f327212ef96	2006	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	112:6f327212ef96	2007	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2008
Kojto	112:6f327212ef96	2009	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	2010	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	2011	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	112:6f327212ef96	2012	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	112:6f327212ef96	2013	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	112:6f327212ef96	2014	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	112:6f327212ef96	2015	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	112:6f327212ef96	2016	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2017	/**
Kojto	112:6f327212ef96	2018	* @}
Kojto	112:6f327212ef96	2019	*/
Kojto	112:6f327212ef96	2020
Kojto	112:6f327212ef96	2021	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	112:6f327212ef96	2022	* @brief Force or release AHB2 peripheral reset.
Kojto	112:6f327212ef96	2023	*/
Kojto	112:6f327212ef96	2024	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2025	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	112:6f327212ef96	2026
Kojto	112:6f327212ef96	2027	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	2028	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	112:6f327212ef96	2029	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	112:6f327212ef96	2030	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	2031
Kojto	112:6f327212ef96	2032	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	2033	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	112:6f327212ef96	2034	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	112:6f327212ef96	2035
Kojto	112:6f327212ef96	2036	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	112:6f327212ef96	2037	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	112:6f327212ef96	2038	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	2039
Kojto	112:6f327212ef96	2040	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	2041	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	2042
Kojto	112:6f327212ef96	2043	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	112:6f327212ef96	2044	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	112:6f327212ef96	2045	/**
Kojto	112:6f327212ef96	2046	* @}
Kojto	112:6f327212ef96	2047	*/
Kojto	112:6f327212ef96	2048
Kojto	112:6f327212ef96	2049	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	112:6f327212ef96	2050	* @brief Force or release AHB3 peripheral reset.
Kojto	112:6f327212ef96	2051	* @{
Kojto	112:6f327212ef96	2052	*/
Kojto	112:6f327212ef96	2053	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2054	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	112:6f327212ef96	2055
Kojto	112:6f327212ef96	2056	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
Kojto	112:6f327212ef96	2057	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto	112:6f327212ef96	2058	/**
Kojto	112:6f327212ef96	2059	* @}
Kojto	112:6f327212ef96	2060	*/
Kojto	112:6f327212ef96	2061
Kojto	112:6f327212ef96	2062	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	2063	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	2064	*/
Kojto	112:6f327212ef96	2065	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	2066	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	2067	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	112:6f327212ef96	2068	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	112:6f327212ef96	2069	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	112:6f327212ef96	2070	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	2071	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	112:6f327212ef96	2072	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	112:6f327212ef96	2073	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	112:6f327212ef96	2074	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	112:6f327212ef96	2075	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	2076	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	2077	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	2078	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	2079	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	2080	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	2081
Kojto	112:6f327212ef96	2082	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	2083	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	2084	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	2085	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	2086	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	2087	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	2088	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	2089	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	112:6f327212ef96	2090	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	112:6f327212ef96	2091	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	112:6f327212ef96	2092	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	2093	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	112:6f327212ef96	2094	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	112:6f327212ef96	2095	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	112:6f327212ef96	2096	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	112:6f327212ef96	2097	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	2098	/**
Kojto	112:6f327212ef96	2099	* @}
Kojto	112:6f327212ef96	2100	*/
Kojto	112:6f327212ef96	2101
Kojto	112:6f327212ef96	2102	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	2103	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	2104	*/
Kojto	112:6f327212ef96	2105	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	112:6f327212ef96	2106	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	2107	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	2108	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	2109
Kojto	112:6f327212ef96	2110	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	2111	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	2112	#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	2113	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	112:6f327212ef96	2114	/**
Kojto	112:6f327212ef96	2115	* @}
Kojto	112:6f327212ef96	2116	*/
Kojto	112:6f327212ef96	2117
Kojto	112:6f327212ef96	2118	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2119	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2120	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2121	* power consumption.
Kojto	112:6f327212ef96	2122	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2123	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2124	*/
Kojto	112:6f327212ef96	2125	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	2126	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	2127	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	112:6f327212ef96	2128	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	112:6f327212ef96	2129	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	112:6f327212ef96	2130	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	112:6f327212ef96	2131	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	112:6f327212ef96	2132	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	112:6f327212ef96	2133	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	112:6f327212ef96	2134	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	112:6f327212ef96	2135	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	112:6f327212ef96	2136	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	112:6f327212ef96	2137	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	2138	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	2139	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	2140	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	2141
Kojto	112:6f327212ef96	2142	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	2143	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	2144	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	112:6f327212ef96	2145	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	112:6f327212ef96	2146	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	112:6f327212ef96	2147	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	112:6f327212ef96	2148	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	112:6f327212ef96	2149	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	112:6f327212ef96	2150	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	112:6f327212ef96	2151	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	112:6f327212ef96	2152	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	112:6f327212ef96	2153	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	112:6f327212ef96	2154	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	2155	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	2156	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	2157	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	2158	/**
Kojto	112:6f327212ef96	2159	* @}
Kojto	112:6f327212ef96	2160	*/
Kojto	112:6f327212ef96	2161
Kojto	112:6f327212ef96	2162	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2163	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2164	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2165	* power consumption.
Kojto	112:6f327212ef96	2166	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2167	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2168	* @{
Kojto	112:6f327212ef96	2169	*/
Kojto	112:6f327212ef96	2170	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	2171	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	2172
Kojto	112:6f327212ef96	2173	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	112:6f327212ef96	2174	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	112:6f327212ef96	2175
Kojto	112:6f327212ef96	2176	#if defined(STM32F407xx)\|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	2177	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	112:6f327212ef96	2178	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	112:6f327212ef96	2179	#endif /* STM32F407xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	2180
Kojto	112:6f327212ef96	2181	#if defined(STM32F415xx) \|\| defined(STM32F417xx)
Kojto	112:6f327212ef96	2182	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	112:6f327212ef96	2183	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	112:6f327212ef96	2184
Kojto	112:6f327212ef96	2185	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	112:6f327212ef96	2186	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	112:6f327212ef96	2187	#endif /* STM32F415xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	2188	/**
Kojto	112:6f327212ef96	2189	* @}
Kojto	112:6f327212ef96	2190	*/
Kojto	112:6f327212ef96	2191
Kojto	112:6f327212ef96	2192	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2193	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2194	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2195	* power consumption.
Kojto	112:6f327212ef96	2196	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2197	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2198	*/
Kojto	112:6f327212ef96	2199	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
Kojto	112:6f327212ef96	2200	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto	112:6f327212ef96	2201	/**
Kojto	112:6f327212ef96	2202	* @}
Kojto	112:6f327212ef96	2203	*/
Kojto	112:6f327212ef96	2204
Kojto	112:6f327212ef96	2205	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2206	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2207	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2208	* power consumption.
Kojto	112:6f327212ef96	2209	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2210	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2211	*/
Kojto	112:6f327212ef96	2212	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	2213	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	2214	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	112:6f327212ef96	2215	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	112:6f327212ef96	2216	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	112:6f327212ef96	2217	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	2218	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	112:6f327212ef96	2219	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	112:6f327212ef96	2220	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	112:6f327212ef96	2221	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	112:6f327212ef96	2222	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	2223	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	2224	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	2225	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	2226	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	2227	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	2228
Kojto	112:6f327212ef96	2229	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	2230	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	2231	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	2232	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	2233	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	2234	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	2235	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	2236	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	112:6f327212ef96	2237	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	112:6f327212ef96	2238	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	112:6f327212ef96	2239	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	2240	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	112:6f327212ef96	2241	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	112:6f327212ef96	2242	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	112:6f327212ef96	2243	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	112:6f327212ef96	2244	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	2245	/**
Kojto	112:6f327212ef96	2246	* @}
Kojto	112:6f327212ef96	2247	*/
Kojto	112:6f327212ef96	2248
Kojto	112:6f327212ef96	2249	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2250	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2251	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2252	* power consumption.
Kojto	112:6f327212ef96	2253	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2254	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2255	*/
Kojto	112:6f327212ef96	2256	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	112:6f327212ef96	2257	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	112:6f327212ef96	2258	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	112:6f327212ef96	2259	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	2260	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	2261	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	2262
Kojto	112:6f327212ef96	2263	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	2264	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	2265	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	2266	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	112:6f327212ef96	2267	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	112:6f327212ef96	2268	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	112:6f327212ef96	2269	/**
Kojto	112:6f327212ef96	2270	* @}
Kojto	112:6f327212ef96	2271	*/
Kojto	112:6f327212ef96	2272	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx */
Kojto	112:6f327212ef96	2273	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	2274
Kojto	112:6f327212ef96	2275	/------------------------- STM32F401xE/STM32F401xC --------------------------/
Kojto	112:6f327212ef96	2276	#if defined(STM32F401xC) \|\| defined(STM32F401xE)
Kojto	112:6f327212ef96	2277	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2278	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	112:6f327212ef96	2279	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2280	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2281	* using it.
Kojto	112:6f327212ef96	2282	* @{
Kojto	112:6f327212ef96	2283	*/
Kojto	112:6f327212ef96	2284	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2285	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2286	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	2287	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2288	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	2289	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2290	} while(0)
Kojto	112:6f327212ef96	2291	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2292	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2293	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	2294	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2295	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	2296	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2297	} while(0)
Kojto	112:6f327212ef96	2298	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2299	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2300	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	2301	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2302	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	2303	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2304	} while(0)
Kojto	112:6f327212ef96	2305	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2306	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2307	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	2308	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2309	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	2310	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2311	} while(0)
Kojto	112:6f327212ef96	2312	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2313	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2314	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	2315	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2316	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	2317	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2318	} while(0)
Kojto	112:6f327212ef96	2319
Kojto	112:6f327212ef96	2320	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	112:6f327212ef96	2321	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	112:6f327212ef96	2322	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	112:6f327212ef96	2323	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	112:6f327212ef96	2324	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	112:6f327212ef96	2325	/**
Kojto	112:6f327212ef96	2326	* @}
Kojto	112:6f327212ef96	2327	*/
Kojto	112:6f327212ef96	2328
Kojto	112:6f327212ef96	2329	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2330	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	112:6f327212ef96	2331	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2332	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2333	* using it.
Kojto	112:6f327212ef96	2334	* @{
Kojto	112:6f327212ef96	2335	*/
Kojto	112:6f327212ef96	2336	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	2337	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	112:6f327212ef96	2338	}while(0)
Kojto	112:6f327212ef96	2339
Kojto	112:6f327212ef96	2340	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	2341	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	112:6f327212ef96	2342	}while(0)
Kojto	112:6f327212ef96	2343	/**
Kojto	112:6f327212ef96	2344	* @}
Kojto	112:6f327212ef96	2345	*/
Kojto	112:6f327212ef96	2346
Kojto	112:6f327212ef96	2347	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2348	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	2349	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2350	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2351	* using it.
Kojto	112:6f327212ef96	2352	* @{
Kojto	112:6f327212ef96	2353	*/
Kojto	112:6f327212ef96	2354	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2355	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2356	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	2357	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2358	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	2359	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2360	} while(0)
Kojto	112:6f327212ef96	2361	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2362	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2363	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	2364	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2365	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	2366	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2367	} while(0)
Kojto	112:6f327212ef96	2368	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2369	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2370	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	2371	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2372	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	2373	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2374	} while(0)
Kojto	112:6f327212ef96	2375	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2376	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2377	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	2378	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2379	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	2380	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2381	} while(0)
Kojto	112:6f327212ef96	2382	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2383	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2384	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	2385	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2386	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	2387	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2388	} while(0)
Kojto	112:6f327212ef96	2389	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	2390	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	2391	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	2392	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	112:6f327212ef96	2393	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	112:6f327212ef96	2394	/**
Kojto	112:6f327212ef96	2395	* @}
Kojto	112:6f327212ef96	2396	*/
Kojto	112:6f327212ef96	2397
Kojto	112:6f327212ef96	2398	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2399	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	2400	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2401	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2402	* using it.
Kojto	112:6f327212ef96	2403	* @{
Kojto	112:6f327212ef96	2404	*/
Kojto	112:6f327212ef96	2405	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2406	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2407	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	2408	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2409	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	2410	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2411	} while(0)
Kojto	112:6f327212ef96	2412	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2413	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2414	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	2415	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2416	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	2417	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2418	} while(0)
Kojto	112:6f327212ef96	2419	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2420	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2421	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	2422	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2423	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	2424	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2425	} while(0)
Kojto	112:6f327212ef96	2426
Kojto	112:6f327212ef96	2427	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	112:6f327212ef96	2428	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	112:6f327212ef96	2429	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	2430	/**
Kojto	112:6f327212ef96	2431	* @}
Kojto	112:6f327212ef96	2432	*/
Kojto	112:6f327212ef96	2433
Kojto	112:6f327212ef96	2434	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	2435	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	2436	* @{
Kojto	112:6f327212ef96	2437	*/
Kojto	112:6f327212ef96	2438	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2439	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	2440	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	2441	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2442
Kojto	112:6f327212ef96	2443	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto	112:6f327212ef96	2444	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	2445	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	2446	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2447	/**
Kojto	112:6f327212ef96	2448	* @}
Kojto	112:6f327212ef96	2449	*/
Kojto	112:6f327212ef96	2450
Kojto	112:6f327212ef96	2451	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	112:6f327212ef96	2452	* @brief Force or release AHB2 peripheral reset.
Kojto	112:6f327212ef96	2453	* @{
Kojto	112:6f327212ef96	2454	*/
Kojto	112:6f327212ef96	2455	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2456	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	2457
Kojto	112:6f327212ef96	2458	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	112:6f327212ef96	2459	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	2460	/**
Kojto	112:6f327212ef96	2461	* @}
Kojto	112:6f327212ef96	2462	*/
Kojto	112:6f327212ef96	2463
Kojto	112:6f327212ef96	2464	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	2465	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	2466	* @{
Kojto	112:6f327212ef96	2467	*/
Kojto	112:6f327212ef96	2468	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2469	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	2470	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	2471	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	2472	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	2473	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	2474
Kojto	112:6f327212ef96	2475	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	112:6f327212ef96	2476	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	2477	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	2478	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	2479	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	2480	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	2481	/**
Kojto	112:6f327212ef96	2482	* @}
Kojto	112:6f327212ef96	2483	*/
Kojto	112:6f327212ef96	2484
Kojto	112:6f327212ef96	2485	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	2486	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	2487	* @{
Kojto	112:6f327212ef96	2488	*/
Kojto	112:6f327212ef96	2489	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2490	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	2491	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	2492	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	2493
Kojto	112:6f327212ef96	2494	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	112:6f327212ef96	2495	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	2496	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	2497	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	2498	/**
Kojto	112:6f327212ef96	2499	* @}
Kojto	112:6f327212ef96	2500	*/
Kojto	112:6f327212ef96	2501
Kojto	112:6f327212ef96	2502	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	112:6f327212ef96	2503	* @brief Force or release AHB3 peripheral reset.
Kojto	112:6f327212ef96	2504	* @{
Kojto	112:6f327212ef96	2505	*/
Kojto	112:6f327212ef96	2506	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2507	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	112:6f327212ef96	2508	/**
Kojto	112:6f327212ef96	2509	* @}
Kojto	112:6f327212ef96	2510	*/
Kojto	112:6f327212ef96	2511
Kojto	112:6f327212ef96	2512	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2513	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2514	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2515	* power consumption.
Kojto	112:6f327212ef96	2516	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2517	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2518	* @{
Kojto	112:6f327212ef96	2519	*/
Kojto	112:6f327212ef96	2520	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	2521	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	2522	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	2523	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	2524	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	2525	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	2526
Kojto	112:6f327212ef96	2527	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	2528	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	2529	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	2530	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	2531	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	2532	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	2533	/**
Kojto	112:6f327212ef96	2534	* @}
Kojto	112:6f327212ef96	2535	*/
Kojto	112:6f327212ef96	2536
Kojto	112:6f327212ef96	2537	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2538	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2539	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2540	* power consumption.
Kojto	112:6f327212ef96	2541	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2542	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2543	* @{
Kojto	112:6f327212ef96	2544	*/
Kojto	112:6f327212ef96	2545	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	2546
Kojto	112:6f327212ef96	2547	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	2548	/**
Kojto	112:6f327212ef96	2549	* @}
Kojto	112:6f327212ef96	2550	*/
Kojto	112:6f327212ef96	2551
Kojto	112:6f327212ef96	2552	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2553	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2554	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2555	* power consumption.
Kojto	112:6f327212ef96	2556	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2557	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2558	* @{
Kojto	112:6f327212ef96	2559	*/
Kojto	112:6f327212ef96	2560	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	2561	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	2562	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	2563	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	2564	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	2565
Kojto	112:6f327212ef96	2566	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	2567	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	2568	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	2569	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	2570	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	2571	/**
Kojto	112:6f327212ef96	2572	* @}
Kojto	112:6f327212ef96	2573	*/
Kojto	112:6f327212ef96	2574
Kojto	112:6f327212ef96	2575	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2576	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2577	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2578	* power consumption.
Kojto	112:6f327212ef96	2579	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2580	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2581	* @{
Kojto	112:6f327212ef96	2582	*/
Kojto	112:6f327212ef96	2583	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	2584	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	2585	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	2586
Kojto	112:6f327212ef96	2587	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	2588	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	2589	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	2590	/**
Kojto	112:6f327212ef96	2591	* @}
Kojto	112:6f327212ef96	2592	*/
Kojto	112:6f327212ef96	2593	#endif /* STM32F401xC \|\| STM32F401xE*/
Kojto	112:6f327212ef96	2594	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	2595
Kojto	112:6f327212ef96	2596	/-------------------------------- STM32F410xx -------------------------------/
Kojto	112:6f327212ef96	2597	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	2598	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2599	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	112:6f327212ef96	2600	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2601	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2602	* using it.
Kojto	112:6f327212ef96	2603	*/
Kojto	112:6f327212ef96	2604	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2605	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2606	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	2607	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2608	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	2609	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2610	} while(0)
Kojto	112:6f327212ef96	2611	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2612	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2613	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	112:6f327212ef96	2614	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2615	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
Kojto	112:6f327212ef96	2616	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2617	} while(0)
Kojto	112:6f327212ef96	2618	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	112:6f327212ef96	2619	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
Kojto	112:6f327212ef96	2620	/**
Kojto	112:6f327212ef96	2621	* @}
Kojto	112:6f327212ef96	2622	*/
Kojto	112:6f327212ef96	2623
Kojto	112:6f327212ef96	2624	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2625	* @brief Enable or disable the High Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	2626	*/
Kojto	112:6f327212ef96	2627	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2628	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2629	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	2630	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2631	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	2632	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2633	} while(0)
Kojto	112:6f327212ef96	2634	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2635	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2636	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	112:6f327212ef96	2637	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2638	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	112:6f327212ef96	2639	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2640	} while(0)
Kojto	112:6f327212ef96	2641	#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2642	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2643	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	112:6f327212ef96	2644	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2645	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
Kojto	112:6f327212ef96	2646	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2647	} while(0)
Kojto	112:6f327212ef96	2648	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2649	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2650	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	112:6f327212ef96	2651	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2652	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	112:6f327212ef96	2653	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2654	} while(0)
Kojto	112:6f327212ef96	2655	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2656	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2657	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	2658	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2659	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	2660	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2661	} while(0)
Kojto	112:6f327212ef96	2662
Kojto	112:6f327212ef96	2663	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	112:6f327212ef96	2664	#define __HAL_RCC_RTCAPB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
Kojto	112:6f327212ef96	2665	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto	112:6f327212ef96	2666	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	112:6f327212ef96	2667	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	112:6f327212ef96	2668	/**
Kojto	112:6f327212ef96	2669	* @}
Kojto	112:6f327212ef96	2670	*/
Kojto	112:6f327212ef96	2671
Kojto	112:6f327212ef96	2672	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2673	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	2674	*/
Kojto	112:6f327212ef96	2675	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2676	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2677	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	112:6f327212ef96	2678	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2679	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	112:6f327212ef96	2680	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2681	} while(0)
Kojto	112:6f327212ef96	2682	#define __HAL_RCC_EXTIT_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2683	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2684	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	112:6f327212ef96	2685	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2686	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
Kojto	112:6f327212ef96	2687	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2688	} while(0)
Kojto	112:6f327212ef96	2689	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	112:6f327212ef96	2690	#define __HAL_RCC_EXTIT_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
Kojto	112:6f327212ef96	2691	/**
Kojto	112:6f327212ef96	2692	* @}
Kojto	112:6f327212ef96	2693	*/
Kojto	112:6f327212ef96	2694
Kojto	112:6f327212ef96	2695	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	2696	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	2697	*/
Kojto	112:6f327212ef96	2698	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2699	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_RNGRST))
Kojto	112:6f327212ef96	2700	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2701	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
Kojto	112:6f327212ef96	2702	/**
Kojto	112:6f327212ef96	2703	* @}
Kojto	112:6f327212ef96	2704	*/
Kojto	112:6f327212ef96	2705
Kojto	112:6f327212ef96	2706	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	112:6f327212ef96	2707	* @brief Force or release AHB2 peripheral reset.
Kojto	112:6f327212ef96	2708	* @{
Kojto	112:6f327212ef96	2709	*/
Kojto	112:6f327212ef96	2710	#define __HAL_RCC_AHB2_FORCE_RESET()
Kojto	112:6f327212ef96	2711	#define __HAL_RCC_AHB2_RELEASE_RESET()
Kojto	112:6f327212ef96	2712	/**
Kojto	112:6f327212ef96	2713	* @}
Kojto	112:6f327212ef96	2714	*/
Kojto	112:6f327212ef96	2715
Kojto	112:6f327212ef96	2716	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	112:6f327212ef96	2717	* @brief Force or release AHB3 peripheral reset.
Kojto	112:6f327212ef96	2718	* @{
Kojto	112:6f327212ef96	2719	*/
Kojto	112:6f327212ef96	2720	#define __HAL_RCC_AHB3_FORCE_RESET()
Kojto	112:6f327212ef96	2721	#define __HAL_RCC_AHB3_RELEASE_RESET()
Kojto	112:6f327212ef96	2722	/**
Kojto	112:6f327212ef96	2723	* @}
Kojto	112:6f327212ef96	2724	*/
Kojto	112:6f327212ef96	2725
Kojto	112:6f327212ef96	2726	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	2727	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	2728	*/
Kojto	112:6f327212ef96	2729	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	2730	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	112:6f327212ef96	2731	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	112:6f327212ef96	2732	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	2733
Kojto	112:6f327212ef96	2734	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	2735	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto	112:6f327212ef96	2736	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	112:6f327212ef96	2737	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	2738	/**
Kojto	112:6f327212ef96	2739	* @}
Kojto	112:6f327212ef96	2740	*/
Kojto	112:6f327212ef96	2741
Kojto	112:6f327212ef96	2742	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	2743	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	2744	*/
Kojto	112:6f327212ef96	2745	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	112:6f327212ef96	2746	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	112:6f327212ef96	2747	/**
Kojto	112:6f327212ef96	2748	* @}
Kojto	112:6f327212ef96	2749	*/
Kojto	112:6f327212ef96	2750
Kojto	112:6f327212ef96	2751	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2752	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2753	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	2754	* power consumption.
Kojto	112:6f327212ef96	2755	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	2756	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	2757	*/
Kojto	112:6f327212ef96	2758	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_RNGLPEN))
Kojto	112:6f327212ef96	2759	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	2760	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	2761	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	2762
Kojto	112:6f327212ef96	2763	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
Kojto	112:6f327212ef96	2764	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	2765	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	2766	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	2767	/**
Kojto	112:6f327212ef96	2768	* @}
Kojto	112:6f327212ef96	2769	*/
Kojto	112:6f327212ef96	2770
Kojto	112:6f327212ef96	2771	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2772	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2773	*/
Kojto	112:6f327212ef96	2774	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	2775	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto	112:6f327212ef96	2776	#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_RTCAPBLPEN))
Kojto	112:6f327212ef96	2777	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	112:6f327212ef96	2778	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	2779
Kojto	112:6f327212ef96	2780	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	2781	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto	112:6f327212ef96	2782	#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
Kojto	112:6f327212ef96	2783	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	112:6f327212ef96	2784	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	2785	/**
Kojto	112:6f327212ef96	2786	* @}
Kojto	112:6f327212ef96	2787	*/
Kojto	112:6f327212ef96	2788
Kojto	112:6f327212ef96	2789	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	2790	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	2791	*/
Kojto	112:6f327212ef96	2792	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	112:6f327212ef96	2793	#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_EXTITLPEN))
Kojto	112:6f327212ef96	2794	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	112:6f327212ef96	2795	#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
Kojto	112:6f327212ef96	2796	/**
Kojto	112:6f327212ef96	2797	* @}
Kojto	112:6f327212ef96	2798	*/
Kojto	112:6f327212ef96	2799
Kojto	112:6f327212ef96	2800	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	2801	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	2802
Kojto	112:6f327212ef96	2803	/-------------------------------- STM32F411xx -------------------------------/
Kojto	112:6f327212ef96	2804	#if defined(STM32F411xE)
Kojto	112:6f327212ef96	2805	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2806	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	112:6f327212ef96	2807	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2808	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2809	* using it.
Kojto	112:6f327212ef96	2810	*/
Kojto	112:6f327212ef96	2811	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2812	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2813	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	2814	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2815	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	2816	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2817	} while(0)
Kojto	112:6f327212ef96	2818	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2819	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2820	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	2821	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2822	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	2823	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2824	} while(0)
Kojto	112:6f327212ef96	2825	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2826	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2827	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	2828	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2829	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	2830	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2831	} while(0)
Kojto	112:6f327212ef96	2832	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2833	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2834	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	2835	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2836	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	2837	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2838	} while(0)
Kojto	112:6f327212ef96	2839	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2840	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2841	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	2842	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2843	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	2844	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2845	} while(0)
Kojto	112:6f327212ef96	2846	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	112:6f327212ef96	2847	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	112:6f327212ef96	2848	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	112:6f327212ef96	2849	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	112:6f327212ef96	2850	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	112:6f327212ef96	2851	/**
Kojto	112:6f327212ef96	2852	* @}
Kojto	112:6f327212ef96	2853	*/
Kojto	112:6f327212ef96	2854
Kojto	112:6f327212ef96	2855	/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2856	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	112:6f327212ef96	2857	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2858	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2859	* using it.
Kojto	112:6f327212ef96	2860	* @{
Kojto	112:6f327212ef96	2861	*/
Kojto	112:6f327212ef96	2862	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	2863	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	112:6f327212ef96	2864	}while(0)
Kojto	112:6f327212ef96	2865
Kojto	112:6f327212ef96	2866	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	2867	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	112:6f327212ef96	2868	}while(0)
Kojto	112:6f327212ef96	2869	/**
Kojto	112:6f327212ef96	2870	* @}
Kojto	112:6f327212ef96	2871	*/
Kojto	112:6f327212ef96	2872
Kojto	112:6f327212ef96	2873	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2874	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	2875	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	2876	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	2877	* using it.
Kojto	112:6f327212ef96	2878	*/
Kojto	112:6f327212ef96	2879	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2880	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2881	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	2882	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2883	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	2884	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2885	} while(0)
Kojto	112:6f327212ef96	2886	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2887	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2888	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	2889	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2890	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	2891	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2892	} while(0)
Kojto	112:6f327212ef96	2893	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2894	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2895	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	2896	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2897	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	2898	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2899	} while(0)
Kojto	112:6f327212ef96	2900	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2901	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	2903	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	2905	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2906	} while(0)
Kojto	112:6f327212ef96	2907	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2908	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2909	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	2910	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2911	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	2912	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2913	} while(0)
Kojto	112:6f327212ef96	2914	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	2915	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	2916	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	2917	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	112:6f327212ef96	2918	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	112:6f327212ef96	2919	/**
Kojto	112:6f327212ef96	2920	* @}
Kojto	112:6f327212ef96	2921	*/
Kojto	112:6f327212ef96	2922	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	2923	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	2924	*/
Kojto	112:6f327212ef96	2925	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2926	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2927	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	112:6f327212ef96	2928	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2929	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	112:6f327212ef96	2930	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2931	} while(0)
Kojto	112:6f327212ef96	2932	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2933	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2934	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	2935	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2936	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	2937	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2938	} while(0)
Kojto	112:6f327212ef96	2939	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2940	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2941	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	2942	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2943	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	2944	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2945	} while(0)
Kojto	112:6f327212ef96	2946	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	2947	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	2948	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	2949	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	2950	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	2951	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	2952	} while(0)
Kojto	112:6f327212ef96	2953	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	112:6f327212ef96	2954	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	112:6f327212ef96	2955	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	2956	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	112:6f327212ef96	2957	/**
Kojto	112:6f327212ef96	2958	* @}
Kojto	112:6f327212ef96	2959	*/
Kojto	112:6f327212ef96	2960
Kojto	112:6f327212ef96	2961	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	2962	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	2963	*/
Kojto	112:6f327212ef96	2964	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	2965	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	2966	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2967
Kojto	112:6f327212ef96	2968	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	2969	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	2970	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	2971	/**
Kojto	112:6f327212ef96	2972	* @}
Kojto	112:6f327212ef96	2973	*/
Kojto	112:6f327212ef96	2974
Kojto	112:6f327212ef96	2975	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	112:6f327212ef96	2976	* @brief Force or release AHB2 peripheral reset.
Kojto	112:6f327212ef96	2977	* @{
Kojto	112:6f327212ef96	2978	*/
Kojto	112:6f327212ef96	2979	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2980	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	2981
Kojto	112:6f327212ef96	2982	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	112:6f327212ef96	2983	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	2984	/**
Kojto	112:6f327212ef96	2985	* @}
Kojto	112:6f327212ef96	2986	*/
Kojto	112:6f327212ef96	2987
Kojto	112:6f327212ef96	2988	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	112:6f327212ef96	2989	* @brief Force or release AHB3 peripheral reset.
Kojto	112:6f327212ef96	2990	* @{
Kojto	112:6f327212ef96	2991	*/
Kojto	112:6f327212ef96	2992	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	2993	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	112:6f327212ef96	2994	/**
Kojto	112:6f327212ef96	2995	* @}
Kojto	112:6f327212ef96	2996	*/
Kojto	112:6f327212ef96	2997
Kojto	112:6f327212ef96	2998	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	2999	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	3000	*/
Kojto	112:6f327212ef96	3001	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	3002	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	3003	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	3004	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	3005	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	3006
Kojto	112:6f327212ef96	3007	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	3008	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	3009	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	3010	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	3011	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	3012	/**
Kojto	112:6f327212ef96	3013	* @}
Kojto	112:6f327212ef96	3014	*/
Kojto	112:6f327212ef96	3015
Kojto	112:6f327212ef96	3016	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	3017	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	3018	*/
Kojto	112:6f327212ef96	3019	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	112:6f327212ef96	3020	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	3021	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	3022	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	3023
Kojto	112:6f327212ef96	3024	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	3025	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	3026	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	3027	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	112:6f327212ef96	3028	/**
Kojto	112:6f327212ef96	3029	* @}
Kojto	112:6f327212ef96	3030	*/
Kojto	112:6f327212ef96	3031
Kojto	112:6f327212ef96	3032	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3033	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3034	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3035	* power consumption.
Kojto	112:6f327212ef96	3036	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3037	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3038	*/
Kojto	112:6f327212ef96	3039	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	3040	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	3041	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	3042	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	3043	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	3044
Kojto	112:6f327212ef96	3045	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	3046	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	3047	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	3048	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	3049	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	3050	/**
Kojto	112:6f327212ef96	3051	* @}
Kojto	112:6f327212ef96	3052	*/
Kojto	112:6f327212ef96	3053
Kojto	112:6f327212ef96	3054	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3055	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3056	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3057	* power consumption.
Kojto	112:6f327212ef96	3058	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3059	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3060	* @{
Kojto	112:6f327212ef96	3061	*/
Kojto	112:6f327212ef96	3062	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	3063	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	3064	/**
Kojto	112:6f327212ef96	3065	* @}
Kojto	112:6f327212ef96	3066	*/
Kojto	112:6f327212ef96	3067
Kojto	112:6f327212ef96	3068	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3069	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3070	*/
Kojto	112:6f327212ef96	3071	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	3072	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	3073	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	3074	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	3075	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	3076
Kojto	112:6f327212ef96	3077	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	3078	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	3079	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	3080	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	3081	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	3082	/**
Kojto	112:6f327212ef96	3083	* @}
Kojto	112:6f327212ef96	3084	*/
Kojto	112:6f327212ef96	3085
Kojto	112:6f327212ef96	3086	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3087	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3088	*/
Kojto	112:6f327212ef96	3089	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	112:6f327212ef96	3090	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	3091	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	3092	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	3093
Kojto	112:6f327212ef96	3094	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	3095	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	3096	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	3097	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	112:6f327212ef96	3098	/**
Kojto	112:6f327212ef96	3099	* @}
Kojto	112:6f327212ef96	3100	*/
Kojto	112:6f327212ef96	3101	#endif /* STM32F411xE */
Kojto	112:6f327212ef96	3102	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	3103
Kojto	112:6f327212ef96	3104	/---------------------------------- STM32F446xx -----------------------------/
Kojto	112:6f327212ef96	3105	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	3106	/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	3107	* @brief Enables or disables the AHB1 peripheral clock.
Kojto	112:6f327212ef96	3108	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	3109	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	3110	* using it.
Kojto	112:6f327212ef96	3111	*/
Kojto	112:6f327212ef96	3112	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3113	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3114	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	3115	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3116	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	112:6f327212ef96	3117	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3118	} while(0)
Kojto	112:6f327212ef96	3119	#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3120	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3121	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	3122	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3123	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto	112:6f327212ef96	3124	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3125	} while(0)
Kojto	112:6f327212ef96	3126	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3127	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3128	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	3129	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3130	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto	112:6f327212ef96	3131	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3132	} while(0)
Kojto	112:6f327212ef96	3133	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3134	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3135	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	3136	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3137	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	112:6f327212ef96	3138	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3139	} while(0)
Kojto	112:6f327212ef96	3140	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3141	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3142	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	3143	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3144	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	112:6f327212ef96	3145	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3146	} while(0)
Kojto	112:6f327212ef96	3147	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3148	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3149	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	112:6f327212ef96	3150	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3151	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	112:6f327212ef96	3152	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3153	} while(0)
Kojto	112:6f327212ef96	3154	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3155	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3156	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	112:6f327212ef96	3157	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3158	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	112:6f327212ef96	3159	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3160	} while(0)
Kojto	112:6f327212ef96	3161	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3162	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3163	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	112:6f327212ef96	3164	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3165	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	112:6f327212ef96	3166	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3167	} while(0)
Kojto	112:6f327212ef96	3168	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3169	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3170	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	112:6f327212ef96	3171	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3172	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	112:6f327212ef96	3173	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3174	} while(0)
Kojto	112:6f327212ef96	3175	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	112:6f327212ef96	3176	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	112:6f327212ef96	3177	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	112:6f327212ef96	3178	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	112:6f327212ef96	3179	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	112:6f327212ef96	3180	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	112:6f327212ef96	3181	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	112:6f327212ef96	3182	#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto	112:6f327212ef96	3183	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto	112:6f327212ef96	3184	/**
Kojto	112:6f327212ef96	3185	* @}
Kojto	112:6f327212ef96	3186	*/
Kojto	112:6f327212ef96	3187
Kojto	112:6f327212ef96	3188	/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	3189	* @brief Enable or disable the AHB2 peripheral clock.
Kojto	112:6f327212ef96	3190	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	3191	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	3192	* using it.
Kojto	112:6f327212ef96	3193	*/
Kojto	112:6f327212ef96	3194	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3195	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3196	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	112:6f327212ef96	3197	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3198	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	112:6f327212ef96	3199	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3200	} while(0)
Kojto	112:6f327212ef96	3201	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	112:6f327212ef96	3202	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	3203	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	112:6f327212ef96	3204	}while(0)
Kojto	112:6f327212ef96	3205
Kojto	112:6f327212ef96	3206	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto	112:6f327212ef96	3207	__HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto	112:6f327212ef96	3208	}while(0)
Kojto	112:6f327212ef96	3209
Kojto	112:6f327212ef96	3210	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3211	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3212	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	112:6f327212ef96	3213	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3214	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	112:6f327212ef96	3215	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3216	} while(0)
Kojto	112:6f327212ef96	3217	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	112:6f327212ef96	3218	/**
Kojto	112:6f327212ef96	3219	* @}
Kojto	112:6f327212ef96	3220	*/
Kojto	112:6f327212ef96	3221
Kojto	112:6f327212ef96	3222	/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	3223	* @brief Enables or disables the AHB3 peripheral clock.
Kojto	112:6f327212ef96	3224	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	3225	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	3226	* using it.
Kojto	112:6f327212ef96	3227	*/
Kojto	112:6f327212ef96	3228	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3229	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3230	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	112:6f327212ef96	3231	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3232	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	112:6f327212ef96	3233	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3234	} while(0)
Kojto	112:6f327212ef96	3235	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3236	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3237	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	112:6f327212ef96	3238	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3239	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	112:6f327212ef96	3240	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3241	} while(0)
Kojto	112:6f327212ef96	3242
Kojto	112:6f327212ef96	3243	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	112:6f327212ef96	3244	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	112:6f327212ef96	3245	/**
Kojto	112:6f327212ef96	3246	* @}
Kojto	112:6f327212ef96	3247	*/
Kojto	112:6f327212ef96	3248
Kojto	112:6f327212ef96	3249	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	3250	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	3251	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	3252	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	3253	* using it.
Kojto	112:6f327212ef96	3254	*/
Kojto	112:6f327212ef96	3255	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3256	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3257	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	3258	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3259	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	112:6f327212ef96	3260	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3261	} while(0)
Kojto	112:6f327212ef96	3262	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3263	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3264	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	112:6f327212ef96	3265	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3266	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	112:6f327212ef96	3267	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3268	} while(0)
Kojto	112:6f327212ef96	3269	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3270	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3271	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	112:6f327212ef96	3272	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3273	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	112:6f327212ef96	3274	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3275	} while(0)
Kojto	112:6f327212ef96	3276	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3277	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3278	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	112:6f327212ef96	3279	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3280	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	112:6f327212ef96	3281	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3282	} while(0)
Kojto	112:6f327212ef96	3283	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3284	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3285	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	3286	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3287	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	112:6f327212ef96	3288	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3289	} while(0)
Kojto	112:6f327212ef96	3290	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3291	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3292	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	112:6f327212ef96	3293	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3294	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	112:6f327212ef96	3295	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3296	} while(0)
Kojto	112:6f327212ef96	3297	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3298	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3299	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	112:6f327212ef96	3300	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3301	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	112:6f327212ef96	3302	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3303	} while(0)
Kojto	112:6f327212ef96	3304	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3305	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3306	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	112:6f327212ef96	3307	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3308	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	112:6f327212ef96	3309	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3310	} while(0)
Kojto	112:6f327212ef96	3311	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3312	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3313	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	112:6f327212ef96	3314	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3315	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	112:6f327212ef96	3316	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3317	} while(0)
Kojto	112:6f327212ef96	3318	#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3319	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3320	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	112:6f327212ef96	3321	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3322	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto	112:6f327212ef96	3323	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3324	} while(0)
Kojto	112:6f327212ef96	3325	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3326	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3327	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	112:6f327212ef96	3328	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3329	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	112:6f327212ef96	3330	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3331	} while(0)
Kojto	112:6f327212ef96	3332	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3333	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3334	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	112:6f327212ef96	3335	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3336	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	112:6f327212ef96	3337	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3338	} while(0)
Kojto	112:6f327212ef96	3339	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3340	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3341	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	112:6f327212ef96	3342	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3343	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	112:6f327212ef96	3344	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3345	} while(0)
Kojto	112:6f327212ef96	3346	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3347	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3348	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	3349	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3350	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	112:6f327212ef96	3351	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3352	} while(0)
Kojto	112:6f327212ef96	3353	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3354	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3355	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	3356	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3357	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	112:6f327212ef96	3358	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3359	} while(0)
Kojto	112:6f327212ef96	3360	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3361	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3362	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	3363	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3364	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	112:6f327212ef96	3365	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3366	} while(0)
Kojto	112:6f327212ef96	3367	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3368	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3369	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	3370	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3371	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	112:6f327212ef96	3372	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3373	} while(0)
Kojto	112:6f327212ef96	3374	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3375	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3376	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	3377	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3378	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	112:6f327212ef96	3379	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3380	} while(0)
Kojto	112:6f327212ef96	3381	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3382	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3383	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	3384	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3385	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	112:6f327212ef96	3386	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3387	} while(0)
Kojto	112:6f327212ef96	3388	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	112:6f327212ef96	3389	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	112:6f327212ef96	3390	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	112:6f327212ef96	3391	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	112:6f327212ef96	3392	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	112:6f327212ef96	3393	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	112:6f327212ef96	3394	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	112:6f327212ef96	3395	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	112:6f327212ef96	3396	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	112:6f327212ef96	3397	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	112:6f327212ef96	3398	#define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	112:6f327212ef96	3399	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	112:6f327212ef96	3400	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	112:6f327212ef96	3401	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	112:6f327212ef96	3402	#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto	112:6f327212ef96	3403	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	112:6f327212ef96	3404	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	112:6f327212ef96	3405	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	112:6f327212ef96	3406	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	112:6f327212ef96	3407	/**
Kojto	112:6f327212ef96	3408	* @}
Kojto	112:6f327212ef96	3409	*/
Kojto	112:6f327212ef96	3410
Kojto	112:6f327212ef96	3411	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	3412	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	3413	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	3414	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	3415	* using it.
Kojto	112:6f327212ef96	3416	*/
Kojto	112:6f327212ef96	3417	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3418	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3419	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	112:6f327212ef96	3420	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3421	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	112:6f327212ef96	3422	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3423	} while(0)
Kojto	112:6f327212ef96	3424	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3425	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3426	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	112:6f327212ef96	3427	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3428	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	112:6f327212ef96	3429	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3430	} while(0)
Kojto	112:6f327212ef96	3431	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3432	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3433	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	112:6f327212ef96	3434	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3435	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	112:6f327212ef96	3436	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3437	} while(0)
Kojto	112:6f327212ef96	3438	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3439	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3440	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	112:6f327212ef96	3441	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3442	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	112:6f327212ef96	3443	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3444	} while(0)
Kojto	112:6f327212ef96	3445	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3446	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3447	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	112:6f327212ef96	3448	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3449	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	112:6f327212ef96	3450	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3451	} while(0)
Kojto	112:6f327212ef96	3452	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3453	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3454	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	3455	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3456	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto	112:6f327212ef96	3457	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3458	} while(0)
Kojto	112:6f327212ef96	3459	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3460	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3461	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	3462	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3463	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	112:6f327212ef96	3464	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3465	} while(0)
Kojto	112:6f327212ef96	3466	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	3467	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	3468	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	3469	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	3470	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	112:6f327212ef96	3471	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	3472	} while(0)
Kojto	112:6f327212ef96	3473	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto	112:6f327212ef96	3474	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	112:6f327212ef96	3475	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	112:6f327212ef96	3476	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	112:6f327212ef96	3477	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	112:6f327212ef96	3478	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	112:6f327212ef96	3479	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	112:6f327212ef96	3480	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	112:6f327212ef96	3481	/**
Kojto	112:6f327212ef96	3482	* @}
Kojto	112:6f327212ef96	3483	*/
Kojto	112:6f327212ef96	3484
Kojto	112:6f327212ef96	3485	/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	3486	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	3487	*/
Kojto	112:6f327212ef96	3488	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	3489	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	3490	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	112:6f327212ef96	3491	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	112:6f327212ef96	3492	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	112:6f327212ef96	3493	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	3494
Kojto	112:6f327212ef96	3495	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	112:6f327212ef96	3496	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	112:6f327212ef96	3497	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	112:6f327212ef96	3498	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	112:6f327212ef96	3499	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	112:6f327212ef96	3500	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto	112:6f327212ef96	3501	/**
Kojto	112:6f327212ef96	3502	* @}
Kojto	112:6f327212ef96	3503	*/
Kojto	112:6f327212ef96	3504
Kojto	112:6f327212ef96	3505	/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto	112:6f327212ef96	3506	* @brief Force or release AHB2 peripheral reset.
Kojto	112:6f327212ef96	3507	* @{
Kojto	112:6f327212ef96	3508	*/
Kojto	112:6f327212ef96	3509	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	3510	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	3511	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	112:6f327212ef96	3512	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	112:6f327212ef96	3513
Kojto	112:6f327212ef96	3514	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	112:6f327212ef96	3515	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	112:6f327212ef96	3516	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	112:6f327212ef96	3517	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	112:6f327212ef96	3518	/**
Kojto	112:6f327212ef96	3519	* @}
Kojto	112:6f327212ef96	3520	*/
Kojto	112:6f327212ef96	3521
Kojto	112:6f327212ef96	3522	/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto	112:6f327212ef96	3523	* @brief Force or release AHB3 peripheral reset.
Kojto	112:6f327212ef96	3524	* @{
Kojto	112:6f327212ef96	3525	*/
Kojto	112:6f327212ef96	3526	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	3527	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	112:6f327212ef96	3528
Kojto	112:6f327212ef96	3529	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	112:6f327212ef96	3530	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	112:6f327212ef96	3531
Kojto	112:6f327212ef96	3532	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	112:6f327212ef96	3533	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	112:6f327212ef96	3534	/**
Kojto	112:6f327212ef96	3535	* @}
Kojto	112:6f327212ef96	3536	*/
Kojto	112:6f327212ef96	3537
Kojto	112:6f327212ef96	3538	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	3539	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	3540	*/
Kojto	112:6f327212ef96	3541	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	3542	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	3543	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	112:6f327212ef96	3544	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	112:6f327212ef96	3545	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	112:6f327212ef96	3546	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	112:6f327212ef96	3547	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	3548	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	112:6f327212ef96	3549	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	112:6f327212ef96	3550	#define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_FMPI2C1RST))
Kojto	112:6f327212ef96	3551	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	112:6f327212ef96	3552	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	112:6f327212ef96	3553	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	112:6f327212ef96	3554	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	3555	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	3556	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	3557	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	3558	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	3559	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	3560
Kojto	112:6f327212ef96	3561	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	112:6f327212ef96	3562	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	112:6f327212ef96	3563	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	112:6f327212ef96	3564	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	112:6f327212ef96	3565	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	112:6f327212ef96	3566	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	112:6f327212ef96	3567	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	112:6f327212ef96	3568	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	112:6f327212ef96	3569	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	112:6f327212ef96	3570	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	112:6f327212ef96	3571	#define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	112:6f327212ef96	3572	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	112:6f327212ef96	3573	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	112:6f327212ef96	3574	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	112:6f327212ef96	3575	#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto	112:6f327212ef96	3576	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	112:6f327212ef96	3577	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	112:6f327212ef96	3578	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	112:6f327212ef96	3579	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	112:6f327212ef96	3580	/**
Kojto	112:6f327212ef96	3581	* @}
Kojto	112:6f327212ef96	3582	*/
Kojto	112:6f327212ef96	3583
Kojto	112:6f327212ef96	3584	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	3585	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	3586	*/
Kojto	112:6f327212ef96	3587	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	112:6f327212ef96	3588	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	112:6f327212ef96	3589	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	112:6f327212ef96	3590	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	3591	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	3592	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	3593
Kojto	112:6f327212ef96	3594	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto	112:6f327212ef96	3595	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	112:6f327212ef96	3596	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	112:6f327212ef96	3597	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	112:6f327212ef96	3598	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	112:6f327212ef96	3599	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	112:6f327212ef96	3600	/**
Kojto	112:6f327212ef96	3601	* @}
Kojto	112:6f327212ef96	3602	*/
Kojto	112:6f327212ef96	3603
Kojto	112:6f327212ef96	3604	/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3605	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3606	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3607	* power consumption.
Kojto	112:6f327212ef96	3608	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3609	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3610	*/
Kojto	112:6f327212ef96	3611	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	3612	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	3613	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	112:6f327212ef96	3614	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	112:6f327212ef96	3615	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	112:6f327212ef96	3616	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	112:6f327212ef96	3617	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	112:6f327212ef96	3618	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	3619	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	3620	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	3621	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	3622
Kojto	112:6f327212ef96	3623	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	112:6f327212ef96	3624	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	112:6f327212ef96	3625	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	112:6f327212ef96	3626	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	112:6f327212ef96	3627	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	112:6f327212ef96	3628	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	112:6f327212ef96	3629	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	112:6f327212ef96	3630	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto	112:6f327212ef96	3631	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	112:6f327212ef96	3632	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	112:6f327212ef96	3633	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	112:6f327212ef96	3634	/**
Kojto	112:6f327212ef96	3635	* @}
Kojto	112:6f327212ef96	3636	*/
Kojto	112:6f327212ef96	3637
Kojto	112:6f327212ef96	3638	/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3639	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3640	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3641	* power consumption.
Kojto	112:6f327212ef96	3642	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3643	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3644	* @{
Kojto	112:6f327212ef96	3645	*/
Kojto	112:6f327212ef96	3646	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	3647	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	112:6f327212ef96	3648
Kojto	112:6f327212ef96	3649	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	112:6f327212ef96	3650	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	112:6f327212ef96	3651
Kojto	112:6f327212ef96	3652	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	112:6f327212ef96	3653	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	112:6f327212ef96	3654	/**
Kojto	112:6f327212ef96	3655	* @}
Kojto	112:6f327212ef96	3656	*/
Kojto	112:6f327212ef96	3657
Kojto	112:6f327212ef96	3658	/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3659	* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3660	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3661	* power consumption.
Kojto	112:6f327212ef96	3662	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3663	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3664	*/
Kojto	112:6f327212ef96	3665	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	112:6f327212ef96	3666	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	112:6f327212ef96	3667
Kojto	112:6f327212ef96	3668	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	112:6f327212ef96	3669	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	112:6f327212ef96	3670	/**
Kojto	112:6f327212ef96	3671	* @}
Kojto	112:6f327212ef96	3672	*/
Kojto	112:6f327212ef96	3673
Kojto	112:6f327212ef96	3674	/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3675	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3676	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3677	* power consumption.
Kojto	112:6f327212ef96	3678	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3679	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3680	*/
Kojto	112:6f327212ef96	3681	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	3682	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	3683	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	112:6f327212ef96	3684	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	112:6f327212ef96	3685	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	112:6f327212ef96	3686	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	112:6f327212ef96	3687	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	3688	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	112:6f327212ef96	3689	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	112:6f327212ef96	3690	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	112:6f327212ef96	3691	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	112:6f327212ef96	3692	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	112:6f327212ef96	3693	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	112:6f327212ef96	3694	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	3695	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	3696	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	3697	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	3698	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	3699	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	3700
Kojto	112:6f327212ef96	3701	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	112:6f327212ef96	3702	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	112:6f327212ef96	3703	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	112:6f327212ef96	3704	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	112:6f327212ef96	3705	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	112:6f327212ef96	3706	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	112:6f327212ef96	3707	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	112:6f327212ef96	3708	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	112:6f327212ef96	3709	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	112:6f327212ef96	3710	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	112:6f327212ef96	3711	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	112:6f327212ef96	3712	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	112:6f327212ef96	3713	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	112:6f327212ef96	3714	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	112:6f327212ef96	3715	#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto	112:6f327212ef96	3716	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	112:6f327212ef96	3717	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	112:6f327212ef96	3718	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	112:6f327212ef96	3719	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	112:6f327212ef96	3720	/**
Kojto	112:6f327212ef96	3721	* @}
Kojto	112:6f327212ef96	3722	*/
Kojto	112:6f327212ef96	3723
Kojto	112:6f327212ef96	3724	/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	3725	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	3726	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	3727	* power consumption.
Kojto	112:6f327212ef96	3728	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	3729	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	3730	*/
Kojto	112:6f327212ef96	3731	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	112:6f327212ef96	3732	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	112:6f327212ef96	3733	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	112:6f327212ef96	3734	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	112:6f327212ef96	3735	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	112:6f327212ef96	3736	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	3737	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	3738	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	3739
Kojto	112:6f327212ef96	3740	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto	112:6f327212ef96	3741	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	112:6f327212ef96	3742	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	112:6f327212ef96	3743	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	112:6f327212ef96	3744	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	112:6f327212ef96	3745	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	112:6f327212ef96	3746	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	112:6f327212ef96	3747	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	112:6f327212ef96	3748	/**
Kojto	112:6f327212ef96	3749	* @}
Kojto	112:6f327212ef96	3750	*/
Kojto	112:6f327212ef96	3751
Kojto	112:6f327212ef96	3752	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	3753	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	3754	/------------------------------- PLL Configuration --------------------------/
Kojto	112:6f327212ef96	3755	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
Kojto	112:6f327212ef96	3756	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	3757	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	112:6f327212ef96	3758	* @note This function must be used only when the main PLL is disabled.
Kojto	112:6f327212ef96	3759	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	112:6f327212ef96	3760	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	3761	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	3762	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	3763	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	112:6f327212ef96	3764	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	112:6f327212ef96	3765	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	112:6f327212ef96	3766	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	112:6f327212ef96	3767	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	112:6f327212ef96	3768	* of 2 MHz to limit PLL jitter.
Kojto	112:6f327212ef96	3769	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	112:6f327212ef96	3770	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3771	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3772	* output frequency is between 192 and 432 MHz.
Kojto	112:6f327212ef96	3773	*
Kojto	112:6f327212ef96	3774	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	112:6f327212ef96	3775	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	112:6f327212ef96	3776	*
Kojto	112:6f327212ef96	3777	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	112:6f327212ef96	3778	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	3779	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	112:6f327212ef96	3780	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	112:6f327212ef96	3781	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	112:6f327212ef96	3782	* correctly.
Kojto	112:6f327212ef96	3783	*
Kojto	112:6f327212ef96	3784	* @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto	112:6f327212ef96	3785	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	3786	* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx devices.
Kojto	112:6f327212ef96	3787	*
Kojto	112:6f327212ef96	3788	*/
Kojto	112:6f327212ef96	3789	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto	112:6f327212ef96	3790	(RCC->PLLCFGR = ((__RCC_PLLSource__) \| (__PLLM__) \| \
Kojto	112:6f327212ef96	3791	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	112:6f327212ef96	3792	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	112:6f327212ef96	3793	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) \| \
Kojto	112:6f327212ef96	3794	((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto	112:6f327212ef96	3795	#else
Kojto	112:6f327212ef96	3796	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto	112:6f327212ef96	3797	* @note This function must be used only when the main PLL is disabled.
Kojto	112:6f327212ef96	3798	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	112:6f327212ef96	3799	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	3800	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	3801	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	3802	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto	112:6f327212ef96	3803	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	112:6f327212ef96	3804	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	112:6f327212ef96	3805	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	112:6f327212ef96	3806	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	112:6f327212ef96	3807	* of 2 MHz to limit PLL jitter.
Kojto	112:6f327212ef96	3808	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto	112:6f327212ef96	3809	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3810	* @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3811	* output frequency is between 192 and 432 MHz.
Kojto	112:6f327212ef96	3812	*
Kojto	112:6f327212ef96	3813	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto	112:6f327212ef96	3814	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	112:6f327212ef96	3815	*
Kojto	112:6f327212ef96	3816	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto	112:6f327212ef96	3817	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	3818	* @note If the USB OTG FS is used in your application, you have to set the
Kojto	112:6f327212ef96	3819	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto	112:6f327212ef96	3820	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto	112:6f327212ef96	3821	* correctly.
Kojto	112:6f327212ef96	3822	*
Kojto	112:6f327212ef96	3823	*/
Kojto	112:6f327212ef96	3824	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto	112:6f327212ef96	3825	(RCC->PLLCFGR = (0x20000000 \| (__RCC_PLLSource__) \| (__PLLM__)\| \
Kojto	112:6f327212ef96	3826	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
Kojto	112:6f327212ef96	3827	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
Kojto	112:6f327212ef96	3828	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto	112:6f327212ef96	3829	#endif /* STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	3830	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	3831
Kojto	112:6f327212ef96	3832	/----------------------------PLLI2S Configuration ---------------------------/
Kojto	112:6f327212ef96	3833	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	112:6f327212ef96	3834	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	112:6f327212ef96	3835	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	112:6f327212ef96	3836	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	3837
Kojto	112:6f327212ef96	3838	/** @brief Macros to enable or disable the PLLI2S.
Kojto	112:6f327212ef96	3839	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	3840	*/
Kojto	112:6f327212ef96	3841	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto	112:6f327212ef96	3842	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto	112:6f327212ef96	3843
Kojto	112:6f327212ef96	3844	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	112:6f327212ef96	3845	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	3846	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	3847	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	112:6f327212ef96	3848	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	112:6f327212ef96	3849	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	112:6f327212ef96	3850	* HAL_RCC_ClockConfig() API).
Kojto	112:6f327212ef96	3851	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	112:6f327212ef96	3852	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	112:6f327212ef96	3853	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	112:6f327212ef96	3854	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	112:6f327212ef96	3855	* of 1 MHz to limit PLLI2S jitter.
Kojto	112:6f327212ef96	3856	*
Kojto	112:6f327212ef96	3857	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	112:6f327212ef96	3858	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3859	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3860	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	3861	*
Kojto	112:6f327212ef96	3862	* @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto	112:6f327212ef96	3863	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	112:6f327212ef96	3864	* @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto	112:6f327212ef96	3865	*
Kojto	112:6f327212ef96	3866	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	112:6f327212ef96	3867	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	3868	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	112:6f327212ef96	3869	* on the I2S clock frequency.
Kojto	112:6f327212ef96	3870	*
Kojto	112:6f327212ef96	3871	* @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto	112:6f327212ef96	3872	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	3873	*/
Kojto	112:6f327212ef96	3874	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	112:6f327212ef96	3875	(RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	112:6f327212ef96	3876	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	112:6f327212ef96	3877	((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	112:6f327212ef96	3878	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	112:6f327212ef96	3879	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	112:6f327212ef96	3880	#else
Kojto	112:6f327212ef96	3881	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	112:6f327212ef96	3882	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	112:6f327212ef96	3883	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	112:6f327212ef96	3884	* HAL_RCC_ClockConfig() API).
Kojto	112:6f327212ef96	3885	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	112:6f327212ef96	3886	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3887	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3888	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	3889	*
Kojto	112:6f327212ef96	3890	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	112:6f327212ef96	3891	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	3892	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	112:6f327212ef96	3893	* on the I2S clock frequency.
Kojto	112:6f327212ef96	3894	*
Kojto	112:6f327212ef96	3895	*/
Kojto	112:6f327212ef96	3896	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto	112:6f327212ef96	3897	(RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	112:6f327212ef96	3898	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	112:6f327212ef96	3899	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	3900
Kojto	112:6f327212ef96	3901	#if defined(STM32F411xE)
Kojto	112:6f327212ef96	3902	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto	112:6f327212ef96	3903	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	112:6f327212ef96	3904	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	112:6f327212ef96	3905	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	112:6f327212ef96	3906	* HAL_RCC_ClockConfig() API).
Kojto	112:6f327212ef96	3907	* @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto	112:6f327212ef96	3908	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	112:6f327212ef96	3909	* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
Kojto	112:6f327212ef96	3910	* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto	112:6f327212ef96	3911	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	112:6f327212ef96	3912	* of 2 MHz to limit PLLI2S jitter.
Kojto	112:6f327212ef96	3913	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto	112:6f327212ef96	3914	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3915	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3916	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	3917	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	112:6f327212ef96	3918	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	3919	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	112:6f327212ef96	3920	* on the I2S clock frequency.
Kojto	112:6f327212ef96	3921	*/
Kojto	112:6f327212ef96	3922	#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) \|\
Kojto	112:6f327212ef96	3923	((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	112:6f327212ef96	3924	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto	112:6f327212ef96	3925	#endif /* STM32F411xE */
Kojto	112:6f327212ef96	3926
Kojto	112:6f327212ef96	3927	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	3928	/** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto	112:6f327212ef96	3929	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	112:6f327212ef96	3930	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	112:6f327212ef96	3931	* HAL_RCC_ClockConfig() API)
Kojto	112:6f327212ef96	3932	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	112:6f327212ef96	3933	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3934	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3935	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	3936	* @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto	112:6f327212ef96	3937	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	3938	* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
Kojto	112:6f327212ef96	3939	* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto	112:6f327212ef96	3940	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	112:6f327212ef96	3941	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	3942	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	112:6f327212ef96	3943	* on the I2S clock frequency.
Kojto	112:6f327212ef96	3944	*/
Kojto	112:6f327212ef96	3945	#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) \|\
Kojto	112:6f327212ef96	3946	((__PLLI2SQ__) << 24) \|\
Kojto	112:6f327212ef96	3947	((__PLLI2SR__) << 28))
Kojto	112:6f327212ef96	3948	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	3949	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	3950
Kojto	112:6f327212ef96	3951	/------------------------------ PLLSAI Configuration ------------------------/
Kojto	112:6f327212ef96	3952	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	3953	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	112:6f327212ef96	3954	* @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto	112:6f327212ef96	3955	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	3956	*/
Kojto	112:6f327212ef96	3957	#define __HAL_RCC_PLLSAI_ENABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = ENABLE)
Kojto	112:6f327212ef96	3958	#define __HAL_RCC_PLLSAI_DISABLE() ((__IO uint32_t ) RCC_CR_PLLSAION_BB = DISABLE)
Kojto	112:6f327212ef96	3959
Kojto	112:6f327212ef96	3960	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	3961	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	112:6f327212ef96	3962	*
Kojto	112:6f327212ef96	3963	* @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto	112:6f327212ef96	3964	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	112:6f327212ef96	3965	* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto	112:6f327212ef96	3966	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	112:6f327212ef96	3967	* of 1 MHz to limit PLLI2S jitter.
Kojto	112:6f327212ef96	3968	* @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto	112:6f327212ef96	3969	*
Kojto	112:6f327212ef96	3970	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	112:6f327212ef96	3971	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3972	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3973	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	3974	*
Kojto	112:6f327212ef96	3975	* @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto	112:6f327212ef96	3976	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	112:6f327212ef96	3977	* @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto	112:6f327212ef96	3978	*
Kojto	112:6f327212ef96	3979	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	112:6f327212ef96	3980	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	3981	*
Kojto	112:6f327212ef96	3982	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	112:6f327212ef96	3983	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	3984	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	112:6f327212ef96	3985	*/
Kojto	112:6f327212ef96	3986	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	112:6f327212ef96	3987	(RCC->PLLSAICFGR = ((__PLLSAIM__) \| \
Kojto	112:6f327212ef96	3988	((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	112:6f327212ef96	3989	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \| \
Kojto	112:6f327212ef96	3990	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto	112:6f327212ef96	3991	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	3992
Kojto	112:6f327212ef96	3993	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	3994	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	112:6f327212ef96	3995	*
Kojto	112:6f327212ef96	3996	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	112:6f327212ef96	3997	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	3998	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	3999	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	4000	*
Kojto	112:6f327212ef96	4001	* @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
Kojto	112:6f327212ef96	4002	* This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto	112:6f327212ef96	4003	*
Kojto	112:6f327212ef96	4004	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	112:6f327212ef96	4005	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	4006	*
Kojto	112:6f327212ef96	4007	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	112:6f327212ef96	4008	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	4009	*/
Kojto	112:6f327212ef96	4010	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	112:6f327212ef96	4011	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
Kojto	112:6f327212ef96	4012	((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
Kojto	112:6f327212ef96	4013	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
Kojto	112:6f327212ef96	4014	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	112:6f327212ef96	4015	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4016
Kojto	112:6f327212ef96	4017	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	112:6f327212ef96	4018	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	112:6f327212ef96	4019	*
Kojto	112:6f327212ef96	4020	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	112:6f327212ef96	4021	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto	112:6f327212ef96	4022	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	112:6f327212ef96	4023	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto	112:6f327212ef96	4024	*
Kojto	112:6f327212ef96	4025	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	112:6f327212ef96	4026	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	112:6f327212ef96	4027	*
Kojto	112:6f327212ef96	4028	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	112:6f327212ef96	4029	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	112:6f327212ef96	4030	* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto	112:6f327212ef96	4031	*/
Kojto	112:6f327212ef96	4032	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	112:6f327212ef96	4033	(RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \| \
Kojto	112:6f327212ef96	4034	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \| \
Kojto	112:6f327212ef96	4035	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto	112:6f327212ef96	4036	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	112:6f327212ef96	4037
Kojto	112:6f327212ef96	4038	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4039	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4040
Kojto	112:6f327212ef96	4041	/------------------- PLLSAI/PLLI2S Dividers Configuration -------------------/
Kojto	112:6f327212ef96	4042	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\|\
Kojto	112:6f327212ef96	4043	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4044	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	112:6f327212ef96	4045	* @note This function must be called before enabling the PLLI2S.
Kojto	112:6f327212ef96	4046	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
Kojto	112:6f327212ef96	4047	* This parameter must be a number between 1 and 32.
Kojto	112:6f327212ef96	4048	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	112:6f327212ef96	4049	*/
Kojto	112:6f327212ef96	4050	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto	112:6f327212ef96	4051
Kojto	112:6f327212ef96	4052	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	112:6f327212ef96	4053	* @note This function must be called before enabling the PLLSAI.
Kojto	112:6f327212ef96	4054	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	112:6f327212ef96	4055	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	112:6f327212ef96	4056	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	112:6f327212ef96	4057	*/
Kojto	112:6f327212ef96	4058	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto	112:6f327212ef96	4059	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4060
Kojto	112:6f327212ef96	4061	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4062	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	112:6f327212ef96	4063	*
Kojto	112:6f327212ef96	4064	* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	112:6f327212ef96	4065	* @note This function must be called before enabling the PLLSAI.
Kojto	112:6f327212ef96	4066	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	112:6f327212ef96	4067	* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto	112:6f327212ef96	4068	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	112:6f327212ef96	4069	*/
Kojto	112:6f327212ef96	4070	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto	112:6f327212ef96	4071	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4072	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4073
Kojto	112:6f327212ef96	4074	/------------------------- Peripheral Clock selection -----------------------/
Kojto	112:6f327212ef96	4075	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Kojto	112:6f327212ef96	4076	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	112:6f327212ef96	4077	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F469xx) \|\|\
Kojto	112:6f327212ef96	4078	defined(STM32F479xx)
Kojto	112:6f327212ef96	4079	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	112:6f327212ef96	4080	* @note This function must be called before enabling the I2S APB clock.
Kojto	112:6f327212ef96	4081	* @param __SOURCE__: specifies the I2S clock source.
Kojto	112:6f327212ef96	4082	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4083	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto	112:6f327212ef96	4084	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	112:6f327212ef96	4085	* used as I2S clock source.
Kojto	112:6f327212ef96	4086	*/
Kojto	112:6f327212ef96	4087	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
Kojto	112:6f327212ef96	4088	#endif /* STM32F40xxx \|\| STM32F41xxx \|\| STM32F42xxx \|\| STM32F43xxx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4089
Kojto	112:6f327212ef96	4090	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4091
Kojto	112:6f327212ef96	4092	/** @brief Macro to configure SAI1BlockA clock source selection.
Kojto	112:6f327212ef96	4093	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	112:6f327212ef96	4094	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	112:6f327212ef96	4095	* the SAI clock.
Kojto	112:6f327212ef96	4096	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	112:6f327212ef96	4097	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4098	* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	112:6f327212ef96	4099	* as SAI1 Block A clock.
Kojto	112:6f327212ef96	4100	* @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	112:6f327212ef96	4101	* as SAI1 Block A clock.
Kojto	112:6f327212ef96	4102	* @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	112:6f327212ef96	4103	* used as SAI1 Block A clock.
Kojto	112:6f327212ef96	4104	*/
Kojto	112:6f327212ef96	4105	#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4106
Kojto	112:6f327212ef96	4107	/** @brief Macro to configure SAI1BlockB clock source selection.
Kojto	112:6f327212ef96	4108	* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
Kojto	112:6f327212ef96	4109	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	112:6f327212ef96	4110	* the SAI clock.
Kojto	112:6f327212ef96	4111	* @param __SOURCE__: specifies the SAI Block B clock source.
Kojto	112:6f327212ef96	4112	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4113	* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	112:6f327212ef96	4114	* as SAI1 Block B clock.
Kojto	112:6f327212ef96	4115	* @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	112:6f327212ef96	4116	* as SAI1 Block B clock.
Kojto	112:6f327212ef96	4117	* @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto	112:6f327212ef96	4118	* used as SAI1 Block B clock.
Kojto	112:6f327212ef96	4119	*/
Kojto	112:6f327212ef96	4120	#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4121	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4122
Kojto	112:6f327212ef96	4123	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	4124	/** @brief Macro to configure SAI1 clock source selection.
Kojto	112:6f327212ef96	4125	* @note This configuration is only available with STM32F446xx Devices.
Kojto	112:6f327212ef96	4126	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	112:6f327212ef96	4127	* the SAI clock.
Kojto	112:6f327212ef96	4128	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	112:6f327212ef96	4129	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4130	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	112:6f327212ef96	4131	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	112:6f327212ef96	4132	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	112:6f327212ef96	4133	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	112:6f327212ef96	4134	*/
Kojto	112:6f327212ef96	4135	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4136
Kojto	112:6f327212ef96	4137	/** @brief Macro to Get SAI1 clock source selection.
Kojto	112:6f327212ef96	4138	* @note This configuration is only available with STM32F446xx Devices.
Kojto	112:6f327212ef96	4139	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4140	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto	112:6f327212ef96	4141	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto	112:6f327212ef96	4142	* @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	112:6f327212ef96	4143	* @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	112:6f327212ef96	4144	*/
Kojto	112:6f327212ef96	4145	#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto	112:6f327212ef96	4146
Kojto	112:6f327212ef96	4147	/** @brief Macro to configure SAI2 clock source selection.
Kojto	112:6f327212ef96	4148	* @note This configuration is only available with STM32F446xx Devices.
Kojto	112:6f327212ef96	4149	* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto	112:6f327212ef96	4150	* the SAI clock.
Kojto	112:6f327212ef96	4151	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	112:6f327212ef96	4152	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4153	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	112:6f327212ef96	4154	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	112:6f327212ef96	4155	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	112:6f327212ef96	4156	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	112:6f327212ef96	4157	*/
Kojto	112:6f327212ef96	4158	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4159
Kojto	112:6f327212ef96	4160	/** @brief Macro to Get SAI2 clock source selection.
Kojto	112:6f327212ef96	4161	* @note This configuration is only available with STM32F446xx Devices.
Kojto	112:6f327212ef96	4162	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4163	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto	112:6f327212ef96	4164	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto	112:6f327212ef96	4165	* @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto	112:6f327212ef96	4166	* @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto	112:6f327212ef96	4167	*/
Kojto	112:6f327212ef96	4168	#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto	112:6f327212ef96	4169
Kojto	112:6f327212ef96	4170	/** @brief Macro to configure I2S APB1 clock source selection.
Kojto	112:6f327212ef96	4171	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	112:6f327212ef96	4172	* @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto	112:6f327212ef96	4173	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4174	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	112:6f327212ef96	4175	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	112:6f327212ef96	4176	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	112:6f327212ef96	4177	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	112:6f327212ef96	4178	*/
Kojto	112:6f327212ef96	4179	#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4180
Kojto	112:6f327212ef96	4181	/** @brief Macro to Get I2S APB1 clock source selection.
Kojto	112:6f327212ef96	4182	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4183	* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	112:6f327212ef96	4184	* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	112:6f327212ef96	4185	* @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	112:6f327212ef96	4186	* @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	112:6f327212ef96	4187	*/
Kojto	112:6f327212ef96	4188	#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto	112:6f327212ef96	4189
Kojto	112:6f327212ef96	4190	/** @brief Macro to configure I2S APB2 clock source selection.
Kojto	112:6f327212ef96	4191	* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto	112:6f327212ef96	4192	* @param __SOURCE__: specifies the SAI Block A clock source.
Kojto	112:6f327212ef96	4193	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4194	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	112:6f327212ef96	4195	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	112:6f327212ef96	4196	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	112:6f327212ef96	4197	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	112:6f327212ef96	4198	*/
Kojto	112:6f327212ef96	4199	#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4200
Kojto	112:6f327212ef96	4201	/** @brief Macro to Get I2S APB2 clock source selection.
Kojto	112:6f327212ef96	4202	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4203	* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	112:6f327212ef96	4204	* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto	112:6f327212ef96	4205	* @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto	112:6f327212ef96	4206	* @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto	112:6f327212ef96	4207	*/
Kojto	112:6f327212ef96	4208	#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto	112:6f327212ef96	4209
Kojto	112:6f327212ef96	4210	/** @brief Macro to configure the CEC clock.
Kojto	112:6f327212ef96	4211	* @param __SOURCE__: specifies the CEC clock source.
Kojto	112:6f327212ef96	4212	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4213	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	112:6f327212ef96	4214	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	112:6f327212ef96	4215	*/
Kojto	112:6f327212ef96	4216	#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4217
Kojto	112:6f327212ef96	4218	/** @brief Macro to Get the CEC clock.
Kojto	112:6f327212ef96	4219	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4220	* @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto	112:6f327212ef96	4221	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	112:6f327212ef96	4222	*/
Kojto	112:6f327212ef96	4223	#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto	112:6f327212ef96	4224
Kojto	112:6f327212ef96	4225	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	112:6f327212ef96	4226	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	112:6f327212ef96	4227	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4228	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4229	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4230	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4231	*/
Kojto	112:6f327212ef96	4232	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4233
Kojto	112:6f327212ef96	4234	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	112:6f327212ef96	4235	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4236	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4237	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4238	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4239	*/
Kojto	112:6f327212ef96	4240	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	112:6f327212ef96	4241
Kojto	112:6f327212ef96	4242	/** @brief Macro to configure the CLK48 clock.
Kojto	112:6f327212ef96	4243	* @param __SOURCE__: specifies the CK48 clock source.
Kojto	112:6f327212ef96	4244	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4245	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	112:6f327212ef96	4246	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	112:6f327212ef96	4247	*/
Kojto	112:6f327212ef96	4248	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4249
Kojto	112:6f327212ef96	4250	/** @brief Macro to Get the CLK48 clock.
Kojto	112:6f327212ef96	4251	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4252	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	112:6f327212ef96	4253	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	112:6f327212ef96	4254	*/
Kojto	112:6f327212ef96	4255	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto	112:6f327212ef96	4256
Kojto	112:6f327212ef96	4257	/** @brief Macro to configure the SDIO clock.
Kojto	112:6f327212ef96	4258	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	112:6f327212ef96	4259	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4260	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	112:6f327212ef96	4261	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	112:6f327212ef96	4262	*/
Kojto	112:6f327212ef96	4263	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4264
Kojto	112:6f327212ef96	4265	/** @brief Macro to Get the SDIO clock.
Kojto	112:6f327212ef96	4266	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4267	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	112:6f327212ef96	4268	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	112:6f327212ef96	4269	*/
Kojto	112:6f327212ef96	4270	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto	112:6f327212ef96	4271
Kojto	112:6f327212ef96	4272	/** @brief Macro to configure the SPDIFRX clock.
Kojto	112:6f327212ef96	4273	* @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto	112:6f327212ef96	4274	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4275	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	112:6f327212ef96	4276	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	112:6f327212ef96	4277	*/
Kojto	112:6f327212ef96	4278	#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4279
Kojto	112:6f327212ef96	4280	/** @brief Macro to Get the SPDIFRX clock.
Kojto	112:6f327212ef96	4281	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4282	* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto	112:6f327212ef96	4283	* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto	112:6f327212ef96	4284	*/
Kojto	112:6f327212ef96	4285	#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto	112:6f327212ef96	4286	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	4287
Kojto	112:6f327212ef96	4288	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4289
Kojto	112:6f327212ef96	4290	/** @brief Macro to configure the CLK48 clock.
Kojto	112:6f327212ef96	4291	* @param __SOURCE__: specifies the CK48 clock source.
Kojto	112:6f327212ef96	4292	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4293	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	112:6f327212ef96	4294	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	112:6f327212ef96	4295	*/
Kojto	112:6f327212ef96	4296	#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4297
Kojto	112:6f327212ef96	4298	/** @brief Macro to Get the CLK48 clock.
Kojto	112:6f327212ef96	4299	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4300	* @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto	112:6f327212ef96	4301	* @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto	112:6f327212ef96	4302	*/
Kojto	112:6f327212ef96	4303	#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
Kojto	112:6f327212ef96	4304
Kojto	112:6f327212ef96	4305	/** @brief Macro to configure the SDIO clock.
Kojto	112:6f327212ef96	4306	* @param __SOURCE__: specifies the SDIO clock source.
Kojto	112:6f327212ef96	4307	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4308	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	112:6f327212ef96	4309	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	112:6f327212ef96	4310	*/
Kojto	112:6f327212ef96	4311	#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4312
Kojto	112:6f327212ef96	4313	/** @brief Macro to Get the SDIO clock.
Kojto	112:6f327212ef96	4314	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4315	* @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto	112:6f327212ef96	4316	* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto	112:6f327212ef96	4317	*/
Kojto	112:6f327212ef96	4318	#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
Kojto	112:6f327212ef96	4319
Kojto	112:6f327212ef96	4320	/** @brief Macro to configure the DSI clock.
Kojto	112:6f327212ef96	4321	* @param __SOURCE__: specifies the DSI clock source.
Kojto	112:6f327212ef96	4322	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4323	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	112:6f327212ef96	4324	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	112:6f327212ef96	4325	*/
Kojto	112:6f327212ef96	4326	#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4327
Kojto	112:6f327212ef96	4328	/** @brief Macro to Get the DSI clock.
Kojto	112:6f327212ef96	4329	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4330	* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto	112:6f327212ef96	4331	* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto	112:6f327212ef96	4332	*/
Kojto	112:6f327212ef96	4333	#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))
Kojto	112:6f327212ef96	4334
Kojto	112:6f327212ef96	4335	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4336
Kojto	112:6f327212ef96	4337	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	4338	/** @brief Macro to configure I2S clock source selection.
Kojto	112:6f327212ef96	4339	* @param __SOURCE__: specifies the I2S clock source.
Kojto	112:6f327212ef96	4340	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4341	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	112:6f327212ef96	4342	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	112:6f327212ef96	4343	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	112:6f327212ef96	4344	*/
Kojto	112:6f327212ef96	4345	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
Kojto	112:6f327212ef96	4346
Kojto	112:6f327212ef96	4347	/** @brief Macro to Get I2S clock source selection.
Kojto	112:6f327212ef96	4348	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4349	* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
Kojto	112:6f327212ef96	4350	* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
Kojto	112:6f327212ef96	4351	* @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
Kojto	112:6f327212ef96	4352	*/
Kojto	112:6f327212ef96	4353	#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
Kojto	112:6f327212ef96	4354
Kojto	112:6f327212ef96	4355	/** @brief Macro to configure the FMPI2C1 clock.
Kojto	112:6f327212ef96	4356	* @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto	112:6f327212ef96	4357	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4358	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4359	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4360	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4361	*/
Kojto	112:6f327212ef96	4362	#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4363
Kojto	112:6f327212ef96	4364	/** @brief Macro to Get the FMPI2C1 clock.
Kojto	112:6f327212ef96	4365	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4366	* @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4367	* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4368	* @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
Kojto	112:6f327212ef96	4369	*/
Kojto	112:6f327212ef96	4370	#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto	112:6f327212ef96	4371
Kojto	112:6f327212ef96	4372	/** @brief Macro to configure the LPTIM1 clock.
Kojto	112:6f327212ef96	4373	* @param __SOURCE__: specifies the LPTIM1 clock source.
Kojto	112:6f327212ef96	4374	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4375	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
Kojto	112:6f327212ef96	4376	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	112:6f327212ef96	4377	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	112:6f327212ef96	4378	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	112:6f327212ef96	4379	*/
Kojto	112:6f327212ef96	4380	#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
Kojto	112:6f327212ef96	4381
Kojto	112:6f327212ef96	4382	/** @brief Macro to Get the LPTIM1 clock.
Kojto	112:6f327212ef96	4383	* @retval The clock source can be one of the following values:
Kojto	112:6f327212ef96	4384	* @arg RCC_LPTIM1CLKSOURCE_PCLK: APB selected as LPTIM1 clock
Kojto	112:6f327212ef96	4385	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
Kojto	112:6f327212ef96	4386	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	112:6f327212ef96	4387	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	112:6f327212ef96	4388	*/
Kojto	112:6f327212ef96	4389	#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
Kojto	112:6f327212ef96	4390	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	4391
Kojto	112:6f327212ef96	4392	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	112:6f327212ef96	4393	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\|\
Kojto	112:6f327212ef96	4394	defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\|\
Kojto	112:6f327212ef96	4395	defined(STM32F479xx)
Kojto	112:6f327212ef96	4396	/** @brief Macro to configure the Timers clocks prescalers
Kojto	112:6f327212ef96	4397	* @note This feature is only available with STM32F429x/439x Devices.
Kojto	112:6f327212ef96	4398	* @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto	112:6f327212ef96	4399	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	4400	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto	112:6f327212ef96	4401	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto	112:6f327212ef96	4402	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto	112:6f327212ef96	4403	* division by 4 or more.
Kojto	112:6f327212ef96	4404	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto	112:6f327212ef96	4405	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto	112:6f327212ef96	4406	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto	112:6f327212ef96	4407	* to division by 8 or more.
Kojto	112:6f327212ef96	4408	*/
Kojto	112:6f327212ef96	4409	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) ((__IO uint32_t ) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Kojto	112:6f327212ef96	4410
Kojto	112:6f327212ef96	4411	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx) \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F410xx \|\| STM32F411xE \|\|\
Kojto	112:6f327212ef96	4412	STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4413
Kojto	112:6f327212ef96	4414	/----------------------------------------------------------------------------/
Kojto	112:6f327212ef96	4415
Kojto	112:6f327212ef96	4416	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4417	/** @brief Enable PLLSAI_RDY interrupt.
Kojto	112:6f327212ef96	4418	*/
Kojto	112:6f327212ef96	4419	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
Kojto	112:6f327212ef96	4420
Kojto	112:6f327212ef96	4421	/** @brief Disable PLLSAI_RDY interrupt.
Kojto	112:6f327212ef96	4422	*/
Kojto	112:6f327212ef96	4423	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto	112:6f327212ef96	4424
Kojto	112:6f327212ef96	4425	/** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto	112:6f327212ef96	4426	*/
Kojto	112:6f327212ef96	4427	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
Kojto	112:6f327212ef96	4428
Kojto	112:6f327212ef96	4429	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto	112:6f327212ef96	4430	* @retval The new state (TRUE or FALSE).
Kojto	112:6f327212ef96	4431	*/
Kojto	112:6f327212ef96	4432	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto	112:6f327212ef96	4433
Kojto	112:6f327212ef96	4434	/** @brief Check PLLSAI RDY flag is set or not.
Kojto	112:6f327212ef96	4435	* @retval The new state (TRUE or FALSE).
Kojto	112:6f327212ef96	4436	*/
Kojto	112:6f327212ef96	4437	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto	112:6f327212ef96	4438
Kojto	112:6f327212ef96	4439	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4440
Kojto	112:6f327212ef96	4441	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	4442	/** @defgroup RCCEx_MCO1_Enable MCO1 Enable
Kojto	112:6f327212ef96	4443	* @brief Macros to enable or disable the RCC MCO1 feature.
Kojto	112:6f327212ef96	4444	*/
Kojto	112:6f327212ef96	4445	#define __HAL_RCC_MCO1_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = ENABLE)
Kojto	112:6f327212ef96	4446	#define __HAL_RCC_MCO1_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO1EN_BB = DISABLE)
Kojto	112:6f327212ef96	4447	/**
Kojto	112:6f327212ef96	4448	* @}
Kojto	112:6f327212ef96	4449	*/
Kojto	112:6f327212ef96	4450
Kojto	112:6f327212ef96	4451	/** @defgroup RCCEx_MCO2_Enable MCO2 Enable
Kojto	112:6f327212ef96	4452	* @brief Macros to enable or disable the RCC MCO2 feature.
Kojto	112:6f327212ef96	4453	*/
Kojto	112:6f327212ef96	4454	#define __HAL_RCC_MCO2_ENABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = ENABLE)
Kojto	112:6f327212ef96	4455	#define __HAL_RCC_MCO2_DISABLE() ((__IO uint32_t ) RCC_CFGR_MCO2EN_BB = DISABLE)
Kojto	112:6f327212ef96	4456	/**
Kojto	112:6f327212ef96	4457	* @}
Kojto	112:6f327212ef96	4458	*/
Kojto	112:6f327212ef96	4459	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	4460
Kojto	112:6f327212ef96	4461	/**
Kojto	112:6f327212ef96	4462	* @}
Kojto	112:6f327212ef96	4463	*/
Kojto	112:6f327212ef96	4464
Kojto	112:6f327212ef96	4465	/* Exported functions --------------------------------------------------------*/
Kojto	112:6f327212ef96	4466	/** @addtogroup RCCEx_Exported_Functions
Kojto	112:6f327212ef96	4467	* @{
Kojto	112:6f327212ef96	4468	*/
Kojto	112:6f327212ef96	4469
Kojto	112:6f327212ef96	4470	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	112:6f327212ef96	4471	* @{
Kojto	112:6f327212ef96	4472	*/
Kojto	112:6f327212ef96	4473	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	112:6f327212ef96	4474	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	112:6f327212ef96	4475
Kojto	112:6f327212ef96	4476	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	4477	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	112:6f327212ef96	4478	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	4479
Kojto	112:6f327212ef96	4480	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F411xE) \|\|\
Kojto	112:6f327212ef96	4481	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4482	void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto	112:6f327212ef96	4483	#endif /* STM32F410xx \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4484	/**
Kojto	112:6f327212ef96	4485	* @}
Kojto	112:6f327212ef96	4486	*/
Kojto	112:6f327212ef96	4487
Kojto	112:6f327212ef96	4488	/**
Kojto	112:6f327212ef96	4489	* @}
Kojto	112:6f327212ef96	4490	*/
Kojto	112:6f327212ef96	4491	/* Private types -------------------------------------------------------------*/
Kojto	112:6f327212ef96	4492	/* Private variables ---------------------------------------------------------*/
Kojto	112:6f327212ef96	4493	/* Private constants ---------------------------------------------------------*/
Kojto	112:6f327212ef96	4494	/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto	112:6f327212ef96	4495	* @{
Kojto	112:6f327212ef96	4496	*/
Kojto	112:6f327212ef96	4497
Kojto	112:6f327212ef96	4498	/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	112:6f327212ef96	4499	* @brief RCC registers bit address in the alias region
Kojto	112:6f327212ef96	4500	* @{
Kojto	112:6f327212ef96	4501	*/
Kojto	112:6f327212ef96	4502	/* --- CR Register ---*/
Kojto	112:6f327212ef96	4503	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	112:6f327212ef96	4504	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4505	/* Alias word address of PLLSAION bit */
Kojto	112:6f327212ef96	4506	#define RCC_PLLSAION_BIT_NUMBER 0x1C
Kojto	112:6f327212ef96	4507	#define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	4508
Kojto	112:6f327212ef96	4509	#define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto	112:6f327212ef96	4510	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4511
Kojto	112:6f327212ef96	4512	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	112:6f327212ef96	4513	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	112:6f327212ef96	4514	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	112:6f327212ef96	4515	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4516	/* Alias word address of PLLI2SON bit */
Kojto	112:6f327212ef96	4517	#define RCC_PLLI2SON_BIT_NUMBER 0x1A
Kojto	112:6f327212ef96	4518	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	4519	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	112:6f327212ef96	4520	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4521
Kojto	112:6f327212ef96	4522	/* --- DCKCFGR Register ---*/
Kojto	112:6f327212ef96	4523	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	112:6f327212ef96	4524	defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx) \|\| defined(STM32F446xx) \|\|\
Kojto	112:6f327212ef96	4525	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4526	/* Alias word address of TIMPRE bit */
Kojto	112:6f327212ef96	4527	#define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto	112:6f327212ef96	4528	#define RCC_TIMPRE_BIT_NUMBER 0x18
Kojto	112:6f327212ef96	4529	#define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	4530	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F410xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4531
Kojto	112:6f327212ef96	4532	/* --- CFGR Register ---*/
Kojto	112:6f327212ef96	4533	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto	112:6f327212ef96	4534	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	112:6f327212ef96	4535	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	112:6f327212ef96	4536	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	112:6f327212ef96	4537	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4538	/* Alias word address of I2SSRC bit */
Kojto	112:6f327212ef96	4539	#define RCC_I2SSRC_BIT_NUMBER 0x17
Kojto	112:6f327212ef96	4540	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	4541
Kojto	112:6f327212ef96	4542	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto	112:6f327212ef96	4543	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	112:6f327212ef96	4544	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4545
Kojto	112:6f327212ef96	4546	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	4547	/* Alias word address of MCO1EN bit */
Kojto	112:6f327212ef96	4548	#define RCC_MCO1EN_BIT_NUMBER 0x8
Kojto	112:6f327212ef96	4549	#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	4550
Kojto	112:6f327212ef96	4551	/* Alias word address of MCO2EN bit */
Kojto	112:6f327212ef96	4552	#define RCC_MCO2EN_BIT_NUMBER 0x9
Kojto	112:6f327212ef96	4553	#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	4554	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	4555
Kojto	112:6f327212ef96	4556	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	112:6f327212ef96	4557	/**
Kojto	112:6f327212ef96	4558	* @}
Kojto	112:6f327212ef96	4559	*/
Kojto	112:6f327212ef96	4560
Kojto	112:6f327212ef96	4561	/**
Kojto	112:6f327212ef96	4562	* @}
Kojto	112:6f327212ef96	4563	*/
Kojto	112:6f327212ef96	4564
Kojto	112:6f327212ef96	4565	/* Private macros ------------------------------------------------------------*/
Kojto	112:6f327212ef96	4566	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	112:6f327212ef96	4567	* @{
Kojto	112:6f327212ef96	4568	*/
Kojto	112:6f327212ef96	4569	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	112:6f327212ef96	4570	* @{
Kojto	112:6f327212ef96	4571	*/
Kojto	112:6f327212ef96	4572
Kojto	112:6f327212ef96	4573	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx)
Kojto	112:6f327212ef96	4574	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000007F))
Kojto	112:6f327212ef96	4575	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	112:6f327212ef96	4576
Kojto	112:6f327212ef96	4577	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
Kojto	112:6f327212ef96	4578	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Kojto	112:6f327212ef96	4579	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000007))
Kojto	112:6f327212ef96	4580	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
Kojto	112:6f327212ef96	4581
Kojto	112:6f327212ef96	4582	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	4583	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000001F))
Kojto	112:6f327212ef96	4584	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	4585
Kojto	112:6f327212ef96	4586	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	4587	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000FFF))
Kojto	112:6f327212ef96	4588	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	4589
Kojto	112:6f327212ef96	4590	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4591	#define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000001FF))
Kojto	112:6f327212ef96	4592	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4593
Kojto	112:6f327212ef96	4594	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto	112:6f327212ef96	4595	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	112:6f327212ef96	4596
Kojto	112:6f327212ef96	4597
Kojto	112:6f327212ef96	4598	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx)\|\| defined(STM32F439xx) \|\|\
Kojto	112:6f327212ef96	4599	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4600	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	112:6f327212ef96	4601
Kojto	112:6f327212ef96	4602	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto	112:6f327212ef96	4603
Kojto	112:6f327212ef96	4604	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	112:6f327212ef96	4605
Kojto	112:6f327212ef96	4606	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	112:6f327212ef96	4607
Kojto	112:6f327212ef96	4608	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	112:6f327212ef96	4609
Kojto	112:6f327212ef96	4610	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	112:6f327212ef96	4611
Kojto	112:6f327212ef96	4612	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	112:6f327212ef96	4613	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	112:6f327212ef96	4614	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	112:6f327212ef96	4615	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	112:6f327212ef96	4616	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4617
Kojto	112:6f327212ef96	4618	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
Kojto	112:6f327212ef96	4619	#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	112:6f327212ef96	4620
Kojto	112:6f327212ef96	4621	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	112:6f327212ef96	4622	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	112:6f327212ef96	4623	#endif /* STM32F411xE \|\| STM32F446xx */
Kojto	112:6f327212ef96	4624
Kojto	112:6f327212ef96	4625	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	4626	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	112:6f327212ef96	4627
Kojto	112:6f327212ef96	4628	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	112:6f327212ef96	4629	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	112:6f327212ef96	4630
Kojto	112:6f327212ef96	4631	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	112:6f327212ef96	4632	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	112:6f327212ef96	4633	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	112:6f327212ef96	4634
Kojto	112:6f327212ef96	4635	#define IS_RCC_LPTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\|\
Kojto	112:6f327212ef96	4636	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\|\
Kojto	112:6f327212ef96	4637	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\|\
Kojto	112:6f327212ef96	4638	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto	112:6f327212ef96	4639
Kojto	112:6f327212ef96	4640	#define IS_RCC_I2SAPBCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4641	((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) \|\|\
Kojto	112:6f327212ef96	4642	((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
Kojto	112:6f327212ef96	4643	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	4644
Kojto	112:6f327212ef96	4645	#if defined(STM32F446xx)
Kojto	112:6f327212ef96	4646	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	112:6f327212ef96	4647
Kojto	112:6f327212ef96	4648	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	112:6f327212ef96	4649	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	112:6f327212ef96	4650	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	112:6f327212ef96	4651	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	112:6f327212ef96	4652
Kojto	112:6f327212ef96	4653	#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	112:6f327212ef96	4654
Kojto	112:6f327212ef96	4655	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	112:6f327212ef96	4656	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	112:6f327212ef96	4657	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	112:6f327212ef96	4658	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	112:6f327212ef96	4659
Kojto	112:6f327212ef96	4660	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\|\
Kojto	112:6f327212ef96	4661	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\|\
Kojto	112:6f327212ef96	4662	((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4663	((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto	112:6f327212ef96	4664
Kojto	112:6f327212ef96	4665	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\|\
Kojto	112:6f327212ef96	4666	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\|\
Kojto	112:6f327212ef96	4667	((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4668	((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto	112:6f327212ef96	4669
Kojto	112:6f327212ef96	4670	#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) \|\|\
Kojto	112:6f327212ef96	4671	((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) \|\|\
Kojto	112:6f327212ef96	4672	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4673	((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto	112:6f327212ef96	4674
Kojto	112:6f327212ef96	4675	#define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) \|\|\
Kojto	112:6f327212ef96	4676	((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) \|\|\
Kojto	112:6f327212ef96	4677	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4678	((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto	112:6f327212ef96	4679
Kojto	112:6f327212ef96	4680	#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) \|\|\
Kojto	112:6f327212ef96	4681	((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) \|\|\
Kojto	112:6f327212ef96	4682	((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto	112:6f327212ef96	4683
Kojto	112:6f327212ef96	4684	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\|\
Kojto	112:6f327212ef96	4685	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	112:6f327212ef96	4686
Kojto	112:6f327212ef96	4687	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
Kojto	112:6f327212ef96	4688	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto	112:6f327212ef96	4689
Kojto	112:6f327212ef96	4690	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
Kojto	112:6f327212ef96	4691	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	112:6f327212ef96	4692
Kojto	112:6f327212ef96	4693	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4694	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto	112:6f327212ef96	4695	#endif /* STM32F446xx */
Kojto	112:6f327212ef96	4696
Kojto	112:6f327212ef96	4697	#if defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4698	#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	112:6f327212ef96	4699
Kojto	112:6f327212ef96	4700	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	112:6f327212ef96	4701	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	112:6f327212ef96	4702	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	112:6f327212ef96	4703	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	112:6f327212ef96	4704
Kojto	112:6f327212ef96	4705	#define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) \|\|\
Kojto	112:6f327212ef96	4706	((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto	112:6f327212ef96	4707
Kojto	112:6f327212ef96	4708	#define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) \|\|\
Kojto	112:6f327212ef96	4709	((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto	112:6f327212ef96	4710
Kojto	112:6f327212ef96	4711	#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) \|\|\
Kojto	112:6f327212ef96	4712	((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
Kojto	112:6f327212ef96	4713
Kojto	112:6f327212ef96	4714	#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) \|\|\
Kojto	112:6f327212ef96	4715	((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto	112:6f327212ef96	4716	#endif /* STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4717
Kojto	112:6f327212ef96	4718	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Kojto	112:6f327212ef96	4719	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Kojto	112:6f327212ef96	4720	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Kojto	112:6f327212ef96	4721	defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	112:6f327212ef96	4722
Kojto	112:6f327212ef96	4723	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
Kojto	112:6f327212ef96	4724	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	112:6f327212ef96	4725
Kojto	112:6f327212ef96	4726	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Kojto	112:6f327212ef96	4727	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	112:6f327212ef96	4728
Kojto	112:6f327212ef96	4729	#if defined(STM32F410Tx) \|\| defined(STM32F410Cx) \|\| defined(STM32F410Rx)
Kojto	112:6f327212ef96	4730	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)\|\| \
Kojto	112:6f327212ef96	4731	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto	112:6f327212ef96	4732	#endif /* STM32F410Tx \|\| STM32F410Cx \|\| STM32F410Rx */
Kojto	112:6f327212ef96	4733	/**
Kojto	112:6f327212ef96	4734	* @}
Kojto	112:6f327212ef96	4735	*/
Kojto	112:6f327212ef96	4736
Kojto	112:6f327212ef96	4737	/**
Kojto	112:6f327212ef96	4738	* @}
Kojto	112:6f327212ef96	4739	*/
Kojto	112:6f327212ef96	4740
Kojto	112:6f327212ef96	4741	/**
Kojto	112:6f327212ef96	4742	* @}
Kojto	112:6f327212ef96	4743	*/
Kojto	112:6f327212ef96	4744
Kojto	112:6f327212ef96	4745	/**
Kojto	112:6f327212ef96	4746	* @}
Kojto	112:6f327212ef96	4747	*/
Kojto	112:6f327212ef96	4748	#ifdef __cplusplus
Kojto	112:6f327212ef96	4749	}
Kojto	112:6f327212ef96	4750	#endif
Kojto	112:6f327212ef96	4751
Kojto	112:6f327212ef96	4752	#endif /* __STM32F4xx_HAL_RCC_EX_H */
Kojto	112:6f327212ef96	4753
Kojto	112:6f327212ef96	4754	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
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The code in this repository is Apache licensed.

TARGET_B96B_F446VE/stm32f4xx_hal_rcc_ex.h@121:672067c3ada4, 2016-04-14 (annotated)

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