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TARGET_B96B_F446VE/stm32f4xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

Committer:: elijahorr
Date:: Thu Apr 14 07:28:54 2016 +0000
Revision:: 121:672067c3ada4
Parent:: 116:c0f6e94411f5

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	112:6f327212ef96	1	/**
Kojto	112:6f327212ef96	2	******************************************************************************
Kojto	112:6f327212ef96	3	* @file stm32f4xx_hal_rcc.h
Kojto	112:6f327212ef96	4	* @author MCD Application Team
Kojto	112:6f327212ef96	5	* @version V1.4.1
Kojto	112:6f327212ef96	6	* @date 09-October-2015
Kojto	112:6f327212ef96	7	* @brief Header file of RCC HAL module.
Kojto	112:6f327212ef96	8	******************************************************************************
Kojto	112:6f327212ef96	9	* @attention
Kojto	112:6f327212ef96	10	*
Kojto	112:6f327212ef96	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	112:6f327212ef96	12	*
Kojto	112:6f327212ef96	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	112:6f327212ef96	14	* are permitted provided that the following conditions are met:
Kojto	112:6f327212ef96	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	112:6f327212ef96	16	* this list of conditions and the following disclaimer.
Kojto	112:6f327212ef96	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	112:6f327212ef96	18	* this list of conditions and the following disclaimer in the documentation
Kojto	112:6f327212ef96	19	* and/or other materials provided with the distribution.
Kojto	112:6f327212ef96	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	112:6f327212ef96	21	* may be used to endorse or promote products derived from this software
Kojto	112:6f327212ef96	22	* without specific prior written permission.
Kojto	112:6f327212ef96	23	*
Kojto	112:6f327212ef96	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	112:6f327212ef96	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	112:6f327212ef96	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	112:6f327212ef96	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	112:6f327212ef96	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	112:6f327212ef96	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	112:6f327212ef96	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	112:6f327212ef96	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	112:6f327212ef96	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	112:6f327212ef96	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	112:6f327212ef96	34	*
Kojto	112:6f327212ef96	35	******************************************************************************
Kojto	112:6f327212ef96	36	*/
Kojto	112:6f327212ef96	37
Kojto	112:6f327212ef96	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	112:6f327212ef96	39	#ifndef __STM32F4xx_HAL_RCC_H
Kojto	112:6f327212ef96	40	#define __STM32F4xx_HAL_RCC_H
Kojto	112:6f327212ef96	41
Kojto	112:6f327212ef96	42	#ifdef __cplusplus
Kojto	112:6f327212ef96	43	extern "C" {
Kojto	112:6f327212ef96	44	#endif
Kojto	112:6f327212ef96	45
Kojto	112:6f327212ef96	46	/* Includes ------------------------------------------------------------------*/
Kojto	112:6f327212ef96	47	#include "stm32f4xx_hal_def.h"
Kojto	112:6f327212ef96	48
Kojto	112:6f327212ef96	49	/* Include RCC HAL Extended module */
Kojto	112:6f327212ef96	50	/* (include on top of file since RCC structures are defined in extended file) */
Kojto	112:6f327212ef96	51	#include "stm32f4xx_hal_rcc_ex.h"
Kojto	112:6f327212ef96	52
Kojto	112:6f327212ef96	53	/** @addtogroup STM32F4xx_HAL_Driver
Kojto	112:6f327212ef96	54	* @{
Kojto	112:6f327212ef96	55	*/
Kojto	112:6f327212ef96	56
Kojto	112:6f327212ef96	57	/** @addtogroup RCC
Kojto	112:6f327212ef96	58	* @{
Kojto	112:6f327212ef96	59	*/
Kojto	112:6f327212ef96	60
Kojto	112:6f327212ef96	61	/* Exported types ------------------------------------------------------------*/
Kojto	112:6f327212ef96	62	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	112:6f327212ef96	63	* @{
Kojto	112:6f327212ef96	64	*/
Kojto	112:6f327212ef96	65
Kojto	112:6f327212ef96	66	/**
Kojto	112:6f327212ef96	67	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	112:6f327212ef96	68	*/
Kojto	112:6f327212ef96	69	typedef struct
Kojto	112:6f327212ef96	70	{
Kojto	112:6f327212ef96	71	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	112:6f327212ef96	72	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	112:6f327212ef96	73
Kojto	112:6f327212ef96	74	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	112:6f327212ef96	75	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	112:6f327212ef96	76
Kojto	112:6f327212ef96	77	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	112:6f327212ef96	78	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	112:6f327212ef96	79
Kojto	112:6f327212ef96	80	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	112:6f327212ef96	81	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	112:6f327212ef96	82
Kojto	112:6f327212ef96	83	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	112:6f327212ef96	84	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	112:6f327212ef96	85
Kojto	112:6f327212ef96	86	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	112:6f327212ef96	87	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	112:6f327212ef96	88
Kojto	112:6f327212ef96	89	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	112:6f327212ef96	90
Kojto	112:6f327212ef96	91	}RCC_OscInitTypeDef;
Kojto	112:6f327212ef96	92
Kojto	112:6f327212ef96	93	/**
Kojto	112:6f327212ef96	94	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	112:6f327212ef96	95	*/
Kojto	112:6f327212ef96	96	typedef struct
Kojto	112:6f327212ef96	97	{
Kojto	112:6f327212ef96	98	uint32_t ClockType; /*!< The clock to be configured.
Kojto	112:6f327212ef96	99	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	112:6f327212ef96	100
Kojto	112:6f327212ef96	101	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	112:6f327212ef96	102	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	112:6f327212ef96	103
Kojto	112:6f327212ef96	104	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	112:6f327212ef96	105	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	112:6f327212ef96	106
Kojto	112:6f327212ef96	107	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	112:6f327212ef96	108	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	112:6f327212ef96	109
Kojto	112:6f327212ef96	110	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	112:6f327212ef96	111	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	112:6f327212ef96	112
Kojto	112:6f327212ef96	113	}RCC_ClkInitTypeDef;
Kojto	112:6f327212ef96	114
Kojto	112:6f327212ef96	115	/**
Kojto	112:6f327212ef96	116	* @}
Kojto	112:6f327212ef96	117	*/
Kojto	112:6f327212ef96	118
Kojto	112:6f327212ef96	119	/* Exported constants --------------------------------------------------------*/
Kojto	112:6f327212ef96	120	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	112:6f327212ef96	121	* @{
Kojto	112:6f327212ef96	122	*/
Kojto	112:6f327212ef96	123
Kojto	112:6f327212ef96	124	/** @defgroup RCC_Oscillator_Type Oscillator Type
Kojto	112:6f327212ef96	125	* @{
Kojto	112:6f327212ef96	126	*/
Kojto	112:6f327212ef96	127	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	128	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	129	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	130	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	131	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	132	/**
Kojto	112:6f327212ef96	133	* @}
Kojto	112:6f327212ef96	134	*/
Kojto	112:6f327212ef96	135
Kojto	112:6f327212ef96	136	/** @defgroup RCC_HSE_Config HSE Config
Kojto	112:6f327212ef96	137	* @{
Kojto	112:6f327212ef96	138	*/
Kojto	112:6f327212ef96	139	#define RCC_HSE_OFF ((uint8_t)0x00)
Kojto	112:6f327212ef96	140	#define RCC_HSE_ON ((uint8_t)0x01)
Kojto	112:6f327212ef96	141	#define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto	112:6f327212ef96	142	/**
Kojto	112:6f327212ef96	143	* @}
Kojto	112:6f327212ef96	144	*/
Kojto	112:6f327212ef96	145
Kojto	112:6f327212ef96	146	/** @defgroup RCC_LSE_Config LSE Config
Kojto	112:6f327212ef96	147	* @{
Kojto	112:6f327212ef96	148	*/
Kojto	112:6f327212ef96	149	#define RCC_LSE_OFF ((uint8_t)0x00)
Kojto	112:6f327212ef96	150	#define RCC_LSE_ON ((uint8_t)0x01)
Kojto	112:6f327212ef96	151	#define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto	112:6f327212ef96	152	/**
Kojto	112:6f327212ef96	153	* @}
Kojto	112:6f327212ef96	154	*/
Kojto	112:6f327212ef96	155
Kojto	112:6f327212ef96	156	/** @defgroup RCC_HSI_Config HSI Config
Kojto	112:6f327212ef96	157	* @{
Kojto	112:6f327212ef96	158	*/
Kojto	112:6f327212ef96	159	#define RCC_HSI_OFF ((uint8_t)0x00)
Kojto	112:6f327212ef96	160	#define RCC_HSI_ON ((uint8_t)0x01)
Kojto	112:6f327212ef96	161	/**
Kojto	112:6f327212ef96	162	* @}
Kojto	112:6f327212ef96	163	*/
Kojto	112:6f327212ef96	164
Kojto	112:6f327212ef96	165	/** @defgroup RCC_LSI_Config LSI Config
Kojto	112:6f327212ef96	166	* @{
Kojto	112:6f327212ef96	167	*/
Kojto	112:6f327212ef96	168	#define RCC_LSI_OFF ((uint8_t)0x00)
Kojto	112:6f327212ef96	169	#define RCC_LSI_ON ((uint8_t)0x01)
Kojto	112:6f327212ef96	170	/**
Kojto	112:6f327212ef96	171	* @}
Kojto	112:6f327212ef96	172	*/
Kojto	112:6f327212ef96	173
Kojto	112:6f327212ef96	174	/** @defgroup RCC_PLL_Config PLL Config
Kojto	112:6f327212ef96	175	* @{
Kojto	112:6f327212ef96	176	*/
Kojto	112:6f327212ef96	177	#define RCC_PLL_NONE ((uint8_t)0x00)
Kojto	112:6f327212ef96	178	#define RCC_PLL_OFF ((uint8_t)0x01)
Kojto	112:6f327212ef96	179	#define RCC_PLL_ON ((uint8_t)0x02)
Kojto	112:6f327212ef96	180	/**
Kojto	112:6f327212ef96	181	* @}
Kojto	112:6f327212ef96	182	*/
Kojto	112:6f327212ef96	183
Kojto	112:6f327212ef96	184	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
Kojto	112:6f327212ef96	185	* @{
Kojto	112:6f327212ef96	186	*/
Kojto	112:6f327212ef96	187	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	188	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	189	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
Kojto	112:6f327212ef96	190	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	191	/**
Kojto	112:6f327212ef96	192	* @}
Kojto	112:6f327212ef96	193	*/
Kojto	112:6f327212ef96	194
Kojto	112:6f327212ef96	195	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
Kojto	112:6f327212ef96	196	* @{
Kojto	112:6f327212ef96	197	*/
Kojto	112:6f327212ef96	198	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
Kojto	112:6f327212ef96	199	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
Kojto	112:6f327212ef96	200	/**
Kojto	112:6f327212ef96	201	* @}
Kojto	112:6f327212ef96	202	*/
Kojto	112:6f327212ef96	203
Kojto	112:6f327212ef96	204	/** @defgroup RCC_System_Clock_Type System Clock Type
Kojto	112:6f327212ef96	205	* @{
Kojto	112:6f327212ef96	206	*/
Kojto	112:6f327212ef96	207	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	208	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	112:6f327212ef96	209	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	112:6f327212ef96	210	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	112:6f327212ef96	211	/**
Kojto	112:6f327212ef96	212	* @}
Kojto	112:6f327212ef96	213	*/
Kojto	112:6f327212ef96	214
Kojto	112:6f327212ef96	215	/** @defgroup RCC_System_Clock_Source System Clock Source
Kojto	112:6f327212ef96	216	* @{
Kojto	112:6f327212ef96	217	*/
Kojto	112:6f327212ef96	218	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	112:6f327212ef96	219	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	112:6f327212ef96	220	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	112:6f327212ef96	221	#define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1))
Kojto	112:6f327212ef96	222	/**
Kojto	112:6f327212ef96	223	* @}
Kojto	112:6f327212ef96	224	*/
Kojto	112:6f327212ef96	225
Kojto	112:6f327212ef96	226	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto	112:6f327212ef96	227	* @{
Kojto	112:6f327212ef96	228	*/
Kojto	112:6f327212ef96	229	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
Kojto	112:6f327212ef96	230	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
Kojto	112:6f327212ef96	231	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
Kojto	112:6f327212ef96	232	#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 \| RCC_CFGR_SW_1)) /!< PLLR used as system clock /
Kojto	112:6f327212ef96	233	/**
Kojto	112:6f327212ef96	234	* @}
Kojto	112:6f327212ef96	235	*/
Kojto	112:6f327212ef96	236
Kojto	112:6f327212ef96	237	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
Kojto	112:6f327212ef96	238	* @{
Kojto	112:6f327212ef96	239	*/
Kojto	112:6f327212ef96	240	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	112:6f327212ef96	241	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	112:6f327212ef96	242	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	112:6f327212ef96	243	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	112:6f327212ef96	244	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	112:6f327212ef96	245	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	112:6f327212ef96	246	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	112:6f327212ef96	247	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	112:6f327212ef96	248	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	112:6f327212ef96	249	/**
Kojto	112:6f327212ef96	250	* @}
Kojto	112:6f327212ef96	251	*/
Kojto	112:6f327212ef96	252
Kojto	112:6f327212ef96	253	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
Kojto	112:6f327212ef96	254	* @{
Kojto	112:6f327212ef96	255	*/
Kojto	112:6f327212ef96	256	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
Kojto	112:6f327212ef96	257	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
Kojto	112:6f327212ef96	258	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
Kojto	112:6f327212ef96	259	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
Kojto	112:6f327212ef96	260	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
Kojto	112:6f327212ef96	261	/**
Kojto	112:6f327212ef96	262	* @}
Kojto	112:6f327212ef96	263	*/
Kojto	112:6f327212ef96	264
Kojto	112:6f327212ef96	265	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
Kojto	112:6f327212ef96	266	* @{
Kojto	112:6f327212ef96	267	*/
Kojto	112:6f327212ef96	268	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
Kojto	112:6f327212ef96	269	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
Kojto	112:6f327212ef96	270	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
Kojto	112:6f327212ef96	271	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
Kojto	112:6f327212ef96	272	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
Kojto	112:6f327212ef96	273	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
Kojto	112:6f327212ef96	274	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
Kojto	112:6f327212ef96	275	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
Kojto	112:6f327212ef96	276	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
Kojto	112:6f327212ef96	277	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
Kojto	112:6f327212ef96	278	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
Kojto	112:6f327212ef96	279	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
Kojto	112:6f327212ef96	280	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
Kojto	112:6f327212ef96	281	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
Kojto	112:6f327212ef96	282	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
Kojto	112:6f327212ef96	283	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
Kojto	112:6f327212ef96	284	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
Kojto	112:6f327212ef96	285	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
Kojto	112:6f327212ef96	286	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
Kojto	112:6f327212ef96	287	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
Kojto	112:6f327212ef96	288	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
Kojto	112:6f327212ef96	289	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
Kojto	112:6f327212ef96	290	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
Kojto	112:6f327212ef96	291	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
Kojto	112:6f327212ef96	292	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
Kojto	112:6f327212ef96	293	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
Kojto	112:6f327212ef96	294	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
Kojto	112:6f327212ef96	295	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
Kojto	112:6f327212ef96	296	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
Kojto	112:6f327212ef96	297	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
Kojto	112:6f327212ef96	298	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
Kojto	112:6f327212ef96	299	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
Kojto	112:6f327212ef96	300	/**
Kojto	112:6f327212ef96	301	* @}
Kojto	112:6f327212ef96	302	*/
Kojto	112:6f327212ef96	303
Kojto	112:6f327212ef96	304	/** @defgroup RCC_MCO_Index MCO Index
Kojto	112:6f327212ef96	305	* @{
Kojto	112:6f327212ef96	306	*/
Kojto	112:6f327212ef96	307	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	308	#define RCC_MCO2 ((uint32_t)0x00000001)
Kojto	112:6f327212ef96	309	/**
Kojto	112:6f327212ef96	310	* @}
Kojto	112:6f327212ef96	311	*/
Kojto	112:6f327212ef96	312
Kojto	112:6f327212ef96	313	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
Kojto	112:6f327212ef96	314	* @{
Kojto	112:6f327212ef96	315	*/
Kojto	112:6f327212ef96	316	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	317	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
Kojto	112:6f327212ef96	318	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
Kojto	112:6f327212ef96	319	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
Kojto	112:6f327212ef96	320	/**
Kojto	112:6f327212ef96	321	* @}
Kojto	112:6f327212ef96	322	*/
Kojto	112:6f327212ef96	323
Kojto	112:6f327212ef96	324	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
Kojto	112:6f327212ef96	325	* @{
Kojto	112:6f327212ef96	326	*/
Kojto	112:6f327212ef96	327	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
Kojto	112:6f327212ef96	328	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
Kojto	112:6f327212ef96	329	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
Kojto	112:6f327212ef96	330	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
Kojto	112:6f327212ef96	331	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
Kojto	112:6f327212ef96	332	/**
Kojto	112:6f327212ef96	333	* @}
Kojto	112:6f327212ef96	334	*/
Kojto	112:6f327212ef96	335
Kojto	112:6f327212ef96	336	/** @defgroup RCC_Interrupt Interrupts
Kojto	112:6f327212ef96	337	* @{
Kojto	112:6f327212ef96	338	*/
Kojto	112:6f327212ef96	339	#define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto	112:6f327212ef96	340	#define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto	112:6f327212ef96	341	#define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto	112:6f327212ef96	342	#define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto	112:6f327212ef96	343	#define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto	112:6f327212ef96	344	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
Kojto	112:6f327212ef96	345	#define RCC_IT_CSS ((uint8_t)0x80)
Kojto	112:6f327212ef96	346	/**
Kojto	112:6f327212ef96	347	* @}
Kojto	112:6f327212ef96	348	*/
Kojto	112:6f327212ef96	349
Kojto	112:6f327212ef96	350	/** @defgroup RCC_Flag Flags
Kojto	112:6f327212ef96	351	* Elements values convention: 0XXYYYYYb
Kojto	112:6f327212ef96	352	* - YYYYY : Flag position in the register
Kojto	112:6f327212ef96	353	* - 0XX : Register index
Kojto	112:6f327212ef96	354	* - 01: CR register
Kojto	112:6f327212ef96	355	* - 10: BDCR register
Kojto	112:6f327212ef96	356	* - 11: CSR register
Kojto	112:6f327212ef96	357	* @{
Kojto	112:6f327212ef96	358	*/
Kojto	112:6f327212ef96	359	/* Flags in the CR register */
Kojto	112:6f327212ef96	360	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
Kojto	112:6f327212ef96	361	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
Kojto	112:6f327212ef96	362	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
Kojto	112:6f327212ef96	363	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
Kojto	112:6f327212ef96	364
Kojto	112:6f327212ef96	365	/* Flags in the BDCR register */
Kojto	112:6f327212ef96	366	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
Kojto	112:6f327212ef96	367
Kojto	112:6f327212ef96	368	/* Flags in the CSR register */
Kojto	112:6f327212ef96	369	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
Kojto	112:6f327212ef96	370	#define RCC_FLAG_BORRST ((uint8_t)0x79)
Kojto	112:6f327212ef96	371	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
Kojto	112:6f327212ef96	372	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
Kojto	112:6f327212ef96	373	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
Kojto	112:6f327212ef96	374	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
Kojto	112:6f327212ef96	375	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
Kojto	112:6f327212ef96	376	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
Kojto	112:6f327212ef96	377	/**
Kojto	112:6f327212ef96	378	* @}
Kojto	112:6f327212ef96	379	*/
Kojto	112:6f327212ef96	380
Kojto	112:6f327212ef96	381	/**
Kojto	112:6f327212ef96	382	* @}
Kojto	112:6f327212ef96	383	*/
Kojto	112:6f327212ef96	384
Kojto	112:6f327212ef96	385	/* Exported macro ------------------------------------------------------------*/
Kojto	112:6f327212ef96	386	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	112:6f327212ef96	387	* @{
Kojto	112:6f327212ef96	388	*/
Kojto	112:6f327212ef96	389
Kojto	112:6f327212ef96	390	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	391	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	112:6f327212ef96	392	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	393	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	394	* using it.
Kojto	112:6f327212ef96	395	* @{
Kojto	112:6f327212ef96	396	*/
Kojto	112:6f327212ef96	397	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	398	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	399	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto	112:6f327212ef96	400	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	401	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto	112:6f327212ef96	402	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	403	} while(0)
Kojto	112:6f327212ef96	404	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	405	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	406	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto	112:6f327212ef96	407	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	408	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto	112:6f327212ef96	409	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	410	} while(0)
Kojto	112:6f327212ef96	411	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	412	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	413	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto	112:6f327212ef96	414	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	415	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto	112:6f327212ef96	416	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	417	} while(0)
Kojto	112:6f327212ef96	418	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	419	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	420	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto	112:6f327212ef96	421	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	422	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto	112:6f327212ef96	423	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	424	} while(0)
Kojto	112:6f327212ef96	425	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	426	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	427	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto	112:6f327212ef96	428	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	429	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto	112:6f327212ef96	430	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	431	} while(0)
Kojto	112:6f327212ef96	432	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	433	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	434	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto	112:6f327212ef96	435	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	436	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto	112:6f327212ef96	437	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	438	} while(0)
Kojto	112:6f327212ef96	439
Kojto	112:6f327212ef96	440	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto	112:6f327212ef96	441	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto	112:6f327212ef96	442	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto	112:6f327212ef96	443	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto	112:6f327212ef96	444	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto	112:6f327212ef96	445	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto	112:6f327212ef96	446
Kojto	112:6f327212ef96	447	/**
Kojto	112:6f327212ef96	448	* @}
Kojto	112:6f327212ef96	449	*/
Kojto	112:6f327212ef96	450
Kojto	112:6f327212ef96	451	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	452	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	112:6f327212ef96	453	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	454	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	455	* using it.
Kojto	112:6f327212ef96	456	* @{
Kojto	112:6f327212ef96	457	*/
Kojto	112:6f327212ef96	458	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	459	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	460	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto	112:6f327212ef96	461	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	462	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto	112:6f327212ef96	463	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	464	} while(0)
Kojto	112:6f327212ef96	465	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	466	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	467	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	112:6f327212ef96	468	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	469	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto	112:6f327212ef96	470	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	471	} while(0)
Kojto	112:6f327212ef96	472	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	473	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	474	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	112:6f327212ef96	475	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	476	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	112:6f327212ef96	477	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	478	} while(0)
Kojto	112:6f327212ef96	479	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	480	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	481	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	112:6f327212ef96	482	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	483	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	112:6f327212ef96	484	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	485	} while(0)
Kojto	112:6f327212ef96	486	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	487	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	488	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	112:6f327212ef96	489	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	490	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	112:6f327212ef96	491	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	492	} while(0)
Kojto	112:6f327212ef96	493	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	494	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	495	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	112:6f327212ef96	496	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	497	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	112:6f327212ef96	498	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	499	} while(0)
Kojto	112:6f327212ef96	500	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	501	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	502	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	112:6f327212ef96	503	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	504	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto	112:6f327212ef96	505	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	506	} while(0)
Kojto	112:6f327212ef96	507
Kojto	112:6f327212ef96	508	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto	112:6f327212ef96	509	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	112:6f327212ef96	510	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	112:6f327212ef96	511	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	112:6f327212ef96	512	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	112:6f327212ef96	513	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	112:6f327212ef96	514	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	112:6f327212ef96	515	/**
Kojto	112:6f327212ef96	516	* @}
Kojto	112:6f327212ef96	517	*/
Kojto	112:6f327212ef96	518
Kojto	112:6f327212ef96	519	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto	112:6f327212ef96	520	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	112:6f327212ef96	521	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	112:6f327212ef96	522	* is disabled and the application software has to enable this clock before
Kojto	112:6f327212ef96	523	* using it.
Kojto	112:6f327212ef96	524	* @{
Kojto	112:6f327212ef96	525	*/
Kojto	112:6f327212ef96	526	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	527	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	528	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	112:6f327212ef96	529	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	530	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	112:6f327212ef96	531	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	532	} while(0)
Kojto	112:6f327212ef96	533	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	534	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	535	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	112:6f327212ef96	536	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	537	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	112:6f327212ef96	538	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	539	} while(0)
Kojto	112:6f327212ef96	540	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	541	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	542	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	112:6f327212ef96	543	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	544	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	112:6f327212ef96	545	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	546	} while(0)
Kojto	112:6f327212ef96	547	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	548	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	549	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	112:6f327212ef96	550	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	551	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	112:6f327212ef96	552	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	553	} while(0)
Kojto	112:6f327212ef96	554	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	555	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	556	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	112:6f327212ef96	557	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	558	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	112:6f327212ef96	559	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	560	} while(0)
Kojto	112:6f327212ef96	561	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	562	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	563	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	112:6f327212ef96	564	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	565	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto	112:6f327212ef96	566	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	567	} while(0)
Kojto	112:6f327212ef96	568	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	569	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	570	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto	112:6f327212ef96	571	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	572	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto	112:6f327212ef96	573	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	574	} while(0)
Kojto	112:6f327212ef96	575	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto	112:6f327212ef96	576	__IO uint32_t tmpreg; \
Kojto	112:6f327212ef96	577	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto	112:6f327212ef96	578	/* Delay after an RCC peripheral clock enabling */ \
Kojto	112:6f327212ef96	579	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto	112:6f327212ef96	580	UNUSED(tmpreg); \
Kojto	112:6f327212ef96	581	} while(0)
Kojto	112:6f327212ef96	582
Kojto	112:6f327212ef96	583	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	112:6f327212ef96	584	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	112:6f327212ef96	585	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	112:6f327212ef96	586	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	112:6f327212ef96	587	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	112:6f327212ef96	588	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	112:6f327212ef96	589	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto	112:6f327212ef96	590	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto	112:6f327212ef96	591	/**
Kojto	112:6f327212ef96	592	* @}
Kojto	112:6f327212ef96	593	*/
Kojto	112:6f327212ef96	594
Kojto	112:6f327212ef96	595	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto	112:6f327212ef96	596	* @brief Force or release AHB1 peripheral reset.
Kojto	112:6f327212ef96	597	* @{
Kojto	112:6f327212ef96	598	*/
Kojto	112:6f327212ef96	599	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	600	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
Kojto	112:6f327212ef96	601	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
Kojto	112:6f327212ef96	602	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
Kojto	112:6f327212ef96	603	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
Kojto	112:6f327212ef96	604	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
Kojto	112:6f327212ef96	605	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
Kojto	112:6f327212ef96	606
Kojto	112:6f327212ef96	607	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto	112:6f327212ef96	608	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto	112:6f327212ef96	609	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto	112:6f327212ef96	610	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto	112:6f327212ef96	611	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto	112:6f327212ef96	612	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto	112:6f327212ef96	613	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto	112:6f327212ef96	614	/**
Kojto	112:6f327212ef96	615	* @}
Kojto	112:6f327212ef96	616	*/
Kojto	112:6f327212ef96	617
Kojto	112:6f327212ef96	618	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto	112:6f327212ef96	619	* @brief Force or release APB1 peripheral reset.
Kojto	112:6f327212ef96	620	* @{
Kojto	112:6f327212ef96	621	*/
Kojto	112:6f327212ef96	622	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	623	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
Kojto	112:6f327212ef96	624	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	112:6f327212ef96	625	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	112:6f327212ef96	626	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	112:6f327212ef96	627	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	112:6f327212ef96	628	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	112:6f327212ef96	629	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	112:6f327212ef96	630
Kojto	112:6f327212ef96	631	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	112:6f327212ef96	632	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto	112:6f327212ef96	633	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	112:6f327212ef96	634	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	112:6f327212ef96	635	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	112:6f327212ef96	636	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	112:6f327212ef96	637	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	112:6f327212ef96	638	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	112:6f327212ef96	639	/**
Kojto	112:6f327212ef96	640	* @}
Kojto	112:6f327212ef96	641	*/
Kojto	112:6f327212ef96	642
Kojto	112:6f327212ef96	643	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto	112:6f327212ef96	644	* @brief Force or release APB2 peripheral reset.
Kojto	112:6f327212ef96	645	* @{
Kojto	112:6f327212ef96	646	*/
Kojto	112:6f327212ef96	647	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	112:6f327212ef96	648	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	112:6f327212ef96	649	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	112:6f327212ef96	650	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	112:6f327212ef96	651	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
Kojto	112:6f327212ef96	652	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	112:6f327212ef96	653	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	112:6f327212ef96	654	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
Kojto	112:6f327212ef96	655	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
Kojto	112:6f327212ef96	656
Kojto	112:6f327212ef96	657	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	112:6f327212ef96	658	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	112:6f327212ef96	659	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	112:6f327212ef96	660	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	112:6f327212ef96	661	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto	112:6f327212ef96	662	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	112:6f327212ef96	663	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	112:6f327212ef96	664	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto	112:6f327212ef96	665	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto	112:6f327212ef96	666	/**
Kojto	112:6f327212ef96	667	* @}
Kojto	112:6f327212ef96	668	*/
Kojto	112:6f327212ef96	669
Kojto	112:6f327212ef96	670	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	671	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	672	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	673	* power consumption.
Kojto	112:6f327212ef96	674	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	675	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	676	* @{
Kojto	112:6f327212ef96	677	*/
Kojto	112:6f327212ef96	678	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
Kojto	112:6f327212ef96	679	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto	112:6f327212ef96	680	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto	112:6f327212ef96	681	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto	112:6f327212ef96	682	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
Kojto	112:6f327212ef96	683	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
Kojto	112:6f327212ef96	684
Kojto	112:6f327212ef96	685	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto	112:6f327212ef96	686	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto	112:6f327212ef96	687	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto	112:6f327212ef96	688	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto	112:6f327212ef96	689	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto	112:6f327212ef96	690	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto	112:6f327212ef96	691	/**
Kojto	112:6f327212ef96	692	* @}
Kojto	112:6f327212ef96	693	*/
Kojto	112:6f327212ef96	694
Kojto	112:6f327212ef96	695	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	696	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	697	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	698	* power consumption.
Kojto	112:6f327212ef96	699	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	700	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	701	* @{
Kojto	112:6f327212ef96	702	*/
Kojto	112:6f327212ef96	703	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
Kojto	112:6f327212ef96	704	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
Kojto	112:6f327212ef96	705	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
Kojto	112:6f327212ef96	706	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
Kojto	112:6f327212ef96	707	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
Kojto	112:6f327212ef96	708	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
Kojto	112:6f327212ef96	709	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
Kojto	112:6f327212ef96	710
Kojto	112:6f327212ef96	711	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto	112:6f327212ef96	712	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto	112:6f327212ef96	713	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto	112:6f327212ef96	714	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto	112:6f327212ef96	715	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto	112:6f327212ef96	716	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto	112:6f327212ef96	717	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto	112:6f327212ef96	718	/**
Kojto	112:6f327212ef96	719	* @}
Kojto	112:6f327212ef96	720	*/
Kojto	112:6f327212ef96	721
Kojto	112:6f327212ef96	722	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto	112:6f327212ef96	723	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	112:6f327212ef96	724	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	112:6f327212ef96	725	* power consumption.
Kojto	112:6f327212ef96	726	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
Kojto	112:6f327212ef96	727	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	112:6f327212ef96	728	* @{
Kojto	112:6f327212ef96	729	*/
Kojto	112:6f327212ef96	730	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
Kojto	112:6f327212ef96	731	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
Kojto	112:6f327212ef96	732	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
Kojto	112:6f327212ef96	733	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
Kojto	112:6f327212ef96	734	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
Kojto	112:6f327212ef96	735	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto	112:6f327212ef96	736	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
Kojto	112:6f327212ef96	737	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
Kojto	112:6f327212ef96	738
Kojto	112:6f327212ef96	739	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto	112:6f327212ef96	740	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto	112:6f327212ef96	741	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto	112:6f327212ef96	742	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto	112:6f327212ef96	743	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto	112:6f327212ef96	744	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto	112:6f327212ef96	745	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto	112:6f327212ef96	746	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto	112:6f327212ef96	747	/**
Kojto	112:6f327212ef96	748	* @}
Kojto	112:6f327212ef96	749	*/
Kojto	112:6f327212ef96	750
Kojto	112:6f327212ef96	751	/** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto	112:6f327212ef96	752	* @{
Kojto	112:6f327212ef96	753	*/
Kojto	112:6f327212ef96	754
Kojto	112:6f327212ef96	755	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	112:6f327212ef96	756	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	757	* It is used (enabled by hardware) as system clock source after startup
Kojto	112:6f327212ef96	758	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
Kojto	112:6f327212ef96	759	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	112:6f327212ef96	760	* Security System CSS is enabled).
Kojto	112:6f327212ef96	761	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	112:6f327212ef96	762	* you have to select another source of the system clock then stop the HSI.
Kojto	112:6f327212ef96	763	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	112:6f327212ef96	764	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	112:6f327212ef96	765	* system clock source.
Kojto	112:6f327212ef96	766	* This parameter can be: ENABLE or DISABLE.
Kojto	112:6f327212ef96	767	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	112:6f327212ef96	768	* clock cycles.
Kojto	112:6f327212ef96	769	*/
Kojto	112:6f327212ef96	770	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
Kojto	112:6f327212ef96	771	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
Kojto	112:6f327212ef96	772
Kojto	112:6f327212ef96	773	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	112:6f327212ef96	774	* @note The calibration is used to compensate for the variations in voltage
Kojto	112:6f327212ef96	775	* and temperature that influence the frequency of the internal HSI RC.
Kojto	112:6f327212ef96	776	* @param __HSICalibrationValue__: specifies the calibration trimming value.
Kojto	112:6f327212ef96	777	* This parameter must be a number between 0 and 0x1F.
Kojto	112:6f327212ef96	778	*/
Kojto	112:6f327212ef96	779	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
Kojto	112:6f327212ef96	780	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto	112:6f327212ef96	781	/**
Kojto	112:6f327212ef96	782	* @}
Kojto	112:6f327212ef96	783	*/
Kojto	112:6f327212ef96	784
Kojto	112:6f327212ef96	785	/** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto	112:6f327212ef96	786	* @{
Kojto	112:6f327212ef96	787	*/
Kojto	112:6f327212ef96	788
Kojto	112:6f327212ef96	789	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	112:6f327212ef96	790	* @note After enabling the LSI, the application software should wait on
Kojto	112:6f327212ef96	791	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	112:6f327212ef96	792	* be used to clock the IWDG and/or the RTC.
Kojto	112:6f327212ef96	793	* @note LSI can not be disabled if the IWDG is running.
Kojto	112:6f327212ef96	794	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	112:6f327212ef96	795	* clock cycles.
Kojto	112:6f327212ef96	796	*/
Kojto	112:6f327212ef96	797	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
Kojto	112:6f327212ef96	798	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
Kojto	112:6f327212ef96	799	/**
Kojto	112:6f327212ef96	800	* @}
Kojto	112:6f327212ef96	801	*/
Kojto	112:6f327212ef96	802
Kojto	112:6f327212ef96	803	/** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto	112:6f327212ef96	804	* @{
Kojto	112:6f327212ef96	805	*/
Kojto	112:6f327212ef96	806
Kojto	112:6f327212ef96	807	/**
Kojto	112:6f327212ef96	808	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	112:6f327212ef96	809	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto	112:6f327212ef96	810	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
Kojto	112:6f327212ef96	811	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	112:6f327212ef96	812	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	112:6f327212ef96	813	* is stable and can be used to clock the PLL and/or system clock.
Kojto	112:6f327212ef96	814	* @note HSE state can not be changed if it is used directly or through the
Kojto	112:6f327212ef96	815	* PLL as system clock. In this case, you have to select another source
Kojto	112:6f327212ef96	816	* of the system clock then change the HSE state (ex. disable it).
Kojto	112:6f327212ef96	817	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	818	* @note This function reset the CSSON bit, so if the clock security system(CSS)
Kojto	112:6f327212ef96	819	* was previously enabled you have to enable it again after calling this
Kojto	112:6f327212ef96	820	* function.
Kojto	112:6f327212ef96	821	* @param __STATE__: specifies the new state of the HSE.
Kojto	112:6f327212ef96	822	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	823	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	112:6f327212ef96	824	* 6 HSE oscillator clock cycles.
Kojto	112:6f327212ef96	825	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
Kojto	112:6f327212ef96	826	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
Kojto	112:6f327212ef96	827	*/
Kojto	112:6f327212ef96	828	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto	112:6f327212ef96	829	/**
Kojto	112:6f327212ef96	830	* @}
Kojto	112:6f327212ef96	831	*/
Kojto	112:6f327212ef96	832
Kojto	112:6f327212ef96	833	/** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto	112:6f327212ef96	834	* @{
Kojto	112:6f327212ef96	835	*/
Kojto	112:6f327212ef96	836
Kojto	112:6f327212ef96	837	/**
Kojto	112:6f327212ef96	838	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	112:6f327212ef96	839	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto	112:6f327212ef96	840	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
Kojto	112:6f327212ef96	841	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	112:6f327212ef96	842	* this domain after reset, you have to enable write access using
Kojto	112:6f327212ef96	843	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	112:6f327212ef96	844	* (to be done once after reset).
Kojto	112:6f327212ef96	845	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	112:6f327212ef96	846	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	112:6f327212ef96	847	* is stable and can be used to clock the RTC.
Kojto	112:6f327212ef96	848	* @param __STATE__: specifies the new state of the LSE.
Kojto	112:6f327212ef96	849	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	850	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	112:6f327212ef96	851	* 6 LSE oscillator clock cycles.
Kojto	112:6f327212ef96	852	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
Kojto	112:6f327212ef96	853	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
Kojto	112:6f327212ef96	854	*/
Kojto	112:6f327212ef96	855	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto	112:6f327212ef96	856
Kojto	112:6f327212ef96	857	/**
Kojto	112:6f327212ef96	858	* @}
Kojto	112:6f327212ef96	859	*/
Kojto	112:6f327212ef96	860
Kojto	112:6f327212ef96	861	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto	112:6f327212ef96	862	* @{
Kojto	112:6f327212ef96	863	*/
Kojto	112:6f327212ef96	864
Kojto	112:6f327212ef96	865	/** @brief Macros to enable or disable the RTC clock.
Kojto	112:6f327212ef96	866	* @note These macros must be used only after the RTC clock source was selected.
Kojto	112:6f327212ef96	867	*/
Kojto	112:6f327212ef96	868	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto	112:6f327212ef96	869	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
Kojto	112:6f327212ef96	870
Kojto	112:6f327212ef96	871	/** @brief Macros to configure the RTC clock (RTCCLK).
Kojto	112:6f327212ef96	872	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	112:6f327212ef96	873	* access is denied to this domain after reset, you have to enable write
Kojto	112:6f327212ef96	874	* access using the Power Backup Access macro before to configure
Kojto	112:6f327212ef96	875	* the RTC clock source (to be done once after reset).
Kojto	112:6f327212ef96	876	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	112:6f327212ef96	877	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto	112:6f327212ef96	878	* a Power On Reset (POR).
Kojto	112:6f327212ef96	879	* @param __RTCCLKSource__: specifies the RTC clock source.
Kojto	112:6f327212ef96	880	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	881	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
Kojto	112:6f327212ef96	882	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
Kojto	112:6f327212ef96	883	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
Kojto	112:6f327212ef96	884	* as RTC clock, where x:[2,31]
Kojto	112:6f327212ef96	885	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	112:6f327212ef96	886	* work in STOP and STANDBY modes, and can be used as wake-up source.
Kojto	112:6f327212ef96	887	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	112:6f327212ef96	888	* cannot be used in STOP and STANDBY modes.
Kojto	112:6f327212ef96	889	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	112:6f327212ef96	890	* RTC clock source).
Kojto	112:6f327212ef96	891	*/
Kojto	112:6f327212ef96	892	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
Kojto	112:6f327212ef96	893	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
Kojto	112:6f327212ef96	894
Kojto	112:6f327212ef96	895	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
Kojto	112:6f327212ef96	896	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
Kojto	112:6f327212ef96	897	} while (0)
Kojto	112:6f327212ef96	898
Kojto	112:6f327212ef96	899	/** @brief Macros to force or release the Backup domain reset.
Kojto	112:6f327212ef96	900	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	112:6f327212ef96	901	* and the RTC clock source selection in RCC_CSR register.
Kojto	112:6f327212ef96	902	* @note The BKPSRAM is not affected by this reset.
Kojto	112:6f327212ef96	903	*/
Kojto	112:6f327212ef96	904	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
Kojto	112:6f327212ef96	905	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
Kojto	112:6f327212ef96	906	/**
Kojto	112:6f327212ef96	907	* @}
Kojto	112:6f327212ef96	908	*/
Kojto	112:6f327212ef96	909
Kojto	112:6f327212ef96	910	/** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto	112:6f327212ef96	911	* @{
Kojto	112:6f327212ef96	912	*/
Kojto	112:6f327212ef96	913
Kojto	112:6f327212ef96	914	/** @brief Macros to enable or disable the main PLL.
Kojto	112:6f327212ef96	915	* @note After enabling the main PLL, the application software should wait on
Kojto	112:6f327212ef96	916	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	112:6f327212ef96	917	* be used as system clock source.
Kojto	112:6f327212ef96	918	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	112:6f327212ef96	919	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	112:6f327212ef96	920	*/
Kojto	112:6f327212ef96	921	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
Kojto	112:6f327212ef96	922	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
Kojto	112:6f327212ef96	923
Kojto	112:6f327212ef96	924	/** @brief Macro to configure the PLL clock source.
Kojto	112:6f327212ef96	925	* @note This function must be used only when the main PLL is disabled.
Kojto	112:6f327212ef96	926	* @param __PLLSOURCE__: specifies the PLL entry clock source.
Kojto	112:6f327212ef96	927	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	928	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	929	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	112:6f327212ef96	930	*
Kojto	112:6f327212ef96	931	*/
Kojto	112:6f327212ef96	932	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto	112:6f327212ef96	933
Kojto	112:6f327212ef96	934	/** @brief Macro to configure the PLL multiplication factor.
Kojto	112:6f327212ef96	935	* @note This function must be used only when the main PLL is disabled.
Kojto	112:6f327212ef96	936	* @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto	112:6f327212ef96	937	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto	112:6f327212ef96	938	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto	112:6f327212ef96	939	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto	112:6f327212ef96	940	* of 2 MHz to limit PLL jitter.
Kojto	112:6f327212ef96	941	*
Kojto	112:6f327212ef96	942	*/
Kojto	112:6f327212ef96	943	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto	112:6f327212ef96	944	/**
Kojto	112:6f327212ef96	945	* @}
Kojto	112:6f327212ef96	946	*/
Kojto	112:6f327212ef96	947
Kojto	112:6f327212ef96	948	/** @defgroup RCC_Get_Clock_source Get Clock source
Kojto	112:6f327212ef96	949	* @{
Kojto	112:6f327212ef96	950	*/
Kojto	112:6f327212ef96	951	/**
Kojto	112:6f327212ef96	952	* @brief Macro to configure the system clock source.
Kojto	112:6f327212ef96	953	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto	112:6f327212ef96	954	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	955	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto	112:6f327212ef96	956	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto	112:6f327212ef96	957	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto	112:6f327212ef96	958	* - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto	112:6f327212ef96	959	*/
Kojto	112:6f327212ef96	960	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
Kojto	112:6f327212ef96	961
Kojto	112:6f327212ef96	962	/** @brief Macro to get the clock source used as system clock.
Kojto	112:6f327212ef96	963	* @retval The clock source used as system clock. The returned value can be one
Kojto	112:6f327212ef96	964	* of the following:
Kojto	112:6f327212ef96	965	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto	112:6f327212ef96	966	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto	112:6f327212ef96	967	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto	112:6f327212ef96	968	* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
Kojto	112:6f327212ef96	969	*/
Kojto	112:6f327212ef96	970	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
Kojto	112:6f327212ef96	971
Kojto	112:6f327212ef96	972	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	112:6f327212ef96	973	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	112:6f327212ef96	974	* of the following:
Kojto	112:6f327212ef96	975	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	112:6f327212ef96	976	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	112:6f327212ef96	977	*/
Kojto	112:6f327212ef96	978	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto	112:6f327212ef96	979	/**
Kojto	112:6f327212ef96	980	* @}
Kojto	112:6f327212ef96	981	*/
Kojto	112:6f327212ef96	982
Kojto	112:6f327212ef96	983	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	112:6f327212ef96	984	* @{
Kojto	112:6f327212ef96	985	*/
Kojto	112:6f327212ef96	986
Kojto	112:6f327212ef96	987	/** @brief Macro to configure the MCO1 clock.
Kojto	112:6f327212ef96	988	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	112:6f327212ef96	989	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	990	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
Kojto	112:6f327212ef96	991	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
Kojto	112:6f327212ef96	992	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
Kojto	112:6f327212ef96	993	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
Kojto	112:6f327212ef96	994	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	112:6f327212ef96	995	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	996	* @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto	112:6f327212ef96	997	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto	112:6f327212ef96	998	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto	112:6f327212ef96	999	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto	112:6f327212ef96	1000	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto	112:6f327212ef96	1001	*/
Kojto	112:6f327212ef96	1002
Kojto	112:6f327212ef96	1003	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	112:6f327212ef96	1004	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
Kojto	112:6f327212ef96	1005
Kojto	112:6f327212ef96	1006	/** @brief Macro to configure the MCO2 clock.
Kojto	112:6f327212ef96	1007	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
Kojto	112:6f327212ef96	1008	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1009	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
Kojto	112:6f327212ef96	1010	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
Kojto	112:6f327212ef96	1011	* @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
Kojto	112:6f327212ef96	1012	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
Kojto	112:6f327212ef96	1013	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
Kojto	112:6f327212ef96	1014	* @param __MCODIV__ specifies the MCO clock prescaler.
Kojto	112:6f327212ef96	1015	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1016	* @arg RCC_MCODIV_1: no division applied to MCOx clock
Kojto	112:6f327212ef96	1017	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
Kojto	112:6f327212ef96	1018	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
Kojto	112:6f327212ef96	1019	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
Kojto	112:6f327212ef96	1020	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
Kojto	112:6f327212ef96	1021	* @note For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
Kojto	112:6f327212ef96	1022	* at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
Kojto	112:6f327212ef96	1023	*/
Kojto	112:6f327212ef96	1024
Kojto	112:6f327212ef96	1025	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
Kojto	112:6f327212ef96	1026	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), (__MCOCLKSOURCE__ \| (__MCODIV__ << 3)));
Kojto	112:6f327212ef96	1027	/**
Kojto	112:6f327212ef96	1028	* @}
Kojto	112:6f327212ef96	1029	*/
Kojto	112:6f327212ef96	1030
Kojto	112:6f327212ef96	1031	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto	112:6f327212ef96	1032	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	112:6f327212ef96	1033	* @{
Kojto	112:6f327212ef96	1034	*/
Kojto	112:6f327212ef96	1035
Kojto	112:6f327212ef96	1036	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	112:6f327212ef96	1037	* the selected interrupts).
Kojto	112:6f327212ef96	1038	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	112:6f327212ef96	1039	* This parameter can be any combination of the following values:
Kojto	112:6f327212ef96	1040	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	112:6f327212ef96	1041	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	112:6f327212ef96	1042	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	112:6f327212ef96	1043	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	112:6f327212ef96	1044	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	112:6f327212ef96	1045	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	112:6f327212ef96	1046	*/
Kojto	112:6f327212ef96	1047	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	112:6f327212ef96	1048
Kojto	112:6f327212ef96	1049	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	112:6f327212ef96	1050	* the selected interrupts).
Kojto	112:6f327212ef96	1051	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	112:6f327212ef96	1052	* This parameter can be any combination of the following values:
Kojto	112:6f327212ef96	1053	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	112:6f327212ef96	1054	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	112:6f327212ef96	1055	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	112:6f327212ef96	1056	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	112:6f327212ef96	1057	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	112:6f327212ef96	1058	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	112:6f327212ef96	1059	*/
Kojto	112:6f327212ef96	1060	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	112:6f327212ef96	1061
Kojto	112:6f327212ef96	1062	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
Kojto	112:6f327212ef96	1063	* bits to clear the selected interrupt pending bits.
Kojto	112:6f327212ef96	1064	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	112:6f327212ef96	1065	* This parameter can be any combination of the following values:
Kojto	112:6f327212ef96	1066	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	112:6f327212ef96	1067	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	112:6f327212ef96	1068	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	112:6f327212ef96	1069	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	112:6f327212ef96	1070	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	112:6f327212ef96	1071	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	112:6f327212ef96	1072	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	112:6f327212ef96	1073	*/
Kojto	112:6f327212ef96	1074	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto	112:6f327212ef96	1075
Kojto	112:6f327212ef96	1076	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	112:6f327212ef96	1077	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	112:6f327212ef96	1078	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1079	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	112:6f327212ef96	1080	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	112:6f327212ef96	1081	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	112:6f327212ef96	1082	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	112:6f327212ef96	1083	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	112:6f327212ef96	1084	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
Kojto	112:6f327212ef96	1085	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	112:6f327212ef96	1086	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	112:6f327212ef96	1087	*/
Kojto	112:6f327212ef96	1088	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	112:6f327212ef96	1089
Kojto	112:6f327212ef96	1090	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
Kojto	112:6f327212ef96	1091	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
Kojto	112:6f327212ef96	1092	*/
Kojto	112:6f327212ef96	1093	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	112:6f327212ef96	1094
Kojto	112:6f327212ef96	1095	/** @brief Check RCC flag is set or not.
Kojto	112:6f327212ef96	1096	* @param __FLAG__: specifies the flag to check.
Kojto	112:6f327212ef96	1097	* This parameter can be one of the following values:
Kojto	112:6f327212ef96	1098	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	112:6f327212ef96	1099	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	112:6f327212ef96	1100	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto	112:6f327212ef96	1101	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
Kojto	112:6f327212ef96	1102	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	112:6f327212ef96	1103	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto	112:6f327212ef96	1104	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto	112:6f327212ef96	1105	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	112:6f327212ef96	1106	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	112:6f327212ef96	1107	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	112:6f327212ef96	1108	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	112:6f327212ef96	1109	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	112:6f327212ef96	1110	* @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto	112:6f327212ef96	1111	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	112:6f327212ef96	1112	*/
Kojto	112:6f327212ef96	1113	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	112:6f327212ef96	1114	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
Kojto	112:6f327212ef96	1115
Kojto	112:6f327212ef96	1116	/**
Kojto	112:6f327212ef96	1117	* @}
Kojto	112:6f327212ef96	1118	*/
Kojto	112:6f327212ef96	1119
Kojto	112:6f327212ef96	1120	/**
Kojto	112:6f327212ef96	1121	* @}
Kojto	112:6f327212ef96	1122	*/
Kojto	112:6f327212ef96	1123
Kojto	112:6f327212ef96	1124	/* Exported functions --------------------------------------------------------*/
Kojto	112:6f327212ef96	1125	/** @addtogroup RCC_Exported_Functions
Kojto	112:6f327212ef96	1126	* @{
Kojto	112:6f327212ef96	1127	*/
Kojto	112:6f327212ef96	1128
Kojto	112:6f327212ef96	1129	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	112:6f327212ef96	1130	* @{
Kojto	112:6f327212ef96	1131	*/
Kojto	112:6f327212ef96	1132	/* Initialization and de-initialization functions ******************************/
Kojto	112:6f327212ef96	1133	void HAL_RCC_DeInit(void);
Kojto	112:6f327212ef96	1134	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	112:6f327212ef96	1135	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	112:6f327212ef96	1136	/**
Kojto	112:6f327212ef96	1137	* @}
Kojto	112:6f327212ef96	1138	*/
Kojto	112:6f327212ef96	1139
Kojto	112:6f327212ef96	1140	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	112:6f327212ef96	1141	* @{
Kojto	112:6f327212ef96	1142	*/
Kojto	112:6f327212ef96	1143	/* Peripheral Control functions ************************************************/
Kojto	112:6f327212ef96	1144	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	112:6f327212ef96	1145	void HAL_RCC_EnableCSS(void);
Kojto	112:6f327212ef96	1146	void HAL_RCC_DisableCSS(void);
Kojto	112:6f327212ef96	1147	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	112:6f327212ef96	1148	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	112:6f327212ef96	1149	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	112:6f327212ef96	1150	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	112:6f327212ef96	1151	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	112:6f327212ef96	1152	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	112:6f327212ef96	1153
Kojto	112:6f327212ef96	1154	/* CSS NMI IRQ handler */
Kojto	112:6f327212ef96	1155	void HAL_RCC_NMI_IRQHandler(void);
Kojto	112:6f327212ef96	1156
Kojto	112:6f327212ef96	1157	/* User Callbacks in non blocking mode (IT mode) */
Kojto	112:6f327212ef96	1158	void HAL_RCC_CSSCallback(void);
Kojto	112:6f327212ef96	1159
Kojto	112:6f327212ef96	1160	/**
Kojto	112:6f327212ef96	1161	* @}
Kojto	112:6f327212ef96	1162	*/
Kojto	112:6f327212ef96	1163
Kojto	112:6f327212ef96	1164	/**
Kojto	112:6f327212ef96	1165	* @}
Kojto	112:6f327212ef96	1166	*/
Kojto	112:6f327212ef96	1167
Kojto	112:6f327212ef96	1168	/* Private types -------------------------------------------------------------*/
Kojto	112:6f327212ef96	1169	/* Private variables ---------------------------------------------------------*/
Kojto	112:6f327212ef96	1170	/* Private constants ---------------------------------------------------------*/
Kojto	112:6f327212ef96	1171	/** @defgroup RCC_Private_Constants RCC Private Constants
Kojto	112:6f327212ef96	1172	* @{
Kojto	112:6f327212ef96	1173	*/
Kojto	112:6f327212ef96	1174
Kojto	112:6f327212ef96	1175	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	112:6f327212ef96	1176	* @brief RCC registers bit address in the alias region
Kojto	112:6f327212ef96	1177	* @{
Kojto	112:6f327212ef96	1178	*/
Kojto	112:6f327212ef96	1179	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	112:6f327212ef96	1180	/* --- CR Register ---*/
Kojto	112:6f327212ef96	1181	/* Alias word address of HSION bit */
Kojto	112:6f327212ef96	1182	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto	112:6f327212ef96	1183	#define RCC_HSION_BIT_NUMBER 0x00
Kojto	112:6f327212ef96	1184	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	1185	/* Alias word address of CSSON bit */
Kojto	112:6f327212ef96	1186	#define RCC_CSSON_BIT_NUMBER 0x13
Kojto	112:6f327212ef96	1187	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	1188	/* Alias word address of PLLON bit */
Kojto	112:6f327212ef96	1189	#define RCC_PLLON_BIT_NUMBER 0x18
Kojto	112:6f327212ef96	1190	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	1191
Kojto	112:6f327212ef96	1192	/* --- BDCR Register ---*/
Kojto	112:6f327212ef96	1193	/* Alias word address of RTCEN bit */
Kojto	112:6f327212ef96	1194	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto	112:6f327212ef96	1195	#define RCC_RTCEN_BIT_NUMBER 0x0F
Kojto	112:6f327212ef96	1196	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	1197	/* Alias word address of BDRST bit */
Kojto	112:6f327212ef96	1198	#define RCC_BDRST_BIT_NUMBER 0x10
Kojto	112:6f327212ef96	1199	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	1200
Kojto	112:6f327212ef96	1201	/* --- CSR Register ---*/
Kojto	112:6f327212ef96	1202	/* Alias word address of LSION bit */
Kojto	112:6f327212ef96	1203	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto	112:6f327212ef96	1204	#define RCC_LSION_BIT_NUMBER 0x00
Kojto	112:6f327212ef96	1205	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
Kojto	112:6f327212ef96	1206
Kojto	112:6f327212ef96	1207	/* CR register byte 3 (Bits[23:16]) base address */
Kojto	112:6f327212ef96	1208	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto	112:6f327212ef96	1209
Kojto	112:6f327212ef96	1210	/* CIR register byte 2 (Bits[15:8]) base address */
Kojto	112:6f327212ef96	1211	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto	112:6f327212ef96	1212
Kojto	112:6f327212ef96	1213	/* CIR register byte 3 (Bits[23:16]) base address */
Kojto	112:6f327212ef96	1214	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto	112:6f327212ef96	1215
Kojto	112:6f327212ef96	1216	/* BDCR register base address */
Kojto	112:6f327212ef96	1217	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto	112:6f327212ef96	1218
Kojto	112:6f327212ef96	1219	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	116:c0f6e94411f5	1220	#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5000 ms */
Kojto	112:6f327212ef96	1221
Kojto	112:6f327212ef96	1222	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto	112:6f327212ef96	1223	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	112:6f327212ef96	1224	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	112:6f327212ef96	1225
Kojto	112:6f327212ef96	1226	/**
Kojto	112:6f327212ef96	1227	* @}
Kojto	112:6f327212ef96	1228	*/
Kojto	112:6f327212ef96	1229
Kojto	112:6f327212ef96	1230	/**
Kojto	112:6f327212ef96	1231	* @}
Kojto	112:6f327212ef96	1232	*/
Kojto	112:6f327212ef96	1233
Kojto	112:6f327212ef96	1234	/* Private macros ------------------------------------------------------------*/
Kojto	112:6f327212ef96	1235	/** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto	112:6f327212ef96	1236	* @{
Kojto	112:6f327212ef96	1237	*/
Kojto	112:6f327212ef96	1238
Kojto	112:6f327212ef96	1239	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	112:6f327212ef96	1240	* @{
Kojto	112:6f327212ef96	1241	*/
Kojto	112:6f327212ef96	1242	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto	112:6f327212ef96	1243
Kojto	112:6f327212ef96	1244	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
Kojto	112:6f327212ef96	1245	((HSE) == RCC_HSE_BYPASS))
Kojto	112:6f327212ef96	1246
Kojto	112:6f327212ef96	1247	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
Kojto	112:6f327212ef96	1248	((LSE) == RCC_LSE_BYPASS))
Kojto	112:6f327212ef96	1249
Kojto	112:6f327212ef96	1250	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
Kojto	112:6f327212ef96	1251
Kojto	112:6f327212ef96	1252	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
Kojto	112:6f327212ef96	1253
Kojto	112:6f327212ef96	1254	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
Kojto	112:6f327212ef96	1255
Kojto	112:6f327212ef96	1256	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	112:6f327212ef96	1257	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	112:6f327212ef96	1258
Kojto	112:6f327212ef96	1259	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	112:6f327212ef96	1260	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	112:6f327212ef96	1261	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
Kojto	112:6f327212ef96	1262	((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto	112:6f327212ef96	1263
Kojto	112:6f327212ef96	1264	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto	112:6f327212ef96	1265
Kojto	112:6f327212ef96	1266	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto	112:6f327212ef96	1267
Kojto	112:6f327212ef96	1268	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
Kojto	112:6f327212ef96	1269
Kojto	112:6f327212ef96	1270	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto	112:6f327212ef96	1271
Kojto	112:6f327212ef96	1272	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
Kojto	112:6f327212ef96	1273	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
Kojto	112:6f327212ef96	1274	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
Kojto	112:6f327212ef96	1275	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
Kojto	112:6f327212ef96	1276	((HCLK) == RCC_SYSCLK_DIV512))
Kojto	112:6f327212ef96	1277
Kojto	112:6f327212ef96	1278	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto	112:6f327212ef96	1279
Kojto	112:6f327212ef96	1280	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
Kojto	112:6f327212ef96	1281	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
Kojto	112:6f327212ef96	1282	((PCLK) == RCC_HCLK_DIV16))
Kojto	112:6f327212ef96	1283
Kojto	112:6f327212ef96	1284	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
Kojto	112:6f327212ef96	1285
Kojto	112:6f327212ef96	1286	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
Kojto	112:6f327212ef96	1287	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto	112:6f327212ef96	1288
Kojto	112:6f327212ef96	1289	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
Kojto	112:6f327212ef96	1290	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
Kojto	112:6f327212ef96	1291	((DIV) == RCC_MCODIV_5))
Kojto	112:6f327212ef96	1292	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto	112:6f327212ef96	1293
Kojto	112:6f327212ef96	1294	/**
Kojto	112:6f327212ef96	1295	* @}
Kojto	112:6f327212ef96	1296	*/
Kojto	112:6f327212ef96	1297
Kojto	112:6f327212ef96	1298	/**
Kojto	112:6f327212ef96	1299	* @}
Kojto	112:6f327212ef96	1300	*/
Kojto	112:6f327212ef96	1301
Kojto	112:6f327212ef96	1302	/**
Kojto	112:6f327212ef96	1303	* @}
Kojto	112:6f327212ef96	1304	*/
Kojto	112:6f327212ef96	1305
Kojto	112:6f327212ef96	1306	/**
Kojto	112:6f327212ef96	1307	* @}
Kojto	112:6f327212ef96	1308	*/
Kojto	112:6f327212ef96	1309
Kojto	112:6f327212ef96	1310	#ifdef __cplusplus
Kojto	112:6f327212ef96	1311	}
Kojto	112:6f327212ef96	1312	#endif
Kojto	112:6f327212ef96	1313
Kojto	112:6f327212ef96	1314	#endif /* __STM32F4xx_HAL_RCC_H */
Kojto	112:6f327212ef96	1315
Kojto	112:6f327212ef96	1316	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_B96B_F446VE/stm32f4xx_hal_rcc.h@121:672067c3ada4, 2016-04-14 (annotated)

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