Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

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Fork of mbed by mbed official

TARGET_SAMR21G18A/ins_tcc0.h@111:4336505e4b1c, 2015-12-15 (annotated)

Committer:
Kojto
Date:
Tue Dec 15 14:39:38 2015 +0000
Revision:
111:4336505e4b1c
Release 111 of the mbed library



Changes:

- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)

- Streams - add var argument (vprintf, vscanf)

- MAXWSNENV - BLE stack library additio

- LPC1768 - fix slave read

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Instance description for TCC0
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_TCC0_INSTANCE_
Kojto 111:4336505e4b1c 45 #define _SAMR21_TCC0_INSTANCE_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========== Register definition for TCC0 peripheral ========== */
Kojto 111:4336505e4b1c 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 49 #define REG_TCC0_CTRLA (0x42002000U) /**< \brief (TCC0) Control A */
Kojto 111:4336505e4b1c 50 #define REG_TCC0_CTRLBCLR (0x42002004U) /**< \brief (TCC0) Control B Clear */
Kojto 111:4336505e4b1c 51 #define REG_TCC0_CTRLBSET (0x42002005U) /**< \brief (TCC0) Control B Set */
Kojto 111:4336505e4b1c 52 #define REG_TCC0_SYNCBUSY (0x42002008U) /**< \brief (TCC0) Synchronization Busy */
Kojto 111:4336505e4b1c 53 #define REG_TCC0_FCTRLA (0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
Kojto 111:4336505e4b1c 54 #define REG_TCC0_FCTRLB (0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
Kojto 111:4336505e4b1c 55 #define REG_TCC0_WEXCTRL (0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
Kojto 111:4336505e4b1c 56 #define REG_TCC0_DRVCTRL (0x42002018U) /**< \brief (TCC0) Driver Control */
Kojto 111:4336505e4b1c 57 #define REG_TCC0_DBGCTRL (0x4200201EU) /**< \brief (TCC0) Debug Control */
Kojto 111:4336505e4b1c 58 #define REG_TCC0_EVCTRL (0x42002020U) /**< \brief (TCC0) Event Control */
Kojto 111:4336505e4b1c 59 #define REG_TCC0_INTENCLR (0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 60 #define REG_TCC0_INTENSET (0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
Kojto 111:4336505e4b1c 61 #define REG_TCC0_INTFLAG (0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 62 #define REG_TCC0_STATUS (0x42002030U) /**< \brief (TCC0) Status */
Kojto 111:4336505e4b1c 63 #define REG_TCC0_COUNT (0x42002034U) /**< \brief (TCC0) Count */
Kojto 111:4336505e4b1c 64 #define REG_TCC0_PATT (0x42002038U) /**< \brief (TCC0) Pattern */
Kojto 111:4336505e4b1c 65 #define REG_TCC0_WAVE (0x4200203CU) /**< \brief (TCC0) Waveform Control */
Kojto 111:4336505e4b1c 66 #define REG_TCC0_PER (0x42002040U) /**< \brief (TCC0) Period */
Kojto 111:4336505e4b1c 67 #define REG_TCC0_CC0 (0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
Kojto 111:4336505e4b1c 68 #define REG_TCC0_CC1 (0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
Kojto 111:4336505e4b1c 69 #define REG_TCC0_CC2 (0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
Kojto 111:4336505e4b1c 70 #define REG_TCC0_CC3 (0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
Kojto 111:4336505e4b1c 71 #define REG_TCC0_PATTB (0x42002064U) /**< \brief (TCC0) Pattern Buffer */
Kojto 111:4336505e4b1c 72 #define REG_TCC0_WAVEB (0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
Kojto 111:4336505e4b1c 73 #define REG_TCC0_PERB (0x4200206CU) /**< \brief (TCC0) Period Buffer */
Kojto 111:4336505e4b1c 74 #define REG_TCC0_CCB0 (0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
Kojto 111:4336505e4b1c 75 #define REG_TCC0_CCB1 (0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
Kojto 111:4336505e4b1c 76 #define REG_TCC0_CCB2 (0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
Kojto 111:4336505e4b1c 77 #define REG_TCC0_CCB3 (0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
Kojto 111:4336505e4b1c 78 #else
Kojto 111:4336505e4b1c 79 #define REG_TCC0_CTRLA (*(RwReg *)0x42002000U) /**< \brief (TCC0) Control A */
Kojto 111:4336505e4b1c 80 #define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004U) /**< \brief (TCC0) Control B Clear */
Kojto 111:4336505e4b1c 81 #define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005U) /**< \brief (TCC0) Control B Set */
Kojto 111:4336505e4b1c 82 #define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008U) /**< \brief (TCC0) Synchronization Busy */
Kojto 111:4336505e4b1c 83 #define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CU) /**< \brief (TCC0) Recoverable Fault A Configuration */
Kojto 111:4336505e4b1c 84 #define REG_TCC0_FCTRLB (*(RwReg *)0x42002010U) /**< \brief (TCC0) Recoverable Fault B Configuration */
Kojto 111:4336505e4b1c 85 #define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014U) /**< \brief (TCC0) Waveform Extension Configuration */
Kojto 111:4336505e4b1c 86 #define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018U) /**< \brief (TCC0) Driver Control */
Kojto 111:4336505e4b1c 87 #define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EU) /**< \brief (TCC0) Debug Control */
Kojto 111:4336505e4b1c 88 #define REG_TCC0_EVCTRL (*(RwReg *)0x42002020U) /**< \brief (TCC0) Event Control */
Kojto 111:4336505e4b1c 89 #define REG_TCC0_INTENCLR (*(RwReg *)0x42002024U) /**< \brief (TCC0) Interrupt Enable Clear */
Kojto 111:4336505e4b1c 90 #define REG_TCC0_INTENSET (*(RwReg *)0x42002028U) /**< \brief (TCC0) Interrupt Enable Set */
Kojto 111:4336505e4b1c 91 #define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CU) /**< \brief (TCC0) Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 92 #define REG_TCC0_STATUS (*(RwReg *)0x42002030U) /**< \brief (TCC0) Status */
Kojto 111:4336505e4b1c 93 #define REG_TCC0_COUNT (*(RwReg *)0x42002034U) /**< \brief (TCC0) Count */
Kojto 111:4336505e4b1c 94 #define REG_TCC0_PATT (*(RwReg16*)0x42002038U) /**< \brief (TCC0) Pattern */
Kojto 111:4336505e4b1c 95 #define REG_TCC0_WAVE (*(RwReg *)0x4200203CU) /**< \brief (TCC0) Waveform Control */
Kojto 111:4336505e4b1c 96 #define REG_TCC0_PER (*(RwReg *)0x42002040U) /**< \brief (TCC0) Period */
Kojto 111:4336505e4b1c 97 #define REG_TCC0_CC0 (*(RwReg *)0x42002044U) /**< \brief (TCC0) Compare and Capture 0 */
Kojto 111:4336505e4b1c 98 #define REG_TCC0_CC1 (*(RwReg *)0x42002048U) /**< \brief (TCC0) Compare and Capture 1 */
Kojto 111:4336505e4b1c 99 #define REG_TCC0_CC2 (*(RwReg *)0x4200204CU) /**< \brief (TCC0) Compare and Capture 2 */
Kojto 111:4336505e4b1c 100 #define REG_TCC0_CC3 (*(RwReg *)0x42002050U) /**< \brief (TCC0) Compare and Capture 3 */
Kojto 111:4336505e4b1c 101 #define REG_TCC0_PATTB (*(RwReg16*)0x42002064U) /**< \brief (TCC0) Pattern Buffer */
Kojto 111:4336505e4b1c 102 #define REG_TCC0_WAVEB (*(RwReg *)0x42002068U) /**< \brief (TCC0) Waveform Control Buffer */
Kojto 111:4336505e4b1c 103 #define REG_TCC0_PERB (*(RwReg *)0x4200206CU) /**< \brief (TCC0) Period Buffer */
Kojto 111:4336505e4b1c 104 #define REG_TCC0_CCB0 (*(RwReg *)0x42002070U) /**< \brief (TCC0) Compare and Capture Buffer 0 */
Kojto 111:4336505e4b1c 105 #define REG_TCC0_CCB1 (*(RwReg *)0x42002074U) /**< \brief (TCC0) Compare and Capture Buffer 1 */
Kojto 111:4336505e4b1c 106 #define REG_TCC0_CCB2 (*(RwReg *)0x42002078U) /**< \brief (TCC0) Compare and Capture Buffer 2 */
Kojto 111:4336505e4b1c 107 #define REG_TCC0_CCB3 (*(RwReg *)0x4200207CU) /**< \brief (TCC0) Compare and Capture Buffer 3 */
Kojto 111:4336505e4b1c 108 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 109
Kojto 111:4336505e4b1c 110 /* ========== Instance parameters for TCC0 peripheral ========== */
Kojto 111:4336505e4b1c 111 #define TCC0_CC_NUM 4 // Number of Compare/Capture units
Kojto 111:4336505e4b1c 112 #define TCC0_DITHERING 1 // Dithering feature implemented
Kojto 111:4336505e4b1c 113 #define TCC0_DMAC_ID_MC_0 14
Kojto 111:4336505e4b1c 114 #define TCC0_DMAC_ID_MC_1 15
Kojto 111:4336505e4b1c 115 #define TCC0_DMAC_ID_MC_2 16
Kojto 111:4336505e4b1c 116 #define TCC0_DMAC_ID_MC_3 17
Kojto 111:4336505e4b1c 117 #define TCC0_DMAC_ID_MC_LSB 14
Kojto 111:4336505e4b1c 118 #define TCC0_DMAC_ID_MC_MSB 17
Kojto 111:4336505e4b1c 119 #define TCC0_DMAC_ID_MC_SIZE 4
Kojto 111:4336505e4b1c 120 #define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger
Kojto 111:4336505e4b1c 121 #define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
Kojto 111:4336505e4b1c 122 #define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
Kojto 111:4336505e4b1c 123 #define TCC0_GCLK_ID 26 // Index of Generic Clock
Kojto 111:4336505e4b1c 124 #define TCC0_OTMX 1 // Output Matrix feature implemented
Kojto 111:4336505e4b1c 125 #define TCC0_OW_NUM 8 // Number of Output Waveforms
Kojto 111:4336505e4b1c 126 #define TCC0_PG 1 // Pattern Generation feature implemented
Kojto 111:4336505e4b1c 127 #define TCC0_SIZE 24
Kojto 111:4336505e4b1c 128 #define TCC0_SWAP 1 // DTI outputs swap feature implemented
Kojto 111:4336505e4b1c 129 #define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
Kojto 111:4336505e4b1c 130
Kojto 111:4336505e4b1c 131 #endif /* _SAMR21_TCC0_INSTANCE_ */