Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_SAMR21G18A/ins_dmac.h@111:4336505e4b1c, 2015-12-15 (annotated)

Committer:
Kojto
Date:
Tue Dec 15 14:39:38 2015 +0000
Revision:
111:4336505e4b1c
Release 111 of the mbed library



Changes:

- new platforms - Atmel targets (SAMR21G18A, SAMD21J18A, SAMD21G18A)

- Streams - add var argument (vprintf, vscanf)

- MAXWSNENV - BLE stack library additio

- LPC1768 - fix slave read

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 111:4336505e4b1c 1 /**
Kojto 111:4336505e4b1c 2 * \file
Kojto 111:4336505e4b1c 3 *
Kojto 111:4336505e4b1c 4 * \brief Instance description for DMAC
Kojto 111:4336505e4b1c 5 *
Kojto 111:4336505e4b1c 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
Kojto 111:4336505e4b1c 7 *
Kojto 111:4336505e4b1c 8 * \asf_license_start
Kojto 111:4336505e4b1c 9 *
Kojto 111:4336505e4b1c 10 * \page License
Kojto 111:4336505e4b1c 11 *
Kojto 111:4336505e4b1c 12 * Redistribution and use in source and binary forms, with or without
Kojto 111:4336505e4b1c 13 * modification, are permitted provided that the following conditions are met:
Kojto 111:4336505e4b1c 14 *
Kojto 111:4336505e4b1c 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 111:4336505e4b1c 16 * this list of conditions and the following disclaimer.
Kojto 111:4336505e4b1c 17 *
Kojto 111:4336505e4b1c 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 111:4336505e4b1c 19 * this list of conditions and the following disclaimer in the documentation
Kojto 111:4336505e4b1c 20 * and/or other materials provided with the distribution.
Kojto 111:4336505e4b1c 21 *
Kojto 111:4336505e4b1c 22 * 3. The name of Atmel may not be used to endorse or promote products derived
Kojto 111:4336505e4b1c 23 * from this software without specific prior written permission.
Kojto 111:4336505e4b1c 24 *
Kojto 111:4336505e4b1c 25 * 4. This software may only be redistributed and used in connection with an
Kojto 111:4336505e4b1c 26 * Atmel microcontroller product.
Kojto 111:4336505e4b1c 27 *
Kojto 111:4336505e4b1c 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
Kojto 111:4336505e4b1c 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
Kojto 111:4336505e4b1c 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
Kojto 111:4336505e4b1c 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
Kojto 111:4336505e4b1c 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 111:4336505e4b1c 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
Kojto 111:4336505e4b1c 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
Kojto 111:4336505e4b1c 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
Kojto 111:4336505e4b1c 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
Kojto 111:4336505e4b1c 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
Kojto 111:4336505e4b1c 38 * POSSIBILITY OF SUCH DAMAGE.
Kojto 111:4336505e4b1c 39 *
Kojto 111:4336505e4b1c 40 * \asf_license_stop
Kojto 111:4336505e4b1c 41 *
Kojto 111:4336505e4b1c 42 */
Kojto 111:4336505e4b1c 43
Kojto 111:4336505e4b1c 44 #ifndef _SAMR21_DMAC_INSTANCE_
Kojto 111:4336505e4b1c 45 #define _SAMR21_DMAC_INSTANCE_
Kojto 111:4336505e4b1c 46
Kojto 111:4336505e4b1c 47 /* ========== Register definition for DMAC peripheral ========== */
Kojto 111:4336505e4b1c 48 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
Kojto 111:4336505e4b1c 49 #define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */
Kojto 111:4336505e4b1c 50 #define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */
Kojto 111:4336505e4b1c 51 #define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */
Kojto 111:4336505e4b1c 52 #define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */
Kojto 111:4336505e4b1c 53 #define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */
Kojto 111:4336505e4b1c 54 #define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */
Kojto 111:4336505e4b1c 55 #define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */
Kojto 111:4336505e4b1c 56 #define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
Kojto 111:4336505e4b1c 57 #define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
Kojto 111:4336505e4b1c 58 #define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
Kojto 111:4336505e4b1c 59 #define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */
Kojto 111:4336505e4b1c 60 #define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */
Kojto 111:4336505e4b1c 61 #define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */
Kojto 111:4336505e4b1c 62 #define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
Kojto 111:4336505e4b1c 63 #define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
Kojto 111:4336505e4b1c 64 #define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
Kojto 111:4336505e4b1c 65 #define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */
Kojto 111:4336505e4b1c 66 #define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */
Kojto 111:4336505e4b1c 67 #define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */
Kojto 111:4336505e4b1c 68 #define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
Kojto 111:4336505e4b1c 69 #define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
Kojto 111:4336505e4b1c 70 #define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 71 #define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */
Kojto 111:4336505e4b1c 72 #else
Kojto 111:4336505e4b1c 73 #define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
Kojto 111:4336505e4b1c 74 #define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
Kojto 111:4336505e4b1c 75 #define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
Kojto 111:4336505e4b1c 76 #define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
Kojto 111:4336505e4b1c 77 #define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
Kojto 111:4336505e4b1c 78 #define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
Kojto 111:4336505e4b1c 79 #define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
Kojto 111:4336505e4b1c 80 #define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
Kojto 111:4336505e4b1c 81 #define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
Kojto 111:4336505e4b1c 82 #define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
Kojto 111:4336505e4b1c 83 #define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
Kojto 111:4336505e4b1c 84 #define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */
Kojto 111:4336505e4b1c 85 #define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
Kojto 111:4336505e4b1c 86 #define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
Kojto 111:4336505e4b1c 87 #define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
Kojto 111:4336505e4b1c 88 #define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
Kojto 111:4336505e4b1c 89 #define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
Kojto 111:4336505e4b1c 90 #define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
Kojto 111:4336505e4b1c 91 #define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */
Kojto 111:4336505e4b1c 92 #define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
Kojto 111:4336505e4b1c 93 #define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
Kojto 111:4336505e4b1c 94 #define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
Kojto 111:4336505e4b1c 95 #define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
Kojto 111:4336505e4b1c 96 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
Kojto 111:4336505e4b1c 97
Kojto 111:4336505e4b1c 98 /* ========== Instance parameters for DMAC peripheral ========== */
Kojto 111:4336505e4b1c 99 #define DMAC_CH_BITS 4 // Number of bits to select channel
Kojto 111:4336505e4b1c 100 #define DMAC_CH_NUM 12 // Number of channels
Kojto 111:4336505e4b1c 101 #define DMAC_CLK_AHB_ID 5 // AHB clock index
Kojto 111:4336505e4b1c 102 #define DMAC_EVIN_NUM 4 // Number of input events
Kojto 111:4336505e4b1c 103 #define DMAC_EVOUT_NUM 4 // Number of output events
Kojto 111:4336505e4b1c 104 #define DMAC_LVL_BITS 2 // Number of bit to select level priority
Kojto 111:4336505e4b1c 105 #define DMAC_LVL_NUM 4 // Enable priority level number
Kojto 111:4336505e4b1c 106 #define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
Kojto 111:4336505e4b1c 107 #define DMAC_TRIG_NUM 45 // Number of peripheral triggers
Kojto 111:4336505e4b1c 108
Kojto 111:4336505e4b1c 109 #endif /* _SAMR21_DMAC_INSTANCE_ */