Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_ELMO_F411RE/stm32f4xx_hal_pwr.h@108:34e6b704fe68, 2015-10-02 (annotated)

Committer:
Kojto
Date:
Fri Oct 02 07:35:07 2015 +0200
Revision:
108:34e6b704fe68
Child:
110:165afa46840b
Release 108  of the mbed library



Changes:

- new platforms - ELMO_F411RE, WIZNET_7500P, ARM_MPS2_BEID

- EFM32 - bugfixes in rtc, serial

- Cortex A cmsis - update files

- STML4 - RAM fixes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 108:34e6b704fe68 1 /**
Kojto 108:34e6b704fe68 2 ******************************************************************************
Kojto 108:34e6b704fe68 3 * @file stm32f4xx_hal_pwr.h
Kojto 108:34e6b704fe68 4 * @author MCD Application Team
Kojto 108:34e6b704fe68 5 * @version V1.3.2
Kojto 108:34e6b704fe68 6 * @date 26-June-2015
Kojto 108:34e6b704fe68 7 * @brief Header file of PWR HAL module.
Kojto 108:34e6b704fe68 8 ******************************************************************************
Kojto 108:34e6b704fe68 9 * @attention
Kojto 108:34e6b704fe68 10 *
Kojto 108:34e6b704fe68 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 108:34e6b704fe68 12 *
Kojto 108:34e6b704fe68 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 108:34e6b704fe68 14 * are permitted provided that the following conditions are met:
Kojto 108:34e6b704fe68 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 108:34e6b704fe68 16 * this list of conditions and the following disclaimer.
Kojto 108:34e6b704fe68 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 108:34e6b704fe68 18 * this list of conditions and the following disclaimer in the documentation
Kojto 108:34e6b704fe68 19 * and/or other materials provided with the distribution.
Kojto 108:34e6b704fe68 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 108:34e6b704fe68 21 * may be used to endorse or promote products derived from this software
Kojto 108:34e6b704fe68 22 * without specific prior written permission.
Kojto 108:34e6b704fe68 23 *
Kojto 108:34e6b704fe68 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 108:34e6b704fe68 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 108:34e6b704fe68 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 108:34e6b704fe68 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 108:34e6b704fe68 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 108:34e6b704fe68 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 108:34e6b704fe68 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 108:34e6b704fe68 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 108:34e6b704fe68 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 108:34e6b704fe68 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 108:34e6b704fe68 34 *
Kojto 108:34e6b704fe68 35 ******************************************************************************
Kojto 108:34e6b704fe68 36 */
Kojto 108:34e6b704fe68 37
Kojto 108:34e6b704fe68 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 108:34e6b704fe68 39 #ifndef __STM32F4xx_HAL_PWR_H
Kojto 108:34e6b704fe68 40 #define __STM32F4xx_HAL_PWR_H
Kojto 108:34e6b704fe68 41
Kojto 108:34e6b704fe68 42 #ifdef __cplusplus
Kojto 108:34e6b704fe68 43 extern "C" {
Kojto 108:34e6b704fe68 44 #endif
Kojto 108:34e6b704fe68 45
Kojto 108:34e6b704fe68 46 /* Includes ------------------------------------------------------------------*/
Kojto 108:34e6b704fe68 47 #include "stm32f4xx_hal_def.h"
Kojto 108:34e6b704fe68 48
Kojto 108:34e6b704fe68 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 108:34e6b704fe68 50 * @{
Kojto 108:34e6b704fe68 51 */
Kojto 108:34e6b704fe68 52
Kojto 108:34e6b704fe68 53 /** @addtogroup PWR
Kojto 108:34e6b704fe68 54 * @{
Kojto 108:34e6b704fe68 55 */
Kojto 108:34e6b704fe68 56
Kojto 108:34e6b704fe68 57 /* Exported types ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 58
Kojto 108:34e6b704fe68 59 /** @defgroup PWR_Exported_Types PWR Exported Types
Kojto 108:34e6b704fe68 60 * @{
Kojto 108:34e6b704fe68 61 */
Kojto 108:34e6b704fe68 62
Kojto 108:34e6b704fe68 63 /**
Kojto 108:34e6b704fe68 64 * @brief PWR PVD configuration structure definition
Kojto 108:34e6b704fe68 65 */
Kojto 108:34e6b704fe68 66 typedef struct
Kojto 108:34e6b704fe68 67 {
Kojto 108:34e6b704fe68 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
Kojto 108:34e6b704fe68 69 This parameter can be a value of @ref PWR_PVD_detection_level */
Kojto 108:34e6b704fe68 70
Kojto 108:34e6b704fe68 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
Kojto 108:34e6b704fe68 72 This parameter can be a value of @ref PWR_PVD_Mode */
Kojto 108:34e6b704fe68 73 }PWR_PVDTypeDef;
Kojto 108:34e6b704fe68 74
Kojto 108:34e6b704fe68 75 /**
Kojto 108:34e6b704fe68 76 * @}
Kojto 108:34e6b704fe68 77 */
Kojto 108:34e6b704fe68 78
Kojto 108:34e6b704fe68 79 /* Exported constants --------------------------------------------------------*/
Kojto 108:34e6b704fe68 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
Kojto 108:34e6b704fe68 81 * @{
Kojto 108:34e6b704fe68 82 */
Kojto 108:34e6b704fe68 83
Kojto 108:34e6b704fe68 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
Kojto 108:34e6b704fe68 85 * @{
Kojto 108:34e6b704fe68 86 */
Kojto 108:34e6b704fe68 87 #define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
Kojto 108:34e6b704fe68 88 #define PWR_WAKEUP_PIN2 ((uint32_t)0x00000080)
Kojto 108:34e6b704fe68 89 /**
Kojto 108:34e6b704fe68 90 * @}
Kojto 108:34e6b704fe68 91 */
Kojto 108:34e6b704fe68 92
Kojto 108:34e6b704fe68 93 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
Kojto 108:34e6b704fe68 94 * @{
Kojto 108:34e6b704fe68 95 */
Kojto 108:34e6b704fe68 96 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
Kojto 108:34e6b704fe68 97 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
Kojto 108:34e6b704fe68 98 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
Kojto 108:34e6b704fe68 99 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
Kojto 108:34e6b704fe68 100 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
Kojto 108:34e6b704fe68 101 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
Kojto 108:34e6b704fe68 102 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 108:34e6b704fe68 103 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
Kojto 108:34e6b704fe68 104 (Compare internally to VREFINT) */
Kojto 108:34e6b704fe68 105 /**
Kojto 108:34e6b704fe68 106 * @}
Kojto 108:34e6b704fe68 107 */
Kojto 108:34e6b704fe68 108
Kojto 108:34e6b704fe68 109 /** @defgroup PWR_PVD_Mode PWR PVD Mode
Kojto 108:34e6b704fe68 110 * @{
Kojto 108:34e6b704fe68 111 */
Kojto 108:34e6b704fe68 112 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 108:34e6b704fe68 113 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 108:34e6b704fe68 114 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 108:34e6b704fe68 115 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 108:34e6b704fe68 116 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 108:34e6b704fe68 117 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 108:34e6b704fe68 118 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
Kojto 108:34e6b704fe68 119 /**
Kojto 108:34e6b704fe68 120 * @}
Kojto 108:34e6b704fe68 121 */
Kojto 108:34e6b704fe68 122
Kojto 108:34e6b704fe68 123
Kojto 108:34e6b704fe68 124 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
Kojto 108:34e6b704fe68 125 * @{
Kojto 108:34e6b704fe68 126 */
Kojto 108:34e6b704fe68 127 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
Kojto 108:34e6b704fe68 128 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
Kojto 108:34e6b704fe68 129 /**
Kojto 108:34e6b704fe68 130 * @}
Kojto 108:34e6b704fe68 131 */
Kojto 108:34e6b704fe68 132
Kojto 108:34e6b704fe68 133 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
Kojto 108:34e6b704fe68 134 * @{
Kojto 108:34e6b704fe68 135 */
Kojto 108:34e6b704fe68 136 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
Kojto 108:34e6b704fe68 137 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
Kojto 108:34e6b704fe68 138 /**
Kojto 108:34e6b704fe68 139 * @}
Kojto 108:34e6b704fe68 140 */
Kojto 108:34e6b704fe68 141
Kojto 108:34e6b704fe68 142 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
Kojto 108:34e6b704fe68 143 * @{
Kojto 108:34e6b704fe68 144 */
Kojto 108:34e6b704fe68 145 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
Kojto 108:34e6b704fe68 146 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
Kojto 108:34e6b704fe68 147 /**
Kojto 108:34e6b704fe68 148 * @}
Kojto 108:34e6b704fe68 149 */
Kojto 108:34e6b704fe68 150
Kojto 108:34e6b704fe68 151 /** @defgroup PWR_Flag PWR Flag
Kojto 108:34e6b704fe68 152 * @{
Kojto 108:34e6b704fe68 153 */
Kojto 108:34e6b704fe68 154 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 108:34e6b704fe68 155 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 108:34e6b704fe68 156 #define PWR_FLAG_PVDO PWR_CSR_PVDO
Kojto 108:34e6b704fe68 157 #define PWR_FLAG_BRR PWR_CSR_BRR
Kojto 108:34e6b704fe68 158 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
Kojto 108:34e6b704fe68 159 /**
Kojto 108:34e6b704fe68 160 * @}
Kojto 108:34e6b704fe68 161 */
Kojto 108:34e6b704fe68 162
Kojto 108:34e6b704fe68 163 /**
Kojto 108:34e6b704fe68 164 * @}
Kojto 108:34e6b704fe68 165 */
Kojto 108:34e6b704fe68 166
Kojto 108:34e6b704fe68 167 /* Exported macro ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 168 /** @defgroup PWR_Exported_Macro PWR Exported Macro
Kojto 108:34e6b704fe68 169 * @{
Kojto 108:34e6b704fe68 170 */
Kojto 108:34e6b704fe68 171
Kojto 108:34e6b704fe68 172 #if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
Kojto 108:34e6b704fe68 173 /** @brief macros configure the main internal regulator output voltage.
Kojto 108:34e6b704fe68 174 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 108:34e6b704fe68 175 * a tradeoff between performance and power consumption when the device does
Kojto 108:34e6b704fe68 176 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 108:34e6b704fe68 177 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 178 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 108:34e6b704fe68 179 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 108:34e6b704fe68 180 * @retval None
Kojto 108:34e6b704fe68 181 */
Kojto 108:34e6b704fe68 182 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 108:34e6b704fe68 183 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 184 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 108:34e6b704fe68 185 /* Delay after an RCC peripheral clock enabling */ \
Kojto 108:34e6b704fe68 186 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 108:34e6b704fe68 187 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 188 } while(0)
Kojto 108:34e6b704fe68 189 #else
Kojto 108:34e6b704fe68 190 /** @brief macros configure the main internal regulator output voltage.
Kojto 108:34e6b704fe68 191 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 108:34e6b704fe68 192 * a tradeoff between performance and power consumption when the device does
Kojto 108:34e6b704fe68 193 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 108:34e6b704fe68 194 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 195 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
Kojto 108:34e6b704fe68 196 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
Kojto 108:34e6b704fe68 197 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
Kojto 108:34e6b704fe68 198 * @retval None
Kojto 108:34e6b704fe68 199 */
Kojto 108:34e6b704fe68 200 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
Kojto 108:34e6b704fe68 201 __IO uint32_t tmpreg; \
Kojto 108:34e6b704fe68 202 MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \
Kojto 108:34e6b704fe68 203 /* Delay after an RCC peripheral clock enabling */ \
Kojto 108:34e6b704fe68 204 tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \
Kojto 108:34e6b704fe68 205 UNUSED(tmpreg); \
Kojto 108:34e6b704fe68 206 } while(0)
Kojto 108:34e6b704fe68 207 #endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */
Kojto 108:34e6b704fe68 208
Kojto 108:34e6b704fe68 209 /** @brief Check PWR flag is set or not.
Kojto 108:34e6b704fe68 210 * @param __FLAG__: specifies the flag to check.
Kojto 108:34e6b704fe68 211 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 212 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
Kojto 108:34e6b704fe68 213 * was received from the WKUP pin or from the RTC alarm (Alarm A
Kojto 108:34e6b704fe68 214 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
Kojto 108:34e6b704fe68 215 * An additional wakeup event is detected if the WKUP pin is enabled
Kojto 108:34e6b704fe68 216 * (by setting the EWUP bit) when the WKUP pin level is already high.
Kojto 108:34e6b704fe68 217 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
Kojto 108:34e6b704fe68 218 * resumed from StandBy mode.
Kojto 108:34e6b704fe68 219 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
Kojto 108:34e6b704fe68 220 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
Kojto 108:34e6b704fe68 221 * For this reason, this bit is equal to 0 after Standby or reset
Kojto 108:34e6b704fe68 222 * until the PVDE bit is set.
Kojto 108:34e6b704fe68 223 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
Kojto 108:34e6b704fe68 224 * when the device wakes up from Standby mode or by a system reset
Kojto 108:34e6b704fe68 225 * or power reset.
Kojto 108:34e6b704fe68 226 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
Kojto 108:34e6b704fe68 227 * scaling output selection is ready.
Kojto 108:34e6b704fe68 228 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 108:34e6b704fe68 229 */
Kojto 108:34e6b704fe68 230 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Kojto 108:34e6b704fe68 231
Kojto 108:34e6b704fe68 232 /** @brief Clear the PWR's pending flags.
Kojto 108:34e6b704fe68 233 * @param __FLAG__: specifies the flag to clear.
Kojto 108:34e6b704fe68 234 * This parameter can be one of the following values:
Kojto 108:34e6b704fe68 235 * @arg PWR_FLAG_WU: Wake Up flag
Kojto 108:34e6b704fe68 236 * @arg PWR_FLAG_SB: StandBy flag
Kojto 108:34e6b704fe68 237 */
Kojto 108:34e6b704fe68 238 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
Kojto 108:34e6b704fe68 239
Kojto 108:34e6b704fe68 240 /**
Kojto 108:34e6b704fe68 241 * @brief Enable the PVD Exti Line 16.
Kojto 108:34e6b704fe68 242 * @retval None.
Kojto 108:34e6b704fe68 243 */
Kojto 108:34e6b704fe68 244 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 245
Kojto 108:34e6b704fe68 246 /**
Kojto 108:34e6b704fe68 247 * @brief Disable the PVD EXTI Line 16.
Kojto 108:34e6b704fe68 248 * @retval None.
Kojto 108:34e6b704fe68 249 */
Kojto 108:34e6b704fe68 250 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 251
Kojto 108:34e6b704fe68 252 /**
Kojto 108:34e6b704fe68 253 * @brief Enable event on PVD Exti Line 16.
Kojto 108:34e6b704fe68 254 * @retval None.
Kojto 108:34e6b704fe68 255 */
Kojto 108:34e6b704fe68 256 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 257
Kojto 108:34e6b704fe68 258 /**
Kojto 108:34e6b704fe68 259 * @brief Disable event on PVD Exti Line 16.
Kojto 108:34e6b704fe68 260 * @retval None.
Kojto 108:34e6b704fe68 261 */
Kojto 108:34e6b704fe68 262 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 263
Kojto 108:34e6b704fe68 264 /**
Kojto 108:34e6b704fe68 265 * @brief Enable the PVD Extended Interrupt Rising Trigger.
Kojto 108:34e6b704fe68 266 * @retval None.
Kojto 108:34e6b704fe68 267 */
Kojto 108:34e6b704fe68 268 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 108:34e6b704fe68 269
Kojto 108:34e6b704fe68 270 /**
Kojto 108:34e6b704fe68 271 * @brief Disable the PVD Extended Interrupt Rising Trigger.
Kojto 108:34e6b704fe68 272 * @retval None.
Kojto 108:34e6b704fe68 273 */
Kojto 108:34e6b704fe68 274 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 108:34e6b704fe68 275
Kojto 108:34e6b704fe68 276 /**
Kojto 108:34e6b704fe68 277 * @brief Enable the PVD Extended Interrupt Falling Trigger.
Kojto 108:34e6b704fe68 278 * @retval None.
Kojto 108:34e6b704fe68 279 */
Kojto 108:34e6b704fe68 280 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 108:34e6b704fe68 281
Kojto 108:34e6b704fe68 282
Kojto 108:34e6b704fe68 283 /**
Kojto 108:34e6b704fe68 284 * @brief Disable the PVD Extended Interrupt Falling Trigger.
Kojto 108:34e6b704fe68 285 * @retval None.
Kojto 108:34e6b704fe68 286 */
Kojto 108:34e6b704fe68 287 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 108:34e6b704fe68 288
Kojto 108:34e6b704fe68 289
Kojto 108:34e6b704fe68 290 /**
Kojto 108:34e6b704fe68 291 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
Kojto 108:34e6b704fe68 292 * @retval None.
Kojto 108:34e6b704fe68 293 */
Kojto 108:34e6b704fe68 294 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
Kojto 108:34e6b704fe68 295
Kojto 108:34e6b704fe68 296 /**
Kojto 108:34e6b704fe68 297 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
Kojto 108:34e6b704fe68 298 * This parameter can be:
Kojto 108:34e6b704fe68 299 * @retval None.
Kojto 108:34e6b704fe68 300 */
Kojto 108:34e6b704fe68 301 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
Kojto 108:34e6b704fe68 302
Kojto 108:34e6b704fe68 303 /**
Kojto 108:34e6b704fe68 304 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
Kojto 108:34e6b704fe68 305 * @retval EXTI PVD Line Status.
Kojto 108:34e6b704fe68 306 */
Kojto 108:34e6b704fe68 307 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 308
Kojto 108:34e6b704fe68 309 /**
Kojto 108:34e6b704fe68 310 * @brief Clear the PVD Exti flag.
Kojto 108:34e6b704fe68 311 * @retval None.
Kojto 108:34e6b704fe68 312 */
Kojto 108:34e6b704fe68 313 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 314
Kojto 108:34e6b704fe68 315 /**
Kojto 108:34e6b704fe68 316 * @brief Generates a Software interrupt on PVD EXTI line.
Kojto 108:34e6b704fe68 317 * @retval None
Kojto 108:34e6b704fe68 318 */
Kojto 108:34e6b704fe68 319 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Kojto 108:34e6b704fe68 320
Kojto 108:34e6b704fe68 321 /**
Kojto 108:34e6b704fe68 322 * @}
Kojto 108:34e6b704fe68 323 */
Kojto 108:34e6b704fe68 324
Kojto 108:34e6b704fe68 325 /* Include PWR HAL Extension module */
Kojto 108:34e6b704fe68 326 #include "stm32f4xx_hal_pwr_ex.h"
Kojto 108:34e6b704fe68 327
Kojto 108:34e6b704fe68 328 /* Exported functions --------------------------------------------------------*/
Kojto 108:34e6b704fe68 329 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
Kojto 108:34e6b704fe68 330 * @{
Kojto 108:34e6b704fe68 331 */
Kojto 108:34e6b704fe68 332
Kojto 108:34e6b704fe68 333 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 108:34e6b704fe68 334 * @{
Kojto 108:34e6b704fe68 335 */
Kojto 108:34e6b704fe68 336 /* Initialization and de-initialization functions *****************************/
Kojto 108:34e6b704fe68 337 void HAL_PWR_DeInit(void);
Kojto 108:34e6b704fe68 338 void HAL_PWR_EnableBkUpAccess(void);
Kojto 108:34e6b704fe68 339 void HAL_PWR_DisableBkUpAccess(void);
Kojto 108:34e6b704fe68 340 /**
Kojto 108:34e6b704fe68 341 * @}
Kojto 108:34e6b704fe68 342 */
Kojto 108:34e6b704fe68 343
Kojto 108:34e6b704fe68 344 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
Kojto 108:34e6b704fe68 345 * @{
Kojto 108:34e6b704fe68 346 */
Kojto 108:34e6b704fe68 347 /* Peripheral Control functions **********************************************/
Kojto 108:34e6b704fe68 348 /* PVD configuration */
Kojto 108:34e6b704fe68 349 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
Kojto 108:34e6b704fe68 350 void HAL_PWR_EnablePVD(void);
Kojto 108:34e6b704fe68 351 void HAL_PWR_DisablePVD(void);
Kojto 108:34e6b704fe68 352
Kojto 108:34e6b704fe68 353 /* WakeUp pins configuration */
Kojto 108:34e6b704fe68 354 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
Kojto 108:34e6b704fe68 355 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
Kojto 108:34e6b704fe68 356
Kojto 108:34e6b704fe68 357 /* Low Power modes entry */
Kojto 108:34e6b704fe68 358 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
Kojto 108:34e6b704fe68 359 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
Kojto 108:34e6b704fe68 360 void HAL_PWR_EnterSTANDBYMode(void);
Kojto 108:34e6b704fe68 361
Kojto 108:34e6b704fe68 362 /* Power PVD IRQ Handler */
Kojto 108:34e6b704fe68 363 void HAL_PWR_PVD_IRQHandler(void);
Kojto 108:34e6b704fe68 364 void HAL_PWR_PVDCallback(void);
Kojto 108:34e6b704fe68 365
Kojto 108:34e6b704fe68 366 /* Cortex System Control functions *******************************************/
Kojto 108:34e6b704fe68 367 void HAL_PWR_EnableSleepOnExit(void);
Kojto 108:34e6b704fe68 368 void HAL_PWR_DisableSleepOnExit(void);
Kojto 108:34e6b704fe68 369 void HAL_PWR_EnableSEVOnPend(void);
Kojto 108:34e6b704fe68 370 void HAL_PWR_DisableSEVOnPend(void);
Kojto 108:34e6b704fe68 371 /**
Kojto 108:34e6b704fe68 372 * @}
Kojto 108:34e6b704fe68 373 */
Kojto 108:34e6b704fe68 374
Kojto 108:34e6b704fe68 375 /**
Kojto 108:34e6b704fe68 376 * @}
Kojto 108:34e6b704fe68 377 */
Kojto 108:34e6b704fe68 378
Kojto 108:34e6b704fe68 379 /* Private types -------------------------------------------------------------*/
Kojto 108:34e6b704fe68 380 /* Private variables ---------------------------------------------------------*/
Kojto 108:34e6b704fe68 381 /* Private constants ---------------------------------------------------------*/
Kojto 108:34e6b704fe68 382 /** @defgroup PWR_Private_Constants PWR Private Constants
Kojto 108:34e6b704fe68 383 * @{
Kojto 108:34e6b704fe68 384 */
Kojto 108:34e6b704fe68 385
Kojto 108:34e6b704fe68 386 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
Kojto 108:34e6b704fe68 387 * @{
Kojto 108:34e6b704fe68 388 */
Kojto 108:34e6b704fe68 389 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 108:34e6b704fe68 390 /**
Kojto 108:34e6b704fe68 391 * @}
Kojto 108:34e6b704fe68 392 */
Kojto 108:34e6b704fe68 393
Kojto 108:34e6b704fe68 394 /** @defgroup PWR_register_alias_address PWR Register alias address
Kojto 108:34e6b704fe68 395 * @{
Kojto 108:34e6b704fe68 396 */
Kojto 108:34e6b704fe68 397 /* ------------- PWR registers bit address in the alias region ---------------*/
Kojto 108:34e6b704fe68 398 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
Kojto 108:34e6b704fe68 399 #define PWR_CR_OFFSET 0x00
Kojto 108:34e6b704fe68 400 #define PWR_CSR_OFFSET 0x04
Kojto 108:34e6b704fe68 401 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
Kojto 108:34e6b704fe68 402 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
Kojto 108:34e6b704fe68 403 /**
Kojto 108:34e6b704fe68 404 * @}
Kojto 108:34e6b704fe68 405 */
Kojto 108:34e6b704fe68 406
Kojto 108:34e6b704fe68 407 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
Kojto 108:34e6b704fe68 408 * @{
Kojto 108:34e6b704fe68 409 */
Kojto 108:34e6b704fe68 410 /* --- CR Register ---*/
Kojto 108:34e6b704fe68 411 /* Alias word address of DBP bit */
Kojto 108:34e6b704fe68 412 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
Kojto 108:34e6b704fe68 413 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
Kojto 108:34e6b704fe68 414
Kojto 108:34e6b704fe68 415 /* Alias word address of PVDE bit */
Kojto 108:34e6b704fe68 416 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
Kojto 108:34e6b704fe68 417 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
Kojto 108:34e6b704fe68 418
Kojto 108:34e6b704fe68 419 /* Alias word address of PMODE bit */
Kojto 108:34e6b704fe68 420 #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
Kojto 108:34e6b704fe68 421 #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
Kojto 108:34e6b704fe68 422 /**
Kojto 108:34e6b704fe68 423 * @}
Kojto 108:34e6b704fe68 424 */
Kojto 108:34e6b704fe68 425
Kojto 108:34e6b704fe68 426 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
Kojto 108:34e6b704fe68 427 * @{
Kojto 108:34e6b704fe68 428 */
Kojto 108:34e6b704fe68 429 /* --- CSR Register ---*/
Kojto 108:34e6b704fe68 430 /* Alias word address of EWUP bit */
Kojto 108:34e6b704fe68 431 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
Kojto 108:34e6b704fe68 432 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
Kojto 108:34e6b704fe68 433 /**
Kojto 108:34e6b704fe68 434 * @}
Kojto 108:34e6b704fe68 435 */
Kojto 108:34e6b704fe68 436
Kojto 108:34e6b704fe68 437 /**
Kojto 108:34e6b704fe68 438 * @}
Kojto 108:34e6b704fe68 439 */
Kojto 108:34e6b704fe68 440 /* Private macros ------------------------------------------------------------*/
Kojto 108:34e6b704fe68 441 /** @defgroup PWR_Private_Macros PWR Private Macros
Kojto 108:34e6b704fe68 442 * @{
Kojto 108:34e6b704fe68 443 */
Kojto 108:34e6b704fe68 444
Kojto 108:34e6b704fe68 445 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
Kojto 108:34e6b704fe68 446 * @{
Kojto 108:34e6b704fe68 447 */
Kojto 108:34e6b704fe68 448 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
Kojto 108:34e6b704fe68 449 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 108:34e6b704fe68 450 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 108:34e6b704fe68 451 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 108:34e6b704fe68 452 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 108:34e6b704fe68 453 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 108:34e6b704fe68 454 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 108:34e6b704fe68 455 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 108:34e6b704fe68 456 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 108:34e6b704fe68 457 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
Kojto 108:34e6b704fe68 458 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
Kojto 108:34e6b704fe68 459 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
Kojto 108:34e6b704fe68 460 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
Kojto 108:34e6b704fe68 461 /**
Kojto 108:34e6b704fe68 462 * @}
Kojto 108:34e6b704fe68 463 */
Kojto 108:34e6b704fe68 464
Kojto 108:34e6b704fe68 465 /**
Kojto 108:34e6b704fe68 466 * @}
Kojto 108:34e6b704fe68 467 */
Kojto 108:34e6b704fe68 468
Kojto 108:34e6b704fe68 469 /**
Kojto 108:34e6b704fe68 470 * @}
Kojto 108:34e6b704fe68 471 */
Kojto 108:34e6b704fe68 472
Kojto 108:34e6b704fe68 473 /**
Kojto 108:34e6b704fe68 474 * @}
Kojto 108:34e6b704fe68 475 */
Kojto 108:34e6b704fe68 476
Kojto 108:34e6b704fe68 477 #ifdef __cplusplus
Kojto 108:34e6b704fe68 478 }
Kojto 108:34e6b704fe68 479 #endif
Kojto 108:34e6b704fe68 480
Kojto 108:34e6b704fe68 481
Kojto 108:34e6b704fe68 482 #endif /* __STM32F4xx_HAL_PWR_H */
Kojto 108:34e6b704fe68 483
Kojto 108:34e6b704fe68 484 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/