sx127x_lora.h

00001 #include "sx127x.h"
00002 
00003 // LoRa registers
00004 #define REG_LR_FIFOADDRPTR                          0x0d
00005 #define REG_LR_FIFOTXBASEADDR                       0x0e
00006 #define REG_LR_FIFORXBASEADDR                       0x0f
00007 #define REG_LR_FIFORXCURRENTADDR /*REG_LR_RXDATAADDR*/  0x10
00008 #define REG_LR_IRQFLAGSMASK                         0x11
00009 #define REG_LR_IRQFLAGS                             0x12
00010 #define REG_LR_RXNBBYTES                            0x13
00011 #define REG_LR_RXHEADERCNTVALUE_MSB                 0x14
00012 #define REG_LR_RXHEADERCNTVALUE_LSB                 0x15
00013 #define REG_LR_RXPACKETCNTVALUE_MSB                 0x16
00014 #define REG_LR_RXPACKETCNTVALUE_LSB                 0x17
00015 #define REG_LR_MODEMSTAT                            0x18
00016 #define REG_LR_PKTSNRVALUE                          0x19
00017 #define REG_LR_PKTRSSIVALUE                         0x1a
00018 #define REG_LR_RSSIVALUE                            0x1b
00019 #define REG_LR_HOPCHANNEL                           0x1c
00020 #define REG_LR_MODEMCONFIG                          0x1d
00021 #define REG_LR_MODEMCONFIG2                         0x1e
00022 #define REG_LR_SYMBTIMEOUTLSB                       0x1f
00023 #define REG_LR_PREAMBLEMSB                          0x20
00024 #define REG_LR_PREAMBLELSB                          0x21
00025 #define REG_LR_PAYLOADLENGTH                        0x22 // and RX length for implicit
00026 #define REG_LR_RX_MAX_PAYLOADLENGTH                 0x23 // length limit for explicit mode
00027 #define REG_LR_HOPPERIOD                            0x24
00028 #define REG_LR_RXBYTEADDR /*REG_LR_RXDATAADDR*/     0x25
00029 #define REG_LR_MODEMCONFIG3                         0x26    // sx1272 REG_LR_PPM_CORRECTION_MSB
00030 #define REG_LR_PPM_CORRECTION_LSB                   0x27
00031 #define REG_LR_TEST28                               0x28  // est_freq_error
00032 #define REG_LR_TEST29                               0x29    // est_freq_error
00033 #define REG_LR_TEST2A                               0x2a    // est_freq_error
00034 #define REG_LR_TEST2B                               0x2b    // 
00035 #define REG_LR_WIDEBAND_RSSI                        0x2c 
00036 #define REG_LR_AGCH_TH                              0x2d    // agc_upper_th
00037 #define REG_LR_AGCL_TH                              0x2e    // agc_lower_th
00038 #define REG_LR_IFFRQH                               0x2f    // if_freq(12:8)
00039 #define REG_LR_IFFRQL                               0x30    // if_freq(7:0)
00040 #define REG_LR_TEST31                               0x31    // if_freq_auto, ...
00041 #define REG_LR_TEST32                               0x32    // 
00042 #define REG_LR_TEST33                               0x33
00043 #define REG_LR_DETECTION_THRESHOLD                  0x37
00044 
00045 typedef union {
00046     struct {    // sx127x register 0x12
00047         uint8_t CadDetected         : 1;    // 0
00048         uint8_t FhssChangeChannel   : 1;    // 1
00049         uint8_t CadDone             : 1;    // 2
00050         uint8_t TxDone              : 1;    // 3
00051         uint8_t ValidHeader         : 1;    // 4
00052         uint8_t PayloadCrcError     : 1;    // 5
00053         uint8_t RxDone              : 1;    // 6
00054         uint8_t RxTimeout           : 1;    // 7
00055     } bits;
00056     uint8_t octet;
00057 } RegIrqFlags_t;
00058 
00059 typedef union {
00060     struct {    // sx127x register 0x18
00061         uint8_t detect          : 1;    // 0
00062         uint8_t sync            : 1;    // 1
00063         uint8_t rx_ongoing      : 1;    // 2
00064         uint8_t header_valid    : 1;    // 3
00065         uint8_t clear           : 1;    // 4
00066         uint8_t RxCodingRate    : 3;    // 5,6,7
00067     } bits;
00068     uint8_t octet;
00069 } RegModemStatus_t;
00070 
00071 typedef union {
00072     struct {    // sx127x register 0x1c
00073         uint8_t FhssPresentChannel  : 6;    // 0,1,2,3,4,5
00074         uint8_t RxPayloadCrcOn      : 1;    // 6
00075         uint8_t PllTimeout          : 1;    // 7
00076     } bits;
00077     uint8_t octet;
00078 } RegHopChannel_t;
00079 
00080 typedef union {
00081     struct {    // sx1276 register 0x1d
00082         uint8_t ImplicitHeaderModeOn    : 1;    // 0
00083         uint8_t CodingRate              : 3;    // 1,2,3
00084         uint8_t Bw                      : 4;    // 4,5,6,7
00085     } sx1276bits;
00086     struct {    // sx1272 register 0x1d
00087         uint8_t LowDataRateOptimize     : 1;    // 0  ppm_offset: number of cyclic shifts possible to encode to symbol
00088         uint8_t RxPayloadCrcOn          : 1;    // 1
00089         uint8_t ImplicitHeaderModeOn    : 1;    // 2
00090         uint8_t CodingRate              : 3;    // 3,4,5
00091         uint8_t Bw                      : 2;    // 6,7
00092     } sx1272bits;
00093     uint8_t octet;
00094 } RegModemConfig_t;
00095 
00096 typedef union {
00097     struct {    // sx1276 register 0x1e
00098         uint8_t SymbTimeoutMsb          : 2;    // 0,1
00099         uint8_t RxPayloadCrcOn          : 1;    // 2
00100         uint8_t TxContinuousMode        : 1;    // 3
00101         uint8_t SpreadingFactor         : 4;    // 4,5,6,7
00102     } sx1276bits;
00103     struct {    // sx1272 register 0x1e
00104         uint8_t SymbTimeoutMsb          : 2;    // 0,1
00105         uint8_t AgcAutoOn               : 1;    // 2
00106         uint8_t TxContinuousMode        : 1;    // 3
00107         uint8_t SpreadingFactor         : 4;    // 4,5,6,7
00108     } sx1272bits;
00109     uint8_t octet;
00110 } RegModemConfig2_t;
00111 
00112 typedef union {
00113     struct {    // sx127x register 0x26
00114         uint8_t reserved    : 2;    // 0,1
00115         uint8_t AgcAutoOn   : 1;    // 2
00116         uint8_t LowDataRateOptimize  : 1;    // 3   ppm_offset
00117         uint8_t unused      : 4;    // 4,5,6,7 
00118     } sx1276bits;
00119     uint8_t octet;
00120     uint8_t sx1272_ppm_correction_msb;
00121 } RegModemConfig3_t;
00122 
00123 
00124 typedef union {
00125     struct {    // sx127x register 0x31
00126         uint8_t detect_trig_same_peaks_nb  : 3;    // 0,1,2
00127         uint8_t disable_pll_timeout        : 1;    // 3
00128         uint8_t tracking_intergral         : 2;    // 4,5
00129         uint8_t frame_sync_gain            : 1;    // 6
00130         uint8_t if_freq_auto               : 1;    // 7
00131     } bits;
00132     uint8_t octet;
00133 } RegTest31_t;
00134 
00135 //class SX127x_lora : public SX127x
00136 class SX127x_lora {
00137     public:
00138         //SX127x_lora(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName dio_0, PinName dio_1, PinName fem_ctx, PinName fem_cps);
00139         SX127x_lora(SX127x& r);
00140         
00141         ~SX127x_lora();
00142         
00143         /** changes from FSK mode to LoRa mdoe */
00144         void enable(void);
00145         
00146         /** fills radio FIFO with payload contents, prior to transmission
00147          * @param len count of bytes to put into FIFO
00148          * @note tx_buf[] should contain desired payload (to send) prior to calling
00149          */
00150         void write_fifo(uint8_t len);     
00151         
00152         /** transmit a packet
00153          * @param len size of packet
00154          * @note Limited to (lora fifo size 256)
00155          */
00156         void start_tx(uint8_t len);
00157         
00158         /** start receive mode
00159          * @note the variable service_action needs to be monitored to indicate read_fifo() needs to be called to pull packet from FIFO.
00160          */
00161         void start_rx(void);
00162         
00163         /** Called by main program when indicated by service_action variable, to pull recevied packet from radio FIFO.
00164          * @returns count of bytes received
00165          * @note received packet in rx_buf[]
00166          */
00167         void read_fifo(uint8_t len);
00168         
00169         /** CodingRate: how much FEC to encoding onto packet */
00170         uint8_t getCodingRate(bool from_rx);    // false:transmitted, true:last recevied packet
00171         void setCodingRate(uint8_t cr);
00172         
00173         /** HeaderMode: explicit mode sents CodingRate and payload length, implicit mode requires assumption by receiver */
00174         bool getHeaderMode(void);
00175         void setHeaderMode(bool hm);
00176 
00177         /** bandwidth: SX1272 has three bandwidths. SX1276 adds more narrower bandwidths. */
00178         uint8_t getBw(void);
00179         void setBw(uint8_t bw);
00180         
00181         /** spreading factor: trade-off between data rate and processing gain (link budget) */
00182         uint8_t getSf(void);
00183         void setSf(uint8_t sf);        
00184         
00185         /** enable CRC in transmitted packet */
00186         bool getRxPayloadCrcOn(void);
00187         void setRxPayloadCrcOn(bool);
00188         
00189         bool getAgcAutoOn(void);
00190         void setAgcAutoOn(bool);
00191         
00192         float get_pkt_rssi(void);
00193         
00194         service_action_e service(void); // (SLIH) ISR bottom half 
00195         
00196         bool poll_vh;
00197         
00198         RegIrqFlags_t       RegIrqFlags;            // 0x12
00199         uint8_t             RegRxNbBytes;           // 0x13
00200         RegModemStatus_t    RegModemStatus;         // 0x18
00201         int8_t              RegPktSnrValue;         // 0x19  signed, s/n can be negative
00202         uint8_t             RegPktRssiValue;        // 0x1a
00203         RegHopChannel_t     RegHopChannel;          // 0x1c
00204         RegModemConfig_t    RegModemConfig;         // 0x1d
00205         RegModemConfig2_t   RegModemConfig2;        // 0x1e
00206         uint16_t            RegPreamble;            // 0x20->0x21
00207         uint8_t             RegPayloadLength;       // 0x22
00208         uint8_t             RegRxMaxPayloadLength;  // 0x23
00209         uint8_t             RegHopPeriod;           // 0x24
00210         RegModemConfig3_t   RegModemConfig3;        // 0x26
00211         RegTest31_t         RegTest31;              // 0x31
00212         
00213     private:
00214         SX127x& m_xcvr;
00215         void set_nb_trig_peaks(int);                                                         
00216 };