shubham c / Mbed 2 deprecated SBC_TEST_CDMS_CODE

CDMS code for testing sbc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

Diff: adf.h

Revision:
176:a5bfe3ca60b1
Parent:
175:e869e7837978
Child:
199:9f03d6ca94c9
--- a/adf.h	Fri Apr 22 11:52:54 2016 +0000
+++ b/adf.h	Fri Apr 22 12:15:09 2016 +0000
@@ -1,14 +1,13 @@
-//Changes made on April 22nd 2016: Included Assert_IRQ_LOW Function
 //without reset feature , with state checks.
 InterruptIn IRQ(ADF_IRQ);
 //Ticker ticker;
+ 
 bool loop_on;
 bool ADF_off;
 bool buffer_state;
 bool finish_write_data;
 uint8_t signal = 0x00;
-/*Modified BBRAM*/unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,/*PA Level Byte*/0x7F/*PA Parameters*/,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x20,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x70,0xE0,0x00,0x10,0x04,0x00,0x00,0x00,0x00,0x00};
-//unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x10,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00};
+unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x10,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00};
  
 //int initialise_card();
 //int disk_initialize();
@@ -46,37 +45,14 @@
 #define CMD_PHY_OFF 0xB0
 #define CMD_PHY_TX 0xB5
 #define CMD_CONFIG_DEV 0xBB
-/*********MEM_RW_CMD*******************/
-#define SPI_MEM_RD_MCR 0x3B
-#define SPI_MEM_RD_BBRAM 0x39
-#define SPI_MEM_RD_BUFFER 0x38
-#define SPI_MEMR_RD_MCR 0x2B 
-#define SPI_MEMR_RD_BBRAM 0x29
-#define SPI_MEMR_RD_BUFFER 0x28
-#define SPI_MEM_WR_MCR 0x1B
-#define SPI_MEM_WR_BBRAM 0x19
-#define SPI_MEM_WR_BUFFER 0x18
-#define SPI_MEMR_WR_MCR 0x0B
-#define SPI_MEMR_WR_BBRAM 0x09
-#define SPI_MEMR_WR_BUFFER 0x08
-/**********MISC*********************/
-#define DEVICE_ID_MSB 0x70
-#define DEVICE_ID_LSB 0x23
-/********************/
-#define assert_IRQ_LOW while(IRQ){\
-        gCS_ADF=0;\
-            spi.write(0x0B);\
-            spi.write(0x36);\
-            spi.write(0xFF);\
-        gCS_ADF=1;\
-        }\
-/********************/
+ 
 #define check_status {\
     unsigned char stat=0;\
     gCS_ADF=0;\
-    spi.write(SPI_NOP);\
-    status = spi.write(SPI_NOP);\
+    spi.write(0xFF);\
+    stat = spi.write(0xFF);\
     gCS_ADF=1;\
+    status = stat;\
 }
  
 // all three arguments are int
@@ -86,7 +62,7 @@
     int state_err_cnt = 0;\
     for(int i = 0 ; i < 40 ;i++){\
         check_status;\
-        if(status&0x1F == 0xB1){\
+        if(status == 0xB1){\
             return_this = 0;\
             break;\
         }\