shubham c / Mbed 2 deprecated SBC_TEST_CDMS_CODE

CDMS code for testing sbc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

i2c.h@206:fba4aeebf004, 2016-06-30 (annotated)

Committer:
chaithanyarss
Date:
Thu Jun 30 14:00:33 2016 +0000
Revision:
206:fba4aeebf004
Parent:
105:5ce0337e7c15
Child:
207:28a07943dded
For integrating PL_Main with rest of CDMS code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aniruddhv 52:0bd68655c651 1 #define tm_len 134
aniruddhv 52:0bd68655c651 2 #define tc_len 135
aniruddhv 52:0bd68655c651 3 #define tc_test_len 135
aniruddhv 52:0bd68655c651 4
aniruddhv 52:0bd68655c651 5 const int addr = 0x20; //slave address
chaithanyarss 206:fba4aeebf004 6 bool write_ack = false;
chaithanyarss 206:fba4aeebf004 7 bool read_ack = false;
chaithanyarss 206:fba4aeebf004 8 const int addr_pl = 0x20<<1; //PL address
chaithanyarss 206:fba4aeebf004 9 const int addr_bae = 0x20; ///bae address
chaithanyarss 206:fba4aeebf004 10 //uint8_t rcv_isr = 0;
aniruddhv 52:0bd68655c651 11
aniruddhv 52:0bd68655c651 12 int count = 0;
aniruddhv 52:0bd68655c651 13
chaithanyarss 206:fba4aeebf004 14 char PL_I2C_DATA[134];//Payload i2c array
chaithanyarss 206:fba4aeebf004 15 uint8_t PL_TM_SIZE;//size of data to bev read from i2c
chaithanyarss 206:fba4aeebf004 16 uint32_t pdirr1;
chaithanyarss 206:fba4aeebf004 17 uint32_t pdirw1;
chaithanyarss 206:fba4aeebf004 18
chaithanyarss 206:fba4aeebf004 19 void I2C_busreset()
chaithanyarss 206:fba4aeebf004 20 {
chaithanyarss 206:fba4aeebf004 21 PORTE->PCR[1] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
chaithanyarss 206:fba4aeebf004 22 PORTE->PCR[0] &= 0xfffffffb; //Enabling high slew rates for SDA and SCL lines
chaithanyarss 206:fba4aeebf004 23 I2C0->C1 &= 0x7f; //Disabling I2C module
chaithanyarss 206:fba4aeebf004 24 SIM->SCGC4 &= 0xffffffbf; //Disabling clock to I2C module
chaithanyarss 206:fba4aeebf004 25 SIM->SCGC4 |= 0x00000040; //Enabling clock to I2C module
chaithanyarss 206:fba4aeebf004 26 I2C0->C1 |= 0x80; //Enabling I2C module
chaithanyarss 206:fba4aeebf004 27 PORTE->PCR[1] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
chaithanyarss 206:fba4aeebf004 28 PORTE->PCR[0] |= 0x00000004; //Disabling high slew rates for SDA and SCL lines
chaithanyarss 206:fba4aeebf004 29 Thread::wait(1); //Wait for all I2C registers to be updates to their their values
chaithanyarss 206:fba4aeebf004 30 }
chaithanyarss 206:fba4aeebf004 31 bool FCTN_I2C_READ_PL(char *data,int length)
chaithanyarss 206:fba4aeebf004 32 {
chaithanyarss 206:fba4aeebf004 33 PL_I2C_GPIO = 1;
chaithanyarss 206:fba4aeebf004 34 read_ack = master.read(addr_pl|1,data,length);
chaithanyarss 206:fba4aeebf004 35 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
chaithanyarss 206:fba4aeebf004 36 pdirr1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 37 uint8_t i2c_count = 0;
chaithanyarss 206:fba4aeebf004 38 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
chaithanyarss 206:fba4aeebf004 39 {
chaithanyarss 206:fba4aeebf004 40 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
chaithanyarss 206:fba4aeebf004 41 {
chaithanyarss 206:fba4aeebf004 42 Thread::wait(1);
chaithanyarss 206:fba4aeebf004 43 pdirr1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 44 i2c_count++;
chaithanyarss 206:fba4aeebf004 45 }
chaithanyarss 206:fba4aeebf004 46 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
chaithanyarss 206:fba4aeebf004 47 {
chaithanyarss 206:fba4aeebf004 48 gPC.printf("\n\rData received from BAE");
chaithanyarss 206:fba4aeebf004 49 }
chaithanyarss 206:fba4aeebf004 50 else
chaithanyarss 206:fba4aeebf004 51 {
chaithanyarss 206:fba4aeebf004 52 I2C_busreset();
chaithanyarss 206:fba4aeebf004 53 read_ack = 1;
chaithanyarss 206:fba4aeebf004 54 }
chaithanyarss 206:fba4aeebf004 55 }
chaithanyarss 206:fba4aeebf004 56 else if (read_ack == 1)
chaithanyarss 206:fba4aeebf004 57 {
chaithanyarss 206:fba4aeebf004 58 I2C_busreset();
chaithanyarss 206:fba4aeebf004 59 }
chaithanyarss 206:fba4aeebf004 60 PL_I2C_GPIO = 0;
chaithanyarss 206:fba4aeebf004 61 i2c_count = 0;
chaithanyarss 206:fba4aeebf004 62 return read_ack;
chaithanyarss 206:fba4aeebf004 63
chaithanyarss 206:fba4aeebf004 64 }
chaithanyarss 206:fba4aeebf004 65 bool FCTN_I2C_WRITE_PL(char *data2,uint8_t tc_len2)
aniruddhv 52:0bd68655c651 66 {
chaithanyarss 206:fba4aeebf004 67 write_ack = master.write(addr_pl|0x00,data2,tc_len2);//address to be defined in payload
chaithanyarss 206:fba4aeebf004 68 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
chaithanyarss 206:fba4aeebf004 69 pdirw1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 70 uint8_t i2c_count = 0;
chaithanyarss 206:fba4aeebf004 71 if(write_ack == 0)
chaithanyarss 206:fba4aeebf004 72 {
chaithanyarss 206:fba4aeebf004 73 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
chaithanyarss 206:fba4aeebf004 74 {
chaithanyarss 206:fba4aeebf004 75 Thread::wait(1);
chaithanyarss 206:fba4aeebf004 76 pdirw1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 77 i2c_count++;
chaithanyarss 206:fba4aeebf004 78 }
chaithanyarss 206:fba4aeebf004 79 if(((pdirw1 & 0x03000000)==0x03000000))
chaithanyarss 206:fba4aeebf004 80 {
chaithanyarss 206:fba4aeebf004 81 gPC.printf("\n\r Data sent");
chaithanyarss 206:fba4aeebf004 82 }
chaithanyarss 206:fba4aeebf004 83 else
chaithanyarss 206:fba4aeebf004 84 {
chaithanyarss 206:fba4aeebf004 85 I2C_busreset();
chaithanyarss 206:fba4aeebf004 86 write_ack = 1;
chaithanyarss 206:fba4aeebf004 87 }
chaithanyarss 206:fba4aeebf004 88 }
chaithanyarss 206:fba4aeebf004 89 if (write_ack == 1)
aniruddhv 52:0bd68655c651 90 {
chaithanyarss 206:fba4aeebf004 91 I2C_busreset();
aniruddhv 52:0bd68655c651 92 }
chaithanyarss 206:fba4aeebf004 93 i2c_count = 0;
chaithanyarss 206:fba4aeebf004 94 return write_ack;
chaithanyarss 206:fba4aeebf004 95 }
chaithanyarss 206:fba4aeebf004 96 bool FCTN_I2C_READ(char *data,int length)
chaithanyarss 206:fba4aeebf004 97 {
chaithanyarss 206:fba4aeebf004 98 CDMS_I2C_GPIO = 1;
chaithanyarss 206:fba4aeebf004 99 read_ack = master.read(addr_bae|1,data,length);
chaithanyarss 206:fba4aeebf004 100 Thread::wait(1); //as per tests Thread::wait not required on master side. But its safe to give 1ms
chaithanyarss 206:fba4aeebf004 101 pdirr1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 102 uint8_t i2c_count = 0;
chaithanyarss 206:fba4aeebf004 103 if(read_ack == 0) //if read_ack says success, it may or may not be successful.Hence we check SCL and SDA
chaithanyarss 206:fba4aeebf004 104 {
chaithanyarss 206:fba4aeebf004 105 while(((pdirr1 & 0x03000000)!=0x03000000)&& i2c_count<10)//checking SCL and SDA for time=10ms
chaithanyarss 206:fba4aeebf004 106 {
chaithanyarss 206:fba4aeebf004 107 Thread::wait(1);
chaithanyarss 206:fba4aeebf004 108 pdirr1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 109 i2c_count++;
chaithanyarss 206:fba4aeebf004 110 }
chaithanyarss 206:fba4aeebf004 111 if(((pdirr1 & 0x03000000)==0x03000000))//if SCL and SDA are both high
chaithanyarss 206:fba4aeebf004 112 {
chaithanyarss 206:fba4aeebf004 113 gPC.printf("\n\rData received from BAE");
chaithanyarss 206:fba4aeebf004 114 }
chaithanyarss 206:fba4aeebf004 115 else
chaithanyarss 206:fba4aeebf004 116 {
chaithanyarss 206:fba4aeebf004 117 I2C_busreset();
chaithanyarss 206:fba4aeebf004 118 read_ack = 1;
chaithanyarss 206:fba4aeebf004 119 }
chaithanyarss 206:fba4aeebf004 120 }
chaithanyarss 206:fba4aeebf004 121 else if (read_ack == 1)
chaithanyarss 206:fba4aeebf004 122 {
chaithanyarss 206:fba4aeebf004 123 I2C_busreset();
chaithanyarss 206:fba4aeebf004 124 }
chaithanyarss 206:fba4aeebf004 125 CDMS_I2C_GPIO = 0;
chaithanyarss 206:fba4aeebf004 126 i2c_count = 0;
chaithanyarss 206:fba4aeebf004 127 return read_ack;
aniruddhv 52:0bd68655c651 128 }
aniruddhv 52:0bd68655c651 129
chaithanyarss 206:fba4aeebf004 130 bool FCTN_I2C_WRITE(char *data,int tc_len2)
chaithanyarss 206:fba4aeebf004 131 {
chaithanyarss 206:fba4aeebf004 132 CDMS_I2C_GPIO = 1;
chaithanyarss 206:fba4aeebf004 133 write_ack = master.write(addr_bae|0x00,data,tc_len2);
chaithanyarss 206:fba4aeebf004 134 Thread::wait(1); //As per the tests Thread::wait is not required on master side but its safe to give 1ms
chaithanyarss 206:fba4aeebf004 135 pdirw1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 136 uint8_t i2c_count = 0;
chaithanyarss 206:fba4aeebf004 137 if(write_ack == 0)
aniruddhv 52:0bd68655c651 138 {
chaithanyarss 206:fba4aeebf004 139 while(((pdirw1 & 0x03000000)!=0x03000000)&& i2c_count<10)
chaithanyarss 206:fba4aeebf004 140 {
chaithanyarss 206:fba4aeebf004 141 Thread::wait(1);
chaithanyarss 206:fba4aeebf004 142 pdirw1=PTE->PDIR;
chaithanyarss 206:fba4aeebf004 143 i2c_count++;
chaithanyarss 206:fba4aeebf004 144 }
chaithanyarss 206:fba4aeebf004 145 if(((pdirw1 & 0x03000000)==0x03000000))
chaithanyarss 206:fba4aeebf004 146 {
chaithanyarss 206:fba4aeebf004 147 gPC.printf("\n\r Data sent");
chaithanyarss 206:fba4aeebf004 148 }
chaithanyarss 206:fba4aeebf004 149 else
chaithanyarss 206:fba4aeebf004 150 {
chaithanyarss 206:fba4aeebf004 151 I2C_busreset();
chaithanyarss 206:fba4aeebf004 152 write_ack = 1;
chaithanyarss 206:fba4aeebf004 153 }
chaithanyarss 206:fba4aeebf004 154 }
chaithanyarss 206:fba4aeebf004 155 if (write_ack == 1)
chaithanyarss 206:fba4aeebf004 156 {
chaithanyarss 206:fba4aeebf004 157 I2C_busreset();
aniruddhv 52:0bd68655c651 158 }
chaithanyarss 206:fba4aeebf004 159 CDMS_I2C_GPIO = 0;
chaithanyarss 206:fba4aeebf004 160 i2c_count = 0;
chaithanyarss 206:fba4aeebf004 161 return write_ack;
aniruddhv 52:0bd68655c651 162 }