shubham c / Mbed 2 deprecated SBC_TEST_CDMS_CODE

CDMS code for testing sbc

Dependencies:   FreescaleIAP SimpleDMA mbed-rtos mbed

Fork of CDMS_CODE by shubham c

DefinitionsAndGlobals.h@256:642ea552ac77, 2016-07-11 (annotated)

Committer:
chaithanyarss
Date:
Mon Jul 11 14:33:02 2016 +0000
Revision:
256:642ea552ac77
Parent:
251:c766afa330a3 
Integration and Testing is in progress

Who changed what in which revision?

UserRevisionLine numberNew contents of line
shreeshas95 0:f016e9e8d48b 1 // **************DEFINITIONS*********************
aniruddhv 69:20f09a0c3fd2 2
ee12b079 245:da9d1bd999da 3 #define bypass_adf 0
aniruddhv 69:20f09a0c3fd2 4
shreeshas95 0:f016e9e8d48b 5 // COM_RX
shreeshas95 5:ab276a17ca07 6 #define RX_TIMEOUT_LIMIT 0.5
ee12b079 197:1369ef45b49e 7 //#define COM_RX_UART_TX PTE20 // For bypassing RX1M (SET BAUD RATE 1200) #define COM_RX_UART_TX USBTX
ee12b079 197:1369ef45b49e 8 //#define COM_RX_UART_RX PTE21 // For bypassing RX1M (SET BAUD RATE 1200) #define COM_RX_UART_RX USBRX
ee12b079 81:1a39e9e14771 9
ee12b079 197:1369ef45b49e 10 #define COM_RX_UART_TX USBTX
ee12b079 197:1369ef45b49e 11 #define COM_RX_UART_RX USBRX
aniruddhv 56:a88e16f6c18e 12
shreeshas95 0:f016e9e8d48b 13 // COMMON SPI
shreeshas95 0:f016e9e8d48b 14 #define SPI_MOSI PTE1
ee12b079 185:3b3cd96a7811 15 #define SPI_MISO PTE3
shreeshas95 0:f016e9e8d48b 16 #define SPI_CLK PTE2
shreeshas95 1:a0055b3280c8 17 #define SPI_CS_ADF PTA15
ee12b079 114:9fb55057b13f 18 #define SPI_CS_SDC PIN20
ee12b079 114:9fb55057b13f 19 #define SPI_CS_RTC PIN26
shreeshas95 2:2caf2a9a13aa 20
shreeshas95 4:104dd82c99b8 21 // COM_TX
shreeshas95 4:104dd82c99b8 22 #define COM_TX_CONFIG_LIMIT 3
aniruddhv 52:0bd68655c651 23 #define COM_TX_TICKER_LIMIT 32
shreeshas95 4:104dd82c99b8 24
ee12b079 209:63e9c8f8b5d2 25 // ADF INTERRUPT
shreeshas95 2:2caf2a9a13aa 26 #define ADF_IRQ PTA14
ee12b079 161:a63672bf4423 27
ee12b079 162:48fda0b8d573 28 //I2C - Payload to CDMS (need to change while using CDMS hardware);
ee12b079 209:63e9c8f8b5d2 29 I2C master(PIN32,PIN31);
ee12b079 209:63e9c8f8b5d2 30 DigitalIn PL_I2C_Intr(PTC13);
ee12b079 209:63e9c8f8b5d2 31 DigitalOut PL_I2C_GPIO(PTC1);
ee12b079 209:63e9c8f8b5d2 32
ee12b079 162:48fda0b8d573 33 //I2C - CDMS to BAE
ee12b079 245:da9d1bd999da 34 DigitalIn BAE_I2C_GPIO(PIN67);//PTB21 from bae to cdms
ee12b079 245:da9d1bd999da 35 DigitalOut CDMS_I2C_GPIO(PIN39);//PTA5 from cdms to bae
ee12b079 162:48fda0b8d573 36
shreeshas95 0:f016e9e8d48b 37 // TC LIST
shreeshas95 2:2caf2a9a13aa 38 #define TCL_STATE_INCOMPLETE 0x00
shreeshas95 5:ab276a17ca07 39 #define TCL_STATE_ABORTED 0x03
shreeshas95 5:ab276a17ca07 40 #define TCL_STATE_EXECUTING 0x04
shreeshas95 5:ab276a17ca07 41 #define TCL_STATE_COMPLETED 0x05
shreeshas95 5:ab276a17ca07 42 #define TCL_STATE_EXCEEDED_LIMIT 0x06
shreeshas95 0:f016e9e8d48b 43
shreeshas95 0:f016e9e8d48b 44 // LIST OF FLAGS
shreeshas95 2:2caf2a9a13aa 45 #define UART_INT_FLAG 0x0001
shreeshas95 2:2caf2a9a13aa 46 #define NEW_TC_RECEIVED 0x0002
shreeshas95 2:2caf2a9a13aa 47 #define COM_SESSION_FLAG 0x0004
shreeshas95 2:2caf2a9a13aa 48 #define COM_RX_FLAG 0x0008
shreeshas95 2:2caf2a9a13aa 49 #define COM_MNG_TMTC_RUNNING_FLAG 0x0010
shreeshas95 2:2caf2a9a13aa 50 #define COM_SESSION_VALIDITY 0x0020
shreeshas95 2:2caf2a9a13aa 51 #define ALL_CRC_PASS_FLAG 0x0040
shreeshas95 2:2caf2a9a13aa 52 #define COM_PA_HOT_FLAG 0x0080
shreeshas95 2:2caf2a9a13aa 53 #define COM_TX_FLAG 0x0100
shreeshas95 6:79d422d1ed42 54 #define COM_SESSION_TIMEOUT_FLAG 0x0200
ee12b079 209:63e9c8f8b5d2 55 #define COM_AUTO_POWER_OFF_BAE_FLAG 0x0400
ee12b079 209:63e9c8f8b5d2 56 #define BAE_SW_EN_FLAG 0x0800
ee12b079 209:63e9c8f8b5d2 57 #define RF_SW_STATUS_FLAG 0x1000
ee12b079 209:63e9c8f8b5d2 58 #define COM_INIT_STATUS_FLAG 0x2000
ee12b079 209:63e9c8f8b5d2 59 #define COM_TX_STATUS_FLAG 0x4000
ee12b079 209:63e9c8f8b5d2 60
ee12b079 209:63e9c8f8b5d2 61 //RF relay STATUS
ee12b079 209:63e9c8f8b5d2 62 #define RF_COM_TX 0
ee12b079 209:63e9c8f8b5d2 63 #define RF_BCN 1
shreeshas95 0:f016e9e8d48b 64
shreeshas95 0:f016e9e8d48b 65 // COM_MNG_TMTC THREAD
shreeshas95 6:79d422d1ed42 66 #define SESSION_TIME_LIMIT 1500
shreeshas95 0:f016e9e8d48b 67 #define COM_MNG_TMTC_SIGNAL_UART_INT 0x01
shreeshas95 0:f016e9e8d48b 68 #define COM_MNG_TMTC_SIGNAL_ADF_NSD 0x02
shreeshas95 0:f016e9e8d48b 69 #define COM_MNG_TMTC_SIGNAL_ADF_SD 0x03
ee12b079 245:da9d1bd999da 70
shreeshas95 0:f016e9e8d48b 71 // COM_MNG_TMTC
shreeshas95 2:2caf2a9a13aa 72 #define COM_PA_COOLING_TIME_LIMIT 20
shreeshas95 4:104dd82c99b8 73 #define COM_MAX_TC_LIMIT 200
shreeshas95 4:104dd82c99b8 74 #define TM_ACK_CODE_INDEX 2
shreeshas95 5:ab276a17ca07 75 #define CRC_FAIL_NACK_CODE 0x01
shreeshas95 2:2caf2a9a13aa 76
shreeshas95 2:2caf2a9a13aa 77 // call sign
shreeshas95 2:2caf2a9a13aa 78 #define PSC_CALLSIGN 0x00
shreeshas95 2:2caf2a9a13aa 79 #define APID_CALLSIGN 0x00
shreeshas95 2:2caf2a9a13aa 80
shreeshas95 2:2caf2a9a13aa 81 // max value of telecommands in a tcl
shreeshas95 2:2caf2a9a13aa 82 #define TCL_OVERFLOW_CONSTANT 256
shreeshas95 4:104dd82c99b8 83 #define TM_OVERFLOW_CONSTANT 256
shreeshas95 2:2caf2a9a13aa 84
shreeshas95 0:f016e9e8d48b 85 // starting value of packet sequence count at each pass
shreeshas95 0:f016e9e8d48b 86 #define PSC_START_VALUE 1
shreeshas95 0:f016e9e8d48b 87
shreeshas95 0:f016e9e8d48b 88 // APID list
aniruddhv 52:0bd68655c651 89 #define APID_COM 0
shreeshas95 0:f016e9e8d48b 90 #define APID_BAE 1
shreeshas95 0:f016e9e8d48b 91 #define APID_CDMS 2
shreeshas95 0:f016e9e8d48b 92 #define APID_SPEED 3
shreeshas95 0:f016e9e8d48b 93
aniruddhv 52:0bd68655c651 94 //SERVICE
aniruddhv 52:0bd68655c651 95 #define SERVICE_OBOSC 0xB
aniruddhv 52:0bd68655c651 96 #define SERVICE_OBSRS 0xF
aniruddhv 52:0bd68655c651 97
shreeshas95 0:f016e9e8d48b 98 // HIGH PRIORITY TC - priority list
shreeshas95 0:f016e9e8d48b 99 // not correct values here
shreeshas95 0:f016e9e8d48b 100 #define HPTC1 5
shreeshas95 0:f016e9e8d48b 101 #define HPTC2 6
shreeshas95 0:f016e9e8d48b 102 // Add more entries above
shreeshas95 0:f016e9e8d48b 103
shreeshas95 0:f016e9e8d48b 104 // TMID list
shreeshas95 0:f016e9e8d48b 105 #define TMID_ACK_L1 0xA
shreeshas95 4:104dd82c99b8 106 #define TMID_ACK_L234 0xB
shreeshas95 4:104dd82c99b8 107 #define TMID_TCL 0x7
shreeshas95 4:104dd82c99b8 108 #define TMID_CALL_SIGN 0xE
shreeshas95 0:f016e9e8d48b 109
shreeshas95 0:f016e9e8d48b 110 // OBOSC SERVICE SUBTYPE
shreeshas95 4:104dd82c99b8 111 #define OBOSC_TCL_MAX_SHORT_SIZE 11
shreeshas95 4:104dd82c99b8 112 #define OBOSC_LONG_TC_FIRST_HALF_SIZE 67
shreeshas95 4:104dd82c99b8 113 #define OBOSC_LONG_TC_SECOND_HALF_SIZE 68
shreeshas95 4:104dd82c99b8 114 #define OBOSC_TCL_TAG_LONG_FIRST_HALF 0x10
shreeshas95 4:104dd82c99b8 115 #define OBOSC_TCL_TAG_LONG_SECOND_HALF 0x11
shreeshas95 4:104dd82c99b8 116
shreeshas95 0:f016e9e8d48b 117 #define OBOSC_SUB_DISABLE 0x01
shreeshas95 0:f016e9e8d48b 118 #define OBOSC_SUB_RETRY 0x05
shreeshas95 4:104dd82c99b8 119 #define OBOSC_SUB_REP_TCLD 0x06
shreeshas95 0:f016e9e8d48b 120 #define OBOSC_SUB_REP_LE 0x0F
shreeshas95 0:f016e9e8d48b 121 #define OBOSC_SUB_RESET 0x07
shreeshas95 0:f016e9e8d48b 122
shreeshas95 101:bece931236a2 123 // PAYLOAD or SCIENCE
shreeshas95 101:bece931236a2 124 #define PAYLOAD_BUFFER_LENGTH 6723
ee12b079 113:b8991d9e3b6c 125 #define PAY_SPI_MOSI PTE18
ee12b079 113:b8991d9e3b6c 126 #define PAY_SPI_MISO PTE19
ee12b079 113:b8991d9e3b6c 127 #define PAY_SPI_CLK PTE17
ee12b079 113:b8991d9e3b6c 128 #define PAY_SPI_CS PTE16
ee12b079 245:da9d1bd999da 129 #define SCIENCE_SIGNAL 0x04
ee12b079 209:63e9c8f8b5d2 130
ee12b079 209:63e9c8f8b5d2 131 //BEACON
ee12b079 209:63e9c8f8b5d2 132 #define BCN_APID_SOURCE 0x41
ee12b079 209:63e9c8f8b5d2 133 #define BCN_SERVICE 0x81
shreeshas95 101:bece931236a2 134
ee12b079 209:63e9c8f8b5d2 135 //BAE
ee12b079 209:63e9c8f8b5d2 136 #define BAE_APID_SOURCE 0x81
ee12b079 209:63e9c8f8b5d2 137 #define BAE_SERVICE 0x81
ee12b079 209:63e9c8f8b5d2 138 #define BAE_POWER_ON_PID 0x13
ee12b079 209:63e9c8f8b5d2 139 #define BAE_POWER_OFF_PID 0x23
ee12b079 209:63e9c8f8b5d2 140 #define BAE_RESET_PID 0x33
ee12b079 209:63e9c8f8b5d2 141
ee12b079 209:63e9c8f8b5d2 142 //RF RELAY
ee12b079 209:63e9c8f8b5d2 143 #define RF_RELAY_CNTRL_TX PTA7
ee12b079 209:63e9c8f8b5d2 144 #define RF_RELAY_CNTRL_BCN PTA12
chaithanyarss 224:3ac1f91e0ebc 145
chaithanyarss 224:3ac1f91e0ebc 146 //CDMS HK
ee12b079 246:565458eefd94 147 #define HK_SIGNAL 0x05
chaithanyarss 224:3ac1f91e0ebc 148 #define COMRX_ALIVE 0x01
chaithanyarss 224:3ac1f91e0ebc 149 #define COMRX_DEAD 0x00
chaithanyarss 224:3ac1f91e0ebc 150 #define DEVICE_ENABLED 0x00
chaithanyarss 224:3ac1f91e0ebc 151 #define DEVICE_POWERED 0x01
chaithanyarss 224:3ac1f91e0ebc 152 #define DEVICE_OC_FAULT 0x02
chaithanyarss 224:3ac1f91e0ebc 153 #define DEVICE_DISABLED 0x03
chaithanyarss 224:3ac1f91e0ebc 154
ee12b079 209:63e9c8f8b5d2 155
shreeshas95 3:6c81fc8834e2 156
shreeshas95 0:f016e9e8d48b 157 // ****************GLOBAL VARIABLES******************
chaithanyarss 251:c766afa330a3 158
chaithanyarss 251:c766afa330a3 159 //Global
chaithanyarss 251:c766afa330a3 160 Mutex gMutex;
chaithanyarss 251:c766afa330a3 161
chaithanyarss 251:c766afa330a3 162
shreeshas95 0:f016e9e8d48b 163 // DEBUG
shreeshas95 0:f016e9e8d48b 164 Serial gPC( USBTX, USBRX );
shreeshas95 4:104dd82c99b8 165 DigitalOut gLEDR(LED_RED);
shreeshas95 4:104dd82c99b8 166 DigitalOut gLEDG(LED_GREEN);
shreeshas95 0:f016e9e8d48b 167
shreeshas95 0:f016e9e8d48b 168 // COM_RX
shreeshas95 0:f016e9e8d48b 169 RawSerial RX1M( COM_RX_UART_TX, COM_RX_UART_RX );
shreeshas95 0:f016e9e8d48b 170 COM_RX_DATA_NODE *gRX_HEAD_DATA_NODE = NULL;
shreeshas95 0:f016e9e8d48b 171 COM_RX_DATA_NODE *gRX_CURRENT_DATA_NODE = NULL;
shreeshas95 2:2caf2a9a13aa 172 // uint8_t *gRX_CURRENT_PTR = NULL;
shreeshas95 0:f016e9e8d48b 173 uint32_t gRX_COUNT = 0;
shreeshas95 0:f016e9e8d48b 174 uint16_t gTOTAL_INCORRECT_SIZE_TC = 0x00;
shreeshas95 0:f016e9e8d48b 175 uint16_t gTOTAL_CRC_FAIL_TC = 0x00;
shreeshas95 2:2caf2a9a13aa 176 uint16_t gTOTAL_REPEATED_TC = 0x00;
shreeshas95 0:f016e9e8d48b 177
shreeshas95 0:f016e9e8d48b 178 // COMMON SPI
shreeshas95 0:f016e9e8d48b 179 SPI spi( SPI_MOSI, SPI_MISO, SPI_CLK );
shreeshas95 1:a0055b3280c8 180 DigitalOut gCS_ADF(SPI_CS_ADF);
ee12b079 86:a26f5f22631d 181 DigitalOut cs_sd(SPI_CS_SDC);
shreeshas95 2:2caf2a9a13aa 182 DigitalOut gCS_RTC(SPI_CS_RTC);
shreeshas95 0:f016e9e8d48b 183 Mutex SPI_mutex;
shreeshas95 0:f016e9e8d48b 184
ee12b079 209:63e9c8f8b5d2 185 //I2C
ee12b079 209:63e9c8f8b5d2 186 Mutex BAE_I2C_mutex;
ee12b079 209:63e9c8f8b5d2 187
ee12b079 209:63e9c8f8b5d2 188 //RF Relay
ee12b079 209:63e9c8f8b5d2 189 DigitalOut RF_SW_CNTRL_BCN(RF_RELAY_CNTRL_BCN);
ee12b079 209:63e9c8f8b5d2 190 DigitalOut RF_SW_CNTRL_TX(RF_RELAY_CNTRL_TX);
ee12b079 209:63e9c8f8b5d2 191
ee12b079 209:63e9c8f8b5d2 192 //COM_RX
ee12b079 209:63e9c8f8b5d2 193 DigitalOut COM_RX_CNTRL(PIN72);
ee12b079 209:63e9c8f8b5d2 194 DigitalOut COM_TX_CNTRL(PIN56);
ee12b079 209:63e9c8f8b5d2 195
shreeshas95 0:f016e9e8d48b 196 // TC LIST
shreeshas95 0:f016e9e8d48b 197 Base_tc* gHEAD_NODE_TCL = NULL;
shreeshas95 0:f016e9e8d48b 198 Base_tc* gLAST_NODE_TCL = NULL;
shreeshas95 2:2caf2a9a13aa 199 uint8_t gMASTER_STATE = TCL_STATE_INCOMPLETE;
shreeshas95 2:2caf2a9a13aa 200 uint16_t gFLAGS = 0x0000;
shreeshas95 0:f016e9e8d48b 201
shreeshas95 0:f016e9e8d48b 202 // COM_MNG_TMTC THREAD
shreeshas95 0:f016e9e8d48b 203 Thread* gCOM_MNG_TMTC_THREAD = NULL;
shreeshas95 0:f016e9e8d48b 204 Timeout gRX_TIMEOUT;
shreeshas95 0:f016e9e8d48b 205 Timeout gSESSION_TIMEOUT;
shreeshas95 0:f016e9e8d48b 206
shreeshas95 0:f016e9e8d48b 207 // COM_MNG_TMTC
shreeshas95 2:2caf2a9a13aa 208
ee12b079 209:63e9c8f8b5d2 209
ee12b079 209:63e9c8f8b5d2 210
shreeshas95 2:2caf2a9a13aa 211 // PA cooling timeout
shreeshas95 4:104dd82c99b8 212 Timeout gCOM_PA_COOLING_TIMEOUT;
shreeshas95 2:2caf2a9a13aa 213
shreeshas95 2:2caf2a9a13aa 214 // GS code for verification
aniruddhv 37:c9a739750806 215 const uint8_t gGSCODE[] = {0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
shreeshas95 2:2caf2a9a13aa 216
shreeshas95 0:f016e9e8d48b 217 uint8_t gTOTAL_VALID_TC = 0x00;
shreeshas95 0:f016e9e8d48b 218 // USE LAST_L1_ACK FOR GENERATING REPORT
shreeshas95 4:104dd82c99b8 219 uint8_t gLAST_TM[TM_LONG_SIZE];
shreeshas95 4:104dd82c99b8 220 uint8_t gLAST_TM_SHORT_OR_LONG = SHORT_TM_CODE;
shreeshas95 3:6c81fc8834e2 221
shreeshas95 101:bece931236a2 222 // PAYLOAD OR SCIENCE_THREAD
shreeshas95 3:6c81fc8834e2 223 Thread* gSCIENCE_THREAD = NULL;
ee12b079 245:da9d1bd999da 224 dmaSPISlave *gPAY_SPI;
ee12b079 189:0636c8391407 225 uint8_t gPAYLOAD_BUFFER[PAYLOAD_BUFFER_LENGTH] = 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chaithanyarss 251:c766afa330a3 226 RtosTimer *PL_wo_dma;
ee12b079 209:63e9c8f8b5d2 227
shreeshas95 4:104dd82c99b8 228 // CALL SIGN TM
shreeshas95 103:b55559925dc1 229 const uint8_t gCALL_SIGN_STRING[TM_SHORT_SIZE] = {0xE0, 0x00, 0x00, 0x00, 0x56, 0x55, 0x32, 0x4E, 0x43, 0x46, 0x00, 0xAC, 0x11};
shreeshas95 103:b55559925dc1 230
ee12b079 245:da9d1bd999da 231 //HK Thread
ee12b079 245:da9d1bd999da 232 Thread* gHK_THREAD = NULL;
ee12b079 245:da9d1bd999da 233 RtosTimer *HK_counter;
ee12b079 245:da9d1bd999da 234
shreeshas95 103:b55559925dc1 235 // CDMS HK
ee12b079 209:63e9c8f8b5d2 236 uint8_t CDMS_STANDBY;
ee12b079 209:63e9c8f8b5d2 237 uint8_t CDMS_HEALTH_DATA[128];
ee12b079 209:63e9c8f8b5d2 238 uint8_t CDMS_RAM[59];
ee12b079 209:63e9c8f8b5d2 239 uint16_t GPIO_STATUS;
ee12b079 209:63e9c8f8b5d2 240 uint8_t CDMS_HK_MAIN_STATUS;
ee12b079 209:63e9c8f8b5d2 241 uint8_t COMRX_STATUS;
ee12b079 209:63e9c8f8b5d2 242 uint8_t RTC_FAULTCOUNT;
ee12b079 209:63e9c8f8b5d2 243 uint16_t SD_FAULTCOUNT;
ee12b079 209:63e9c8f8b5d2 244 uint8_t SD_STATUS;
ee12b079 209:63e9c8f8b5d2 245 uint8_t BAE_FAULTCOUNT;
ee12b079 209:63e9c8f8b5d2 246 uint8_t BAE_STATUS;
ee12b079 209:63e9c8f8b5d2 247 uint8_t PL_STATUS;
ee12b079 209:63e9c8f8b5d2 248 uint16_t PL_FAULTCOUNT;
ee12b079 209:63e9c8f8b5d2 249 bool BAE_HK_I2C;
ee12b079 209:63e9c8f8b5d2 250 uint8_t RTC_STATUS;
ee12b079 209:63e9c8f8b5d2 251 float RSSI_volatge;
ee12b079 209:63e9c8f8b5d2 252
shreeshas95 103:b55559925dc1 253 CDMS_HK_actual actual_data;
shreeshas95 103:b55559925dc1 254 CDMS_HK_quant quant_data;
shreeshas95 103:b55559925dc1 255 CDMS_HK_min_max min_max_data;
ee12b079 193:ab528911780d 256 bool firstCount=true;
ee12b079 193:ab528911780d 257
ee12b079 209:63e9c8f8b5d2 258 //GPIO PINS
ee12b079 209:63e9c8f8b5d2 259 DigitalIn V_A_PGOOD (PIN88);
ee12b079 209:63e9c8f8b5d2 260 DigitalIn V_B_PGOOD_1 (PIN6);
ee12b079 209:63e9c8f8b5d2 261 DigitalIn V_B_PGOOD_2 (PIN7);
ee12b079 209:63e9c8f8b5d2 262 DigitalIn V_C_PGOOD (PIN54);
ee12b079 209:63e9c8f8b5d2 263 DigitalIn COMRX_OC_FAULT (PIN68);
ee12b079 209:63e9c8f8b5d2 264 DigitalIn COMTX_OC_FAULT (PIN69);
ee12b079 209:63e9c8f8b5d2 265 DigitalIn BAE_OC_FAULT (PIN92);
chaithanyarss 256:642ea552ac77 266 DigitalOut PL_GPIO_1_STATUS (PIN71);
chaithanyarss 256:642ea552ac77 267 DigitalOut PL_GPIO_2_STATUS (PIN81);
chaithanyarss 256:642ea552ac77 268 DigitalOut PL_GPIO_3_STATUS (PIN80);
chaithanyarss 224:3ac1f91e0ebc 269 DigitalIn PL_BEE_SW_OC_FAULT (PIN91);
chaithanyarss 224:3ac1f91e0ebc 270 DigitalIn PL_EPS_LATCH_SW_OC_FAULT (PIN5);
chaithanyarss 256:642ea552ac77 271 DigitalOut EPS_V_C_EN_STATUS (PIN72);
chaithanyarss 256:642ea552ac77 272 DigitalOut EPS_V_D_EN_STATUS (PIN56);
chaithanyarss 256:642ea552ac77 273
ee12b079 209:63e9c8f8b5d2 274
ee12b079 209:63e9c8f8b5d2 275
ee12b079 209:63e9c8f8b5d2 276 DigitalIn SD_OC_FAULT (PIN90);
ee12b079 209:63e9c8f8b5d2 277 DigitalOut SD_SW_EN_DS (PIN97);
ee12b079 209:63e9c8f8b5d2 278 DigitalOut BAE_SW_EN_DS (PIN47);
chaithanyarss 256:642ea552ac77 279 DigitalOut TRXY_EN (PIN84);
chaithanyarss 256:642ea552ac77 280 DigitalOut TRZ_EN (PIN88);
chaithanyarss 256:642ea552ac77 281 DigitalOut V_A_EN (PIN99);
chaithanyarss 256:642ea552ac77 282 DigitalOut Sys_pwr_rst (PIN96);
ee12b079 245:da9d1bd999da 283
ee12b079 245:da9d1bd999da 284 DigitalOut PYLD_DFF (PIN73);
ee12b079 245:da9d1bd999da 285 DigitalOut PYLD_DFF_CLK (PIN65);
ee12b079 245:da9d1bd999da 286 DigitalOut PYLD_EPS_DFF_PWR (PIN64);
ee12b079 245:da9d1bd999da 287 DigitalOut PYLD_EPS_DFF_PWR_CLK (PIN40);
ee12b079 245:da9d1bd999da 288
ee12b079 245:da9d1bd999da 289 DigitalOut RESET_TO_BAE(PIN93,1);
ee12b079 245:da9d1bd999da 290 DigitalOut RESET_TO_PYLD(PIN21);
ee12b079 209:63e9c8f8b5d2 291
ee12b079 193:ab528911780d 292 //SD HK
ee12b079 193:ab528911780d 293 uint32_t FSC_CURRENT[6];
ee12b079 195:6a549c0e9287 294 uint32_t FSC_LAST[6];
ee12b079 209:63e9c8f8b5d2 295 uint8_t SD_RD_ERROR;
ee12b079 209:63e9c8f8b5d2 296
ee12b079 209:63e9c8f8b5d2 297 //Time's
ee12b079 209:63e9c8f8b5d2 298 uint32_t TIME_LATEST_RTC;
ee12b079 209:63e9c8f8b5d2 299 uint32_t TIME_LATEST_I2C_BAE;
ee12b079 209:63e9c8f8b5d2 300 uint32_t TIME_LATEST_I2C_SPEED;
ee12b079 209:63e9c8f8b5d2 301 uint32_t TIME_LATEST_SD_WR;
ee12b079 209:63e9c8f8b5d2 302 uint32_t TIME_LATEST_SD_RD;
ee12b079 209:63e9c8f8b5d2 303 uint32_t TIME_LATEST_SPI_SPEED;
ee12b079 209:63e9c8f8b5d2 304
ee12b079 209:63e9c8f8b5d2 305 //Counter's
ee12b079 209:63e9c8f8b5d2 306 uint16_t CDMS_I2C_ERR_SPEED_COUNTER;
ee12b079 209:63e9c8f8b5d2 307 uint16_t CDMS_I2C_ERR_BAE_COUNTER;
ee12b079 209:63e9c8f8b5d2 308 uint16_t CDMS_HK_MAIN_COUNTER;
ee12b079 209:63e9c8f8b5d2 309 uint16_t COMRX_RESET_COUNTER;
ee12b079 209:63e9c8f8b5d2 310 uint16_t PL_MAIN_COUNTER;
ee12b079 209:63e9c8f8b5d2 311 uint16_t PL_RCV_SC_DATA_COUNTER;
chaithanyarss 256:642ea552ac77 312 uint16_t CDMS_WR_SD_FAULT_COUNTER;
chaithanyarss 256:642ea552ac77 313 uint16_t SD_LIB_WRITES = 0;
ee12b079 209:63e9c8f8b5d2 314
ee12b079 209:63e9c8f8b5d2 315 //CDMS RAM parameters
ee12b079 209:63e9c8f8b5d2 316 uint8_t PL_INIT_STATUS;
ee12b079 209:63e9c8f8b5d2 317 uint8_t PL_MAIN_STATUS;
ee12b079 209:63e9c8f8b5d2 318 uint8_t PL_LOW_POWER;
ee12b079 209:63e9c8f8b5d2 319 uint8_t PL_STATE;
ee12b079 209:63e9c8f8b5d2 320 uint8_t PL_RCV_SC_DATA_STATUS;
ee12b079 209:63e9c8f8b5d2 321 uint8_t COM_SESSION;
ee12b079 209:63e9c8f8b5d2 322 uint8_t COM_RX;
ee12b079 209:63e9c8f8b5d2 323 uint8_t RF_SW_STATUS;
ee12b079 209:63e9c8f8b5d2 324 uint8_t COM_TX;
ee12b079 209:63e9c8f8b5d2 325 uint8_t COM_TX_STATUS;
ee12b079 209:63e9c8f8b5d2 326 uint8_t COM_MNG_TMTC;
chaithanyarss 256:642ea552ac77 327 uint8_t EN_CDMS_HK;
chaithanyarss 256:642ea552ac77 328 uint8_t EN_PL;
chaithanyarss 256:642ea552ac77 329 uint8_t EN_RCV_SC;
ee12b079 209:63e9c8f8b5d2 330 uint8_t CDMS_INIT_STATUS;
ee12b079 209:63e9c8f8b5d2 331 uint8_t CDMS_HK_STATUS;
chaithanyarss 256:642ea552ac77 332 uint8_t COM_RX_STATUS;
chaithanyarss 256:642ea552ac77 333 uint8_t CDMS_RTC_BL;
chaithanyarss 256:642ea552ac77 334
chaithanyarss 256:642ea552ac77 335 //CDMS FLASH parameters
chaithanyarss 256:642ea552ac77 336 uint8_t EPS_V_A_EN_STATUS;
chaithanyarss 256:642ea552ac77 337 uint8_t BAE_SW_STATUS;
chaithanyarss 256:642ea552ac77 338 uint8_t CDMS_SD_SW_STATUS;
chaithanyarss 256:642ea552ac77 339 uint8_t PL_BEE_SW_STATUS;
chaithanyarss 256:642ea552ac77 340 uint8_t PL_EPS_LATCH_SW_EN;
chaithanyarss 256:642ea552ac77 341 uint8_t RTC_INIT_STATUS;
chaithanyarss 256:642ea552ac77 342 uint8_t CDMS_RTC_DISABLE;
chaithanyarss 256:642ea552ac77 343 uint16_t CDMS_RESET_COUNTER;
chaithanyarss 256:642ea552ac77 344 uint32_t TIME_LATEST_CDSMS_RESET;
chaithanyarss 256:642ea552ac77 345 uint16_t COM_TC_BYTES_LIMIT;
chaithanyarss 256:642ea552ac77 346 uint8_t COM_RX_CURRENT_MAX;
chaithanyarss 256:642ea552ac77 347 uint8_t COM_RX_DISABLE_TIMEOUT;
chaithanyarss 256:642ea552ac77 348 uint8_t COM_PA_TMP_HIGH;
chaithanyarss 256:642ea552ac77 349 uint8_t COM_PA_RECOVERY_TIMEOUT;
chaithanyarss 256:642ea552ac77 350 uint8_t COM_SESSION_TIMEOUT;
chaithanyarss 256:642ea552ac77 351 uint8_t COM_RSSI_MIN;
chaithanyarss 256:642ea552ac77 352 uint16_t SD_LIB_BLK_CURRENT;