Revision 0:15355bb24274, committed 2015-02-06

Comitter:

ee12b079

Date:

Fri Feb 06 15:57:03 2015 +0000

Commit message:

For_BAE_integration

Changed in this revision

diff -r 000000000000 -r 15355bb24274 beacon.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/beacon.h	Fri Feb 06 15:57:03 2015 +0000
@@ -0,0 +1,3 @@
+#include "mbed.h"
+void writereg(uint8_t ,uint8_t );
+uint8_t readreg(uint8_t);
\ No newline at end of file

diff -r 000000000000 -r 15355bb24274 main.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp	Fri Feb 06 15:57:03 2015 +0000
@@ -0,0 +1,202 @@
+//switch off the sync!!!!!!!
+//switch off the preamble!!!!!!!
+/*for crc in tx:
+regIrq2(0x28) :
+
+regpacketconfig 1(0x37) :
+set crc detection/calc. on : | 0x10
+crcautoclearoff : | 0x08  
+
+for data whitening : regpacketconfig 1(0x37) :| 0x40
+for 
+//checked for wait insted of an interrupt
+
+
+*/
+// 6CC000 for 435 MHz
+//set all values as FF for checking on spectrum analyzer
+#include "beacon.h"
+//Serial pc(USBTX, USBRX);           // tx, rx
+Serial pc(USBTX, USBRX);
+SPI spi(D11, D12, D13);               // mosi, miso, sclk
+DigitalOut cs_bar(D10);                 //slave select or chip select
+//InterruptIn button(p9);
+//#define TIMES 16      
+//Timer t;
+
+/*void interrupt_func()
+{
+    pc.printf("INTERRUPT_FUNC TRIGGERED\n  wait for 3 secs\n"); 
+    wait_ms(800);
+    
+}*/
+void writereg(uint8_t reg,uint8_t val)
+{
+    cs_bar = 0;
+    spi.write(reg | 0x80);      
+    spi.write(val);
+    cs_bar = 1;
+}
+uint8_t readreg(uint8_t reg)
+{
+    uint8_t val;
+    cs_bar = 0;
+    spi.write(reg & ~0x80);        
+    val = spi.write(0);
+    cs_bar = 1;
+    return val;
+}
+        
+main() {
+    int n = 0;
+    //button.rise(&interrupt_func);         //interrupt enabled ( rising edge of pin 9)
+    wait(0.02);                                                           // pl. update this value  or even avoid it!!!                  
+    //extract values from short_beacon[]
+    uint8_t byte_counter = 0;
+    struct Short_beacon{
+        uint8_t Voltage[1];
+        uint8_t AngularSpeed[2];
+        uint8_t SubsystemStatus[1];
+        uint8_t Temp[3];
+        uint8_t ErrorFlag[1];
+        }Shortbeacon = { {0x88}, {0x99, 0xAA} , {0xAA},{0xAA,0xDD,0xEE}, {0x00} };
+    
+    //filling hk data
+    //uint8_t short_beacon[] = { 0xAB, 0x8A, 0xE2, 0xBB, 0xB8, 0xA2, 0x8E,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
+    uint8_t short_beacon[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,Shortbeacon.Voltage[0],Shortbeacon.AngularSpeed[0], Shortbeacon.AngularSpeed[1],Shortbeacon.SubsystemStatus[0],Shortbeacon.Temp[0],Shortbeacon.Temp[1],Shortbeacon.Temp[2],Shortbeacon.ErrorFlag[0]};
+    //mask
+    //uint8_t mask[] = {0x80, 0x40, 0x20,0x10,0x8,0x4,0x2,0x1};
+        
+    /*for(int i = 0; i < 15 ; i++)
+    {
+        pc.printf("0x%X\n",(short_beacon[i]));    
+    }*/
+    
+    spi.format(8,0);                    
+    spi.frequency(10000000);             //10MHz SCLK frequency(its max for rfm69hcw)
+    
+    cs_bar = 1;                              // Chip must be deselected
+    
+       if (readreg(0x15) == 0xB0) pc.printf("spi connection valid\n");
+    else {pc.printf("error in spi connection\n"); wait(10); }
+    
+    //initialization
+    //Common configuration registers
+    writereg(0x01,0x00);       //sequencer on,standby mode
+    writereg(0x02,0x08);// |0x01);       //packet, ook, no dc           //0x00 for fsk   //default = 0x08 for ook
+    writereg(0x03,0x68);       //1200bps
+    writereg(0x04,0x2B);       //1200bps
+    writereg(0x07,0x6C);       
+    writereg(0x08,0xC0);    
+    writereg(0x09,0x00);       //try 6C C0 00 for 435 MHZ    //try 6C 40 00 for 432.something            //try E4 C0 00 for 915
+    
+    //FSK settings
+    /*writereg(0x05,0x06);
+    writereg(0x06,0x66);//for fdev ~ 100kHz*/
+    
+    
+    //Transmitter registers
+    // RegPaLevel
+    
+    //IRQ and Pin Mapping Registers
+    //no DIO mapped yet
+    //irq1: modeready used
+    //irq2: fifofull, fifothresh,packetsent used
+    
+    //Packet Engine Registers
+    writereg(0x2C,0x00);        //set preamble
+    writereg(0x2D,0x0A);        //set preamble default(0x0A)
+    writereg(0x2E,0x80);        //sync off               ..........................
+    writereg(0x2F,0x5E);        //sync word 1               .........................
+    writereg(0x37,0x08 | 0x10);// | 0x40);        //packetconfig1 data whitening(0x40), crc (0x10)               packet issue even if crc fails???..........................
+    writereg(0x38,0x00);        //payload length = 0 ... unlimited payload mode
+    writereg(0x3C,0xB0);         //fifothresh = 48      because we want it cleared once its 40!!!!
+    //Initialization complete
+    
+    pc.printf("press t \n");
+    while(pc.getc() == 't'){
+    //t.start();  
+    //Filling Data into FIFO 64 BYTES : eff.32 bits = 4bytes                  //fread
+    cs_bar = 0; 
+    spi.write(0x80);//fifo write access
+    for(byte_counter=0 ; byte_counter<4; byte_counter++)
+    {    
+        for(int i=7; i>=0  ; i--)
+        {
+            if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
+            //if((short_beacon[byte_counter] & mask[i]) != 0)
+            {
+                spi.write(0xFF);
+                spi.write(0xFF);
+            }
+    else
+            {
+                spi.write(0x00);
+                spi.write(0x00);
+            }
+        }
+    }
+    cs_bar = 1; //cs_bar
+                pc.printf("%d",n++);
+    //Check for fifoThresh
+    while((readreg(0x28) & 0x20) != 0x20);                         
+    
+    //Highpower settings
+    writereg(0x11,0x7F);    //RegPalevel (20db)                //~
+    writereg(0x13,0x0F);    //RegOCP
+    writereg(0x5A,0x5D);    //RegTestPa1
+    writereg(0x5C,0x7C);    //RegTestPa2
+        
+    //Set to Tx mode
+    writereg(0x01,0x0C);
+    
+
+        //Check for fifoThresh
+        while((readreg(0x28) & 0x20) != 0x00);  
+                
+        while(byte_counter!=15){
+            
+        //writing again
+        cs_bar = 0;
+        spi.write(0x80);   
+        for(int i=7; i>=0 ;i--)
+        {
+            //pc.printf("%d\n",byte_counter);
+            if((short_beacon[byte_counter] & (uint8_t) pow(2.0,i))!=0)
+            //if((short_beacon[byte_counter] & mask[i]) != 0)
+        {
+            spi.write(0xFF);
+            spi.write(0xFF);
+        }
+        else
+        {
+            spi.write(0x00);
+            spi.write(0x00);
+            
+        }
+        }
+        cs_bar = 1;
+        byte_counter++;
+        //wait(1);       
+        //Check for fifoThresh
+        while((readreg(0x28) & 0x20) != 0x00);
+        
+    }
+    //wait for packet sent bit to fire
+    while((readreg(0x28) & 0x08) != 0x08);
+    pc.printf("packet sent!!! \n");    
+    
+    //Switch back to Standby Mode
+    writereg(0x01,0x04);
+    
+    //Low power mode
+    writereg(0x11,0x9F);    //RegPalevel (13db)
+    writereg(0x13,0x1A);    //RegOCP
+    writereg(0x5A,0x55);    //RegTestPa1(setting PA_BOOST on RFIO)
+    writereg(0x5C,0x70);    //RegTestPa2(setting PA_BOOST on RFIO)
+    //wait for modeready
+    while((readreg(0x27)&0x80)!=0x80);
+    //t.stop();
+    //pc.printf(" time taken to init + transmit = %f \n", t.read()) ;
+    }
+}
\ No newline at end of file

diff -r 000000000000 -r 15355bb24274 mbed.bld
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mbed.bld	Fri Feb 06 15:57:03 2015 +0000
@@ -0,0 +1,1 @@
+http://mbed.org/users/mbed_official/code/mbed/builds/4fc01daae5a5
\ No newline at end of file