shubham c / Mbed 2 deprecated 08_imp_tx

imp_tx_flow

Dependencies:   mbed

main.cpp@0:ae1d21fa5544, 2015-01-08 (annotated)

Committer:
ee12b079
Date:
Thu Jan 08 16:22:33 2015 +0000
Revision:
0:ae1d21fa5544
imp_rx_flow

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ee12b079 0:ae1d21fa5544 1 // 6CC000 for 435 MHz
ee12b079 0:ae1d21fa5544 2 //set all values as FF for checking on spectrum analyzer
ee12b079 0:ae1d21fa5544 3 #include "beacon.h"
ee12b079 0:ae1d21fa5544 4 //Serial pc(USBTX, USBRX); // tx, rx
ee12b079 0:ae1d21fa5544 5 Serial pc(USBTX, USBRX);
ee12b079 0:ae1d21fa5544 6 SPI spi(D11, D12, D13); // mosi, miso, sclk
ee12b079 0:ae1d21fa5544 7 DigitalOut cs_bar(D10); //slave select or chip select
ee12b079 0:ae1d21fa5544 8 //InterruptIn button(p9);
ee12b079 0:ae1d21fa5544 9 #define TX_DATA 182 //218-2=216bytes when destuffed becomes 180 bytes //doesnt work if sync < 11
ee12b079 0:ae1d21fa5544 10 //Timer t;
ee12b079 0:ae1d21fa5544 11 #define B(x) S_to_binary_(#x)
ee12b079 0:ae1d21fa5544 12
ee12b079 0:ae1d21fa5544 13 static inline unsigned long long S_to_binary_(const char *s)
ee12b079 0:ae1d21fa5544 14 {
ee12b079 0:ae1d21fa5544 15 unsigned long long i = 0;
ee12b079 0:ae1d21fa5544 16 while (*s) {
ee12b079 0:ae1d21fa5544 17 i <<= 1;
ee12b079 0:ae1d21fa5544 18 i += *s++ - '0';
ee12b079 0:ae1d21fa5544 19 }
ee12b079 0:ae1d21fa5544 20 return i;
ee12b079 0:ae1d21fa5544 21 }
ee12b079 0:ae1d21fa5544 22
ee12b079 0:ae1d21fa5544 23 void writereg(uint8_t reg,uint8_t val)
ee12b079 0:ae1d21fa5544 24 {
ee12b079 0:ae1d21fa5544 25 cs_bar = 0;
ee12b079 0:ae1d21fa5544 26 spi.write(reg | 0x80);
ee12b079 0:ae1d21fa5544 27 spi.write(val);
ee12b079 0:ae1d21fa5544 28 cs_bar = 1;
ee12b079 0:ae1d21fa5544 29 }
ee12b079 0:ae1d21fa5544 30 uint8_t readreg(uint8_t reg)
ee12b079 0:ae1d21fa5544 31 {
ee12b079 0:ae1d21fa5544 32 uint8_t val;
ee12b079 0:ae1d21fa5544 33 cs_bar = 0;
ee12b079 0:ae1d21fa5544 34 spi.write(reg & ~0x80);
ee12b079 0:ae1d21fa5544 35 val = spi.write(0);
ee12b079 0:ae1d21fa5544 36 cs_bar = 1;
ee12b079 0:ae1d21fa5544 37 return val;
ee12b079 0:ae1d21fa5544 38 }
ee12b079 0:ae1d21fa5544 39
ee12b079 0:ae1d21fa5544 40 main() {
ee12b079 0:ae1d21fa5544 41 int n = 0;
ee12b079 0:ae1d21fa5544 42 //button.rise(&interrupt_func); //interrupt enabled ( rising edge of pin 9)
ee12b079 0:ae1d21fa5544 43 wait(0.02); // pl. update this value or even avoid it!!!
ee12b079 0:ae1d21fa5544 44 //extract values from short_beacon[]
ee12b079 0:ae1d21fa5544 45
ee12b079 0:ae1d21fa5544 46 //pc.baud(115200);
ee12b079 0:ae1d21fa5544 47 spi.format(8,0);
ee12b079 0:ae1d21fa5544 48 spi.frequency(10000000); //10MHz SCLK frequency(its max for rfm69hcw)
ee12b079 0:ae1d21fa5544 49
ee12b079 0:ae1d21fa5544 50 cs_bar = 1; // Chip must be deselected
ee12b079 0:ae1d21fa5544 51
ee12b079 0:ae1d21fa5544 52 if (readreg(0x15) == 0xB0) pc.printf("spi connection valid\n");
ee12b079 0:ae1d21fa5544 53 else {pc.printf("error in spi connection\n"); exit(0); }
ee12b079 0:ae1d21fa5544 54
ee12b079 0:ae1d21fa5544 55 //initialization
ee12b079 0:ae1d21fa5544 56 //Common configuration registers
ee12b079 0:ae1d21fa5544 57 writereg(0x01,0x00); //sequencer on,standby mode
ee12b079 0:ae1d21fa5544 58 writereg(0x02,0x08);// |0x01); //packet, ook, no dc //0x00 for fsk //default = 0x08 for ook
ee12b079 0:ae1d21fa5544 59 writereg(0x03,0x68); //1200bps
ee12b079 0:ae1d21fa5544 60 writereg(0x04,0x2B); //1200bps
ee12b079 0:ae1d21fa5544 61 writereg(0x07,0x6C);
ee12b079 0:ae1d21fa5544 62 writereg(0x08,0xC0);
ee12b079 0:ae1d21fa5544 63 writereg(0x09,0x00); //try 6C C0 00 for 435 MHZ //try 6C 40 00 for 432.something //try E4 C0 00 for 915
ee12b079 0:ae1d21fa5544 64
ee12b079 0:ae1d21fa5544 65 //FSK settings
ee12b079 0:ae1d21fa5544 66 writereg(0x06,0x52);// = (actual Fdev)*0.016384 //0x52 for 5khz //0x14 for 1.2khz //0x0A for0.6khz
ee12b079 0:ae1d21fa5544 67
ee12b079 0:ae1d21fa5544 68
ee12b079 0:ae1d21fa5544 69 //Transmitter registers
ee12b079 0:ae1d21fa5544 70 // RegPaLevel
ee12b079 0:ae1d21fa5544 71
ee12b079 0:ae1d21fa5544 72 //IRQ and Pin Mapping Registers
ee12b079 0:ae1d21fa5544 73 //no DIO mapped yet
ee12b079 0:ae1d21fa5544 74 //irq1: modeready used
ee12b079 0:ae1d21fa5544 75 //irq2: fifofull, fifothresh,packetsent used
ee12b079 0:ae1d21fa5544 76
ee12b079 0:ae1d21fa5544 77 //rx registers
ee12b079 0:ae1d21fa5544 78 writereg(0x18,0x08); //RegLNA using agc
ee12b079 0:ae1d21fa5544 79 writereg(0x19,0x51); //Regrxbw (data is successfully received from 5.2 khz onwards for 1200bps)
ee12b079 0:ae1d21fa5544 80 //keep it as 0x51 for 83.3kHz, 0x42 for 62.5kHz, 0x49 for 100 kHz, 0x40 for 250khz, 57 for 1.3khz, 56 for 2.6khz
ee12b079 0:ae1d21fa5544 81 //46 for 3.9khz//0x57:2.6khz for 1.2khz
ee12b079 0:ae1d21fa5544 82
ee12b079 0:ae1d21fa5544 83 writereg(0x29,0x78); //rssi_thresh = -110 (0x6E) //0xB4 for -180 //0x96 for -150dBm
ee12b079 0:ae1d21fa5544 84 //0x78 for -120
ee12b079 0:ae1d21fa5544 85
ee12b079 0:ae1d21fa5544 86
ee12b079 0:ae1d21fa5544 87 //Packet Engine Registers
ee12b079 0:ae1d21fa5544 88 writereg(0x2C,0x00); //set preamble
ee12b079 0:ae1d21fa5544 89 writereg(0x2D,0x0A); //set preamble default(0x0A)
ee12b079 0:ae1d21fa5544 90 writereg(0x2E,0x80); //sync off ..........................
ee12b079 0:ae1d21fa5544 91 writereg(0x2F,0x5E); //sync word 1 .........................
ee12b079 0:ae1d21fa5544 92 writereg(0x37,0x08);// | 0x10);// | 0x40); //packetconfig1 data whitening(0x40), crc (0x10) packet issue even if crc fails???..........................
ee12b079 0:ae1d21fa5544 93 writereg(0x38,0x00); //payload length = 0 ... unlimited payload mode
ee12b079 0:ae1d21fa5544 94 writereg(0x3C,20); //fifothresh = 48 because we want it cleared once its 40!!!!
ee12b079 0:ae1d21fa5544 95 //Initialization complete
ee12b079 0:ae1d21fa5544 96
ee12b079 0:ae1d21fa5544 97 int data[TX_DATA];
ee12b079 0:ae1d21fa5544 98 data[0]=0x7E;
ee12b079 0:ae1d21fa5544 99 for(int i = 1; i < TX_DATA-1;)
ee12b079 0:ae1d21fa5544 100 {//data[i++] = 0xAA;
ee12b079 0:ae1d21fa5544 101 data[i++] = B(11111000);
ee12b079 0:ae1d21fa5544 102 data[i++] = B(01111100);
ee12b079 0:ae1d21fa5544 103 data[i++] = B(00111110);
ee12b079 0:ae1d21fa5544 104 data[i++] = B(00011111);
ee12b079 0:ae1d21fa5544 105 data[i++] = B(00001111);
ee12b079 0:ae1d21fa5544 106 data[i++] = B(10000111);
ee12b079 0:ae1d21fa5544 107 data[i++] = B(11000011);
ee12b079 0:ae1d21fa5544 108 data[i++] = B(11100001);
ee12b079 0:ae1d21fa5544 109 data[i++] = B(11110000);
ee12b079 0:ae1d21fa5544 110 }
ee12b079 0:ae1d21fa5544 111
ee12b079 0:ae1d21fa5544 112 data[TX_DATA-1]= 0x7E;
ee12b079 0:ae1d21fa5544 113 for(int i = 0; i< TX_DATA;i++)
ee12b079 0:ae1d21fa5544 114 printf("%X\n",data[i]);
ee12b079 0:ae1d21fa5544 115 int x=0;
ee12b079 0:ae1d21fa5544 116
ee12b079 0:ae1d21fa5544 117 pc.printf("press t \n");
ee12b079 0:ae1d21fa5544 118 while(pc.getc() == 't'){
ee12b079 0:ae1d21fa5544 119 //Check for fifoThresh
ee12b079 0:ae1d21fa5544 120 //while((readreg(0x28) & 0x20) != 0x20);
ee12b079 0:ae1d21fa5544 121 //Check for fifoThresh
ee12b079 0:ae1d21fa5544 122 //while((readreg(0x28) & 0x20) != 0x00);
ee12b079 0:ae1d21fa5544 123
ee12b079 0:ae1d21fa5544 124 //Highpower settings
ee12b079 0:ae1d21fa5544 125 writereg(0x11,0x7F); //RegPalevel (20db) //~
ee12b079 0:ae1d21fa5544 126 writereg(0x13,0x0F); //RegOCP
ee12b079 0:ae1d21fa5544 127 writereg(0x5A,0x5D); //RegTestPa1
ee12b079 0:ae1d21fa5544 128 writereg(0x5C,0x7C); //RegTestPa2
ee12b079 0:ae1d21fa5544 129
ee12b079 0:ae1d21fa5544 130 //Set to Tx mode
ee12b079 0:ae1d21fa5544 131 writereg(0x01,0x0C);
ee12b079 0:ae1d21fa5544 132
ee12b079 0:ae1d21fa5544 133
ee12b079 0:ae1d21fa5544 134 while(x!=TX_DATA){
ee12b079 0:ae1d21fa5544 135 //Check for fifoThresh
ee12b079 0:ae1d21fa5544 136 //Check for fifoThresh
ee12b079 0:ae1d21fa5544 137 while((readreg(0x28) & 0x20) != 0x00);
ee12b079 0:ae1d21fa5544 138 //writing again
ee12b079 0:ae1d21fa5544 139 cs_bar = 0;
ee12b079 0:ae1d21fa5544 140 spi.write(0x80);
ee12b079 0:ae1d21fa5544 141 int thresh;
ee12b079 0:ae1d21fa5544 142 thresh = TX_DATA-x;
ee12b079 0:ae1d21fa5544 143 if((TX_DATA-x)>20)
ee12b079 0:ae1d21fa5544 144 for(int i=0; i<20 ;i++,x++)
ee12b079 0:ae1d21fa5544 145 spi.write(data[x]);
ee12b079 0:ae1d21fa5544 146 else
ee12b079 0:ae1d21fa5544 147 for(int i=0; i<thresh ;i++,x++)
ee12b079 0:ae1d21fa5544 148 {spi.write(data[x]);
ee12b079 0:ae1d21fa5544 149 printf("%d\n",x);
ee12b079 0:ae1d21fa5544 150 }
ee12b079 0:ae1d21fa5544 151 cs_bar = 1;
ee12b079 0:ae1d21fa5544 152 }
ee12b079 0:ae1d21fa5544 153 //wait for packet sent bit to fire
ee12b079 0:ae1d21fa5544 154 while((readreg(0x28) & 0x08) != 0x08);
ee12b079 0:ae1d21fa5544 155 pc.printf("packet sent!!! \n");
ee12b079 0:ae1d21fa5544 156
ee12b079 0:ae1d21fa5544 157 //Switch back to Standby Mode
ee12b079 0:ae1d21fa5544 158 writereg(0x01,0x04);
ee12b079 0:ae1d21fa5544 159
ee12b079 0:ae1d21fa5544 160 //wait for modeready
ee12b079 0:ae1d21fa5544 161 while((readreg(0x27)&0x80)!=0x80);
ee12b079 0:ae1d21fa5544 162 //t.stop();
ee12b079 0:ae1d21fa5544 163 //pc.printf(" time taken to init + transmit = %f \n", t.read()) ;
ee12b079 0:ae1d21fa5544 164 }
ee12b079 0:ae1d21fa5544 165 }