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Dependents:   FRDM-KL46Z_LCD_Test FRDM-KL46Z_LCD_Test FRDM-KL46Z_Plantilla FRDM-KL46Z_Plantilla ... more

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.s@0:6bc4ac881c8e, 2016-07-28 (annotated)

Committer:
ebrus
Date:
Thu Jul 28 15:56:34 2016 +0000
Revision:
0:6bc4ac881c8e
1;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:6bc4ac881c8e 1 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
ebrus 0:6bc4ac881c8e 2 ;* File Name : startup_stm32f401xe.s
ebrus 0:6bc4ac881c8e 3 ;* Author : MCD Application Team
ebrus 0:6bc4ac881c8e 4 ;* Version : V2.1.0RC2
ebrus 0:6bc4ac881c8e 5 ;* Date : 14-May-2014
ebrus 0:6bc4ac881c8e 6 ;* Description : STM32F401xe devices vector table for MDK-ARM_MICRO toolchain.
ebrus 0:6bc4ac881c8e 7 ;* This module performs:
ebrus 0:6bc4ac881c8e 8 ;* - Set the initial SP
ebrus 0:6bc4ac881c8e 9 ;* - Set the initial PC == Reset_Handler
ebrus 0:6bc4ac881c8e 10 ;* - Set the vector table entries with the exceptions ISR address
ebrus 0:6bc4ac881c8e 11 ;* - Branches to __main in the C library (which eventually
ebrus 0:6bc4ac881c8e 12 ;* calls main()).
ebrus 0:6bc4ac881c8e 13 ;* After Reset the CortexM4 processor is in Thread mode,
ebrus 0:6bc4ac881c8e 14 ;* priority is Privileged, and the Stack is set to Main.
ebrus 0:6bc4ac881c8e 15 ;* <<< Use Configuration Wizard in Context Menu >>>
ebrus 0:6bc4ac881c8e 16 ;*******************************************************************************
ebrus 0:6bc4ac881c8e 17 ;
ebrus 0:6bc4ac881c8e 18 ;* Redistribution and use in source and binary forms, with or without modification,
ebrus 0:6bc4ac881c8e 19 ;* are permitted provided that the following conditions are met:
ebrus 0:6bc4ac881c8e 20 ;* 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:6bc4ac881c8e 21 ;* this list of conditions and the following disclaimer.
ebrus 0:6bc4ac881c8e 22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:6bc4ac881c8e 23 ;* this list of conditions and the following disclaimer in the documentation
ebrus 0:6bc4ac881c8e 24 ;* and/or other materials provided with the distribution.
ebrus 0:6bc4ac881c8e 25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:6bc4ac881c8e 26 ;* may be used to endorse or promote products derived from this software
ebrus 0:6bc4ac881c8e 27 ;* without specific prior written permission.
ebrus 0:6bc4ac881c8e 28 ;*
ebrus 0:6bc4ac881c8e 29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:6bc4ac881c8e 30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:6bc4ac881c8e 31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:6bc4ac881c8e 32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:6bc4ac881c8e 33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:6bc4ac881c8e 34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:6bc4ac881c8e 35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:6bc4ac881c8e 36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:6bc4ac881c8e 37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:6bc4ac881c8e 38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:6bc4ac881c8e 39 ;
ebrus 0:6bc4ac881c8e 40 ;*******************************************************************************
ebrus 0:6bc4ac881c8e 41
ebrus 0:6bc4ac881c8e 42 ; Amount of memory (in bytes) allocated for Stack
ebrus 0:6bc4ac881c8e 43 ; Tailor this value to your application needs
ebrus 0:6bc4ac881c8e 44 ; <h> Stack Configuration
ebrus 0:6bc4ac881c8e 45 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
ebrus 0:6bc4ac881c8e 46 ; </h>
ebrus 0:6bc4ac881c8e 47
ebrus 0:6bc4ac881c8e 48 Stack_Size EQU 0x00000400
ebrus 0:6bc4ac881c8e 49
ebrus 0:6bc4ac881c8e 50 AREA STACK, NOINIT, READWRITE, ALIGN=3
ebrus 0:6bc4ac881c8e 51 EXPORT __initial_sp
ebrus 0:6bc4ac881c8e 52
ebrus 0:6bc4ac881c8e 53 Stack_Mem SPACE Stack_Size
ebrus 0:6bc4ac881c8e 54 __initial_sp EQU 0x20018000 ; Top of RAM
ebrus 0:6bc4ac881c8e 55
ebrus 0:6bc4ac881c8e 56
ebrus 0:6bc4ac881c8e 57 ; <h> Heap Configuration
ebrus 0:6bc4ac881c8e 58 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
ebrus 0:6bc4ac881c8e 59 ; </h>
ebrus 0:6bc4ac881c8e 60
ebrus 0:6bc4ac881c8e 61 Heap_Size EQU 0x00000400
ebrus 0:6bc4ac881c8e 62
ebrus 0:6bc4ac881c8e 63 AREA HEAP, NOINIT, READWRITE, ALIGN=3
ebrus 0:6bc4ac881c8e 64 EXPORT __heap_base
ebrus 0:6bc4ac881c8e 65 EXPORT __heap_limit
ebrus 0:6bc4ac881c8e 66
ebrus 0:6bc4ac881c8e 67 __heap_base
ebrus 0:6bc4ac881c8e 68 Heap_Mem SPACE Heap_Size
ebrus 0:6bc4ac881c8e 69 __heap_limit EQU (__initial_sp - Stack_Size)
ebrus 0:6bc4ac881c8e 70
ebrus 0:6bc4ac881c8e 71 PRESERVE8
ebrus 0:6bc4ac881c8e 72 THUMB
ebrus 0:6bc4ac881c8e 73
ebrus 0:6bc4ac881c8e 74
ebrus 0:6bc4ac881c8e 75 ; Vector Table Mapped to Address 0 at Reset
ebrus 0:6bc4ac881c8e 76 AREA RESET, DATA, READONLY
ebrus 0:6bc4ac881c8e 77 EXPORT __Vectors
ebrus 0:6bc4ac881c8e 78 EXPORT __Vectors_End
ebrus 0:6bc4ac881c8e 79 EXPORT __Vectors_Size
ebrus 0:6bc4ac881c8e 80
ebrus 0:6bc4ac881c8e 81 __Vectors DCD __initial_sp ; Top of Stack
ebrus 0:6bc4ac881c8e 82 DCD Reset_Handler ; Reset Handler
ebrus 0:6bc4ac881c8e 83 DCD NMI_Handler ; NMI Handler
ebrus 0:6bc4ac881c8e 84 DCD HardFault_Handler ; Hard Fault Handler
ebrus 0:6bc4ac881c8e 85 DCD MemManage_Handler ; MPU Fault Handler
ebrus 0:6bc4ac881c8e 86 DCD BusFault_Handler ; Bus Fault Handler
ebrus 0:6bc4ac881c8e 87 DCD UsageFault_Handler ; Usage Fault Handler
ebrus 0:6bc4ac881c8e 88 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 89 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 90 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 91 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 92 DCD SVC_Handler ; SVCall Handler
ebrus 0:6bc4ac881c8e 93 DCD DebugMon_Handler ; Debug Monitor Handler
ebrus 0:6bc4ac881c8e 94 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 95 DCD PendSV_Handler ; PendSV Handler
ebrus 0:6bc4ac881c8e 96 DCD SysTick_Handler ; SysTick Handler
ebrus 0:6bc4ac881c8e 97
ebrus 0:6bc4ac881c8e 98 ; External Interrupts
ebrus 0:6bc4ac881c8e 99 DCD WWDG_IRQHandler ; Window WatchDog
ebrus 0:6bc4ac881c8e 100 DCD PVD_IRQHandler ; PVD through EXTI Line detection
ebrus 0:6bc4ac881c8e 101 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
ebrus 0:6bc4ac881c8e 102 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
ebrus 0:6bc4ac881c8e 103 DCD FLASH_IRQHandler ; FLASH
ebrus 0:6bc4ac881c8e 104 DCD RCC_IRQHandler ; RCC
ebrus 0:6bc4ac881c8e 105 DCD EXTI0_IRQHandler ; EXTI Line0
ebrus 0:6bc4ac881c8e 106 DCD EXTI1_IRQHandler ; EXTI Line1
ebrus 0:6bc4ac881c8e 107 DCD EXTI2_IRQHandler ; EXTI Line2
ebrus 0:6bc4ac881c8e 108 DCD EXTI3_IRQHandler ; EXTI Line3
ebrus 0:6bc4ac881c8e 109 DCD EXTI4_IRQHandler ; EXTI Line4
ebrus 0:6bc4ac881c8e 110 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
ebrus 0:6bc4ac881c8e 111 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
ebrus 0:6bc4ac881c8e 112 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
ebrus 0:6bc4ac881c8e 113 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
ebrus 0:6bc4ac881c8e 114 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
ebrus 0:6bc4ac881c8e 115 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
ebrus 0:6bc4ac881c8e 116 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
ebrus 0:6bc4ac881c8e 117 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
ebrus 0:6bc4ac881c8e 118 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 119 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 120 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 121 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 122 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
ebrus 0:6bc4ac881c8e 123 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
ebrus 0:6bc4ac881c8e 124 DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
ebrus 0:6bc4ac881c8e 125 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
ebrus 0:6bc4ac881c8e 126 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
ebrus 0:6bc4ac881c8e 127 DCD TIM2_IRQHandler ; TIM2
ebrus 0:6bc4ac881c8e 128 DCD TIM3_IRQHandler ; TIM3
ebrus 0:6bc4ac881c8e 129 DCD TIM4_IRQHandler ; TIM4
ebrus 0:6bc4ac881c8e 130 DCD I2C1_EV_IRQHandler ; I2C1 Event
ebrus 0:6bc4ac881c8e 131 DCD I2C1_ER_IRQHandler ; I2C1 Error
ebrus 0:6bc4ac881c8e 132 DCD I2C2_EV_IRQHandler ; I2C2 Event
ebrus 0:6bc4ac881c8e 133 DCD I2C2_ER_IRQHandler ; I2C2 Error
ebrus 0:6bc4ac881c8e 134 DCD SPI1_IRQHandler ; SPI1
ebrus 0:6bc4ac881c8e 135 DCD SPI2_IRQHandler ; SPI2
ebrus 0:6bc4ac881c8e 136 DCD USART1_IRQHandler ; USART1
ebrus 0:6bc4ac881c8e 137 DCD USART2_IRQHandler ; USART2
ebrus 0:6bc4ac881c8e 138 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 139 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
ebrus 0:6bc4ac881c8e 140 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
ebrus 0:6bc4ac881c8e 141 DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
ebrus 0:6bc4ac881c8e 142 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 143 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 144 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 145 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 146 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
ebrus 0:6bc4ac881c8e 147 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 148 DCD SDIO_IRQHandler ; SDIO
ebrus 0:6bc4ac881c8e 149 DCD TIM5_IRQHandler ; TIM5
ebrus 0:6bc4ac881c8e 150 DCD SPI3_IRQHandler ; SPI3
ebrus 0:6bc4ac881c8e 151 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 152 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 153 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 154 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 155 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
ebrus 0:6bc4ac881c8e 156 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
ebrus 0:6bc4ac881c8e 157 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
ebrus 0:6bc4ac881c8e 158 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
ebrus 0:6bc4ac881c8e 159 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
ebrus 0:6bc4ac881c8e 160 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 161 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 162 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 163 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 164 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 165 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 166 DCD OTG_FS_IRQHandler ; USB OTG FS
ebrus 0:6bc4ac881c8e 167 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
ebrus 0:6bc4ac881c8e 168 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
ebrus 0:6bc4ac881c8e 169 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
ebrus 0:6bc4ac881c8e 170 DCD USART6_IRQHandler ; USART6
ebrus 0:6bc4ac881c8e 171 DCD I2C3_EV_IRQHandler ; I2C3 event
ebrus 0:6bc4ac881c8e 172 DCD I2C3_ER_IRQHandler ; I2C3 error
ebrus 0:6bc4ac881c8e 173 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 174 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 175 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 176 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 177 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 178 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 179 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 180 DCD FPU_IRQHandler ; FPU
ebrus 0:6bc4ac881c8e 181 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 182 DCD 0 ; Reserved
ebrus 0:6bc4ac881c8e 183 DCD SPI4_IRQHandler ; SPI4
ebrus 0:6bc4ac881c8e 184
ebrus 0:6bc4ac881c8e 185 __Vectors_End
ebrus 0:6bc4ac881c8e 186
ebrus 0:6bc4ac881c8e 187 __Vectors_Size EQU __Vectors_End - __Vectors
ebrus 0:6bc4ac881c8e 188
ebrus 0:6bc4ac881c8e 189 AREA |.text|, CODE, READONLY
ebrus 0:6bc4ac881c8e 190
ebrus 0:6bc4ac881c8e 191 ; Reset handler
ebrus 0:6bc4ac881c8e 192 Reset_Handler PROC
ebrus 0:6bc4ac881c8e 193 EXPORT Reset_Handler [WEAK]
ebrus 0:6bc4ac881c8e 194 IMPORT SystemInit
ebrus 0:6bc4ac881c8e 195 IMPORT __main
ebrus 0:6bc4ac881c8e 196
ebrus 0:6bc4ac881c8e 197 LDR R0, =SystemInit
ebrus 0:6bc4ac881c8e 198 BLX R0
ebrus 0:6bc4ac881c8e 199 LDR R0, =__main
ebrus 0:6bc4ac881c8e 200 BX R0
ebrus 0:6bc4ac881c8e 201 ENDP
ebrus 0:6bc4ac881c8e 202
ebrus 0:6bc4ac881c8e 203 ; Dummy Exception Handlers (infinite loops which can be modified)
ebrus 0:6bc4ac881c8e 204
ebrus 0:6bc4ac881c8e 205 NMI_Handler PROC
ebrus 0:6bc4ac881c8e 206 EXPORT NMI_Handler [WEAK]
ebrus 0:6bc4ac881c8e 207 B .
ebrus 0:6bc4ac881c8e 208 ENDP
ebrus 0:6bc4ac881c8e 209 HardFault_Handler\
ebrus 0:6bc4ac881c8e 210 PROC
ebrus 0:6bc4ac881c8e 211 EXPORT HardFault_Handler [WEAK]
ebrus 0:6bc4ac881c8e 212 B .
ebrus 0:6bc4ac881c8e 213 ENDP
ebrus 0:6bc4ac881c8e 214 MemManage_Handler\
ebrus 0:6bc4ac881c8e 215 PROC
ebrus 0:6bc4ac881c8e 216 EXPORT MemManage_Handler [WEAK]
ebrus 0:6bc4ac881c8e 217 B .
ebrus 0:6bc4ac881c8e 218 ENDP
ebrus 0:6bc4ac881c8e 219 BusFault_Handler\
ebrus 0:6bc4ac881c8e 220 PROC
ebrus 0:6bc4ac881c8e 221 EXPORT BusFault_Handler [WEAK]
ebrus 0:6bc4ac881c8e 222 B .
ebrus 0:6bc4ac881c8e 223 ENDP
ebrus 0:6bc4ac881c8e 224 UsageFault_Handler\
ebrus 0:6bc4ac881c8e 225 PROC
ebrus 0:6bc4ac881c8e 226 EXPORT UsageFault_Handler [WEAK]
ebrus 0:6bc4ac881c8e 227 B .
ebrus 0:6bc4ac881c8e 228 ENDP
ebrus 0:6bc4ac881c8e 229 SVC_Handler PROC
ebrus 0:6bc4ac881c8e 230 EXPORT SVC_Handler [WEAK]
ebrus 0:6bc4ac881c8e 231 B .
ebrus 0:6bc4ac881c8e 232 ENDP
ebrus 0:6bc4ac881c8e 233 DebugMon_Handler\
ebrus 0:6bc4ac881c8e 234 PROC
ebrus 0:6bc4ac881c8e 235 EXPORT DebugMon_Handler [WEAK]
ebrus 0:6bc4ac881c8e 236 B .
ebrus 0:6bc4ac881c8e 237 ENDP
ebrus 0:6bc4ac881c8e 238 PendSV_Handler PROC
ebrus 0:6bc4ac881c8e 239 EXPORT PendSV_Handler [WEAK]
ebrus 0:6bc4ac881c8e 240 B .
ebrus 0:6bc4ac881c8e 241 ENDP
ebrus 0:6bc4ac881c8e 242 SysTick_Handler PROC
ebrus 0:6bc4ac881c8e 243 EXPORT SysTick_Handler [WEAK]
ebrus 0:6bc4ac881c8e 244 B .
ebrus 0:6bc4ac881c8e 245 ENDP
ebrus 0:6bc4ac881c8e 246
ebrus 0:6bc4ac881c8e 247 Default_Handler PROC
ebrus 0:6bc4ac881c8e 248
ebrus 0:6bc4ac881c8e 249 EXPORT WWDG_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 250 EXPORT PVD_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 251 EXPORT TAMP_STAMP_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 252 EXPORT RTC_WKUP_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 253 EXPORT FLASH_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 254 EXPORT RCC_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 255 EXPORT EXTI0_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 256 EXPORT EXTI1_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 257 EXPORT EXTI2_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 258 EXPORT EXTI3_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 259 EXPORT EXTI4_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 260 EXPORT DMA1_Stream0_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 261 EXPORT DMA1_Stream1_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 262 EXPORT DMA1_Stream2_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 263 EXPORT DMA1_Stream3_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 264 EXPORT DMA1_Stream4_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 265 EXPORT DMA1_Stream5_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 266 EXPORT DMA1_Stream6_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 267 EXPORT ADC_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 268 EXPORT EXTI9_5_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 269 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 270 EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 271 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 272 EXPORT TIM1_CC_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 273 EXPORT TIM2_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 274 EXPORT TIM3_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 275 EXPORT TIM4_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 276 EXPORT I2C1_EV_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 277 EXPORT I2C1_ER_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 278 EXPORT I2C2_EV_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 279 EXPORT I2C2_ER_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 280 EXPORT SPI1_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 281 EXPORT SPI2_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 282 EXPORT USART1_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 283 EXPORT USART2_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 284 EXPORT EXTI15_10_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 285 EXPORT RTC_Alarm_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 286 EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 287 EXPORT DMA1_Stream7_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 288 EXPORT SDIO_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 289 EXPORT TIM5_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 290 EXPORT SPI3_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 291 EXPORT DMA2_Stream0_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 292 EXPORT DMA2_Stream1_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 293 EXPORT DMA2_Stream2_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 294 EXPORT DMA2_Stream3_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 295 EXPORT DMA2_Stream4_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 296 EXPORT OTG_FS_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 297 EXPORT DMA2_Stream5_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 298 EXPORT DMA2_Stream6_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 299 EXPORT DMA2_Stream7_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 300 EXPORT USART6_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 301 EXPORT I2C3_EV_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 302 EXPORT I2C3_ER_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 303 EXPORT FPU_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 304 EXPORT SPI4_IRQHandler [WEAK]
ebrus 0:6bc4ac881c8e 305
ebrus 0:6bc4ac881c8e 306 WWDG_IRQHandler
ebrus 0:6bc4ac881c8e 307 PVD_IRQHandler
ebrus 0:6bc4ac881c8e 308 TAMP_STAMP_IRQHandler
ebrus 0:6bc4ac881c8e 309 RTC_WKUP_IRQHandler
ebrus 0:6bc4ac881c8e 310 FLASH_IRQHandler
ebrus 0:6bc4ac881c8e 311 RCC_IRQHandler
ebrus 0:6bc4ac881c8e 312 EXTI0_IRQHandler
ebrus 0:6bc4ac881c8e 313 EXTI1_IRQHandler
ebrus 0:6bc4ac881c8e 314 EXTI2_IRQHandler
ebrus 0:6bc4ac881c8e 315 EXTI3_IRQHandler
ebrus 0:6bc4ac881c8e 316 EXTI4_IRQHandler
ebrus 0:6bc4ac881c8e 317 DMA1_Stream0_IRQHandler
ebrus 0:6bc4ac881c8e 318 DMA1_Stream1_IRQHandler
ebrus 0:6bc4ac881c8e 319 DMA1_Stream2_IRQHandler
ebrus 0:6bc4ac881c8e 320 DMA1_Stream3_IRQHandler
ebrus 0:6bc4ac881c8e 321 DMA1_Stream4_IRQHandler
ebrus 0:6bc4ac881c8e 322 DMA1_Stream5_IRQHandler
ebrus 0:6bc4ac881c8e 323 DMA1_Stream6_IRQHandler
ebrus 0:6bc4ac881c8e 324 ADC_IRQHandler
ebrus 0:6bc4ac881c8e 325 EXTI9_5_IRQHandler
ebrus 0:6bc4ac881c8e 326 TIM1_BRK_TIM9_IRQHandler
ebrus 0:6bc4ac881c8e 327 TIM1_UP_TIM10_IRQHandler
ebrus 0:6bc4ac881c8e 328 TIM1_TRG_COM_TIM11_IRQHandler
ebrus 0:6bc4ac881c8e 329 TIM1_CC_IRQHandler
ebrus 0:6bc4ac881c8e 330 TIM2_IRQHandler
ebrus 0:6bc4ac881c8e 331 TIM3_IRQHandler
ebrus 0:6bc4ac881c8e 332 TIM4_IRQHandler
ebrus 0:6bc4ac881c8e 333 I2C1_EV_IRQHandler
ebrus 0:6bc4ac881c8e 334 I2C1_ER_IRQHandler
ebrus 0:6bc4ac881c8e 335 I2C2_EV_IRQHandler
ebrus 0:6bc4ac881c8e 336 I2C2_ER_IRQHandler
ebrus 0:6bc4ac881c8e 337 SPI1_IRQHandler
ebrus 0:6bc4ac881c8e 338 SPI2_IRQHandler
ebrus 0:6bc4ac881c8e 339 USART1_IRQHandler
ebrus 0:6bc4ac881c8e 340 USART2_IRQHandler
ebrus 0:6bc4ac881c8e 341 EXTI15_10_IRQHandler
ebrus 0:6bc4ac881c8e 342 RTC_Alarm_IRQHandler
ebrus 0:6bc4ac881c8e 343 OTG_FS_WKUP_IRQHandler
ebrus 0:6bc4ac881c8e 344 DMA1_Stream7_IRQHandler
ebrus 0:6bc4ac881c8e 345 SDIO_IRQHandler
ebrus 0:6bc4ac881c8e 346 TIM5_IRQHandler
ebrus 0:6bc4ac881c8e 347 SPI3_IRQHandler
ebrus 0:6bc4ac881c8e 348 DMA2_Stream0_IRQHandler
ebrus 0:6bc4ac881c8e 349 DMA2_Stream1_IRQHandler
ebrus 0:6bc4ac881c8e 350 DMA2_Stream2_IRQHandler
ebrus 0:6bc4ac881c8e 351 DMA2_Stream3_IRQHandler
ebrus 0:6bc4ac881c8e 352 DMA2_Stream4_IRQHandler
ebrus 0:6bc4ac881c8e 353 OTG_FS_IRQHandler
ebrus 0:6bc4ac881c8e 354 DMA2_Stream5_IRQHandler
ebrus 0:6bc4ac881c8e 355 DMA2_Stream6_IRQHandler
ebrus 0:6bc4ac881c8e 356 DMA2_Stream7_IRQHandler
ebrus 0:6bc4ac881c8e 357 USART6_IRQHandler
ebrus 0:6bc4ac881c8e 358 I2C3_EV_IRQHandler
ebrus 0:6bc4ac881c8e 359 I2C3_ER_IRQHandler
ebrus 0:6bc4ac881c8e 360 FPU_IRQHandler
ebrus 0:6bc4ac881c8e 361 SPI4_IRQHandler
ebrus 0:6bc4ac881c8e 362
ebrus 0:6bc4ac881c8e 363 B .
ebrus 0:6bc4ac881c8e 364
ebrus 0:6bc4ac881c8e 365 ENDP
ebrus 0:6bc4ac881c8e 366
ebrus 0:6bc4ac881c8e 367 ALIGN
ebrus 0:6bc4ac881c8e 368 END