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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_can.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f10x_can.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V3.6.1
ebrus 0:0a673c671a56 6 * @date 05-March-2012
ebrus 0:0a673c671a56 7 * @brief This file provides all the CAN firmware functions.
ebrus 0:0a673c671a56 8 *******************************************************************************
ebrus 0:0a673c671a56 9 * Copyright (c) 2014, STMicroelectronics
ebrus 0:0a673c671a56 10 * All rights reserved.
ebrus 0:0a673c671a56 11 *
ebrus 0:0a673c671a56 12 * Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 13 * modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 14 *
ebrus 0:0a673c671a56 15 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 16 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 18 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 19 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 21 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 22 * without specific prior written permission.
ebrus 0:0a673c671a56 23 *
ebrus 0:0a673c671a56 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 34 *******************************************************************************
ebrus 0:0a673c671a56 35 */
ebrus 0:0a673c671a56 36
ebrus 0:0a673c671a56 37 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 38 #include "stm32f10x_can.h"
ebrus 0:0a673c671a56 39 #include "stm32f10x_rcc.h"
ebrus 0:0a673c671a56 40
ebrus 0:0a673c671a56 41 /** @addtogroup STM32F10x_StdPeriph_Driver
ebrus 0:0a673c671a56 42 * @{
ebrus 0:0a673c671a56 43 */
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45 /** @defgroup CAN
ebrus 0:0a673c671a56 46 * @brief CAN driver modules
ebrus 0:0a673c671a56 47 * @{
ebrus 0:0a673c671a56 48 */
ebrus 0:0a673c671a56 49
ebrus 0:0a673c671a56 50 /** @defgroup CAN_Private_TypesDefinitions
ebrus 0:0a673c671a56 51 * @{
ebrus 0:0a673c671a56 52 */
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 /**
ebrus 0:0a673c671a56 55 * @}
ebrus 0:0a673c671a56 56 */
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 /** @defgroup CAN_Private_Defines
ebrus 0:0a673c671a56 59 * @{
ebrus 0:0a673c671a56 60 */
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62 /* CAN Master Control Register bits */
ebrus 0:0a673c671a56 63
ebrus 0:0a673c671a56 64 #define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
ebrus 0:0a673c671a56 65
ebrus 0:0a673c671a56 66 /* CAN Mailbox Transmit Request */
ebrus 0:0a673c671a56 67 #define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
ebrus 0:0a673c671a56 68
ebrus 0:0a673c671a56 69 /* CAN Filter Master Register bits */
ebrus 0:0a673c671a56 70 #define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
ebrus 0:0a673c671a56 71
ebrus 0:0a673c671a56 72 /* Time out for INAK bit */
ebrus 0:0a673c671a56 73 #define INAK_TIMEOUT ((uint32_t)0x0000FFFF)
ebrus 0:0a673c671a56 74 /* Time out for SLAK bit */
ebrus 0:0a673c671a56 75 #define SLAK_TIMEOUT ((uint32_t)0x0000FFFF)
ebrus 0:0a673c671a56 76
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 /* Flags in TSR register */
ebrus 0:0a673c671a56 80 #define CAN_FLAGS_TSR ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 81 /* Flags in RF1R register */
ebrus 0:0a673c671a56 82 #define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 83 /* Flags in RF0R register */
ebrus 0:0a673c671a56 84 #define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 85 /* Flags in MSR register */
ebrus 0:0a673c671a56 86 #define CAN_FLAGS_MSR ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 87 /* Flags in ESR register */
ebrus 0:0a673c671a56 88 #define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
ebrus 0:0a673c671a56 89
ebrus 0:0a673c671a56 90 /* Mailboxes definition */
ebrus 0:0a673c671a56 91 #define CAN_TXMAILBOX_0 ((uint8_t)0x00)
ebrus 0:0a673c671a56 92 #define CAN_TXMAILBOX_1 ((uint8_t)0x01)
ebrus 0:0a673c671a56 93 #define CAN_TXMAILBOX_2 ((uint8_t)0x02)
ebrus 0:0a673c671a56 94
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96
ebrus 0:0a673c671a56 97 #define CAN_MODE_MASK ((uint32_t) 0x00000003)
ebrus 0:0a673c671a56 98 /**
ebrus 0:0a673c671a56 99 * @}
ebrus 0:0a673c671a56 100 */
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 /** @defgroup CAN_Private_Macros
ebrus 0:0a673c671a56 103 * @{
ebrus 0:0a673c671a56 104 */
ebrus 0:0a673c671a56 105
ebrus 0:0a673c671a56 106 /**
ebrus 0:0a673c671a56 107 * @}
ebrus 0:0a673c671a56 108 */
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 /** @defgroup CAN_Private_Variables
ebrus 0:0a673c671a56 111 * @{
ebrus 0:0a673c671a56 112 */
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 /**
ebrus 0:0a673c671a56 115 * @}
ebrus 0:0a673c671a56 116 */
ebrus 0:0a673c671a56 117
ebrus 0:0a673c671a56 118 /** @defgroup CAN_Private_FunctionPrototypes
ebrus 0:0a673c671a56 119 * @{
ebrus 0:0a673c671a56 120 */
ebrus 0:0a673c671a56 121
ebrus 0:0a673c671a56 122 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
ebrus 0:0a673c671a56 123
ebrus 0:0a673c671a56 124 /**
ebrus 0:0a673c671a56 125 * @}
ebrus 0:0a673c671a56 126 */
ebrus 0:0a673c671a56 127
ebrus 0:0a673c671a56 128 /** @defgroup CAN_Private_Functions
ebrus 0:0a673c671a56 129 * @{
ebrus 0:0a673c671a56 130 */
ebrus 0:0a673c671a56 131
ebrus 0:0a673c671a56 132 /**
ebrus 0:0a673c671a56 133 * @brief Deinitializes the CAN peripheral registers to their default reset values.
ebrus 0:0a673c671a56 134 * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
ebrus 0:0a673c671a56 135 * @retval None.
ebrus 0:0a673c671a56 136 */
ebrus 0:0a673c671a56 137 void CAN_DeInit(CAN_TypeDef* CANx)
ebrus 0:0a673c671a56 138 {
ebrus 0:0a673c671a56 139 /* Check the parameters */
ebrus 0:0a673c671a56 140 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 141
ebrus 0:0a673c671a56 142 if (CANx == CAN1)
ebrus 0:0a673c671a56 143 {
ebrus 0:0a673c671a56 144 /* Enable CAN1 reset state */
ebrus 0:0a673c671a56 145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
ebrus 0:0a673c671a56 146 /* Release CAN1 from reset state */
ebrus 0:0a673c671a56 147 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
ebrus 0:0a673c671a56 148 }
ebrus 0:0a673c671a56 149 else
ebrus 0:0a673c671a56 150 {
ebrus 0:0a673c671a56 151 /* Enable CAN2 reset state */
ebrus 0:0a673c671a56 152 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
ebrus 0:0a673c671a56 153 /* Release CAN2 from reset state */
ebrus 0:0a673c671a56 154 RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
ebrus 0:0a673c671a56 155 }
ebrus 0:0a673c671a56 156 }
ebrus 0:0a673c671a56 157
ebrus 0:0a673c671a56 158 /**
ebrus 0:0a673c671a56 159 * @brief Initializes the CAN peripheral according to the specified
ebrus 0:0a673c671a56 160 * parameters in the CAN_InitStruct.
ebrus 0:0a673c671a56 161 * @param CANx: where x can be 1 or 2 to to select the CAN
ebrus 0:0a673c671a56 162 * peripheral.
ebrus 0:0a673c671a56 163 * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that
ebrus 0:0a673c671a56 164 * contains the configuration information for the
ebrus 0:0a673c671a56 165 * CAN peripheral.
ebrus 0:0a673c671a56 166 * @retval Constant indicates initialization succeed which will be
ebrus 0:0a673c671a56 167 * CAN_InitStatus_Failed or CAN_InitStatus_Success.
ebrus 0:0a673c671a56 168 */
ebrus 0:0a673c671a56 169 uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
ebrus 0:0a673c671a56 170 {
ebrus 0:0a673c671a56 171 uint8_t InitStatus = CAN_InitStatus_Failed;
ebrus 0:0a673c671a56 172 uint32_t wait_ack = 0x00000000;
ebrus 0:0a673c671a56 173 /* Check the parameters */
ebrus 0:0a673c671a56 174 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 175 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
ebrus 0:0a673c671a56 176 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
ebrus 0:0a673c671a56 177 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
ebrus 0:0a673c671a56 178 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
ebrus 0:0a673c671a56 179 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
ebrus 0:0a673c671a56 180 assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
ebrus 0:0a673c671a56 181 assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
ebrus 0:0a673c671a56 182 assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
ebrus 0:0a673c671a56 183 assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
ebrus 0:0a673c671a56 184 assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
ebrus 0:0a673c671a56 185 assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
ebrus 0:0a673c671a56 186
ebrus 0:0a673c671a56 187 /* Exit from sleep mode */
ebrus 0:0a673c671a56 188 CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
ebrus 0:0a673c671a56 189
ebrus 0:0a673c671a56 190 /* Request initialisation */
ebrus 0:0a673c671a56 191 CANx->MCR |= CAN_MCR_INRQ ;
ebrus 0:0a673c671a56 192
ebrus 0:0a673c671a56 193 /* Wait the acknowledge */
ebrus 0:0a673c671a56 194 while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
ebrus 0:0a673c671a56 195 {
ebrus 0:0a673c671a56 196 wait_ack++;
ebrus 0:0a673c671a56 197 }
ebrus 0:0a673c671a56 198
ebrus 0:0a673c671a56 199 /* Check acknowledge */
ebrus 0:0a673c671a56 200 if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
ebrus 0:0a673c671a56 201 {
ebrus 0:0a673c671a56 202 InitStatus = CAN_InitStatus_Failed;
ebrus 0:0a673c671a56 203 }
ebrus 0:0a673c671a56 204 else
ebrus 0:0a673c671a56 205 {
ebrus 0:0a673c671a56 206 /* Set the time triggered communication mode */
ebrus 0:0a673c671a56 207 if (CAN_InitStruct->CAN_TTCM == ENABLE)
ebrus 0:0a673c671a56 208 {
ebrus 0:0a673c671a56 209 CANx->MCR |= CAN_MCR_TTCM;
ebrus 0:0a673c671a56 210 }
ebrus 0:0a673c671a56 211 else
ebrus 0:0a673c671a56 212 {
ebrus 0:0a673c671a56 213 CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
ebrus 0:0a673c671a56 214 }
ebrus 0:0a673c671a56 215
ebrus 0:0a673c671a56 216 /* Set the automatic bus-off management */
ebrus 0:0a673c671a56 217 if (CAN_InitStruct->CAN_ABOM == ENABLE)
ebrus 0:0a673c671a56 218 {
ebrus 0:0a673c671a56 219 CANx->MCR |= CAN_MCR_ABOM;
ebrus 0:0a673c671a56 220 }
ebrus 0:0a673c671a56 221 else
ebrus 0:0a673c671a56 222 {
ebrus 0:0a673c671a56 223 CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
ebrus 0:0a673c671a56 224 }
ebrus 0:0a673c671a56 225
ebrus 0:0a673c671a56 226 /* Set the automatic wake-up mode */
ebrus 0:0a673c671a56 227 if (CAN_InitStruct->CAN_AWUM == ENABLE)
ebrus 0:0a673c671a56 228 {
ebrus 0:0a673c671a56 229 CANx->MCR |= CAN_MCR_AWUM;
ebrus 0:0a673c671a56 230 }
ebrus 0:0a673c671a56 231 else
ebrus 0:0a673c671a56 232 {
ebrus 0:0a673c671a56 233 CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
ebrus 0:0a673c671a56 234 }
ebrus 0:0a673c671a56 235
ebrus 0:0a673c671a56 236 /* Set the no automatic retransmission */
ebrus 0:0a673c671a56 237 if (CAN_InitStruct->CAN_NART == ENABLE)
ebrus 0:0a673c671a56 238 {
ebrus 0:0a673c671a56 239 CANx->MCR |= CAN_MCR_NART;
ebrus 0:0a673c671a56 240 }
ebrus 0:0a673c671a56 241 else
ebrus 0:0a673c671a56 242 {
ebrus 0:0a673c671a56 243 CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
ebrus 0:0a673c671a56 244 }
ebrus 0:0a673c671a56 245
ebrus 0:0a673c671a56 246 /* Set the receive FIFO locked mode */
ebrus 0:0a673c671a56 247 if (CAN_InitStruct->CAN_RFLM == ENABLE)
ebrus 0:0a673c671a56 248 {
ebrus 0:0a673c671a56 249 CANx->MCR |= CAN_MCR_RFLM;
ebrus 0:0a673c671a56 250 }
ebrus 0:0a673c671a56 251 else
ebrus 0:0a673c671a56 252 {
ebrus 0:0a673c671a56 253 CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
ebrus 0:0a673c671a56 254 }
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 /* Set the transmit FIFO priority */
ebrus 0:0a673c671a56 257 if (CAN_InitStruct->CAN_TXFP == ENABLE)
ebrus 0:0a673c671a56 258 {
ebrus 0:0a673c671a56 259 CANx->MCR |= CAN_MCR_TXFP;
ebrus 0:0a673c671a56 260 }
ebrus 0:0a673c671a56 261 else
ebrus 0:0a673c671a56 262 {
ebrus 0:0a673c671a56 263 CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
ebrus 0:0a673c671a56 264 }
ebrus 0:0a673c671a56 265
ebrus 0:0a673c671a56 266 /* Set the bit timing register */
ebrus 0:0a673c671a56 267 CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
ebrus 0:0a673c671a56 268 ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
ebrus 0:0a673c671a56 269 ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
ebrus 0:0a673c671a56 270 ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
ebrus 0:0a673c671a56 271 ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
ebrus 0:0a673c671a56 272
ebrus 0:0a673c671a56 273 /* Request leave initialisation */
ebrus 0:0a673c671a56 274 CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
ebrus 0:0a673c671a56 275
ebrus 0:0a673c671a56 276 /* Wait the acknowledge */
ebrus 0:0a673c671a56 277 wait_ack = 0;
ebrus 0:0a673c671a56 278
ebrus 0:0a673c671a56 279 while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
ebrus 0:0a673c671a56 280 {
ebrus 0:0a673c671a56 281 wait_ack++;
ebrus 0:0a673c671a56 282 }
ebrus 0:0a673c671a56 283
ebrus 0:0a673c671a56 284 /* ...and check acknowledged */
ebrus 0:0a673c671a56 285 if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
ebrus 0:0a673c671a56 286 {
ebrus 0:0a673c671a56 287 InitStatus = CAN_InitStatus_Failed;
ebrus 0:0a673c671a56 288 }
ebrus 0:0a673c671a56 289 else
ebrus 0:0a673c671a56 290 {
ebrus 0:0a673c671a56 291 InitStatus = CAN_InitStatus_Success ;
ebrus 0:0a673c671a56 292 }
ebrus 0:0a673c671a56 293 }
ebrus 0:0a673c671a56 294
ebrus 0:0a673c671a56 295 /* At this step, return the status of initialization */
ebrus 0:0a673c671a56 296 return InitStatus;
ebrus 0:0a673c671a56 297 }
ebrus 0:0a673c671a56 298
ebrus 0:0a673c671a56 299 /**
ebrus 0:0a673c671a56 300 * @brief Initializes the CAN peripheral according to the specified
ebrus 0:0a673c671a56 301 * parameters in the CAN_FilterInitStruct.
ebrus 0:0a673c671a56 302 * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
ebrus 0:0a673c671a56 303 * structure that contains the configuration
ebrus 0:0a673c671a56 304 * information.
ebrus 0:0a673c671a56 305 * @retval None.
ebrus 0:0a673c671a56 306 */
ebrus 0:0a673c671a56 307 void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
ebrus 0:0a673c671a56 308 {
ebrus 0:0a673c671a56 309 uint32_t filter_number_bit_pos = 0;
ebrus 0:0a673c671a56 310 /* Check the parameters */
ebrus 0:0a673c671a56 311 assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
ebrus 0:0a673c671a56 312 assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
ebrus 0:0a673c671a56 313 assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
ebrus 0:0a673c671a56 314 assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
ebrus 0:0a673c671a56 315 assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
ebrus 0:0a673c671a56 316
ebrus 0:0a673c671a56 317 filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
ebrus 0:0a673c671a56 318
ebrus 0:0a673c671a56 319 /* Initialisation mode for the filter */
ebrus 0:0a673c671a56 320 CAN1->FMR |= FMR_FINIT;
ebrus 0:0a673c671a56 321
ebrus 0:0a673c671a56 322 /* Filter Deactivation */
ebrus 0:0a673c671a56 323 CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
ebrus 0:0a673c671a56 324
ebrus 0:0a673c671a56 325 /* Filter Scale */
ebrus 0:0a673c671a56 326 if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
ebrus 0:0a673c671a56 327 {
ebrus 0:0a673c671a56 328 /* 16-bit scale for the filter */
ebrus 0:0a673c671a56 329 CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
ebrus 0:0a673c671a56 330
ebrus 0:0a673c671a56 331 /* First 16-bit identifier and First 16-bit mask */
ebrus 0:0a673c671a56 332 /* Or First 16-bit identifier and Second 16-bit identifier */
ebrus 0:0a673c671a56 333 CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
ebrus 0:0a673c671a56 334 ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
ebrus 0:0a673c671a56 335 (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
ebrus 0:0a673c671a56 336
ebrus 0:0a673c671a56 337 /* Second 16-bit identifier and Second 16-bit mask */
ebrus 0:0a673c671a56 338 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
ebrus 0:0a673c671a56 339 CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
ebrus 0:0a673c671a56 340 ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
ebrus 0:0a673c671a56 341 (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
ebrus 0:0a673c671a56 342 }
ebrus 0:0a673c671a56 343
ebrus 0:0a673c671a56 344 if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
ebrus 0:0a673c671a56 345 {
ebrus 0:0a673c671a56 346 /* 32-bit scale for the filter */
ebrus 0:0a673c671a56 347 CAN1->FS1R |= filter_number_bit_pos;
ebrus 0:0a673c671a56 348 /* 32-bit identifier or First 32-bit identifier */
ebrus 0:0a673c671a56 349 CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
ebrus 0:0a673c671a56 350 ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
ebrus 0:0a673c671a56 351 (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
ebrus 0:0a673c671a56 352 /* 32-bit mask or Second 32-bit identifier */
ebrus 0:0a673c671a56 353 CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
ebrus 0:0a673c671a56 354 ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
ebrus 0:0a673c671a56 355 (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
ebrus 0:0a673c671a56 356 }
ebrus 0:0a673c671a56 357
ebrus 0:0a673c671a56 358 /* Filter Mode */
ebrus 0:0a673c671a56 359 if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
ebrus 0:0a673c671a56 360 {
ebrus 0:0a673c671a56 361 /*Id/Mask mode for the filter*/
ebrus 0:0a673c671a56 362 CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
ebrus 0:0a673c671a56 363 }
ebrus 0:0a673c671a56 364 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
ebrus 0:0a673c671a56 365 {
ebrus 0:0a673c671a56 366 /*Identifier list mode for the filter*/
ebrus 0:0a673c671a56 367 CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
ebrus 0:0a673c671a56 368 }
ebrus 0:0a673c671a56 369
ebrus 0:0a673c671a56 370 /* Filter FIFO assignment */
ebrus 0:0a673c671a56 371 if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
ebrus 0:0a673c671a56 372 {
ebrus 0:0a673c671a56 373 /* FIFO 0 assignation for the filter */
ebrus 0:0a673c671a56 374 CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
ebrus 0:0a673c671a56 375 }
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
ebrus 0:0a673c671a56 378 {
ebrus 0:0a673c671a56 379 /* FIFO 1 assignation for the filter */
ebrus 0:0a673c671a56 380 CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
ebrus 0:0a673c671a56 381 }
ebrus 0:0a673c671a56 382
ebrus 0:0a673c671a56 383 /* Filter activation */
ebrus 0:0a673c671a56 384 if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
ebrus 0:0a673c671a56 385 {
ebrus 0:0a673c671a56 386 CAN1->FA1R |= filter_number_bit_pos;
ebrus 0:0a673c671a56 387 }
ebrus 0:0a673c671a56 388
ebrus 0:0a673c671a56 389 /* Leave the initialisation mode for the filter */
ebrus 0:0a673c671a56 390 CAN1->FMR &= ~FMR_FINIT;
ebrus 0:0a673c671a56 391 }
ebrus 0:0a673c671a56 392
ebrus 0:0a673c671a56 393 /**
ebrus 0:0a673c671a56 394 * @brief Fills each CAN_InitStruct member with its default value.
ebrus 0:0a673c671a56 395 * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which
ebrus 0:0a673c671a56 396 * will be initialized.
ebrus 0:0a673c671a56 397 * @retval None.
ebrus 0:0a673c671a56 398 */
ebrus 0:0a673c671a56 399 void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
ebrus 0:0a673c671a56 400 {
ebrus 0:0a673c671a56 401 /* Reset CAN init structure parameters values */
ebrus 0:0a673c671a56 402
ebrus 0:0a673c671a56 403 /* Initialize the time triggered communication mode */
ebrus 0:0a673c671a56 404 CAN_InitStruct->CAN_TTCM = DISABLE;
ebrus 0:0a673c671a56 405
ebrus 0:0a673c671a56 406 /* Initialize the automatic bus-off management */
ebrus 0:0a673c671a56 407 CAN_InitStruct->CAN_ABOM = DISABLE;
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 /* Initialize the automatic wake-up mode */
ebrus 0:0a673c671a56 410 CAN_InitStruct->CAN_AWUM = DISABLE;
ebrus 0:0a673c671a56 411
ebrus 0:0a673c671a56 412 /* Initialize the no automatic retransmission */
ebrus 0:0a673c671a56 413 CAN_InitStruct->CAN_NART = DISABLE;
ebrus 0:0a673c671a56 414
ebrus 0:0a673c671a56 415 /* Initialize the receive FIFO locked mode */
ebrus 0:0a673c671a56 416 CAN_InitStruct->CAN_RFLM = DISABLE;
ebrus 0:0a673c671a56 417
ebrus 0:0a673c671a56 418 /* Initialize the transmit FIFO priority */
ebrus 0:0a673c671a56 419 CAN_InitStruct->CAN_TXFP = DISABLE;
ebrus 0:0a673c671a56 420
ebrus 0:0a673c671a56 421 /* Initialize the CAN_Mode member */
ebrus 0:0a673c671a56 422 CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
ebrus 0:0a673c671a56 423
ebrus 0:0a673c671a56 424 /* Initialize the CAN_SJW member */
ebrus 0:0a673c671a56 425 CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
ebrus 0:0a673c671a56 426
ebrus 0:0a673c671a56 427 /* Initialize the CAN_BS1 member */
ebrus 0:0a673c671a56 428 CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
ebrus 0:0a673c671a56 429
ebrus 0:0a673c671a56 430 /* Initialize the CAN_BS2 member */
ebrus 0:0a673c671a56 431 CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
ebrus 0:0a673c671a56 432
ebrus 0:0a673c671a56 433 /* Initialize the CAN_Prescaler member */
ebrus 0:0a673c671a56 434 CAN_InitStruct->CAN_Prescaler = 1;
ebrus 0:0a673c671a56 435 }
ebrus 0:0a673c671a56 436
ebrus 0:0a673c671a56 437 /**
ebrus 0:0a673c671a56 438 * @brief Select the start bank filter for slave CAN.
ebrus 0:0a673c671a56 439 * @note This function applies only to STM32 Connectivity line devices.
ebrus 0:0a673c671a56 440 * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
ebrus 0:0a673c671a56 441 * @retval None.
ebrus 0:0a673c671a56 442 */
ebrus 0:0a673c671a56 443 void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
ebrus 0:0a673c671a56 444 {
ebrus 0:0a673c671a56 445 /* Check the parameters */
ebrus 0:0a673c671a56 446 assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
ebrus 0:0a673c671a56 447
ebrus 0:0a673c671a56 448 /* Enter Initialisation mode for the filter */
ebrus 0:0a673c671a56 449 CAN1->FMR |= FMR_FINIT;
ebrus 0:0a673c671a56 450
ebrus 0:0a673c671a56 451 /* Select the start slave bank */
ebrus 0:0a673c671a56 452 CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
ebrus 0:0a673c671a56 453 CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
ebrus 0:0a673c671a56 454
ebrus 0:0a673c671a56 455 /* Leave Initialisation mode for the filter */
ebrus 0:0a673c671a56 456 CAN1->FMR &= ~FMR_FINIT;
ebrus 0:0a673c671a56 457 }
ebrus 0:0a673c671a56 458
ebrus 0:0a673c671a56 459 /**
ebrus 0:0a673c671a56 460 * @brief Enables or disables the DBG Freeze for CAN.
ebrus 0:0a673c671a56 461 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 462 * @param NewState: new state of the CAN peripheral. This parameter can
ebrus 0:0a673c671a56 463 * be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 464 * @retval None.
ebrus 0:0a673c671a56 465 */
ebrus 0:0a673c671a56 466 void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
ebrus 0:0a673c671a56 467 {
ebrus 0:0a673c671a56 468 /* Check the parameters */
ebrus 0:0a673c671a56 469 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 470 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 471
ebrus 0:0a673c671a56 472 if (NewState != DISABLE)
ebrus 0:0a673c671a56 473 {
ebrus 0:0a673c671a56 474 /* Enable Debug Freeze */
ebrus 0:0a673c671a56 475 CANx->MCR |= MCR_DBF;
ebrus 0:0a673c671a56 476 }
ebrus 0:0a673c671a56 477 else
ebrus 0:0a673c671a56 478 {
ebrus 0:0a673c671a56 479 /* Disable Debug Freeze */
ebrus 0:0a673c671a56 480 CANx->MCR &= ~MCR_DBF;
ebrus 0:0a673c671a56 481 }
ebrus 0:0a673c671a56 482 }
ebrus 0:0a673c671a56 483
ebrus 0:0a673c671a56 484
ebrus 0:0a673c671a56 485 /**
ebrus 0:0a673c671a56 486 * @brief Enables or disabes the CAN Time TriggerOperation communication mode.
ebrus 0:0a673c671a56 487 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 488 * @param NewState : Mode new state , can be one of @ref FunctionalState.
ebrus 0:0a673c671a56 489 * @note when enabled, Time stamp (TIME[15:0]) value is sent in the last
ebrus 0:0a673c671a56 490 * two data bytes of the 8-byte message: TIME[7:0] in data byte 6
ebrus 0:0a673c671a56 491 * and TIME[15:8] in data byte 7
ebrus 0:0a673c671a56 492 * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
ebrus 0:0a673c671a56 493 * sent over the CAN bus.
ebrus 0:0a673c671a56 494 * @retval None
ebrus 0:0a673c671a56 495 */
ebrus 0:0a673c671a56 496 void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
ebrus 0:0a673c671a56 497 {
ebrus 0:0a673c671a56 498 /* Check the parameters */
ebrus 0:0a673c671a56 499 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 500 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 501 if (NewState != DISABLE)
ebrus 0:0a673c671a56 502 {
ebrus 0:0a673c671a56 503 /* Enable the TTCM mode */
ebrus 0:0a673c671a56 504 CANx->MCR |= CAN_MCR_TTCM;
ebrus 0:0a673c671a56 505
ebrus 0:0a673c671a56 506 /* Set TGT bits */
ebrus 0:0a673c671a56 507 CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
ebrus 0:0a673c671a56 508 CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
ebrus 0:0a673c671a56 509 CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
ebrus 0:0a673c671a56 510 }
ebrus 0:0a673c671a56 511 else
ebrus 0:0a673c671a56 512 {
ebrus 0:0a673c671a56 513 /* Disable the TTCM mode */
ebrus 0:0a673c671a56 514 CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
ebrus 0:0a673c671a56 515
ebrus 0:0a673c671a56 516 /* Reset TGT bits */
ebrus 0:0a673c671a56 517 CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
ebrus 0:0a673c671a56 518 CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
ebrus 0:0a673c671a56 519 CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
ebrus 0:0a673c671a56 520 }
ebrus 0:0a673c671a56 521 }
ebrus 0:0a673c671a56 522 /**
ebrus 0:0a673c671a56 523 * @brief Initiates the transmission of a message.
ebrus 0:0a673c671a56 524 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 525 * @param TxMessage: pointer to a structure which contains CAN Id, CAN
ebrus 0:0a673c671a56 526 * DLC and CAN data.
ebrus 0:0a673c671a56 527 * @retval The number of the mailbox that is used for transmission
ebrus 0:0a673c671a56 528 * or CAN_TxStatus_NoMailBox if there is no empty mailbox.
ebrus 0:0a673c671a56 529 */
ebrus 0:0a673c671a56 530 uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
ebrus 0:0a673c671a56 531 {
ebrus 0:0a673c671a56 532 uint8_t transmit_mailbox = 0;
ebrus 0:0a673c671a56 533 /* Check the parameters */
ebrus 0:0a673c671a56 534 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 535 assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
ebrus 0:0a673c671a56 536 assert_param(IS_CAN_RTR(TxMessage->RTR));
ebrus 0:0a673c671a56 537 assert_param(IS_CAN_DLC(TxMessage->DLC));
ebrus 0:0a673c671a56 538
ebrus 0:0a673c671a56 539 /* Select one empty transmit mailbox */
ebrus 0:0a673c671a56 540 if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
ebrus 0:0a673c671a56 541 {
ebrus 0:0a673c671a56 542 transmit_mailbox = 0;
ebrus 0:0a673c671a56 543 }
ebrus 0:0a673c671a56 544 else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
ebrus 0:0a673c671a56 545 {
ebrus 0:0a673c671a56 546 transmit_mailbox = 1;
ebrus 0:0a673c671a56 547 }
ebrus 0:0a673c671a56 548 else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
ebrus 0:0a673c671a56 549 {
ebrus 0:0a673c671a56 550 transmit_mailbox = 2;
ebrus 0:0a673c671a56 551 }
ebrus 0:0a673c671a56 552 else
ebrus 0:0a673c671a56 553 {
ebrus 0:0a673c671a56 554 transmit_mailbox = CAN_TxStatus_NoMailBox;
ebrus 0:0a673c671a56 555 }
ebrus 0:0a673c671a56 556
ebrus 0:0a673c671a56 557 if (transmit_mailbox != CAN_TxStatus_NoMailBox)
ebrus 0:0a673c671a56 558 {
ebrus 0:0a673c671a56 559 /* Set up the Id */
ebrus 0:0a673c671a56 560 CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
ebrus 0:0a673c671a56 561 if (TxMessage->IDE == CAN_Id_Standard)
ebrus 0:0a673c671a56 562 {
ebrus 0:0a673c671a56 563 assert_param(IS_CAN_STDID(TxMessage->StdId));
ebrus 0:0a673c671a56 564 CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
ebrus 0:0a673c671a56 565 TxMessage->RTR);
ebrus 0:0a673c671a56 566 }
ebrus 0:0a673c671a56 567 else
ebrus 0:0a673c671a56 568 {
ebrus 0:0a673c671a56 569 assert_param(IS_CAN_EXTID(TxMessage->ExtId));
ebrus 0:0a673c671a56 570 CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
ebrus 0:0a673c671a56 571 TxMessage->IDE | \
ebrus 0:0a673c671a56 572 TxMessage->RTR);
ebrus 0:0a673c671a56 573 }
ebrus 0:0a673c671a56 574
ebrus 0:0a673c671a56 575 /* Set up the DLC */
ebrus 0:0a673c671a56 576 TxMessage->DLC &= (uint8_t)0x0000000F;
ebrus 0:0a673c671a56 577 CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
ebrus 0:0a673c671a56 578 CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
ebrus 0:0a673c671a56 579
ebrus 0:0a673c671a56 580 /* Set up the data field */
ebrus 0:0a673c671a56 581 CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
ebrus 0:0a673c671a56 582 ((uint32_t)TxMessage->Data[2] << 16) |
ebrus 0:0a673c671a56 583 ((uint32_t)TxMessage->Data[1] << 8) |
ebrus 0:0a673c671a56 584 ((uint32_t)TxMessage->Data[0]));
ebrus 0:0a673c671a56 585 CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
ebrus 0:0a673c671a56 586 ((uint32_t)TxMessage->Data[6] << 16) |
ebrus 0:0a673c671a56 587 ((uint32_t)TxMessage->Data[5] << 8) |
ebrus 0:0a673c671a56 588 ((uint32_t)TxMessage->Data[4]));
ebrus 0:0a673c671a56 589 /* Request transmission */
ebrus 0:0a673c671a56 590 CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
ebrus 0:0a673c671a56 591 }
ebrus 0:0a673c671a56 592 return transmit_mailbox;
ebrus 0:0a673c671a56 593 }
ebrus 0:0a673c671a56 594
ebrus 0:0a673c671a56 595 /**
ebrus 0:0a673c671a56 596 * @brief Checks the transmission of a message.
ebrus 0:0a673c671a56 597 * @param CANx: where x can be 1 or 2 to to select the
ebrus 0:0a673c671a56 598 * CAN peripheral.
ebrus 0:0a673c671a56 599 * @param TransmitMailbox: the number of the mailbox that is used for
ebrus 0:0a673c671a56 600 * transmission.
ebrus 0:0a673c671a56 601 * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, CAN_TxStatus_Failed
ebrus 0:0a673c671a56 602 * in an other case.
ebrus 0:0a673c671a56 603 */
ebrus 0:0a673c671a56 604 uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
ebrus 0:0a673c671a56 605 {
ebrus 0:0a673c671a56 606 uint32_t state = 0;
ebrus 0:0a673c671a56 607
ebrus 0:0a673c671a56 608 /* Check the parameters */
ebrus 0:0a673c671a56 609 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 610 assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
ebrus 0:0a673c671a56 611
ebrus 0:0a673c671a56 612 switch (TransmitMailbox)
ebrus 0:0a673c671a56 613 {
ebrus 0:0a673c671a56 614 case (CAN_TXMAILBOX_0):
ebrus 0:0a673c671a56 615 state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
ebrus 0:0a673c671a56 616 break;
ebrus 0:0a673c671a56 617 case (CAN_TXMAILBOX_1):
ebrus 0:0a673c671a56 618 state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
ebrus 0:0a673c671a56 619 break;
ebrus 0:0a673c671a56 620 case (CAN_TXMAILBOX_2):
ebrus 0:0a673c671a56 621 state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
ebrus 0:0a673c671a56 622 break;
ebrus 0:0a673c671a56 623 default:
ebrus 0:0a673c671a56 624 state = CAN_TxStatus_Failed;
ebrus 0:0a673c671a56 625 break;
ebrus 0:0a673c671a56 626 }
ebrus 0:0a673c671a56 627 switch (state)
ebrus 0:0a673c671a56 628 {
ebrus 0:0a673c671a56 629 /* transmit pending */
ebrus 0:0a673c671a56 630 case (0x0): state = CAN_TxStatus_Pending;
ebrus 0:0a673c671a56 631 break;
ebrus 0:0a673c671a56 632 /* transmit failed */
ebrus 0:0a673c671a56 633 case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
ebrus 0:0a673c671a56 634 break;
ebrus 0:0a673c671a56 635 case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
ebrus 0:0a673c671a56 636 break;
ebrus 0:0a673c671a56 637 case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
ebrus 0:0a673c671a56 638 break;
ebrus 0:0a673c671a56 639 /* transmit succeeded */
ebrus 0:0a673c671a56 640 case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
ebrus 0:0a673c671a56 641 break;
ebrus 0:0a673c671a56 642 case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
ebrus 0:0a673c671a56 643 break;
ebrus 0:0a673c671a56 644 case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
ebrus 0:0a673c671a56 645 break;
ebrus 0:0a673c671a56 646 default: state = CAN_TxStatus_Failed;
ebrus 0:0a673c671a56 647 break;
ebrus 0:0a673c671a56 648 }
ebrus 0:0a673c671a56 649 return (uint8_t) state;
ebrus 0:0a673c671a56 650 }
ebrus 0:0a673c671a56 651
ebrus 0:0a673c671a56 652 /**
ebrus 0:0a673c671a56 653 * @brief Cancels a transmit request.
ebrus 0:0a673c671a56 654 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 655 * @param Mailbox: Mailbox number.
ebrus 0:0a673c671a56 656 * @retval None.
ebrus 0:0a673c671a56 657 */
ebrus 0:0a673c671a56 658 void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
ebrus 0:0a673c671a56 659 {
ebrus 0:0a673c671a56 660 /* Check the parameters */
ebrus 0:0a673c671a56 661 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 662 assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
ebrus 0:0a673c671a56 663 /* abort transmission */
ebrus 0:0a673c671a56 664 switch (Mailbox)
ebrus 0:0a673c671a56 665 {
ebrus 0:0a673c671a56 666 case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
ebrus 0:0a673c671a56 667 break;
ebrus 0:0a673c671a56 668 case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
ebrus 0:0a673c671a56 669 break;
ebrus 0:0a673c671a56 670 case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
ebrus 0:0a673c671a56 671 break;
ebrus 0:0a673c671a56 672 default:
ebrus 0:0a673c671a56 673 break;
ebrus 0:0a673c671a56 674 }
ebrus 0:0a673c671a56 675 }
ebrus 0:0a673c671a56 676
ebrus 0:0a673c671a56 677
ebrus 0:0a673c671a56 678 /**
ebrus 0:0a673c671a56 679 * @brief Receives a message.
ebrus 0:0a673c671a56 680 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 681 * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
ebrus 0:0a673c671a56 682 * @param RxMessage: pointer to a structure receive message which contains
ebrus 0:0a673c671a56 683 * CAN Id, CAN DLC, CAN datas and FMI number.
ebrus 0:0a673c671a56 684 * @retval None.
ebrus 0:0a673c671a56 685 */
ebrus 0:0a673c671a56 686 void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
ebrus 0:0a673c671a56 687 {
ebrus 0:0a673c671a56 688 /* Check the parameters */
ebrus 0:0a673c671a56 689 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 690 assert_param(IS_CAN_FIFO(FIFONumber));
ebrus 0:0a673c671a56 691 /* Get the Id */
ebrus 0:0a673c671a56 692 RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
ebrus 0:0a673c671a56 693 if (RxMessage->IDE == CAN_Id_Standard)
ebrus 0:0a673c671a56 694 {
ebrus 0:0a673c671a56 695 RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
ebrus 0:0a673c671a56 696 }
ebrus 0:0a673c671a56 697 else
ebrus 0:0a673c671a56 698 {
ebrus 0:0a673c671a56 699 RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
ebrus 0:0a673c671a56 700 }
ebrus 0:0a673c671a56 701
ebrus 0:0a673c671a56 702 RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
ebrus 0:0a673c671a56 703 /* Get the DLC */
ebrus 0:0a673c671a56 704 RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
ebrus 0:0a673c671a56 705 /* Get the FMI */
ebrus 0:0a673c671a56 706 RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
ebrus 0:0a673c671a56 707 /* Get the data field */
ebrus 0:0a673c671a56 708 RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
ebrus 0:0a673c671a56 709 RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
ebrus 0:0a673c671a56 710 RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
ebrus 0:0a673c671a56 711 RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
ebrus 0:0a673c671a56 712 RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
ebrus 0:0a673c671a56 713 RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
ebrus 0:0a673c671a56 714 RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
ebrus 0:0a673c671a56 715 RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
ebrus 0:0a673c671a56 716 /* Release the FIFO */
ebrus 0:0a673c671a56 717 /* Release FIFO0 */
ebrus 0:0a673c671a56 718 if (FIFONumber == CAN_FIFO0)
ebrus 0:0a673c671a56 719 {
ebrus 0:0a673c671a56 720 CANx->RF0R |= CAN_RF0R_RFOM0;
ebrus 0:0a673c671a56 721 }
ebrus 0:0a673c671a56 722 /* Release FIFO1 */
ebrus 0:0a673c671a56 723 else /* FIFONumber == CAN_FIFO1 */
ebrus 0:0a673c671a56 724 {
ebrus 0:0a673c671a56 725 CANx->RF1R |= CAN_RF1R_RFOM1;
ebrus 0:0a673c671a56 726 }
ebrus 0:0a673c671a56 727 }
ebrus 0:0a673c671a56 728
ebrus 0:0a673c671a56 729 /**
ebrus 0:0a673c671a56 730 * @brief Releases the specified FIFO.
ebrus 0:0a673c671a56 731 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 732 * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
ebrus 0:0a673c671a56 733 * @retval None.
ebrus 0:0a673c671a56 734 */
ebrus 0:0a673c671a56 735 void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
ebrus 0:0a673c671a56 736 {
ebrus 0:0a673c671a56 737 /* Check the parameters */
ebrus 0:0a673c671a56 738 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 739 assert_param(IS_CAN_FIFO(FIFONumber));
ebrus 0:0a673c671a56 740 /* Release FIFO0 */
ebrus 0:0a673c671a56 741 if (FIFONumber == CAN_FIFO0)
ebrus 0:0a673c671a56 742 {
ebrus 0:0a673c671a56 743 CANx->RF0R |= CAN_RF0R_RFOM0;
ebrus 0:0a673c671a56 744 }
ebrus 0:0a673c671a56 745 /* Release FIFO1 */
ebrus 0:0a673c671a56 746 else /* FIFONumber == CAN_FIFO1 */
ebrus 0:0a673c671a56 747 {
ebrus 0:0a673c671a56 748 CANx->RF1R |= CAN_RF1R_RFOM1;
ebrus 0:0a673c671a56 749 }
ebrus 0:0a673c671a56 750 }
ebrus 0:0a673c671a56 751
ebrus 0:0a673c671a56 752 /**
ebrus 0:0a673c671a56 753 * @brief Returns the number of pending messages.
ebrus 0:0a673c671a56 754 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 755 * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
ebrus 0:0a673c671a56 756 * @retval NbMessage : which is the number of pending message.
ebrus 0:0a673c671a56 757 */
ebrus 0:0a673c671a56 758 uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
ebrus 0:0a673c671a56 759 {
ebrus 0:0a673c671a56 760 uint8_t message_pending=0;
ebrus 0:0a673c671a56 761 /* Check the parameters */
ebrus 0:0a673c671a56 762 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 763 assert_param(IS_CAN_FIFO(FIFONumber));
ebrus 0:0a673c671a56 764 if (FIFONumber == CAN_FIFO0)
ebrus 0:0a673c671a56 765 {
ebrus 0:0a673c671a56 766 message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
ebrus 0:0a673c671a56 767 }
ebrus 0:0a673c671a56 768 else if (FIFONumber == CAN_FIFO1)
ebrus 0:0a673c671a56 769 {
ebrus 0:0a673c671a56 770 message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
ebrus 0:0a673c671a56 771 }
ebrus 0:0a673c671a56 772 else
ebrus 0:0a673c671a56 773 {
ebrus 0:0a673c671a56 774 message_pending = 0;
ebrus 0:0a673c671a56 775 }
ebrus 0:0a673c671a56 776 return message_pending;
ebrus 0:0a673c671a56 777 }
ebrus 0:0a673c671a56 778
ebrus 0:0a673c671a56 779
ebrus 0:0a673c671a56 780 /**
ebrus 0:0a673c671a56 781 * @brief Select the CAN Operation mode.
ebrus 0:0a673c671a56 782 * @param CAN_OperatingMode : CAN Operating Mode. This parameter can be one
ebrus 0:0a673c671a56 783 * of @ref CAN_OperatingMode_TypeDef enumeration.
ebrus 0:0a673c671a56 784 * @retval status of the requested mode which can be
ebrus 0:0a673c671a56 785 * - CAN_ModeStatus_Failed CAN failed entering the specific mode
ebrus 0:0a673c671a56 786 * - CAN_ModeStatus_Success CAN Succeed entering the specific mode
ebrus 0:0a673c671a56 787
ebrus 0:0a673c671a56 788 */
ebrus 0:0a673c671a56 789 uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
ebrus 0:0a673c671a56 790 {
ebrus 0:0a673c671a56 791 uint8_t status = CAN_ModeStatus_Failed;
ebrus 0:0a673c671a56 792
ebrus 0:0a673c671a56 793 /* Timeout for INAK or also for SLAK bits*/
ebrus 0:0a673c671a56 794 uint32_t timeout = INAK_TIMEOUT;
ebrus 0:0a673c671a56 795
ebrus 0:0a673c671a56 796 /* Check the parameters */
ebrus 0:0a673c671a56 797 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 798 assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
ebrus 0:0a673c671a56 799
ebrus 0:0a673c671a56 800 if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
ebrus 0:0a673c671a56 801 {
ebrus 0:0a673c671a56 802 /* Request initialisation */
ebrus 0:0a673c671a56 803 CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
ebrus 0:0a673c671a56 804
ebrus 0:0a673c671a56 805 /* Wait the acknowledge */
ebrus 0:0a673c671a56 806 while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
ebrus 0:0a673c671a56 807 {
ebrus 0:0a673c671a56 808 timeout--;
ebrus 0:0a673c671a56 809 }
ebrus 0:0a673c671a56 810 if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
ebrus 0:0a673c671a56 811 {
ebrus 0:0a673c671a56 812 status = CAN_ModeStatus_Failed;
ebrus 0:0a673c671a56 813 }
ebrus 0:0a673c671a56 814 else
ebrus 0:0a673c671a56 815 {
ebrus 0:0a673c671a56 816 status = CAN_ModeStatus_Success;
ebrus 0:0a673c671a56 817 }
ebrus 0:0a673c671a56 818 }
ebrus 0:0a673c671a56 819 else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
ebrus 0:0a673c671a56 820 {
ebrus 0:0a673c671a56 821 /* Request leave initialisation and sleep mode and enter Normal mode */
ebrus 0:0a673c671a56 822 CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
ebrus 0:0a673c671a56 823
ebrus 0:0a673c671a56 824 /* Wait the acknowledge */
ebrus 0:0a673c671a56 825 while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
ebrus 0:0a673c671a56 826 {
ebrus 0:0a673c671a56 827 timeout--;
ebrus 0:0a673c671a56 828 }
ebrus 0:0a673c671a56 829 if ((CANx->MSR & CAN_MODE_MASK) != 0)
ebrus 0:0a673c671a56 830 {
ebrus 0:0a673c671a56 831 status = CAN_ModeStatus_Failed;
ebrus 0:0a673c671a56 832 }
ebrus 0:0a673c671a56 833 else
ebrus 0:0a673c671a56 834 {
ebrus 0:0a673c671a56 835 status = CAN_ModeStatus_Success;
ebrus 0:0a673c671a56 836 }
ebrus 0:0a673c671a56 837 }
ebrus 0:0a673c671a56 838 else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
ebrus 0:0a673c671a56 839 {
ebrus 0:0a673c671a56 840 /* Request Sleep mode */
ebrus 0:0a673c671a56 841 CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
ebrus 0:0a673c671a56 842
ebrus 0:0a673c671a56 843 /* Wait the acknowledge */
ebrus 0:0a673c671a56 844 while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
ebrus 0:0a673c671a56 845 {
ebrus 0:0a673c671a56 846 timeout--;
ebrus 0:0a673c671a56 847 }
ebrus 0:0a673c671a56 848 if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
ebrus 0:0a673c671a56 849 {
ebrus 0:0a673c671a56 850 status = CAN_ModeStatus_Failed;
ebrus 0:0a673c671a56 851 }
ebrus 0:0a673c671a56 852 else
ebrus 0:0a673c671a56 853 {
ebrus 0:0a673c671a56 854 status = CAN_ModeStatus_Success;
ebrus 0:0a673c671a56 855 }
ebrus 0:0a673c671a56 856 }
ebrus 0:0a673c671a56 857 else
ebrus 0:0a673c671a56 858 {
ebrus 0:0a673c671a56 859 status = CAN_ModeStatus_Failed;
ebrus 0:0a673c671a56 860 }
ebrus 0:0a673c671a56 861
ebrus 0:0a673c671a56 862 return (uint8_t) status;
ebrus 0:0a673c671a56 863 }
ebrus 0:0a673c671a56 864
ebrus 0:0a673c671a56 865 /**
ebrus 0:0a673c671a56 866 * @brief Enters the low power mode.
ebrus 0:0a673c671a56 867 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 868 * @retval status: CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed in an
ebrus 0:0a673c671a56 869 * other case.
ebrus 0:0a673c671a56 870 */
ebrus 0:0a673c671a56 871 uint8_t CAN_Sleep(CAN_TypeDef* CANx)
ebrus 0:0a673c671a56 872 {
ebrus 0:0a673c671a56 873 uint8_t sleepstatus = CAN_Sleep_Failed;
ebrus 0:0a673c671a56 874
ebrus 0:0a673c671a56 875 /* Check the parameters */
ebrus 0:0a673c671a56 876 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 877
ebrus 0:0a673c671a56 878 /* Request Sleep mode */
ebrus 0:0a673c671a56 879 CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
ebrus 0:0a673c671a56 880
ebrus 0:0a673c671a56 881 /* Sleep mode status */
ebrus 0:0a673c671a56 882 if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
ebrus 0:0a673c671a56 883 {
ebrus 0:0a673c671a56 884 /* Sleep mode not entered */
ebrus 0:0a673c671a56 885 sleepstatus = CAN_Sleep_Ok;
ebrus 0:0a673c671a56 886 }
ebrus 0:0a673c671a56 887 /* return sleep mode status */
ebrus 0:0a673c671a56 888 return (uint8_t)sleepstatus;
ebrus 0:0a673c671a56 889 }
ebrus 0:0a673c671a56 890
ebrus 0:0a673c671a56 891 /**
ebrus 0:0a673c671a56 892 * @brief Wakes the CAN up.
ebrus 0:0a673c671a56 893 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 894 * @retval status: CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed in an
ebrus 0:0a673c671a56 895 * other case.
ebrus 0:0a673c671a56 896 */
ebrus 0:0a673c671a56 897 uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
ebrus 0:0a673c671a56 898 {
ebrus 0:0a673c671a56 899 uint32_t wait_slak = SLAK_TIMEOUT;
ebrus 0:0a673c671a56 900 uint8_t wakeupstatus = CAN_WakeUp_Failed;
ebrus 0:0a673c671a56 901
ebrus 0:0a673c671a56 902 /* Check the parameters */
ebrus 0:0a673c671a56 903 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 904
ebrus 0:0a673c671a56 905 /* Wake up request */
ebrus 0:0a673c671a56 906 CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
ebrus 0:0a673c671a56 907
ebrus 0:0a673c671a56 908 /* Sleep mode status */
ebrus 0:0a673c671a56 909 while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
ebrus 0:0a673c671a56 910 {
ebrus 0:0a673c671a56 911 wait_slak--;
ebrus 0:0a673c671a56 912 }
ebrus 0:0a673c671a56 913 if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
ebrus 0:0a673c671a56 914 {
ebrus 0:0a673c671a56 915 /* wake up done : Sleep mode exited */
ebrus 0:0a673c671a56 916 wakeupstatus = CAN_WakeUp_Ok;
ebrus 0:0a673c671a56 917 }
ebrus 0:0a673c671a56 918 /* return wakeup status */
ebrus 0:0a673c671a56 919 return (uint8_t)wakeupstatus;
ebrus 0:0a673c671a56 920 }
ebrus 0:0a673c671a56 921
ebrus 0:0a673c671a56 922
ebrus 0:0a673c671a56 923 /**
ebrus 0:0a673c671a56 924 * @brief Returns the CANx's last error code (LEC).
ebrus 0:0a673c671a56 925 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 926 * @retval CAN_ErrorCode: specifies the Error code :
ebrus 0:0a673c671a56 927 * - CAN_ERRORCODE_NoErr No Error
ebrus 0:0a673c671a56 928 * - CAN_ERRORCODE_StuffErr Stuff Error
ebrus 0:0a673c671a56 929 * - CAN_ERRORCODE_FormErr Form Error
ebrus 0:0a673c671a56 930 * - CAN_ERRORCODE_ACKErr Acknowledgment Error
ebrus 0:0a673c671a56 931 * - CAN_ERRORCODE_BitRecessiveErr Bit Recessive Error
ebrus 0:0a673c671a56 932 * - CAN_ERRORCODE_BitDominantErr Bit Dominant Error
ebrus 0:0a673c671a56 933 * - CAN_ERRORCODE_CRCErr CRC Error
ebrus 0:0a673c671a56 934 * - CAN_ERRORCODE_SoftwareSetErr Software Set Error
ebrus 0:0a673c671a56 935 */
ebrus 0:0a673c671a56 936
ebrus 0:0a673c671a56 937 uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
ebrus 0:0a673c671a56 938 {
ebrus 0:0a673c671a56 939 uint8_t errorcode=0;
ebrus 0:0a673c671a56 940
ebrus 0:0a673c671a56 941 /* Check the parameters */
ebrus 0:0a673c671a56 942 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 943
ebrus 0:0a673c671a56 944 /* Get the error code*/
ebrus 0:0a673c671a56 945 errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
ebrus 0:0a673c671a56 946
ebrus 0:0a673c671a56 947 /* Return the error code*/
ebrus 0:0a673c671a56 948 return errorcode;
ebrus 0:0a673c671a56 949 }
ebrus 0:0a673c671a56 950 /**
ebrus 0:0a673c671a56 951 * @brief Returns the CANx Receive Error Counter (REC).
ebrus 0:0a673c671a56 952 * @note In case of an error during reception, this counter is incremented
ebrus 0:0a673c671a56 953 * by 1 or by 8 depending on the error condition as defined by the CAN
ebrus 0:0a673c671a56 954 * standard. After every successful reception, the counter is
ebrus 0:0a673c671a56 955 * decremented by 1 or reset to 120 if its value was higher than 128.
ebrus 0:0a673c671a56 956 * When the counter value exceeds 127, the CAN controller enters the
ebrus 0:0a673c671a56 957 * error passive state.
ebrus 0:0a673c671a56 958 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 959 * @retval CAN Receive Error Counter.
ebrus 0:0a673c671a56 960 */
ebrus 0:0a673c671a56 961 uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
ebrus 0:0a673c671a56 962 {
ebrus 0:0a673c671a56 963 uint8_t counter=0;
ebrus 0:0a673c671a56 964
ebrus 0:0a673c671a56 965 /* Check the parameters */
ebrus 0:0a673c671a56 966 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 967
ebrus 0:0a673c671a56 968 /* Get the Receive Error Counter*/
ebrus 0:0a673c671a56 969 counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
ebrus 0:0a673c671a56 970
ebrus 0:0a673c671a56 971 /* Return the Receive Error Counter*/
ebrus 0:0a673c671a56 972 return counter;
ebrus 0:0a673c671a56 973 }
ebrus 0:0a673c671a56 974
ebrus 0:0a673c671a56 975
ebrus 0:0a673c671a56 976 /**
ebrus 0:0a673c671a56 977 * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
ebrus 0:0a673c671a56 978 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 979 * @retval LSB of the 9-bit CAN Transmit Error Counter.
ebrus 0:0a673c671a56 980 */
ebrus 0:0a673c671a56 981 uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
ebrus 0:0a673c671a56 982 {
ebrus 0:0a673c671a56 983 uint8_t counter=0;
ebrus 0:0a673c671a56 984
ebrus 0:0a673c671a56 985 /* Check the parameters */
ebrus 0:0a673c671a56 986 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 987
ebrus 0:0a673c671a56 988 /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
ebrus 0:0a673c671a56 989 counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
ebrus 0:0a673c671a56 990
ebrus 0:0a673c671a56 991 /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
ebrus 0:0a673c671a56 992 return counter;
ebrus 0:0a673c671a56 993 }
ebrus 0:0a673c671a56 994
ebrus 0:0a673c671a56 995
ebrus 0:0a673c671a56 996 /**
ebrus 0:0a673c671a56 997 * @brief Enables or disables the specified CANx interrupts.
ebrus 0:0a673c671a56 998 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 999 * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
ebrus 0:0a673c671a56 1000 * This parameter can be:
ebrus 0:0a673c671a56 1001 * - CAN_IT_TME,
ebrus 0:0a673c671a56 1002 * - CAN_IT_FMP0,
ebrus 0:0a673c671a56 1003 * - CAN_IT_FF0,
ebrus 0:0a673c671a56 1004 * - CAN_IT_FOV0,
ebrus 0:0a673c671a56 1005 * - CAN_IT_FMP1,
ebrus 0:0a673c671a56 1006 * - CAN_IT_FF1,
ebrus 0:0a673c671a56 1007 * - CAN_IT_FOV1,
ebrus 0:0a673c671a56 1008 * - CAN_IT_EWG,
ebrus 0:0a673c671a56 1009 * - CAN_IT_EPV,
ebrus 0:0a673c671a56 1010 * - CAN_IT_LEC,
ebrus 0:0a673c671a56 1011 * - CAN_IT_ERR,
ebrus 0:0a673c671a56 1012 * - CAN_IT_WKU or
ebrus 0:0a673c671a56 1013 * - CAN_IT_SLK.
ebrus 0:0a673c671a56 1014 * @param NewState: new state of the CAN interrupts.
ebrus 0:0a673c671a56 1015 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1016 * @retval None.
ebrus 0:0a673c671a56 1017 */
ebrus 0:0a673c671a56 1018 void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
ebrus 0:0a673c671a56 1019 {
ebrus 0:0a673c671a56 1020 /* Check the parameters */
ebrus 0:0a673c671a56 1021 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 1022 assert_param(IS_CAN_IT(CAN_IT));
ebrus 0:0a673c671a56 1023 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1024
ebrus 0:0a673c671a56 1025 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1026 {
ebrus 0:0a673c671a56 1027 /* Enable the selected CANx interrupt */
ebrus 0:0a673c671a56 1028 CANx->IER |= CAN_IT;
ebrus 0:0a673c671a56 1029 }
ebrus 0:0a673c671a56 1030 else
ebrus 0:0a673c671a56 1031 {
ebrus 0:0a673c671a56 1032 /* Disable the selected CANx interrupt */
ebrus 0:0a673c671a56 1033 CANx->IER &= ~CAN_IT;
ebrus 0:0a673c671a56 1034 }
ebrus 0:0a673c671a56 1035 }
ebrus 0:0a673c671a56 1036 /**
ebrus 0:0a673c671a56 1037 * @brief Checks whether the specified CAN flag is set or not.
ebrus 0:0a673c671a56 1038 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 1039 * @param CAN_FLAG: specifies the flag to check.
ebrus 0:0a673c671a56 1040 * This parameter can be one of the following flags:
ebrus 0:0a673c671a56 1041 * - CAN_FLAG_EWG
ebrus 0:0a673c671a56 1042 * - CAN_FLAG_EPV
ebrus 0:0a673c671a56 1043 * - CAN_FLAG_BOF
ebrus 0:0a673c671a56 1044 * - CAN_FLAG_RQCP0
ebrus 0:0a673c671a56 1045 * - CAN_FLAG_RQCP1
ebrus 0:0a673c671a56 1046 * - CAN_FLAG_RQCP2
ebrus 0:0a673c671a56 1047 * - CAN_FLAG_FMP1
ebrus 0:0a673c671a56 1048 * - CAN_FLAG_FF1
ebrus 0:0a673c671a56 1049 * - CAN_FLAG_FOV1
ebrus 0:0a673c671a56 1050 * - CAN_FLAG_FMP0
ebrus 0:0a673c671a56 1051 * - CAN_FLAG_FF0
ebrus 0:0a673c671a56 1052 * - CAN_FLAG_FOV0
ebrus 0:0a673c671a56 1053 * - CAN_FLAG_WKU
ebrus 0:0a673c671a56 1054 * - CAN_FLAG_SLAK
ebrus 0:0a673c671a56 1055 * - CAN_FLAG_LEC
ebrus 0:0a673c671a56 1056 * @retval The new state of CAN_FLAG (SET or RESET).
ebrus 0:0a673c671a56 1057 */
ebrus 0:0a673c671a56 1058 FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
ebrus 0:0a673c671a56 1059 {
ebrus 0:0a673c671a56 1060 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 1061
ebrus 0:0a673c671a56 1062 /* Check the parameters */
ebrus 0:0a673c671a56 1063 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 1064 assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
ebrus 0:0a673c671a56 1065
ebrus 0:0a673c671a56 1066
ebrus 0:0a673c671a56 1067 if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1068 {
ebrus 0:0a673c671a56 1069 /* Check the status of the specified CAN flag */
ebrus 0:0a673c671a56 1070 if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1071 {
ebrus 0:0a673c671a56 1072 /* CAN_FLAG is set */
ebrus 0:0a673c671a56 1073 bitstatus = SET;
ebrus 0:0a673c671a56 1074 }
ebrus 0:0a673c671a56 1075 else
ebrus 0:0a673c671a56 1076 {
ebrus 0:0a673c671a56 1077 /* CAN_FLAG is reset */
ebrus 0:0a673c671a56 1078 bitstatus = RESET;
ebrus 0:0a673c671a56 1079 }
ebrus 0:0a673c671a56 1080 }
ebrus 0:0a673c671a56 1081 else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1082 {
ebrus 0:0a673c671a56 1083 /* Check the status of the specified CAN flag */
ebrus 0:0a673c671a56 1084 if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1085 {
ebrus 0:0a673c671a56 1086 /* CAN_FLAG is set */
ebrus 0:0a673c671a56 1087 bitstatus = SET;
ebrus 0:0a673c671a56 1088 }
ebrus 0:0a673c671a56 1089 else
ebrus 0:0a673c671a56 1090 {
ebrus 0:0a673c671a56 1091 /* CAN_FLAG is reset */
ebrus 0:0a673c671a56 1092 bitstatus = RESET;
ebrus 0:0a673c671a56 1093 }
ebrus 0:0a673c671a56 1094 }
ebrus 0:0a673c671a56 1095 else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1096 {
ebrus 0:0a673c671a56 1097 /* Check the status of the specified CAN flag */
ebrus 0:0a673c671a56 1098 if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1099 {
ebrus 0:0a673c671a56 1100 /* CAN_FLAG is set */
ebrus 0:0a673c671a56 1101 bitstatus = SET;
ebrus 0:0a673c671a56 1102 }
ebrus 0:0a673c671a56 1103 else
ebrus 0:0a673c671a56 1104 {
ebrus 0:0a673c671a56 1105 /* CAN_FLAG is reset */
ebrus 0:0a673c671a56 1106 bitstatus = RESET;
ebrus 0:0a673c671a56 1107 }
ebrus 0:0a673c671a56 1108 }
ebrus 0:0a673c671a56 1109 else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1110 {
ebrus 0:0a673c671a56 1111 /* Check the status of the specified CAN flag */
ebrus 0:0a673c671a56 1112 if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1113 {
ebrus 0:0a673c671a56 1114 /* CAN_FLAG is set */
ebrus 0:0a673c671a56 1115 bitstatus = SET;
ebrus 0:0a673c671a56 1116 }
ebrus 0:0a673c671a56 1117 else
ebrus 0:0a673c671a56 1118 {
ebrus 0:0a673c671a56 1119 /* CAN_FLAG is reset */
ebrus 0:0a673c671a56 1120 bitstatus = RESET;
ebrus 0:0a673c671a56 1121 }
ebrus 0:0a673c671a56 1122 }
ebrus 0:0a673c671a56 1123 else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
ebrus 0:0a673c671a56 1124 {
ebrus 0:0a673c671a56 1125 /* Check the status of the specified CAN flag */
ebrus 0:0a673c671a56 1126 if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1127 {
ebrus 0:0a673c671a56 1128 /* CAN_FLAG is set */
ebrus 0:0a673c671a56 1129 bitstatus = SET;
ebrus 0:0a673c671a56 1130 }
ebrus 0:0a673c671a56 1131 else
ebrus 0:0a673c671a56 1132 {
ebrus 0:0a673c671a56 1133 /* CAN_FLAG is reset */
ebrus 0:0a673c671a56 1134 bitstatus = RESET;
ebrus 0:0a673c671a56 1135 }
ebrus 0:0a673c671a56 1136 }
ebrus 0:0a673c671a56 1137 /* Return the CAN_FLAG status */
ebrus 0:0a673c671a56 1138 return bitstatus;
ebrus 0:0a673c671a56 1139 }
ebrus 0:0a673c671a56 1140
ebrus 0:0a673c671a56 1141 /**
ebrus 0:0a673c671a56 1142 * @brief Clears the CAN's pending flags.
ebrus 0:0a673c671a56 1143 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 1144 * @param CAN_FLAG: specifies the flag to clear.
ebrus 0:0a673c671a56 1145 * This parameter can be one of the following flags:
ebrus 0:0a673c671a56 1146 * - CAN_FLAG_RQCP0
ebrus 0:0a673c671a56 1147 * - CAN_FLAG_RQCP1
ebrus 0:0a673c671a56 1148 * - CAN_FLAG_RQCP2
ebrus 0:0a673c671a56 1149 * - CAN_FLAG_FF1
ebrus 0:0a673c671a56 1150 * - CAN_FLAG_FOV1
ebrus 0:0a673c671a56 1151 * - CAN_FLAG_FF0
ebrus 0:0a673c671a56 1152 * - CAN_FLAG_FOV0
ebrus 0:0a673c671a56 1153 * - CAN_FLAG_WKU
ebrus 0:0a673c671a56 1154 * - CAN_FLAG_SLAK
ebrus 0:0a673c671a56 1155 * - CAN_FLAG_LEC
ebrus 0:0a673c671a56 1156 * @retval None.
ebrus 0:0a673c671a56 1157 */
ebrus 0:0a673c671a56 1158 void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
ebrus 0:0a673c671a56 1159 {
ebrus 0:0a673c671a56 1160 uint32_t flagtmp=0;
ebrus 0:0a673c671a56 1161 /* Check the parameters */
ebrus 0:0a673c671a56 1162 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 1163 assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
ebrus 0:0a673c671a56 1164
ebrus 0:0a673c671a56 1165 if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
ebrus 0:0a673c671a56 1166 {
ebrus 0:0a673c671a56 1167 /* Clear the selected CAN flags */
ebrus 0:0a673c671a56 1168 CANx->ESR = (uint32_t)RESET;
ebrus 0:0a673c671a56 1169 }
ebrus 0:0a673c671a56 1170 else /* MSR or TSR or RF0R or RF1R */
ebrus 0:0a673c671a56 1171 {
ebrus 0:0a673c671a56 1172 flagtmp = CAN_FLAG & 0x000FFFFF;
ebrus 0:0a673c671a56 1173
ebrus 0:0a673c671a56 1174 if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
ebrus 0:0a673c671a56 1175 {
ebrus 0:0a673c671a56 1176 /* Receive Flags */
ebrus 0:0a673c671a56 1177 CANx->RF0R = (uint32_t)(flagtmp);
ebrus 0:0a673c671a56 1178 }
ebrus 0:0a673c671a56 1179 else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
ebrus 0:0a673c671a56 1180 {
ebrus 0:0a673c671a56 1181 /* Receive Flags */
ebrus 0:0a673c671a56 1182 CANx->RF1R = (uint32_t)(flagtmp);
ebrus 0:0a673c671a56 1183 }
ebrus 0:0a673c671a56 1184 else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
ebrus 0:0a673c671a56 1185 {
ebrus 0:0a673c671a56 1186 /* Transmit Flags */
ebrus 0:0a673c671a56 1187 CANx->TSR = (uint32_t)(flagtmp);
ebrus 0:0a673c671a56 1188 }
ebrus 0:0a673c671a56 1189 else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
ebrus 0:0a673c671a56 1190 {
ebrus 0:0a673c671a56 1191 /* Operating mode Flags */
ebrus 0:0a673c671a56 1192 CANx->MSR = (uint32_t)(flagtmp);
ebrus 0:0a673c671a56 1193 }
ebrus 0:0a673c671a56 1194 }
ebrus 0:0a673c671a56 1195 }
ebrus 0:0a673c671a56 1196
ebrus 0:0a673c671a56 1197 /**
ebrus 0:0a673c671a56 1198 * @brief Checks whether the specified CANx interrupt has occurred or not.
ebrus 0:0a673c671a56 1199 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 1200 * @param CAN_IT: specifies the CAN interrupt source to check.
ebrus 0:0a673c671a56 1201 * This parameter can be one of the following flags:
ebrus 0:0a673c671a56 1202 * - CAN_IT_TME
ebrus 0:0a673c671a56 1203 * - CAN_IT_FMP0
ebrus 0:0a673c671a56 1204 * - CAN_IT_FF0
ebrus 0:0a673c671a56 1205 * - CAN_IT_FOV0
ebrus 0:0a673c671a56 1206 * - CAN_IT_FMP1
ebrus 0:0a673c671a56 1207 * - CAN_IT_FF1
ebrus 0:0a673c671a56 1208 * - CAN_IT_FOV1
ebrus 0:0a673c671a56 1209 * - CAN_IT_WKU
ebrus 0:0a673c671a56 1210 * - CAN_IT_SLK
ebrus 0:0a673c671a56 1211 * - CAN_IT_EWG
ebrus 0:0a673c671a56 1212 * - CAN_IT_EPV
ebrus 0:0a673c671a56 1213 * - CAN_IT_BOF
ebrus 0:0a673c671a56 1214 * - CAN_IT_LEC
ebrus 0:0a673c671a56 1215 * - CAN_IT_ERR
ebrus 0:0a673c671a56 1216 * @retval The current state of CAN_IT (SET or RESET).
ebrus 0:0a673c671a56 1217 */
ebrus 0:0a673c671a56 1218 ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
ebrus 0:0a673c671a56 1219 {
ebrus 0:0a673c671a56 1220 ITStatus itstatus = RESET;
ebrus 0:0a673c671a56 1221 /* Check the parameters */
ebrus 0:0a673c671a56 1222 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 1223 assert_param(IS_CAN_IT(CAN_IT));
ebrus 0:0a673c671a56 1224
ebrus 0:0a673c671a56 1225 /* check the enable interrupt bit */
ebrus 0:0a673c671a56 1226 if((CANx->IER & CAN_IT) != RESET)
ebrus 0:0a673c671a56 1227 {
ebrus 0:0a673c671a56 1228 /* in case the Interrupt is enabled, .... */
ebrus 0:0a673c671a56 1229 switch (CAN_IT)
ebrus 0:0a673c671a56 1230 {
ebrus 0:0a673c671a56 1231 case CAN_IT_TME:
ebrus 0:0a673c671a56 1232 /* Check CAN_TSR_RQCPx bits */
ebrus 0:0a673c671a56 1233 itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
ebrus 0:0a673c671a56 1234 break;
ebrus 0:0a673c671a56 1235 case CAN_IT_FMP0:
ebrus 0:0a673c671a56 1236 /* Check CAN_RF0R_FMP0 bit */
ebrus 0:0a673c671a56 1237 itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
ebrus 0:0a673c671a56 1238 break;
ebrus 0:0a673c671a56 1239 case CAN_IT_FF0:
ebrus 0:0a673c671a56 1240 /* Check CAN_RF0R_FULL0 bit */
ebrus 0:0a673c671a56 1241 itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
ebrus 0:0a673c671a56 1242 break;
ebrus 0:0a673c671a56 1243 case CAN_IT_FOV0:
ebrus 0:0a673c671a56 1244 /* Check CAN_RF0R_FOVR0 bit */
ebrus 0:0a673c671a56 1245 itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
ebrus 0:0a673c671a56 1246 break;
ebrus 0:0a673c671a56 1247 case CAN_IT_FMP1:
ebrus 0:0a673c671a56 1248 /* Check CAN_RF1R_FMP1 bit */
ebrus 0:0a673c671a56 1249 itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
ebrus 0:0a673c671a56 1250 break;
ebrus 0:0a673c671a56 1251 case CAN_IT_FF1:
ebrus 0:0a673c671a56 1252 /* Check CAN_RF1R_FULL1 bit */
ebrus 0:0a673c671a56 1253 itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
ebrus 0:0a673c671a56 1254 break;
ebrus 0:0a673c671a56 1255 case CAN_IT_FOV1:
ebrus 0:0a673c671a56 1256 /* Check CAN_RF1R_FOVR1 bit */
ebrus 0:0a673c671a56 1257 itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
ebrus 0:0a673c671a56 1258 break;
ebrus 0:0a673c671a56 1259 case CAN_IT_WKU:
ebrus 0:0a673c671a56 1260 /* Check CAN_MSR_WKUI bit */
ebrus 0:0a673c671a56 1261 itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
ebrus 0:0a673c671a56 1262 break;
ebrus 0:0a673c671a56 1263 case CAN_IT_SLK:
ebrus 0:0a673c671a56 1264 /* Check CAN_MSR_SLAKI bit */
ebrus 0:0a673c671a56 1265 itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
ebrus 0:0a673c671a56 1266 break;
ebrus 0:0a673c671a56 1267 case CAN_IT_EWG:
ebrus 0:0a673c671a56 1268 /* Check CAN_ESR_EWGF bit */
ebrus 0:0a673c671a56 1269 itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
ebrus 0:0a673c671a56 1270 break;
ebrus 0:0a673c671a56 1271 case CAN_IT_EPV:
ebrus 0:0a673c671a56 1272 /* Check CAN_ESR_EPVF bit */
ebrus 0:0a673c671a56 1273 itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
ebrus 0:0a673c671a56 1274 break;
ebrus 0:0a673c671a56 1275 case CAN_IT_BOF:
ebrus 0:0a673c671a56 1276 /* Check CAN_ESR_BOFF bit */
ebrus 0:0a673c671a56 1277 itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
ebrus 0:0a673c671a56 1278 break;
ebrus 0:0a673c671a56 1279 case CAN_IT_LEC:
ebrus 0:0a673c671a56 1280 /* Check CAN_ESR_LEC bit */
ebrus 0:0a673c671a56 1281 itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
ebrus 0:0a673c671a56 1282 break;
ebrus 0:0a673c671a56 1283 case CAN_IT_ERR:
ebrus 0:0a673c671a56 1284 /* Check CAN_MSR_ERRI bit */
ebrus 0:0a673c671a56 1285 itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
ebrus 0:0a673c671a56 1286 break;
ebrus 0:0a673c671a56 1287 default :
ebrus 0:0a673c671a56 1288 /* in case of error, return RESET */
ebrus 0:0a673c671a56 1289 itstatus = RESET;
ebrus 0:0a673c671a56 1290 break;
ebrus 0:0a673c671a56 1291 }
ebrus 0:0a673c671a56 1292 }
ebrus 0:0a673c671a56 1293 else
ebrus 0:0a673c671a56 1294 {
ebrus 0:0a673c671a56 1295 /* in case the Interrupt is not enabled, return RESET */
ebrus 0:0a673c671a56 1296 itstatus = RESET;
ebrus 0:0a673c671a56 1297 }
ebrus 0:0a673c671a56 1298
ebrus 0:0a673c671a56 1299 /* Return the CAN_IT status */
ebrus 0:0a673c671a56 1300 return itstatus;
ebrus 0:0a673c671a56 1301 }
ebrus 0:0a673c671a56 1302
ebrus 0:0a673c671a56 1303 /**
ebrus 0:0a673c671a56 1304 * @brief Clears the CANx's interrupt pending bits.
ebrus 0:0a673c671a56 1305 * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
ebrus 0:0a673c671a56 1306 * @param CAN_IT: specifies the interrupt pending bit to clear.
ebrus 0:0a673c671a56 1307 * - CAN_IT_TME
ebrus 0:0a673c671a56 1308 * - CAN_IT_FF0
ebrus 0:0a673c671a56 1309 * - CAN_IT_FOV0
ebrus 0:0a673c671a56 1310 * - CAN_IT_FF1
ebrus 0:0a673c671a56 1311 * - CAN_IT_FOV1
ebrus 0:0a673c671a56 1312 * - CAN_IT_WKU
ebrus 0:0a673c671a56 1313 * - CAN_IT_SLK
ebrus 0:0a673c671a56 1314 * - CAN_IT_EWG
ebrus 0:0a673c671a56 1315 * - CAN_IT_EPV
ebrus 0:0a673c671a56 1316 * - CAN_IT_BOF
ebrus 0:0a673c671a56 1317 * - CAN_IT_LEC
ebrus 0:0a673c671a56 1318 * - CAN_IT_ERR
ebrus 0:0a673c671a56 1319 * @retval None.
ebrus 0:0a673c671a56 1320 */
ebrus 0:0a673c671a56 1321 void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
ebrus 0:0a673c671a56 1322 {
ebrus 0:0a673c671a56 1323 /* Check the parameters */
ebrus 0:0a673c671a56 1324 assert_param(IS_CAN_ALL_PERIPH(CANx));
ebrus 0:0a673c671a56 1325 assert_param(IS_CAN_CLEAR_IT(CAN_IT));
ebrus 0:0a673c671a56 1326
ebrus 0:0a673c671a56 1327 switch (CAN_IT)
ebrus 0:0a673c671a56 1328 {
ebrus 0:0a673c671a56 1329 case CAN_IT_TME:
ebrus 0:0a673c671a56 1330 /* Clear CAN_TSR_RQCPx (rc_w1)*/
ebrus 0:0a673c671a56 1331 CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
ebrus 0:0a673c671a56 1332 break;
ebrus 0:0a673c671a56 1333 case CAN_IT_FF0:
ebrus 0:0a673c671a56 1334 /* Clear CAN_RF0R_FULL0 (rc_w1)*/
ebrus 0:0a673c671a56 1335 CANx->RF0R = CAN_RF0R_FULL0;
ebrus 0:0a673c671a56 1336 break;
ebrus 0:0a673c671a56 1337 case CAN_IT_FOV0:
ebrus 0:0a673c671a56 1338 /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
ebrus 0:0a673c671a56 1339 CANx->RF0R = CAN_RF0R_FOVR0;
ebrus 0:0a673c671a56 1340 break;
ebrus 0:0a673c671a56 1341 case CAN_IT_FF1:
ebrus 0:0a673c671a56 1342 /* Clear CAN_RF1R_FULL1 (rc_w1)*/
ebrus 0:0a673c671a56 1343 CANx->RF1R = CAN_RF1R_FULL1;
ebrus 0:0a673c671a56 1344 break;
ebrus 0:0a673c671a56 1345 case CAN_IT_FOV1:
ebrus 0:0a673c671a56 1346 /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
ebrus 0:0a673c671a56 1347 CANx->RF1R = CAN_RF1R_FOVR1;
ebrus 0:0a673c671a56 1348 break;
ebrus 0:0a673c671a56 1349 case CAN_IT_WKU:
ebrus 0:0a673c671a56 1350 /* Clear CAN_MSR_WKUI (rc_w1)*/
ebrus 0:0a673c671a56 1351 CANx->MSR = CAN_MSR_WKUI;
ebrus 0:0a673c671a56 1352 break;
ebrus 0:0a673c671a56 1353 case CAN_IT_SLK:
ebrus 0:0a673c671a56 1354 /* Clear CAN_MSR_SLAKI (rc_w1)*/
ebrus 0:0a673c671a56 1355 CANx->MSR = CAN_MSR_SLAKI;
ebrus 0:0a673c671a56 1356 break;
ebrus 0:0a673c671a56 1357 case CAN_IT_EWG:
ebrus 0:0a673c671a56 1358 /* Clear CAN_MSR_ERRI (rc_w1) */
ebrus 0:0a673c671a56 1359 CANx->MSR = CAN_MSR_ERRI;
ebrus 0:0a673c671a56 1360 /* Note : the corresponding Flag is cleared by hardware depending
ebrus 0:0a673c671a56 1361 of the CAN Bus status*/
ebrus 0:0a673c671a56 1362 break;
ebrus 0:0a673c671a56 1363 case CAN_IT_EPV:
ebrus 0:0a673c671a56 1364 /* Clear CAN_MSR_ERRI (rc_w1) */
ebrus 0:0a673c671a56 1365 CANx->MSR = CAN_MSR_ERRI;
ebrus 0:0a673c671a56 1366 /* Note : the corresponding Flag is cleared by hardware depending
ebrus 0:0a673c671a56 1367 of the CAN Bus status*/
ebrus 0:0a673c671a56 1368 break;
ebrus 0:0a673c671a56 1369 case CAN_IT_BOF:
ebrus 0:0a673c671a56 1370 /* Clear CAN_MSR_ERRI (rc_w1) */
ebrus 0:0a673c671a56 1371 CANx->MSR = CAN_MSR_ERRI;
ebrus 0:0a673c671a56 1372 /* Note : the corresponding Flag is cleared by hardware depending
ebrus 0:0a673c671a56 1373 of the CAN Bus status*/
ebrus 0:0a673c671a56 1374 break;
ebrus 0:0a673c671a56 1375 case CAN_IT_LEC:
ebrus 0:0a673c671a56 1376 /* Clear LEC bits */
ebrus 0:0a673c671a56 1377 CANx->ESR = RESET;
ebrus 0:0a673c671a56 1378 /* Clear CAN_MSR_ERRI (rc_w1) */
ebrus 0:0a673c671a56 1379 CANx->MSR = CAN_MSR_ERRI;
ebrus 0:0a673c671a56 1380 break;
ebrus 0:0a673c671a56 1381 case CAN_IT_ERR:
ebrus 0:0a673c671a56 1382 /*Clear LEC bits */
ebrus 0:0a673c671a56 1383 CANx->ESR = RESET;
ebrus 0:0a673c671a56 1384 /* Clear CAN_MSR_ERRI (rc_w1) */
ebrus 0:0a673c671a56 1385 CANx->MSR = CAN_MSR_ERRI;
ebrus 0:0a673c671a56 1386 /* Note : BOFF, EPVF and EWGF Flags are cleared by hardware depending
ebrus 0:0a673c671a56 1387 of the CAN Bus status*/
ebrus 0:0a673c671a56 1388 break;
ebrus 0:0a673c671a56 1389 default :
ebrus 0:0a673c671a56 1390 break;
ebrus 0:0a673c671a56 1391 }
ebrus 0:0a673c671a56 1392 }
ebrus 0:0a673c671a56 1393
ebrus 0:0a673c671a56 1394 /**
ebrus 0:0a673c671a56 1395 * @brief Checks whether the CAN interrupt has occurred or not.
ebrus 0:0a673c671a56 1396 * @param CAN_Reg: specifies the CAN interrupt register to check.
ebrus 0:0a673c671a56 1397 * @param It_Bit: specifies the interrupt source bit to check.
ebrus 0:0a673c671a56 1398 * @retval The new state of the CAN Interrupt (SET or RESET).
ebrus 0:0a673c671a56 1399 */
ebrus 0:0a673c671a56 1400 static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
ebrus 0:0a673c671a56 1401 {
ebrus 0:0a673c671a56 1402 ITStatus pendingbitstatus = RESET;
ebrus 0:0a673c671a56 1403
ebrus 0:0a673c671a56 1404 if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
ebrus 0:0a673c671a56 1405 {
ebrus 0:0a673c671a56 1406 /* CAN_IT is set */
ebrus 0:0a673c671a56 1407 pendingbitstatus = SET;
ebrus 0:0a673c671a56 1408 }
ebrus 0:0a673c671a56 1409 else
ebrus 0:0a673c671a56 1410 {
ebrus 0:0a673c671a56 1411 /* CAN_IT is reset */
ebrus 0:0a673c671a56 1412 pendingbitstatus = RESET;
ebrus 0:0a673c671a56 1413 }
ebrus 0:0a673c671a56 1414 return pendingbitstatus;
ebrus 0:0a673c671a56 1415 }
ebrus 0:0a673c671a56 1416
ebrus 0:0a673c671a56 1417
ebrus 0:0a673c671a56 1418 /**
ebrus 0:0a673c671a56 1419 * @}
ebrus 0:0a673c671a56 1420 */
ebrus 0:0a673c671a56 1421
ebrus 0:0a673c671a56 1422 /**
ebrus 0:0a673c671a56 1423 * @}
ebrus 0:0a673c671a56 1424 */
ebrus 0:0a673c671a56 1425
ebrus 0:0a673c671a56 1426 /**
ebrus 0:0a673c671a56 1427 * @}
ebrus 0:0a673c671a56 1428 */
ebrus 0:0a673c671a56 1429
ebrus 0:0a673c671a56 1430 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/