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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_usart.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_usart.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file contains all the functions prototypes for the USART
ebrus 0:0a673c671a56 8 * firmware library.
ebrus 0:0a673c671a56 9 ******************************************************************************
ebrus 0:0a673c671a56 10 * @attention
ebrus 0:0a673c671a56 11 *
ebrus 0:0a673c671a56 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 13 *
ebrus 0:0a673c671a56 14 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 15 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 16 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 17 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 20 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 22 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 23 * without specific prior written permission.
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 *
ebrus 0:0a673c671a56 36 ******************************************************************************
ebrus 0:0a673c671a56 37 */
ebrus 0:0a673c671a56 38
ebrus 0:0a673c671a56 39 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 40 #ifndef __STM32F30x_USART_H
ebrus 0:0a673c671a56 41 #define __STM32F30x_USART_H
ebrus 0:0a673c671a56 42
ebrus 0:0a673c671a56 43 #ifdef __cplusplus
ebrus 0:0a673c671a56 44 extern "C" {
ebrus 0:0a673c671a56 45 #endif
ebrus 0:0a673c671a56 46
ebrus 0:0a673c671a56 47 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 48 #include "stm32f30x.h"
ebrus 0:0a673c671a56 49
ebrus 0:0a673c671a56 50 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 51 * @{
ebrus 0:0a673c671a56 52 */
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 /** @addtogroup USART
ebrus 0:0a673c671a56 55 * @{
ebrus 0:0a673c671a56 56 */
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 /* Exported types ------------------------------------------------------------*/
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62 /**
ebrus 0:0a673c671a56 63 * @brief USART Init Structure definition
ebrus 0:0a673c671a56 64 */
ebrus 0:0a673c671a56 65
ebrus 0:0a673c671a56 66 typedef struct
ebrus 0:0a673c671a56 67 {
ebrus 0:0a673c671a56 68 uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
ebrus 0:0a673c671a56 69 The baud rate is computed using the following formula:
ebrus 0:0a673c671a56 70 - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
ebrus 0:0a673c671a56 71 - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73 uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
ebrus 0:0a673c671a56 74 This parameter can be a value of @ref USART_Word_Length */
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
ebrus 0:0a673c671a56 77 This parameter can be a value of @ref USART_Stop_Bits */
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 uint32_t USART_Parity; /*!< Specifies the parity mode.
ebrus 0:0a673c671a56 80 This parameter can be a value of @ref USART_Parity
ebrus 0:0a673c671a56 81 @note When parity is enabled, the computed parity is inserted
ebrus 0:0a673c671a56 82 at the MSB position of the transmitted data (9th bit when
ebrus 0:0a673c671a56 83 the word length is set to 9 data bits; 8th bit when the
ebrus 0:0a673c671a56 84 word length is set to 8 data bits). */
ebrus 0:0a673c671a56 85
ebrus 0:0a673c671a56 86 uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
ebrus 0:0a673c671a56 87 This parameter can be a value of @ref USART_Mode */
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
ebrus 0:0a673c671a56 90 or disabled.
ebrus 0:0a673c671a56 91 This parameter can be a value of @ref USART_Hardware_Flow_Control*/
ebrus 0:0a673c671a56 92 } USART_InitTypeDef;
ebrus 0:0a673c671a56 93
ebrus 0:0a673c671a56 94 /**
ebrus 0:0a673c671a56 95 * @brief USART Clock Init Structure definition
ebrus 0:0a673c671a56 96 */
ebrus 0:0a673c671a56 97
ebrus 0:0a673c671a56 98 typedef struct
ebrus 0:0a673c671a56 99 {
ebrus 0:0a673c671a56 100 uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
ebrus 0:0a673c671a56 101 This parameter can be a value of @ref USART_Clock */
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
ebrus 0:0a673c671a56 104 This parameter can be a value of @ref USART_Clock_Polarity */
ebrus 0:0a673c671a56 105
ebrus 0:0a673c671a56 106 uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
ebrus 0:0a673c671a56 107 This parameter can be a value of @ref USART_Clock_Phase */
ebrus 0:0a673c671a56 108
ebrus 0:0a673c671a56 109 uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
ebrus 0:0a673c671a56 110 data bit (MSB) has to be output on the SCLK pin in synchronous mode.
ebrus 0:0a673c671a56 111 This parameter can be a value of @ref USART_Last_Bit */
ebrus 0:0a673c671a56 112 } USART_ClockInitTypeDef;
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 /* Exported constants --------------------------------------------------------*/
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 /** @defgroup USART_Exported_Constants
ebrus 0:0a673c671a56 117 * @{
ebrus 0:0a673c671a56 118 */
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120 #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
ebrus 0:0a673c671a56 121 ((PERIPH) == USART2) || \
ebrus 0:0a673c671a56 122 ((PERIPH) == USART3) || \
ebrus 0:0a673c671a56 123 ((PERIPH) == UART4) || \
ebrus 0:0a673c671a56 124 ((PERIPH) == UART5))
ebrus 0:0a673c671a56 125
ebrus 0:0a673c671a56 126 #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
ebrus 0:0a673c671a56 127 ((PERIPH) == USART2) || \
ebrus 0:0a673c671a56 128 ((PERIPH) == USART3))
ebrus 0:0a673c671a56 129
ebrus 0:0a673c671a56 130 #define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \
ebrus 0:0a673c671a56 131 ((PERIPH) == USART2) || \
ebrus 0:0a673c671a56 132 ((PERIPH) == USART3) || \
ebrus 0:0a673c671a56 133 ((PERIPH) == UART4))
ebrus 0:0a673c671a56 134
ebrus 0:0a673c671a56 135
ebrus 0:0a673c671a56 136 /** @defgroup USART_Word_Length
ebrus 0:0a673c671a56 137 * @{
ebrus 0:0a673c671a56 138 */
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 #define USART_WordLength_8b ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 141 #define USART_WordLength_9b USART_CR1_M
ebrus 0:0a673c671a56 142 #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
ebrus 0:0a673c671a56 143 ((LENGTH) == USART_WordLength_9b))
ebrus 0:0a673c671a56 144 /**
ebrus 0:0a673c671a56 145 * @}
ebrus 0:0a673c671a56 146 */
ebrus 0:0a673c671a56 147
ebrus 0:0a673c671a56 148 /** @defgroup USART_Stop_Bits
ebrus 0:0a673c671a56 149 * @{
ebrus 0:0a673c671a56 150 */
ebrus 0:0a673c671a56 151
ebrus 0:0a673c671a56 152 #define USART_StopBits_1 ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 153 #define USART_StopBits_2 USART_CR2_STOP_1
ebrus 0:0a673c671a56 154 #define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
ebrus 0:0a673c671a56 155 #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
ebrus 0:0a673c671a56 156 ((STOPBITS) == USART_StopBits_2) || \
ebrus 0:0a673c671a56 157 ((STOPBITS) == USART_StopBits_1_5))
ebrus 0:0a673c671a56 158 /**
ebrus 0:0a673c671a56 159 * @}
ebrus 0:0a673c671a56 160 */
ebrus 0:0a673c671a56 161
ebrus 0:0a673c671a56 162 /** @defgroup USART_Parity
ebrus 0:0a673c671a56 163 * @{
ebrus 0:0a673c671a56 164 */
ebrus 0:0a673c671a56 165
ebrus 0:0a673c671a56 166 #define USART_Parity_No ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 167 #define USART_Parity_Even USART_CR1_PCE
ebrus 0:0a673c671a56 168 #define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
ebrus 0:0a673c671a56 169 #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
ebrus 0:0a673c671a56 170 ((PARITY) == USART_Parity_Even) || \
ebrus 0:0a673c671a56 171 ((PARITY) == USART_Parity_Odd))
ebrus 0:0a673c671a56 172 /**
ebrus 0:0a673c671a56 173 * @}
ebrus 0:0a673c671a56 174 */
ebrus 0:0a673c671a56 175
ebrus 0:0a673c671a56 176 /** @defgroup USART_Mode
ebrus 0:0a673c671a56 177 * @{
ebrus 0:0a673c671a56 178 */
ebrus 0:0a673c671a56 179
ebrus 0:0a673c671a56 180 #define USART_Mode_Rx USART_CR1_RE
ebrus 0:0a673c671a56 181 #define USART_Mode_Tx USART_CR1_TE
ebrus 0:0a673c671a56 182 #define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
ebrus 0:0a673c671a56 183 ((MODE) != (uint32_t)0x00))
ebrus 0:0a673c671a56 184 /**
ebrus 0:0a673c671a56 185 * @}
ebrus 0:0a673c671a56 186 */
ebrus 0:0a673c671a56 187
ebrus 0:0a673c671a56 188 /** @defgroup USART_Hardware_Flow_Control
ebrus 0:0a673c671a56 189 * @{
ebrus 0:0a673c671a56 190 */
ebrus 0:0a673c671a56 191
ebrus 0:0a673c671a56 192 #define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 193 #define USART_HardwareFlowControl_RTS USART_CR3_RTSE
ebrus 0:0a673c671a56 194 #define USART_HardwareFlowControl_CTS USART_CR3_CTSE
ebrus 0:0a673c671a56 195 #define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
ebrus 0:0a673c671a56 196 #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
ebrus 0:0a673c671a56 197 (((CONTROL) == USART_HardwareFlowControl_None) || \
ebrus 0:0a673c671a56 198 ((CONTROL) == USART_HardwareFlowControl_RTS) || \
ebrus 0:0a673c671a56 199 ((CONTROL) == USART_HardwareFlowControl_CTS) || \
ebrus 0:0a673c671a56 200 ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
ebrus 0:0a673c671a56 201 /**
ebrus 0:0a673c671a56 202 * @}
ebrus 0:0a673c671a56 203 */
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205 /** @defgroup USART_Clock
ebrus 0:0a673c671a56 206 * @{
ebrus 0:0a673c671a56 207 */
ebrus 0:0a673c671a56 208
ebrus 0:0a673c671a56 209 #define USART_Clock_Disable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 210 #define USART_Clock_Enable USART_CR2_CLKEN
ebrus 0:0a673c671a56 211 #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
ebrus 0:0a673c671a56 212 ((CLOCK) == USART_Clock_Enable))
ebrus 0:0a673c671a56 213 /**
ebrus 0:0a673c671a56 214 * @}
ebrus 0:0a673c671a56 215 */
ebrus 0:0a673c671a56 216
ebrus 0:0a673c671a56 217 /** @defgroup USART_Clock_Polarity
ebrus 0:0a673c671a56 218 * @{
ebrus 0:0a673c671a56 219 */
ebrus 0:0a673c671a56 220
ebrus 0:0a673c671a56 221 #define USART_CPOL_Low ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 222 #define USART_CPOL_High USART_CR2_CPOL
ebrus 0:0a673c671a56 223 #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
ebrus 0:0a673c671a56 224
ebrus 0:0a673c671a56 225 /**
ebrus 0:0a673c671a56 226 * @}
ebrus 0:0a673c671a56 227 */
ebrus 0:0a673c671a56 228
ebrus 0:0a673c671a56 229 /** @defgroup USART_Clock_Phase
ebrus 0:0a673c671a56 230 * @{
ebrus 0:0a673c671a56 231 */
ebrus 0:0a673c671a56 232
ebrus 0:0a673c671a56 233 #define USART_CPHA_1Edge ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 234 #define USART_CPHA_2Edge USART_CR2_CPHA
ebrus 0:0a673c671a56 235 #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
ebrus 0:0a673c671a56 236
ebrus 0:0a673c671a56 237 /**
ebrus 0:0a673c671a56 238 * @}
ebrus 0:0a673c671a56 239 */
ebrus 0:0a673c671a56 240
ebrus 0:0a673c671a56 241 /** @defgroup USART_Last_Bit
ebrus 0:0a673c671a56 242 * @{
ebrus 0:0a673c671a56 243 */
ebrus 0:0a673c671a56 244
ebrus 0:0a673c671a56 245 #define USART_LastBit_Disable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 246 #define USART_LastBit_Enable USART_CR2_LBCL
ebrus 0:0a673c671a56 247 #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
ebrus 0:0a673c671a56 248 ((LASTBIT) == USART_LastBit_Enable))
ebrus 0:0a673c671a56 249 /**
ebrus 0:0a673c671a56 250 * @}
ebrus 0:0a673c671a56 251 */
ebrus 0:0a673c671a56 252
ebrus 0:0a673c671a56 253 /** @defgroup USART_DMA_Requests
ebrus 0:0a673c671a56 254 * @{
ebrus 0:0a673c671a56 255 */
ebrus 0:0a673c671a56 256
ebrus 0:0a673c671a56 257 #define USART_DMAReq_Tx USART_CR3_DMAT
ebrus 0:0a673c671a56 258 #define USART_DMAReq_Rx USART_CR3_DMAR
ebrus 0:0a673c671a56 259 #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
ebrus 0:0a673c671a56 260 ((DMAREQ) != (uint32_t)0x00))
ebrus 0:0a673c671a56 261
ebrus 0:0a673c671a56 262 /**
ebrus 0:0a673c671a56 263 * @}
ebrus 0:0a673c671a56 264 */
ebrus 0:0a673c671a56 265
ebrus 0:0a673c671a56 266 /** @defgroup USART_DMA_Recception_Error
ebrus 0:0a673c671a56 267 * @{
ebrus 0:0a673c671a56 268 */
ebrus 0:0a673c671a56 269
ebrus 0:0a673c671a56 270 #define USART_DMAOnError_Enable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 271 #define USART_DMAOnError_Disable USART_CR3_DDRE
ebrus 0:0a673c671a56 272 #define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
ebrus 0:0a673c671a56 273 ((DMAERROR) == USART_DMAOnError_Enable))
ebrus 0:0a673c671a56 274 /**
ebrus 0:0a673c671a56 275 * @}
ebrus 0:0a673c671a56 276 */
ebrus 0:0a673c671a56 277
ebrus 0:0a673c671a56 278 /** @defgroup USART_MuteMode_WakeUp_methods
ebrus 0:0a673c671a56 279 * @{
ebrus 0:0a673c671a56 280 */
ebrus 0:0a673c671a56 281
ebrus 0:0a673c671a56 282 #define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 283 #define USART_WakeUp_AddressMark USART_CR1_WAKE
ebrus 0:0a673c671a56 284 #define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
ebrus 0:0a673c671a56 285 ((WAKEUP) == USART_WakeUp_AddressMark))
ebrus 0:0a673c671a56 286 /**
ebrus 0:0a673c671a56 287 * @}
ebrus 0:0a673c671a56 288 */
ebrus 0:0a673c671a56 289
ebrus 0:0a673c671a56 290 /** @defgroup USART_Address_Detection
ebrus 0:0a673c671a56 291 * @{
ebrus 0:0a673c671a56 292 */
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294 #define USART_AddressLength_4b ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 295 #define USART_AddressLength_7b USART_CR2_ADDM7
ebrus 0:0a673c671a56 296 #define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
ebrus 0:0a673c671a56 297 ((ADDRESS) == USART_AddressLength_7b))
ebrus 0:0a673c671a56 298 /**
ebrus 0:0a673c671a56 299 * @}
ebrus 0:0a673c671a56 300 */
ebrus 0:0a673c671a56 301
ebrus 0:0a673c671a56 302 /** @defgroup USART_StopMode_WakeUp_methods
ebrus 0:0a673c671a56 303 * @{
ebrus 0:0a673c671a56 304 */
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306 #define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 307 #define USART_WakeUpSource_StartBit USART_CR3_WUS_1
ebrus 0:0a673c671a56 308 #define USART_WakeUpSource_RXNE (uint32_t)(USART_CR3_WUS_0 | USART_CR3_WUS_1)
ebrus 0:0a673c671a56 309 #define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
ebrus 0:0a673c671a56 310 ((SOURCE) == USART_WakeUpSource_StartBit) || \
ebrus 0:0a673c671a56 311 ((SOURCE) == USART_WakeUpSource_RXNE))
ebrus 0:0a673c671a56 312 /**
ebrus 0:0a673c671a56 313 * @}
ebrus 0:0a673c671a56 314 */
ebrus 0:0a673c671a56 315
ebrus 0:0a673c671a56 316 /** @defgroup USART_LIN_Break_Detection_Length
ebrus 0:0a673c671a56 317 * @{
ebrus 0:0a673c671a56 318 */
ebrus 0:0a673c671a56 319
ebrus 0:0a673c671a56 320 #define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 321 #define USART_LINBreakDetectLength_11b USART_CR2_LBDL
ebrus 0:0a673c671a56 322 #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
ebrus 0:0a673c671a56 323 (((LENGTH) == USART_LINBreakDetectLength_10b) || \
ebrus 0:0a673c671a56 324 ((LENGTH) == USART_LINBreakDetectLength_11b))
ebrus 0:0a673c671a56 325 /**
ebrus 0:0a673c671a56 326 * @}
ebrus 0:0a673c671a56 327 */
ebrus 0:0a673c671a56 328
ebrus 0:0a673c671a56 329 /** @defgroup USART_IrDA_Low_Power
ebrus 0:0a673c671a56 330 * @{
ebrus 0:0a673c671a56 331 */
ebrus 0:0a673c671a56 332
ebrus 0:0a673c671a56 333 #define USART_IrDAMode_LowPower USART_CR3_IRLP
ebrus 0:0a673c671a56 334 #define USART_IrDAMode_Normal ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 335 #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
ebrus 0:0a673c671a56 336 ((MODE) == USART_IrDAMode_Normal))
ebrus 0:0a673c671a56 337 /**
ebrus 0:0a673c671a56 338 * @}
ebrus 0:0a673c671a56 339 */
ebrus 0:0a673c671a56 340
ebrus 0:0a673c671a56 341 /** @defgroup USART_DE_Polarity
ebrus 0:0a673c671a56 342 * @{
ebrus 0:0a673c671a56 343 */
ebrus 0:0a673c671a56 344
ebrus 0:0a673c671a56 345 #define USART_DEPolarity_High ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 346 #define USART_DEPolarity_Low USART_CR3_DEP
ebrus 0:0a673c671a56 347 #define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
ebrus 0:0a673c671a56 348 ((POLARITY) == USART_DEPolarity_High))
ebrus 0:0a673c671a56 349 /**
ebrus 0:0a673c671a56 350 * @}
ebrus 0:0a673c671a56 351 */
ebrus 0:0a673c671a56 352
ebrus 0:0a673c671a56 353 /** @defgroup USART_Inversion_Pins
ebrus 0:0a673c671a56 354 * @{
ebrus 0:0a673c671a56 355 */
ebrus 0:0a673c671a56 356
ebrus 0:0a673c671a56 357 #define USART_InvPin_Tx USART_CR2_TXINV
ebrus 0:0a673c671a56 358 #define USART_InvPin_Rx USART_CR2_RXINV
ebrus 0:0a673c671a56 359 #define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
ebrus 0:0a673c671a56 360 ((PIN) != (uint32_t)0x00))
ebrus 0:0a673c671a56 361
ebrus 0:0a673c671a56 362 /**
ebrus 0:0a673c671a56 363 * @}
ebrus 0:0a673c671a56 364 */
ebrus 0:0a673c671a56 365
ebrus 0:0a673c671a56 366 /** @defgroup USART_AutoBaudRate_Mode
ebrus 0:0a673c671a56 367 * @{
ebrus 0:0a673c671a56 368 */
ebrus 0:0a673c671a56 369
ebrus 0:0a673c671a56 370 #define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 371 #define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
ebrus 0:0a673c671a56 372 #define USART_AutoBaudRate_0x7FFrame USART_CR2_ABRMODE_1
ebrus 0:0a673c671a56 373 #define USART_AutoBaudRate_0x55Frame (USART_CR2_ABRMODE_0 | USART_CR2_ABRMODE_1)
ebrus 0:0a673c671a56 374 #define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
ebrus 0:0a673c671a56 375 ((MODE) == USART_AutoBaudRate_FallingEdge) || \
ebrus 0:0a673c671a56 376 ((MODE) == USART_AutoBaudRate_0x7FFrame) || \
ebrus 0:0a673c671a56 377 ((MODE) == USART_AutoBaudRate_0x55Frame))
ebrus 0:0a673c671a56 378 /**
ebrus 0:0a673c671a56 379 * @}
ebrus 0:0a673c671a56 380 */
ebrus 0:0a673c671a56 381
ebrus 0:0a673c671a56 382 /** @defgroup USART_OVR_DETECTION
ebrus 0:0a673c671a56 383 * @{
ebrus 0:0a673c671a56 384 */
ebrus 0:0a673c671a56 385
ebrus 0:0a673c671a56 386 #define USART_OVRDetection_Enable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 387 #define USART_OVRDetection_Disable USART_CR3_OVRDIS
ebrus 0:0a673c671a56 388 #define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
ebrus 0:0a673c671a56 389 ((OVR) == USART_OVRDetection_Disable))
ebrus 0:0a673c671a56 390 /**
ebrus 0:0a673c671a56 391 * @}
ebrus 0:0a673c671a56 392 */
ebrus 0:0a673c671a56 393 /** @defgroup USART_Request
ebrus 0:0a673c671a56 394 * @{
ebrus 0:0a673c671a56 395 */
ebrus 0:0a673c671a56 396
ebrus 0:0a673c671a56 397 #define USART_Request_ABRRQ USART_RQR_ABRRQ
ebrus 0:0a673c671a56 398 #define USART_Request_SBKRQ USART_RQR_SBKRQ
ebrus 0:0a673c671a56 399 #define USART_Request_MMRQ USART_RQR_MMRQ
ebrus 0:0a673c671a56 400 #define USART_Request_RXFRQ USART_RQR_RXFRQ
ebrus 0:0a673c671a56 401 #define USART_Request_TXFRQ USART_RQR_TXFRQ
ebrus 0:0a673c671a56 402
ebrus 0:0a673c671a56 403 #define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
ebrus 0:0a673c671a56 404 ((REQUEST) == USART_Request_RXFRQ) || \
ebrus 0:0a673c671a56 405 ((REQUEST) == USART_Request_MMRQ) || \
ebrus 0:0a673c671a56 406 ((REQUEST) == USART_Request_SBKRQ) || \
ebrus 0:0a673c671a56 407 ((REQUEST) == USART_Request_ABRRQ))
ebrus 0:0a673c671a56 408 /**
ebrus 0:0a673c671a56 409 * @}
ebrus 0:0a673c671a56 410 */
ebrus 0:0a673c671a56 411
ebrus 0:0a673c671a56 412 /** @defgroup USART_Flags
ebrus 0:0a673c671a56 413 * @{
ebrus 0:0a673c671a56 414 */
ebrus 0:0a673c671a56 415 #define USART_FLAG_REACK USART_ISR_REACK
ebrus 0:0a673c671a56 416 #define USART_FLAG_TEACK USART_ISR_TEACK
ebrus 0:0a673c671a56 417 #define USART_FLAG_WU USART_ISR_WUF
ebrus 0:0a673c671a56 418 #define USART_FLAG_RWU USART_ISR_RWU
ebrus 0:0a673c671a56 419 #define USART_FLAG_SBK USART_ISR_SBKF
ebrus 0:0a673c671a56 420 #define USART_FLAG_CM USART_ISR_CMF
ebrus 0:0a673c671a56 421 #define USART_FLAG_BUSY USART_ISR_BUSY
ebrus 0:0a673c671a56 422 #define USART_FLAG_ABRF USART_ISR_ABRF
ebrus 0:0a673c671a56 423 #define USART_FLAG_ABRE USART_ISR_ABRE
ebrus 0:0a673c671a56 424 #define USART_FLAG_EOB USART_ISR_EOBF
ebrus 0:0a673c671a56 425 #define USART_FLAG_RTO USART_ISR_RTOF
ebrus 0:0a673c671a56 426 #define USART_FLAG_nCTSS USART_ISR_CTS
ebrus 0:0a673c671a56 427 #define USART_FLAG_CTS USART_ISR_CTSIF
ebrus 0:0a673c671a56 428 #define USART_FLAG_LBD USART_ISR_LBD
ebrus 0:0a673c671a56 429 #define USART_FLAG_TXE USART_ISR_TXE
ebrus 0:0a673c671a56 430 #define USART_FLAG_TC USART_ISR_TC
ebrus 0:0a673c671a56 431 #define USART_FLAG_RXNE USART_ISR_RXNE
ebrus 0:0a673c671a56 432 #define USART_FLAG_IDLE USART_ISR_IDLE
ebrus 0:0a673c671a56 433 #define USART_FLAG_ORE USART_ISR_ORE
ebrus 0:0a673c671a56 434 #define USART_FLAG_NE USART_ISR_NE
ebrus 0:0a673c671a56 435 #define USART_FLAG_FE USART_ISR_FE
ebrus 0:0a673c671a56 436 #define USART_FLAG_PE USART_ISR_PE
ebrus 0:0a673c671a56 437 #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
ebrus 0:0a673c671a56 438 ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
ebrus 0:0a673c671a56 439 ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
ebrus 0:0a673c671a56 440 ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
ebrus 0:0a673c671a56 441 ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
ebrus 0:0a673c671a56 442 ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
ebrus 0:0a673c671a56 443 ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
ebrus 0:0a673c671a56 444 ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
ebrus 0:0a673c671a56 445 ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
ebrus 0:0a673c671a56 446 ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
ebrus 0:0a673c671a56 447 ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
ebrus 0:0a673c671a56 448
ebrus 0:0a673c671a56 449 #define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
ebrus 0:0a673c671a56 450 ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
ebrus 0:0a673c671a56 451 ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
ebrus 0:0a673c671a56 452 ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
ebrus 0:0a673c671a56 453 ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
ebrus 0:0a673c671a56 454 ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
ebrus 0:0a673c671a56 455 /**
ebrus 0:0a673c671a56 456 * @}
ebrus 0:0a673c671a56 457 */
ebrus 0:0a673c671a56 458
ebrus 0:0a673c671a56 459 /** @defgroup USART_Interrupt_definition
ebrus 0:0a673c671a56 460 * @brief USART Interrupt definition
ebrus 0:0a673c671a56 461 * USART_IT possible values
ebrus 0:0a673c671a56 462 * Elements values convention: 0xZZZZYYXX
ebrus 0:0a673c671a56 463 * XX: Position of the corresponding Interrupt
ebrus 0:0a673c671a56 464 * YY: Register index
ebrus 0:0a673c671a56 465 * ZZZZ: Flag position
ebrus 0:0a673c671a56 466 * @{
ebrus 0:0a673c671a56 467 */
ebrus 0:0a673c671a56 468
ebrus 0:0a673c671a56 469 #define USART_IT_WU ((uint32_t)0x00140316)
ebrus 0:0a673c671a56 470 #define USART_IT_CM ((uint32_t)0x0011010E)
ebrus 0:0a673c671a56 471 #define USART_IT_EOB ((uint32_t)0x000C011B)
ebrus 0:0a673c671a56 472 #define USART_IT_RTO ((uint32_t)0x000B011A)
ebrus 0:0a673c671a56 473 #define USART_IT_PE ((uint32_t)0x00000108)
ebrus 0:0a673c671a56 474 #define USART_IT_TXE ((uint32_t)0x00070107)
ebrus 0:0a673c671a56 475 #define USART_IT_TC ((uint32_t)0x00060106)
ebrus 0:0a673c671a56 476 #define USART_IT_RXNE ((uint32_t)0x00050105)
ebrus 0:0a673c671a56 477 #define USART_IT_IDLE ((uint32_t)0x00040104)
ebrus 0:0a673c671a56 478 #define USART_IT_LBD ((uint32_t)0x00080206)
ebrus 0:0a673c671a56 479 #define USART_IT_CTS ((uint32_t)0x0009030A)
ebrus 0:0a673c671a56 480 #define USART_IT_ERR ((uint32_t)0x00000300)
ebrus 0:0a673c671a56 481 #define USART_IT_ORE ((uint32_t)0x00030300)
ebrus 0:0a673c671a56 482 #define USART_IT_NE ((uint32_t)0x00020300)
ebrus 0:0a673c671a56 483 #define USART_IT_FE ((uint32_t)0x00010300)
ebrus 0:0a673c671a56 484
ebrus 0:0a673c671a56 485 #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
ebrus 0:0a673c671a56 486 ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
ebrus 0:0a673c671a56 487 ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
ebrus 0:0a673c671a56 488 ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
ebrus 0:0a673c671a56 489 ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
ebrus 0:0a673c671a56 490 ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
ebrus 0:0a673c671a56 491
ebrus 0:0a673c671a56 492 #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
ebrus 0:0a673c671a56 493 ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
ebrus 0:0a673c671a56 494 ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
ebrus 0:0a673c671a56 495 ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
ebrus 0:0a673c671a56 496 ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
ebrus 0:0a673c671a56 497 ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
ebrus 0:0a673c671a56 498 ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
ebrus 0:0a673c671a56 499
ebrus 0:0a673c671a56 500 #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
ebrus 0:0a673c671a56 501 ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
ebrus 0:0a673c671a56 502 ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
ebrus 0:0a673c671a56 503 ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
ebrus 0:0a673c671a56 504 ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
ebrus 0:0a673c671a56 505 ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
ebrus 0:0a673c671a56 506 /**
ebrus 0:0a673c671a56 507 * @}
ebrus 0:0a673c671a56 508 */
ebrus 0:0a673c671a56 509
ebrus 0:0a673c671a56 510 /** @defgroup USART_Global_definition
ebrus 0:0a673c671a56 511 * @{
ebrus 0:0a673c671a56 512 */
ebrus 0:0a673c671a56 513
ebrus 0:0a673c671a56 514 #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
ebrus 0:0a673c671a56 515 #define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
ebrus 0:0a673c671a56 516 #define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
ebrus 0:0a673c671a56 517 #define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
ebrus 0:0a673c671a56 518 #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
ebrus 0:0a673c671a56 519
ebrus 0:0a673c671a56 520 /**
ebrus 0:0a673c671a56 521 * @}
ebrus 0:0a673c671a56 522 */
ebrus 0:0a673c671a56 523
ebrus 0:0a673c671a56 524 /**
ebrus 0:0a673c671a56 525 * @}
ebrus 0:0a673c671a56 526 */
ebrus 0:0a673c671a56 527
ebrus 0:0a673c671a56 528 /* Exported macro ------------------------------------------------------------*/
ebrus 0:0a673c671a56 529 /* Exported functions ------------------------------------------------------- */
ebrus 0:0a673c671a56 530
ebrus 0:0a673c671a56 531 /* Initialization and Configuration functions *********************************/
ebrus 0:0a673c671a56 532 void USART_DeInit(USART_TypeDef* USARTx);
ebrus 0:0a673c671a56 533 void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
ebrus 0:0a673c671a56 534 void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
ebrus 0:0a673c671a56 535 void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
ebrus 0:0a673c671a56 536 void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
ebrus 0:0a673c671a56 537 void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 538 void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
ebrus 0:0a673c671a56 539 void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
ebrus 0:0a673c671a56 540 void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 541 void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 542 void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 543 void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 544 void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
ebrus 0:0a673c671a56 545 void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 546 void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 547 void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
ebrus 0:0a673c671a56 548
ebrus 0:0a673c671a56 549 /* STOP Mode functions ********************************************************/
ebrus 0:0a673c671a56 550 void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 551 void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource);
ebrus 0:0a673c671a56 552
ebrus 0:0a673c671a56 553 /* AutoBaudRate functions *****************************************************/
ebrus 0:0a673c671a56 554 void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 555 void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
ebrus 0:0a673c671a56 556
ebrus 0:0a673c671a56 557 /* Data transfers functions ***************************************************/
ebrus 0:0a673c671a56 558 void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
ebrus 0:0a673c671a56 559 uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
ebrus 0:0a673c671a56 560
ebrus 0:0a673c671a56 561 /* Multi-Processor Communication functions ************************************/
ebrus 0:0a673c671a56 562 void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
ebrus 0:0a673c671a56 563 void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
ebrus 0:0a673c671a56 564 void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 565 void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
ebrus 0:0a673c671a56 566 /* LIN mode functions *********************************************************/
ebrus 0:0a673c671a56 567 void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength);
ebrus 0:0a673c671a56 568 void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 569
ebrus 0:0a673c671a56 570 /* Half-duplex mode function **************************************************/
ebrus 0:0a673c671a56 571 void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 572
ebrus 0:0a673c671a56 573 /* Smartcard mode functions ***************************************************/
ebrus 0:0a673c671a56 574 void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 575 void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 576 void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
ebrus 0:0a673c671a56 577 void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount);
ebrus 0:0a673c671a56 578 void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength);
ebrus 0:0a673c671a56 579
ebrus 0:0a673c671a56 580 /* IrDA mode functions ********************************************************/
ebrus 0:0a673c671a56 581 void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode);
ebrus 0:0a673c671a56 582 void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 583
ebrus 0:0a673c671a56 584 /* RS485 mode functions *******************************************************/
ebrus 0:0a673c671a56 585 void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
ebrus 0:0a673c671a56 586 void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
ebrus 0:0a673c671a56 587 void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
ebrus 0:0a673c671a56 588 void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
ebrus 0:0a673c671a56 589
ebrus 0:0a673c671a56 590 /* DMA transfers management functions *****************************************/
ebrus 0:0a673c671a56 591 void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
ebrus 0:0a673c671a56 592 void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
ebrus 0:0a673c671a56 593
ebrus 0:0a673c671a56 594 /* Interrupts and flags management functions **********************************/
ebrus 0:0a673c671a56 595 void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
ebrus 0:0a673c671a56 596 void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
ebrus 0:0a673c671a56 597 void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
ebrus 0:0a673c671a56 598 FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
ebrus 0:0a673c671a56 599 void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
ebrus 0:0a673c671a56 600 ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
ebrus 0:0a673c671a56 601 void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
ebrus 0:0a673c671a56 602
ebrus 0:0a673c671a56 603 #ifdef __cplusplus
ebrus 0:0a673c671a56 604 }
ebrus 0:0a673c671a56 605 #endif
ebrus 0:0a673c671a56 606
ebrus 0:0a673c671a56 607 #endif /* __STM32F30x_USART_H */
ebrus 0:0a673c671a56 608
ebrus 0:0a673c671a56 609 /**
ebrus 0:0a673c671a56 610 * @}
ebrus 0:0a673c671a56 611 */
ebrus 0:0a673c671a56 612
ebrus 0:0a673c671a56 613 /**
ebrus 0:0a673c671a56 614 * @}
ebrus 0:0a673c671a56 615 */
ebrus 0:0a673c671a56 616
ebrus 0:0a673c671a56 617 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/