Ermanno Brusadin
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mbed-src
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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_spi.h@0:0a673c671a56, 2016-07-27 (annotated)
- Committer:
- ebrus
- Date:
- Wed Jul 27 18:35:32 2016 +0000
- Revision:
- 0:0a673c671a56
4
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| ebrus | 0:0a673c671a56 | 1 | /** |
| ebrus | 0:0a673c671a56 | 2 | ****************************************************************************** |
| ebrus | 0:0a673c671a56 | 3 | * @file stm32f30x_spi.h |
| ebrus | 0:0a673c671a56 | 4 | * @author MCD Application Team |
| ebrus | 0:0a673c671a56 | 5 | * @version V1.1.0 |
| ebrus | 0:0a673c671a56 | 6 | * @date 27-February-2014 |
| ebrus | 0:0a673c671a56 | 7 | * @brief This file contains all the functions prototypes for the SPI |
| ebrus | 0:0a673c671a56 | 8 | * firmware library. |
| ebrus | 0:0a673c671a56 | 9 | ****************************************************************************** |
| ebrus | 0:0a673c671a56 | 10 | * @attention |
| ebrus | 0:0a673c671a56 | 11 | * |
| ebrus | 0:0a673c671a56 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| ebrus | 0:0a673c671a56 | 13 | * |
| ebrus | 0:0a673c671a56 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| ebrus | 0:0a673c671a56 | 15 | * are permitted provided that the following conditions are met: |
| ebrus | 0:0a673c671a56 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| ebrus | 0:0a673c671a56 | 17 | * this list of conditions and the following disclaimer. |
| ebrus | 0:0a673c671a56 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| ebrus | 0:0a673c671a56 | 19 | * this list of conditions and the following disclaimer in the documentation |
| ebrus | 0:0a673c671a56 | 20 | * and/or other materials provided with the distribution. |
| ebrus | 0:0a673c671a56 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| ebrus | 0:0a673c671a56 | 22 | * may be used to endorse or promote products derived from this software |
| ebrus | 0:0a673c671a56 | 23 | * without specific prior written permission. |
| ebrus | 0:0a673c671a56 | 24 | * |
| ebrus | 0:0a673c671a56 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| ebrus | 0:0a673c671a56 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| ebrus | 0:0a673c671a56 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| ebrus | 0:0a673c671a56 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| ebrus | 0:0a673c671a56 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| ebrus | 0:0a673c671a56 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| ebrus | 0:0a673c671a56 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| ebrus | 0:0a673c671a56 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| ebrus | 0:0a673c671a56 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| ebrus | 0:0a673c671a56 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| ebrus | 0:0a673c671a56 | 35 | * |
| ebrus | 0:0a673c671a56 | 36 | ****************************************************************************** |
| ebrus | 0:0a673c671a56 | 37 | */ |
| ebrus | 0:0a673c671a56 | 38 | |
| ebrus | 0:0a673c671a56 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| ebrus | 0:0a673c671a56 | 40 | #ifndef __STM32F30x_SPI_H |
| ebrus | 0:0a673c671a56 | 41 | #define __STM32F30x_SPI_H |
| ebrus | 0:0a673c671a56 | 42 | |
| ebrus | 0:0a673c671a56 | 43 | #ifdef __cplusplus |
| ebrus | 0:0a673c671a56 | 44 | extern "C" { |
| ebrus | 0:0a673c671a56 | 45 | #endif |
| ebrus | 0:0a673c671a56 | 46 | |
| ebrus | 0:0a673c671a56 | 47 | /* Includes ------------------------------------------------------------------*/ |
| ebrus | 0:0a673c671a56 | 48 | #include "stm32f30x.h" |
| ebrus | 0:0a673c671a56 | 49 | |
| ebrus | 0:0a673c671a56 | 50 | /** @addtogroup STM32F30x_StdPeriph_Driver |
| ebrus | 0:0a673c671a56 | 51 | * @{ |
| ebrus | 0:0a673c671a56 | 52 | */ |
| ebrus | 0:0a673c671a56 | 53 | |
| ebrus | 0:0a673c671a56 | 54 | /** @addtogroup SPI |
| ebrus | 0:0a673c671a56 | 55 | * @{ |
| ebrus | 0:0a673c671a56 | 56 | */ |
| ebrus | 0:0a673c671a56 | 57 | |
| ebrus | 0:0a673c671a56 | 58 | /* Exported types ------------------------------------------------------------*/ |
| ebrus | 0:0a673c671a56 | 59 | |
| ebrus | 0:0a673c671a56 | 60 | /** |
| ebrus | 0:0a673c671a56 | 61 | * @brief SPI Init structure definition |
| ebrus | 0:0a673c671a56 | 62 | */ |
| ebrus | 0:0a673c671a56 | 63 | |
| ebrus | 0:0a673c671a56 | 64 | typedef struct |
| ebrus | 0:0a673c671a56 | 65 | { |
| ebrus | 0:0a673c671a56 | 66 | uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. |
| ebrus | 0:0a673c671a56 | 67 | This parameter can be a value of @ref SPI_data_direction */ |
| ebrus | 0:0a673c671a56 | 68 | |
| ebrus | 0:0a673c671a56 | 69 | uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). |
| ebrus | 0:0a673c671a56 | 70 | This parameter can be a value of @ref SPI_mode */ |
| ebrus | 0:0a673c671a56 | 71 | |
| ebrus | 0:0a673c671a56 | 72 | uint16_t SPI_DataSize; /*!< Specifies the SPI data size. |
| ebrus | 0:0a673c671a56 | 73 | This parameter can be a value of @ref SPI_data_size */ |
| ebrus | 0:0a673c671a56 | 74 | |
| ebrus | 0:0a673c671a56 | 75 | uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. |
| ebrus | 0:0a673c671a56 | 76 | This parameter can be a value of @ref SPI_Clock_Polarity */ |
| ebrus | 0:0a673c671a56 | 77 | |
| ebrus | 0:0a673c671a56 | 78 | uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. |
| ebrus | 0:0a673c671a56 | 79 | This parameter can be a value of @ref SPI_Clock_Phase */ |
| ebrus | 0:0a673c671a56 | 80 | |
| ebrus | 0:0a673c671a56 | 81 | uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by |
| ebrus | 0:0a673c671a56 | 82 | hardware (NSS pin) or by software using the SSI bit. |
| ebrus | 0:0a673c671a56 | 83 | This parameter can be a value of @ref SPI_Slave_Select_management */ |
| ebrus | 0:0a673c671a56 | 84 | |
| ebrus | 0:0a673c671a56 | 85 | uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be |
| ebrus | 0:0a673c671a56 | 86 | used to configure the transmit and receive SCK clock. |
| ebrus | 0:0a673c671a56 | 87 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. |
| ebrus | 0:0a673c671a56 | 88 | @note The communication clock is derived from the master |
| ebrus | 0:0a673c671a56 | 89 | clock. The slave clock does not need to be set. */ |
| ebrus | 0:0a673c671a56 | 90 | |
| ebrus | 0:0a673c671a56 | 91 | uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. |
| ebrus | 0:0a673c671a56 | 92 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ |
| ebrus | 0:0a673c671a56 | 93 | |
| ebrus | 0:0a673c671a56 | 94 | uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ |
| ebrus | 0:0a673c671a56 | 95 | }SPI_InitTypeDef; |
| ebrus | 0:0a673c671a56 | 96 | |
| ebrus | 0:0a673c671a56 | 97 | |
| ebrus | 0:0a673c671a56 | 98 | /** |
| ebrus | 0:0a673c671a56 | 99 | * @brief I2S Init structure definition |
| ebrus | 0:0a673c671a56 | 100 | */ |
| ebrus | 0:0a673c671a56 | 101 | |
| ebrus | 0:0a673c671a56 | 102 | typedef struct |
| ebrus | 0:0a673c671a56 | 103 | { |
| ebrus | 0:0a673c671a56 | 104 | uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. |
| ebrus | 0:0a673c671a56 | 105 | This parameter can be a value of @ref I2S_Mode */ |
| ebrus | 0:0a673c671a56 | 106 | |
| ebrus | 0:0a673c671a56 | 107 | uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. |
| ebrus | 0:0a673c671a56 | 108 | This parameter can be a value of @ref I2S_Standard */ |
| ebrus | 0:0a673c671a56 | 109 | |
| ebrus | 0:0a673c671a56 | 110 | uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. |
| ebrus | 0:0a673c671a56 | 111 | This parameter can be a value of @ref I2S_Data_Format */ |
| ebrus | 0:0a673c671a56 | 112 | |
| ebrus | 0:0a673c671a56 | 113 | uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. |
| ebrus | 0:0a673c671a56 | 114 | This parameter can be a value of @ref I2S_MCLK_Output */ |
| ebrus | 0:0a673c671a56 | 115 | |
| ebrus | 0:0a673c671a56 | 116 | uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. |
| ebrus | 0:0a673c671a56 | 117 | This parameter can be a value of @ref I2S_Audio_Frequency */ |
| ebrus | 0:0a673c671a56 | 118 | |
| ebrus | 0:0a673c671a56 | 119 | uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. |
| ebrus | 0:0a673c671a56 | 120 | This parameter can be a value of @ref I2S_Clock_Polarity */ |
| ebrus | 0:0a673c671a56 | 121 | }I2S_InitTypeDef; |
| ebrus | 0:0a673c671a56 | 122 | |
| ebrus | 0:0a673c671a56 | 123 | /* Exported constants --------------------------------------------------------*/ |
| ebrus | 0:0a673c671a56 | 124 | |
| ebrus | 0:0a673c671a56 | 125 | /** @defgroup SPI_Exported_Constants |
| ebrus | 0:0a673c671a56 | 126 | * @{ |
| ebrus | 0:0a673c671a56 | 127 | */ |
| ebrus | 0:0a673c671a56 | 128 | |
| ebrus | 0:0a673c671a56 | 129 | #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ |
| ebrus | 0:0a673c671a56 | 130 | ((PERIPH) == SPI2) || \ |
| ebrus | 0:0a673c671a56 | 131 | ((PERIPH) == SPI3)) |
| ebrus | 0:0a673c671a56 | 132 | |
| ebrus | 0:0a673c671a56 | 133 | #define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ |
| ebrus | 0:0a673c671a56 | 134 | ((PERIPH) == SPI2) || \ |
| ebrus | 0:0a673c671a56 | 135 | ((PERIPH) == SPI3) || \ |
| ebrus | 0:0a673c671a56 | 136 | ((PERIPH) == I2S2ext) || \ |
| ebrus | 0:0a673c671a56 | 137 | ((PERIPH) == I2S3ext)) |
| ebrus | 0:0a673c671a56 | 138 | |
| ebrus | 0:0a673c671a56 | 139 | #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ |
| ebrus | 0:0a673c671a56 | 140 | ((PERIPH) == SPI3)) |
| ebrus | 0:0a673c671a56 | 141 | |
| ebrus | 0:0a673c671a56 | 142 | #define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ |
| ebrus | 0:0a673c671a56 | 143 | ((PERIPH) == SPI3) || \ |
| ebrus | 0:0a673c671a56 | 144 | ((PERIPH) == I2S2ext) || \ |
| ebrus | 0:0a673c671a56 | 145 | ((PERIPH) == I2S3ext)) |
| ebrus | 0:0a673c671a56 | 146 | |
| ebrus | 0:0a673c671a56 | 147 | #define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ |
| ebrus | 0:0a673c671a56 | 148 | ((PERIPH) == I2S3ext)) |
| ebrus | 0:0a673c671a56 | 149 | |
| ebrus | 0:0a673c671a56 | 150 | /** @defgroup SPI_data_direction |
| ebrus | 0:0a673c671a56 | 151 | * @{ |
| ebrus | 0:0a673c671a56 | 152 | */ |
| ebrus | 0:0a673c671a56 | 153 | |
| ebrus | 0:0a673c671a56 | 154 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 155 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) |
| ebrus | 0:0a673c671a56 | 156 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) |
| ebrus | 0:0a673c671a56 | 157 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) |
| ebrus | 0:0a673c671a56 | 158 | #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ |
| ebrus | 0:0a673c671a56 | 159 | ((MODE) == SPI_Direction_2Lines_RxOnly) || \ |
| ebrus | 0:0a673c671a56 | 160 | ((MODE) == SPI_Direction_1Line_Rx) || \ |
| ebrus | 0:0a673c671a56 | 161 | ((MODE) == SPI_Direction_1Line_Tx)) |
| ebrus | 0:0a673c671a56 | 162 | /** |
| ebrus | 0:0a673c671a56 | 163 | * @} |
| ebrus | 0:0a673c671a56 | 164 | */ |
| ebrus | 0:0a673c671a56 | 165 | |
| ebrus | 0:0a673c671a56 | 166 | /** @defgroup SPI_mode |
| ebrus | 0:0a673c671a56 | 167 | * @{ |
| ebrus | 0:0a673c671a56 | 168 | */ |
| ebrus | 0:0a673c671a56 | 169 | |
| ebrus | 0:0a673c671a56 | 170 | #define SPI_Mode_Master ((uint16_t)0x0104) |
| ebrus | 0:0a673c671a56 | 171 | #define SPI_Mode_Slave ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 172 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ |
| ebrus | 0:0a673c671a56 | 173 | ((MODE) == SPI_Mode_Slave)) |
| ebrus | 0:0a673c671a56 | 174 | /** |
| ebrus | 0:0a673c671a56 | 175 | * @} |
| ebrus | 0:0a673c671a56 | 176 | */ |
| ebrus | 0:0a673c671a56 | 177 | |
| ebrus | 0:0a673c671a56 | 178 | /** @defgroup SPI_data_size |
| ebrus | 0:0a673c671a56 | 179 | * @{ |
| ebrus | 0:0a673c671a56 | 180 | */ |
| ebrus | 0:0a673c671a56 | 181 | |
| ebrus | 0:0a673c671a56 | 182 | #define SPI_DataSize_4b ((uint16_t)0x0300) |
| ebrus | 0:0a673c671a56 | 183 | #define SPI_DataSize_5b ((uint16_t)0x0400) |
| ebrus | 0:0a673c671a56 | 184 | #define SPI_DataSize_6b ((uint16_t)0x0500) |
| ebrus | 0:0a673c671a56 | 185 | #define SPI_DataSize_7b ((uint16_t)0x0600) |
| ebrus | 0:0a673c671a56 | 186 | #define SPI_DataSize_8b ((uint16_t)0x0700) |
| ebrus | 0:0a673c671a56 | 187 | #define SPI_DataSize_9b ((uint16_t)0x0800) |
| ebrus | 0:0a673c671a56 | 188 | #define SPI_DataSize_10b ((uint16_t)0x0900) |
| ebrus | 0:0a673c671a56 | 189 | #define SPI_DataSize_11b ((uint16_t)0x0A00) |
| ebrus | 0:0a673c671a56 | 190 | #define SPI_DataSize_12b ((uint16_t)0x0B00) |
| ebrus | 0:0a673c671a56 | 191 | #define SPI_DataSize_13b ((uint16_t)0x0C00) |
| ebrus | 0:0a673c671a56 | 192 | #define SPI_DataSize_14b ((uint16_t)0x0D00) |
| ebrus | 0:0a673c671a56 | 193 | #define SPI_DataSize_15b ((uint16_t)0x0E00) |
| ebrus | 0:0a673c671a56 | 194 | #define SPI_DataSize_16b ((uint16_t)0x0F00) |
| ebrus | 0:0a673c671a56 | 195 | #define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ |
| ebrus | 0:0a673c671a56 | 196 | ((SIZE) == SPI_DataSize_5b) || \ |
| ebrus | 0:0a673c671a56 | 197 | ((SIZE) == SPI_DataSize_6b) || \ |
| ebrus | 0:0a673c671a56 | 198 | ((SIZE) == SPI_DataSize_7b) || \ |
| ebrus | 0:0a673c671a56 | 199 | ((SIZE) == SPI_DataSize_8b) || \ |
| ebrus | 0:0a673c671a56 | 200 | ((SIZE) == SPI_DataSize_9b) || \ |
| ebrus | 0:0a673c671a56 | 201 | ((SIZE) == SPI_DataSize_10b) || \ |
| ebrus | 0:0a673c671a56 | 202 | ((SIZE) == SPI_DataSize_11b) || \ |
| ebrus | 0:0a673c671a56 | 203 | ((SIZE) == SPI_DataSize_12b) || \ |
| ebrus | 0:0a673c671a56 | 204 | ((SIZE) == SPI_DataSize_13b) || \ |
| ebrus | 0:0a673c671a56 | 205 | ((SIZE) == SPI_DataSize_14b) || \ |
| ebrus | 0:0a673c671a56 | 206 | ((SIZE) == SPI_DataSize_15b) || \ |
| ebrus | 0:0a673c671a56 | 207 | ((SIZE) == SPI_DataSize_16b)) |
| ebrus | 0:0a673c671a56 | 208 | /** |
| ebrus | 0:0a673c671a56 | 209 | * @} |
| ebrus | 0:0a673c671a56 | 210 | */ |
| ebrus | 0:0a673c671a56 | 211 | |
| ebrus | 0:0a673c671a56 | 212 | /** @defgroup SPI_CRC_length |
| ebrus | 0:0a673c671a56 | 213 | * @{ |
| ebrus | 0:0a673c671a56 | 214 | */ |
| ebrus | 0:0a673c671a56 | 215 | |
| ebrus | 0:0a673c671a56 | 216 | #define SPI_CRCLength_8b ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 217 | #define SPI_CRCLength_16b ((uint16_t)0x0800) |
| ebrus | 0:0a673c671a56 | 218 | #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ |
| ebrus | 0:0a673c671a56 | 219 | ((LENGTH) == SPI_CRCLength_16b)) |
| ebrus | 0:0a673c671a56 | 220 | /** |
| ebrus | 0:0a673c671a56 | 221 | * @} |
| ebrus | 0:0a673c671a56 | 222 | */ |
| ebrus | 0:0a673c671a56 | 223 | |
| ebrus | 0:0a673c671a56 | 224 | /** @defgroup SPI_Clock_Polarity |
| ebrus | 0:0a673c671a56 | 225 | * @{ |
| ebrus | 0:0a673c671a56 | 226 | */ |
| ebrus | 0:0a673c671a56 | 227 | |
| ebrus | 0:0a673c671a56 | 228 | #define SPI_CPOL_Low ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 229 | #define SPI_CPOL_High ((uint16_t)0x0002) |
| ebrus | 0:0a673c671a56 | 230 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ |
| ebrus | 0:0a673c671a56 | 231 | ((CPOL) == SPI_CPOL_High)) |
| ebrus | 0:0a673c671a56 | 232 | /** |
| ebrus | 0:0a673c671a56 | 233 | * @} |
| ebrus | 0:0a673c671a56 | 234 | */ |
| ebrus | 0:0a673c671a56 | 235 | |
| ebrus | 0:0a673c671a56 | 236 | /** @defgroup SPI_Clock_Phase |
| ebrus | 0:0a673c671a56 | 237 | * @{ |
| ebrus | 0:0a673c671a56 | 238 | */ |
| ebrus | 0:0a673c671a56 | 239 | |
| ebrus | 0:0a673c671a56 | 240 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 241 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) |
| ebrus | 0:0a673c671a56 | 242 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ |
| ebrus | 0:0a673c671a56 | 243 | ((CPHA) == SPI_CPHA_2Edge)) |
| ebrus | 0:0a673c671a56 | 244 | /** |
| ebrus | 0:0a673c671a56 | 245 | * @} |
| ebrus | 0:0a673c671a56 | 246 | */ |
| ebrus | 0:0a673c671a56 | 247 | |
| ebrus | 0:0a673c671a56 | 248 | /** @defgroup SPI_Slave_Select_management |
| ebrus | 0:0a673c671a56 | 249 | * @{ |
| ebrus | 0:0a673c671a56 | 250 | */ |
| ebrus | 0:0a673c671a56 | 251 | |
| ebrus | 0:0a673c671a56 | 252 | #define SPI_NSS_Soft ((uint16_t)0x0200) |
| ebrus | 0:0a673c671a56 | 253 | #define SPI_NSS_Hard ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 254 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ |
| ebrus | 0:0a673c671a56 | 255 | ((NSS) == SPI_NSS_Hard)) |
| ebrus | 0:0a673c671a56 | 256 | /** |
| ebrus | 0:0a673c671a56 | 257 | * @} |
| ebrus | 0:0a673c671a56 | 258 | */ |
| ebrus | 0:0a673c671a56 | 259 | |
| ebrus | 0:0a673c671a56 | 260 | /** @defgroup SPI_BaudRate_Prescaler |
| ebrus | 0:0a673c671a56 | 261 | * @{ |
| ebrus | 0:0a673c671a56 | 262 | */ |
| ebrus | 0:0a673c671a56 | 263 | |
| ebrus | 0:0a673c671a56 | 264 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 265 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) |
| ebrus | 0:0a673c671a56 | 266 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) |
| ebrus | 0:0a673c671a56 | 267 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) |
| ebrus | 0:0a673c671a56 | 268 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) |
| ebrus | 0:0a673c671a56 | 269 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) |
| ebrus | 0:0a673c671a56 | 270 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) |
| ebrus | 0:0a673c671a56 | 271 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) |
| ebrus | 0:0a673c671a56 | 272 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ |
| ebrus | 0:0a673c671a56 | 273 | ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ |
| ebrus | 0:0a673c671a56 | 274 | ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ |
| ebrus | 0:0a673c671a56 | 275 | ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ |
| ebrus | 0:0a673c671a56 | 276 | ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ |
| ebrus | 0:0a673c671a56 | 277 | ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ |
| ebrus | 0:0a673c671a56 | 278 | ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ |
| ebrus | 0:0a673c671a56 | 279 | ((PRESCALER) == SPI_BaudRatePrescaler_256)) |
| ebrus | 0:0a673c671a56 | 280 | /** |
| ebrus | 0:0a673c671a56 | 281 | * @} |
| ebrus | 0:0a673c671a56 | 282 | */ |
| ebrus | 0:0a673c671a56 | 283 | |
| ebrus | 0:0a673c671a56 | 284 | /** @defgroup SPI_MSB_LSB_transmission |
| ebrus | 0:0a673c671a56 | 285 | * @{ |
| ebrus | 0:0a673c671a56 | 286 | */ |
| ebrus | 0:0a673c671a56 | 287 | |
| ebrus | 0:0a673c671a56 | 288 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 289 | #define SPI_FirstBit_LSB ((uint16_t)0x0080) |
| ebrus | 0:0a673c671a56 | 290 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ |
| ebrus | 0:0a673c671a56 | 291 | ((BIT) == SPI_FirstBit_LSB)) |
| ebrus | 0:0a673c671a56 | 292 | /** |
| ebrus | 0:0a673c671a56 | 293 | * @} |
| ebrus | 0:0a673c671a56 | 294 | */ |
| ebrus | 0:0a673c671a56 | 295 | |
| ebrus | 0:0a673c671a56 | 296 | /** @defgroup I2S_Mode |
| ebrus | 0:0a673c671a56 | 297 | * @{ |
| ebrus | 0:0a673c671a56 | 298 | */ |
| ebrus | 0:0a673c671a56 | 299 | |
| ebrus | 0:0a673c671a56 | 300 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 301 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) |
| ebrus | 0:0a673c671a56 | 302 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) |
| ebrus | 0:0a673c671a56 | 303 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) |
| ebrus | 0:0a673c671a56 | 304 | #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ |
| ebrus | 0:0a673c671a56 | 305 | ((MODE) == I2S_Mode_SlaveRx) || \ |
| ebrus | 0:0a673c671a56 | 306 | ((MODE) == I2S_Mode_MasterTx)|| \ |
| ebrus | 0:0a673c671a56 | 307 | ((MODE) == I2S_Mode_MasterRx)) |
| ebrus | 0:0a673c671a56 | 308 | /** |
| ebrus | 0:0a673c671a56 | 309 | * @} |
| ebrus | 0:0a673c671a56 | 310 | */ |
| ebrus | 0:0a673c671a56 | 311 | |
| ebrus | 0:0a673c671a56 | 312 | /** @defgroup I2S_Standard |
| ebrus | 0:0a673c671a56 | 313 | * @{ |
| ebrus | 0:0a673c671a56 | 314 | */ |
| ebrus | 0:0a673c671a56 | 315 | |
| ebrus | 0:0a673c671a56 | 316 | #define I2S_Standard_Phillips ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 317 | #define I2S_Standard_MSB ((uint16_t)0x0010) |
| ebrus | 0:0a673c671a56 | 318 | #define I2S_Standard_LSB ((uint16_t)0x0020) |
| ebrus | 0:0a673c671a56 | 319 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) |
| ebrus | 0:0a673c671a56 | 320 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) |
| ebrus | 0:0a673c671a56 | 321 | #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ |
| ebrus | 0:0a673c671a56 | 322 | ((STANDARD) == I2S_Standard_MSB) || \ |
| ebrus | 0:0a673c671a56 | 323 | ((STANDARD) == I2S_Standard_LSB) || \ |
| ebrus | 0:0a673c671a56 | 324 | ((STANDARD) == I2S_Standard_PCMShort) || \ |
| ebrus | 0:0a673c671a56 | 325 | ((STANDARD) == I2S_Standard_PCMLong)) |
| ebrus | 0:0a673c671a56 | 326 | /** |
| ebrus | 0:0a673c671a56 | 327 | * @} |
| ebrus | 0:0a673c671a56 | 328 | */ |
| ebrus | 0:0a673c671a56 | 329 | |
| ebrus | 0:0a673c671a56 | 330 | /** @defgroup I2S_Data_Format |
| ebrus | 0:0a673c671a56 | 331 | * @{ |
| ebrus | 0:0a673c671a56 | 332 | */ |
| ebrus | 0:0a673c671a56 | 333 | |
| ebrus | 0:0a673c671a56 | 334 | #define I2S_DataFormat_16b ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 335 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) |
| ebrus | 0:0a673c671a56 | 336 | #define I2S_DataFormat_24b ((uint16_t)0x0003) |
| ebrus | 0:0a673c671a56 | 337 | #define I2S_DataFormat_32b ((uint16_t)0x0005) |
| ebrus | 0:0a673c671a56 | 338 | #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ |
| ebrus | 0:0a673c671a56 | 339 | ((FORMAT) == I2S_DataFormat_16bextended) || \ |
| ebrus | 0:0a673c671a56 | 340 | ((FORMAT) == I2S_DataFormat_24b) || \ |
| ebrus | 0:0a673c671a56 | 341 | ((FORMAT) == I2S_DataFormat_32b)) |
| ebrus | 0:0a673c671a56 | 342 | /** |
| ebrus | 0:0a673c671a56 | 343 | * @} |
| ebrus | 0:0a673c671a56 | 344 | */ |
| ebrus | 0:0a673c671a56 | 345 | |
| ebrus | 0:0a673c671a56 | 346 | /** @defgroup I2S_MCLK_Output |
| ebrus | 0:0a673c671a56 | 347 | * @{ |
| ebrus | 0:0a673c671a56 | 348 | */ |
| ebrus | 0:0a673c671a56 | 349 | |
| ebrus | 0:0a673c671a56 | 350 | #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) |
| ebrus | 0:0a673c671a56 | 351 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 352 | #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ |
| ebrus | 0:0a673c671a56 | 353 | ((OUTPUT) == I2S_MCLKOutput_Disable)) |
| ebrus | 0:0a673c671a56 | 354 | /** |
| ebrus | 0:0a673c671a56 | 355 | * @} |
| ebrus | 0:0a673c671a56 | 356 | */ |
| ebrus | 0:0a673c671a56 | 357 | |
| ebrus | 0:0a673c671a56 | 358 | /** @defgroup I2S_Audio_Frequency |
| ebrus | 0:0a673c671a56 | 359 | * @{ |
| ebrus | 0:0a673c671a56 | 360 | */ |
| ebrus | 0:0a673c671a56 | 361 | |
| ebrus | 0:0a673c671a56 | 362 | #define I2S_AudioFreq_192k ((uint32_t)192000) |
| ebrus | 0:0a673c671a56 | 363 | #define I2S_AudioFreq_96k ((uint32_t)96000) |
| ebrus | 0:0a673c671a56 | 364 | #define I2S_AudioFreq_48k ((uint32_t)48000) |
| ebrus | 0:0a673c671a56 | 365 | #define I2S_AudioFreq_44k ((uint32_t)44100) |
| ebrus | 0:0a673c671a56 | 366 | #define I2S_AudioFreq_32k ((uint32_t)32000) |
| ebrus | 0:0a673c671a56 | 367 | #define I2S_AudioFreq_22k ((uint32_t)22050) |
| ebrus | 0:0a673c671a56 | 368 | #define I2S_AudioFreq_16k ((uint32_t)16000) |
| ebrus | 0:0a673c671a56 | 369 | #define I2S_AudioFreq_11k ((uint32_t)11025) |
| ebrus | 0:0a673c671a56 | 370 | #define I2S_AudioFreq_8k ((uint32_t)8000) |
| ebrus | 0:0a673c671a56 | 371 | #define I2S_AudioFreq_Default ((uint32_t)2) |
| ebrus | 0:0a673c671a56 | 372 | |
| ebrus | 0:0a673c671a56 | 373 | #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ |
| ebrus | 0:0a673c671a56 | 374 | ((FREQ) <= I2S_AudioFreq_192k)) || \ |
| ebrus | 0:0a673c671a56 | 375 | ((FREQ) == I2S_AudioFreq_Default)) |
| ebrus | 0:0a673c671a56 | 376 | /** |
| ebrus | 0:0a673c671a56 | 377 | * @} |
| ebrus | 0:0a673c671a56 | 378 | */ |
| ebrus | 0:0a673c671a56 | 379 | |
| ebrus | 0:0a673c671a56 | 380 | /** @defgroup I2S_Clock_Polarity |
| ebrus | 0:0a673c671a56 | 381 | * @{ |
| ebrus | 0:0a673c671a56 | 382 | */ |
| ebrus | 0:0a673c671a56 | 383 | |
| ebrus | 0:0a673c671a56 | 384 | #define I2S_CPOL_Low ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 385 | #define I2S_CPOL_High ((uint16_t)0x0008) |
| ebrus | 0:0a673c671a56 | 386 | #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ |
| ebrus | 0:0a673c671a56 | 387 | ((CPOL) == I2S_CPOL_High)) |
| ebrus | 0:0a673c671a56 | 388 | /** |
| ebrus | 0:0a673c671a56 | 389 | * @} |
| ebrus | 0:0a673c671a56 | 390 | */ |
| ebrus | 0:0a673c671a56 | 391 | |
| ebrus | 0:0a673c671a56 | 392 | /** @defgroup SPI_FIFO_reception_threshold |
| ebrus | 0:0a673c671a56 | 393 | * @{ |
| ebrus | 0:0a673c671a56 | 394 | */ |
| ebrus | 0:0a673c671a56 | 395 | |
| ebrus | 0:0a673c671a56 | 396 | #define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 397 | #define SPI_RxFIFOThreshold_QF ((uint16_t)0x1000) |
| ebrus | 0:0a673c671a56 | 398 | #define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ |
| ebrus | 0:0a673c671a56 | 399 | ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) |
| ebrus | 0:0a673c671a56 | 400 | /** |
| ebrus | 0:0a673c671a56 | 401 | * @} |
| ebrus | 0:0a673c671a56 | 402 | */ |
| ebrus | 0:0a673c671a56 | 403 | |
| ebrus | 0:0a673c671a56 | 404 | /** @defgroup SPI_I2S_DMA_transfer_requests |
| ebrus | 0:0a673c671a56 | 405 | * @{ |
| ebrus | 0:0a673c671a56 | 406 | */ |
| ebrus | 0:0a673c671a56 | 407 | |
| ebrus | 0:0a673c671a56 | 408 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) |
| ebrus | 0:0a673c671a56 | 409 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) |
| ebrus | 0:0a673c671a56 | 410 | #define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) |
| ebrus | 0:0a673c671a56 | 411 | /** |
| ebrus | 0:0a673c671a56 | 412 | * @} |
| ebrus | 0:0a673c671a56 | 413 | */ |
| ebrus | 0:0a673c671a56 | 414 | |
| ebrus | 0:0a673c671a56 | 415 | /** @defgroup SPI_last_DMA_transfers |
| ebrus | 0:0a673c671a56 | 416 | * @{ |
| ebrus | 0:0a673c671a56 | 417 | */ |
| ebrus | 0:0a673c671a56 | 418 | |
| ebrus | 0:0a673c671a56 | 419 | #define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 420 | #define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) |
| ebrus | 0:0a673c671a56 | 421 | #define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) |
| ebrus | 0:0a673c671a56 | 422 | #define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) |
| ebrus | 0:0a673c671a56 | 423 | #define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ |
| ebrus | 0:0a673c671a56 | 424 | ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ |
| ebrus | 0:0a673c671a56 | 425 | ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ |
| ebrus | 0:0a673c671a56 | 426 | ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) |
| ebrus | 0:0a673c671a56 | 427 | /** |
| ebrus | 0:0a673c671a56 | 428 | * @} |
| ebrus | 0:0a673c671a56 | 429 | */ |
| ebrus | 0:0a673c671a56 | 430 | /** @defgroup SPI_NSS_internal_software_management |
| ebrus | 0:0a673c671a56 | 431 | * @{ |
| ebrus | 0:0a673c671a56 | 432 | */ |
| ebrus | 0:0a673c671a56 | 433 | |
| ebrus | 0:0a673c671a56 | 434 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) |
| ebrus | 0:0a673c671a56 | 435 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) |
| ebrus | 0:0a673c671a56 | 436 | #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ |
| ebrus | 0:0a673c671a56 | 437 | ((INTERNAL) == SPI_NSSInternalSoft_Reset)) |
| ebrus | 0:0a673c671a56 | 438 | /** |
| ebrus | 0:0a673c671a56 | 439 | * @} |
| ebrus | 0:0a673c671a56 | 440 | */ |
| ebrus | 0:0a673c671a56 | 441 | |
| ebrus | 0:0a673c671a56 | 442 | /** @defgroup SPI_CRC_Transmit_Receive |
| ebrus | 0:0a673c671a56 | 443 | * @{ |
| ebrus | 0:0a673c671a56 | 444 | */ |
| ebrus | 0:0a673c671a56 | 445 | |
| ebrus | 0:0a673c671a56 | 446 | #define SPI_CRC_Tx ((uint8_t)0x00) |
| ebrus | 0:0a673c671a56 | 447 | #define SPI_CRC_Rx ((uint8_t)0x01) |
| ebrus | 0:0a673c671a56 | 448 | #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) |
| ebrus | 0:0a673c671a56 | 449 | /** |
| ebrus | 0:0a673c671a56 | 450 | * @} |
| ebrus | 0:0a673c671a56 | 451 | */ |
| ebrus | 0:0a673c671a56 | 452 | |
| ebrus | 0:0a673c671a56 | 453 | /** @defgroup SPI_direction_transmit_receive |
| ebrus | 0:0a673c671a56 | 454 | * @{ |
| ebrus | 0:0a673c671a56 | 455 | */ |
| ebrus | 0:0a673c671a56 | 456 | |
| ebrus | 0:0a673c671a56 | 457 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) |
| ebrus | 0:0a673c671a56 | 458 | #define SPI_Direction_Tx ((uint16_t)0x4000) |
| ebrus | 0:0a673c671a56 | 459 | #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ |
| ebrus | 0:0a673c671a56 | 460 | ((DIRECTION) == SPI_Direction_Tx)) |
| ebrus | 0:0a673c671a56 | 461 | /** |
| ebrus | 0:0a673c671a56 | 462 | * @} |
| ebrus | 0:0a673c671a56 | 463 | */ |
| ebrus | 0:0a673c671a56 | 464 | |
| ebrus | 0:0a673c671a56 | 465 | /** @defgroup SPI_I2S_interrupts_definition |
| ebrus | 0:0a673c671a56 | 466 | * @{ |
| ebrus | 0:0a673c671a56 | 467 | */ |
| ebrus | 0:0a673c671a56 | 468 | |
| ebrus | 0:0a673c671a56 | 469 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) |
| ebrus | 0:0a673c671a56 | 470 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) |
| ebrus | 0:0a673c671a56 | 471 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) |
| ebrus | 0:0a673c671a56 | 472 | |
| ebrus | 0:0a673c671a56 | 473 | #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ |
| ebrus | 0:0a673c671a56 | 474 | ((IT) == SPI_I2S_IT_RXNE) || \ |
| ebrus | 0:0a673c671a56 | 475 | ((IT) == SPI_I2S_IT_ERR)) |
| ebrus | 0:0a673c671a56 | 476 | |
| ebrus | 0:0a673c671a56 | 477 | #define I2S_IT_UDR ((uint8_t)0x53) |
| ebrus | 0:0a673c671a56 | 478 | #define SPI_IT_MODF ((uint8_t)0x55) |
| ebrus | 0:0a673c671a56 | 479 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) |
| ebrus | 0:0a673c671a56 | 480 | #define SPI_I2S_IT_FRE ((uint8_t)0x58) |
| ebrus | 0:0a673c671a56 | 481 | |
| ebrus | 0:0a673c671a56 | 482 | #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ |
| ebrus | 0:0a673c671a56 | 483 | ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \ |
| ebrus | 0:0a673c671a56 | 484 | ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR)) |
| ebrus | 0:0a673c671a56 | 485 | /** |
| ebrus | 0:0a673c671a56 | 486 | * @} |
| ebrus | 0:0a673c671a56 | 487 | */ |
| ebrus | 0:0a673c671a56 | 488 | |
| ebrus | 0:0a673c671a56 | 489 | |
| ebrus | 0:0a673c671a56 | 490 | /** @defgroup SPI_transmission_fifo_status_level |
| ebrus | 0:0a673c671a56 | 491 | * @{ |
| ebrus | 0:0a673c671a56 | 492 | */ |
| ebrus | 0:0a673c671a56 | 493 | |
| ebrus | 0:0a673c671a56 | 494 | #define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 495 | #define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) |
| ebrus | 0:0a673c671a56 | 496 | #define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) |
| ebrus | 0:0a673c671a56 | 497 | #define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) |
| ebrus | 0:0a673c671a56 | 498 | |
| ebrus | 0:0a673c671a56 | 499 | /** |
| ebrus | 0:0a673c671a56 | 500 | * @} |
| ebrus | 0:0a673c671a56 | 501 | */ |
| ebrus | 0:0a673c671a56 | 502 | |
| ebrus | 0:0a673c671a56 | 503 | /** @defgroup SPI_reception_fifo_status_level |
| ebrus | 0:0a673c671a56 | 504 | * @{ |
| ebrus | 0:0a673c671a56 | 505 | */ |
| ebrus | 0:0a673c671a56 | 506 | #define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) |
| ebrus | 0:0a673c671a56 | 507 | #define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) |
| ebrus | 0:0a673c671a56 | 508 | #define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) |
| ebrus | 0:0a673c671a56 | 509 | #define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) |
| ebrus | 0:0a673c671a56 | 510 | |
| ebrus | 0:0a673c671a56 | 511 | /** |
| ebrus | 0:0a673c671a56 | 512 | * @} |
| ebrus | 0:0a673c671a56 | 513 | */ |
| ebrus | 0:0a673c671a56 | 514 | |
| ebrus | 0:0a673c671a56 | 515 | |
| ebrus | 0:0a673c671a56 | 516 | /** @defgroup SPI_I2S_flags_definition |
| ebrus | 0:0a673c671a56 | 517 | * @{ |
| ebrus | 0:0a673c671a56 | 518 | */ |
| ebrus | 0:0a673c671a56 | 519 | |
| ebrus | 0:0a673c671a56 | 520 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) |
| ebrus | 0:0a673c671a56 | 521 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) |
| ebrus | 0:0a673c671a56 | 522 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) |
| ebrus | 0:0a673c671a56 | 523 | #define I2S_FLAG_UDR ((uint16_t)0x0008) |
| ebrus | 0:0a673c671a56 | 524 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) |
| ebrus | 0:0a673c671a56 | 525 | #define SPI_FLAG_MODF ((uint16_t)0x0020) |
| ebrus | 0:0a673c671a56 | 526 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) |
| ebrus | 0:0a673c671a56 | 527 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) |
| ebrus | 0:0a673c671a56 | 528 | #define SPI_I2S_FLAG_FRE ((uint16_t)0x0100) |
| ebrus | 0:0a673c671a56 | 529 | |
| ebrus | 0:0a673c671a56 | 530 | |
| ebrus | 0:0a673c671a56 | 531 | |
| ebrus | 0:0a673c671a56 | 532 | #define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) |
| ebrus | 0:0a673c671a56 | 533 | #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ |
| ebrus | 0:0a673c671a56 | 534 | ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ |
| ebrus | 0:0a673c671a56 | 535 | ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ |
| ebrus | 0:0a673c671a56 | 536 | ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \ |
| ebrus | 0:0a673c671a56 | 537 | ((FLAG) == I2S_FLAG_UDR)) |
| ebrus | 0:0a673c671a56 | 538 | /** |
| ebrus | 0:0a673c671a56 | 539 | * @} |
| ebrus | 0:0a673c671a56 | 540 | */ |
| ebrus | 0:0a673c671a56 | 541 | |
| ebrus | 0:0a673c671a56 | 542 | /** @defgroup SPI_CRC_polynomial |
| ebrus | 0:0a673c671a56 | 543 | * @{ |
| ebrus | 0:0a673c671a56 | 544 | */ |
| ebrus | 0:0a673c671a56 | 545 | |
| ebrus | 0:0a673c671a56 | 546 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) |
| ebrus | 0:0a673c671a56 | 547 | /** |
| ebrus | 0:0a673c671a56 | 548 | * @} |
| ebrus | 0:0a673c671a56 | 549 | */ |
| ebrus | 0:0a673c671a56 | 550 | |
| ebrus | 0:0a673c671a56 | 551 | /** |
| ebrus | 0:0a673c671a56 | 552 | * @} |
| ebrus | 0:0a673c671a56 | 553 | */ |
| ebrus | 0:0a673c671a56 | 554 | |
| ebrus | 0:0a673c671a56 | 555 | /* Exported macro ------------------------------------------------------------*/ |
| ebrus | 0:0a673c671a56 | 556 | /* Exported functions ------------------------------------------------------- */ |
| ebrus | 0:0a673c671a56 | 557 | |
| ebrus | 0:0a673c671a56 | 558 | /* Function used to set the SPI configuration to the default reset state*******/ |
| ebrus | 0:0a673c671a56 | 559 | void SPI_I2S_DeInit(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 560 | |
| ebrus | 0:0a673c671a56 | 561 | /* Initialization and Configuration functions *********************************/ |
| ebrus | 0:0a673c671a56 | 562 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); |
| ebrus | 0:0a673c671a56 | 563 | void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); |
| ebrus | 0:0a673c671a56 | 564 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); |
| ebrus | 0:0a673c671a56 | 565 | void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); |
| ebrus | 0:0a673c671a56 | 566 | void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 567 | void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 568 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 569 | void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 570 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); |
| ebrus | 0:0a673c671a56 | 571 | void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); |
| ebrus | 0:0a673c671a56 | 572 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); |
| ebrus | 0:0a673c671a56 | 573 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); |
| ebrus | 0:0a673c671a56 | 574 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 575 | void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); |
| ebrus | 0:0a673c671a56 | 576 | |
| ebrus | 0:0a673c671a56 | 577 | /* Data transfers functions ***************************************************/ |
| ebrus | 0:0a673c671a56 | 578 | void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); |
| ebrus | 0:0a673c671a56 | 579 | void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data); |
| ebrus | 0:0a673c671a56 | 580 | uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 581 | uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 582 | |
| ebrus | 0:0a673c671a56 | 583 | /* Hardware CRC Calculation functions *****************************************/ |
| ebrus | 0:0a673c671a56 | 584 | void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); |
| ebrus | 0:0a673c671a56 | 585 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 586 | void SPI_TransmitCRC(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 587 | uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); |
| ebrus | 0:0a673c671a56 | 588 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 589 | |
| ebrus | 0:0a673c671a56 | 590 | /* DMA transfers management functions *****************************************/ |
| ebrus | 0:0a673c671a56 | 591 | void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 592 | void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); |
| ebrus | 0:0a673c671a56 | 593 | |
| ebrus | 0:0a673c671a56 | 594 | /* Interrupts and flags management functions **********************************/ |
| ebrus | 0:0a673c671a56 | 595 | void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); |
| ebrus | 0:0a673c671a56 | 596 | uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 597 | uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); |
| ebrus | 0:0a673c671a56 | 598 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); |
| ebrus | 0:0a673c671a56 | 599 | void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); |
| ebrus | 0:0a673c671a56 | 600 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); |
| ebrus | 0:0a673c671a56 | 601 | |
| ebrus | 0:0a673c671a56 | 602 | #ifdef __cplusplus |
| ebrus | 0:0a673c671a56 | 603 | } |
| ebrus | 0:0a673c671a56 | 604 | #endif |
| ebrus | 0:0a673c671a56 | 605 | |
| ebrus | 0:0a673c671a56 | 606 | #endif /*__STM32F30x_SPI_H */ |
| ebrus | 0:0a673c671a56 | 607 | |
| ebrus | 0:0a673c671a56 | 608 | /** |
| ebrus | 0:0a673c671a56 | 609 | * @} |
| ebrus | 0:0a673c671a56 | 610 | */ |
| ebrus | 0:0a673c671a56 | 611 | |
| ebrus | 0:0a673c671a56 | 612 | /** |
| ebrus | 0:0a673c671a56 | 613 | * @} |
| ebrus | 0:0a673c671a56 | 614 | */ |
| ebrus | 0:0a673c671a56 | 615 | |
| ebrus | 0:0a673c671a56 | 616 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |