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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_i2c.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_i2c.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 8 * functionalities of the Inter-Integrated circuit (I2C):
ebrus 0:0a673c671a56 9 * + Initialization and Configuration
ebrus 0:0a673c671a56 10 * + Communications handling
ebrus 0:0a673c671a56 11 * + SMBUS management
ebrus 0:0a673c671a56 12 * + I2C registers management
ebrus 0:0a673c671a56 13 * + Data transfers management
ebrus 0:0a673c671a56 14 * + DMA transfers management
ebrus 0:0a673c671a56 15 * + Interrupts and flags management
ebrus 0:0a673c671a56 16 *
ebrus 0:0a673c671a56 17 * @verbatim
ebrus 0:0a673c671a56 18 ============================================================================
ebrus 0:0a673c671a56 19 ##### How to use this driver #####
ebrus 0:0a673c671a56 20 ============================================================================
ebrus 0:0a673c671a56 21 [..]
ebrus 0:0a673c671a56 22 (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
ebrus 0:0a673c671a56 23 function for I2C1 or I2C2.
ebrus 0:0a673c671a56 24 (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
ebrus 0:0a673c671a56 25 RCC_AHBPeriphClockCmd() function.
ebrus 0:0a673c671a56 26 (#) Peripherals alternate function:
ebrus 0:0a673c671a56 27 (++) Connect the pin to the desired peripherals' Alternate
ebrus 0:0a673c671a56 28 Function (AF) using GPIO_PinAFConfig() function.
ebrus 0:0a673c671a56 29 (++) Configure the desired pin in alternate function by:
ebrus 0:0a673c671a56 30 GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
ebrus 0:0a673c671a56 31 (++) Select the type, OpenDrain and speed via
ebrus 0:0a673c671a56 32 GPIO_PuPd, GPIO_OType and GPIO_Speed members
ebrus 0:0a673c671a56 33 (++) Call GPIO_Init() function.
ebrus 0:0a673c671a56 34 (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
ebrus 0:0a673c671a56 35 using the I2C_Init() function.
ebrus 0:0a673c671a56 36 (#) Optionally you can enable/configure the following parameters without
ebrus 0:0a673c671a56 37 re-initialization (i.e there is no need to call again I2C_Init() function):
ebrus 0:0a673c671a56 38 (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
ebrus 0:0a673c671a56 39 (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
ebrus 0:0a673c671a56 40 (++) Enable the general call using the I2C_GeneralCallCmd() function.
ebrus 0:0a673c671a56 41 (++) Enable the clock stretching using I2C_StretchClockCmd() function.
ebrus 0:0a673c671a56 42 (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
ebrus 0:0a673c671a56 43 (++) For SMBus Mode:
ebrus 0:0a673c671a56 44 (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
ebrus 0:0a673c671a56 45 (#) Enable the NVIC and the corresponding interrupt using the function
ebrus 0:0a673c671a56 46 I2C_ITConfig() if you need to use interrupt mode.
ebrus 0:0a673c671a56 47 (#) When using the DMA mode
ebrus 0:0a673c671a56 48 (++) Configure the DMA using DMA_Init() function.
ebrus 0:0a673c671a56 49 (++) Active the needed channel Request using I2C_DMACmd() function.
ebrus 0:0a673c671a56 50 (#) Enable the I2C using the I2C_Cmd() function.
ebrus 0:0a673c671a56 51 (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
ebrus 0:0a673c671a56 52 transfers.
ebrus 0:0a673c671a56 53 [..]
ebrus 0:0a673c671a56 54 (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
ebrus 0:0a673c671a56 55 must be enabled by setting the driving capability control bit in SYSCFG.
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 @endverbatim
ebrus 0:0a673c671a56 58 ******************************************************************************
ebrus 0:0a673c671a56 59 * @attention
ebrus 0:0a673c671a56 60 *
ebrus 0:0a673c671a56 61 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 62 *
ebrus 0:0a673c671a56 63 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 64 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 65 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 66 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 67 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 68 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 69 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 70 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 71 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 72 * without specific prior written permission.
ebrus 0:0a673c671a56 73 *
ebrus 0:0a673c671a56 74 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 75 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 76 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 77 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 78 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 79 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 80 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 81 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 82 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 84 *
ebrus 0:0a673c671a56 85 ******************************************************************************
ebrus 0:0a673c671a56 86 */
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 89 #include "stm32f30x_i2c.h"
ebrus 0:0a673c671a56 90 #include "stm32f30x_rcc.h"
ebrus 0:0a673c671a56 91
ebrus 0:0a673c671a56 92 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 93 * @{
ebrus 0:0a673c671a56 94 */
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96 /** @defgroup I2C
ebrus 0:0a673c671a56 97 * @brief I2C driver modules
ebrus 0:0a673c671a56 98 * @{
ebrus 0:0a673c671a56 99 */
ebrus 0:0a673c671a56 100
ebrus 0:0a673c671a56 101 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 102 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 103
ebrus 0:0a673c671a56 104 #define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */
ebrus 0:0a673c671a56 105 #define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */
ebrus 0:0a673c671a56 106 #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
ebrus 0:0a673c671a56 107 #define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */
ebrus 0:0a673c671a56 108 #define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 111 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 112 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 113 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 114
ebrus 0:0a673c671a56 115 /** @defgroup I2C_Private_Functions
ebrus 0:0a673c671a56 116 * @{
ebrus 0:0a673c671a56 117 */
ebrus 0:0a673c671a56 118
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120 /** @defgroup I2C_Group1 Initialization and Configuration functions
ebrus 0:0a673c671a56 121 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 122 *
ebrus 0:0a673c671a56 123 @verbatim
ebrus 0:0a673c671a56 124 ===============================================================================
ebrus 0:0a673c671a56 125 ##### Initialization and Configuration functions #####
ebrus 0:0a673c671a56 126 ===============================================================================
ebrus 0:0a673c671a56 127 [..] This section provides a set of functions allowing to initialize the I2C Mode,
ebrus 0:0a673c671a56 128 I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
ebrus 0:0a673c671a56 129
ebrus 0:0a673c671a56 130 [..] The I2C_Init() function follows the I2C configuration procedures (these procedures
ebrus 0:0a673c671a56 131 are available in reference manual).
ebrus 0:0a673c671a56 132
ebrus 0:0a673c671a56 133 [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
ebrus 0:0a673c671a56 134 states machines are reset and communication control bits, as well as status bits come
ebrus 0:0a673c671a56 135 back to their reset value.
ebrus 0:0a673c671a56 136
ebrus 0:0a673c671a56 137 [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
ebrus 0:0a673c671a56 138 HSI and Digital filters must be disabled.
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
ebrus 0:0a673c671a56 141 configured using I2C_OwnAddress2Config() function.
ebrus 0:0a673c671a56 142
ebrus 0:0a673c671a56 143 [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of
ebrus 0:0a673c671a56 144 each byte in slave mode when NBYTES is set to 0x01.
ebrus 0:0a673c671a56 145
ebrus 0:0a673c671a56 146 @endverbatim
ebrus 0:0a673c671a56 147 * @{
ebrus 0:0a673c671a56 148 */
ebrus 0:0a673c671a56 149
ebrus 0:0a673c671a56 150 /**
ebrus 0:0a673c671a56 151 * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
ebrus 0:0a673c671a56 152 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 153 * @retval None
ebrus 0:0a673c671a56 154 */
ebrus 0:0a673c671a56 155 void I2C_DeInit(I2C_TypeDef* I2Cx)
ebrus 0:0a673c671a56 156 {
ebrus 0:0a673c671a56 157 /* Check the parameters */
ebrus 0:0a673c671a56 158 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 159
ebrus 0:0a673c671a56 160 if (I2Cx == I2C1)
ebrus 0:0a673c671a56 161 {
ebrus 0:0a673c671a56 162 /* Enable I2C1 reset state */
ebrus 0:0a673c671a56 163 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
ebrus 0:0a673c671a56 164 /* Release I2C1 from reset state */
ebrus 0:0a673c671a56 165 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
ebrus 0:0a673c671a56 166 }
ebrus 0:0a673c671a56 167 else
ebrus 0:0a673c671a56 168 {
ebrus 0:0a673c671a56 169 /* Enable I2C2 reset state */
ebrus 0:0a673c671a56 170 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
ebrus 0:0a673c671a56 171 /* Release I2C2 from reset state */
ebrus 0:0a673c671a56 172 RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
ebrus 0:0a673c671a56 173 }
ebrus 0:0a673c671a56 174 }
ebrus 0:0a673c671a56 175
ebrus 0:0a673c671a56 176 /**
ebrus 0:0a673c671a56 177 * @brief Initializes the I2Cx peripheral according to the specified
ebrus 0:0a673c671a56 178 * parameters in the I2C_InitStruct.
ebrus 0:0a673c671a56 179 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 180 * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
ebrus 0:0a673c671a56 181 * contains the configuration information for the specified I2C peripheral.
ebrus 0:0a673c671a56 182 * @retval None
ebrus 0:0a673c671a56 183 */
ebrus 0:0a673c671a56 184 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
ebrus 0:0a673c671a56 185 {
ebrus 0:0a673c671a56 186 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 187
ebrus 0:0a673c671a56 188 /* Check the parameters */
ebrus 0:0a673c671a56 189 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 190 assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
ebrus 0:0a673c671a56 191 assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
ebrus 0:0a673c671a56 192 assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
ebrus 0:0a673c671a56 193 assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
ebrus 0:0a673c671a56 194 assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
ebrus 0:0a673c671a56 195 assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
ebrus 0:0a673c671a56 196
ebrus 0:0a673c671a56 197 /* Disable I2Cx Peripheral */
ebrus 0:0a673c671a56 198 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200 /*---------------------------- I2Cx FILTERS Configuration ------------------*/
ebrus 0:0a673c671a56 201 /* Get the I2Cx CR1 value */
ebrus 0:0a673c671a56 202 tmpreg = I2Cx->CR1;
ebrus 0:0a673c671a56 203 /* Clear I2Cx CR1 register */
ebrus 0:0a673c671a56 204 tmpreg &= CR1_CLEAR_MASK;
ebrus 0:0a673c671a56 205 /* Configure I2Cx: analog and digital filter */
ebrus 0:0a673c671a56 206 /* Set ANFOFF bit according to I2C_AnalogFilter value */
ebrus 0:0a673c671a56 207 /* Set DFN bits according to I2C_DigitalFilter value */
ebrus 0:0a673c671a56 208 tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210 /* Write to I2Cx CR1 */
ebrus 0:0a673c671a56 211 I2Cx->CR1 = tmpreg;
ebrus 0:0a673c671a56 212
ebrus 0:0a673c671a56 213 /*---------------------------- I2Cx TIMING Configuration -------------------*/
ebrus 0:0a673c671a56 214 /* Configure I2Cx: Timing */
ebrus 0:0a673c671a56 215 /* Set TIMINGR bits according to I2C_Timing */
ebrus 0:0a673c671a56 216 /* Write to I2Cx TIMING */
ebrus 0:0a673c671a56 217 I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
ebrus 0:0a673c671a56 218
ebrus 0:0a673c671a56 219 /* Enable I2Cx Peripheral */
ebrus 0:0a673c671a56 220 I2Cx->CR1 |= I2C_CR1_PE;
ebrus 0:0a673c671a56 221
ebrus 0:0a673c671a56 222 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
ebrus 0:0a673c671a56 223 /* Clear tmpreg local variable */
ebrus 0:0a673c671a56 224 tmpreg = 0;
ebrus 0:0a673c671a56 225 /* Clear OAR1 register */
ebrus 0:0a673c671a56 226 I2Cx->OAR1 = (uint32_t)tmpreg;
ebrus 0:0a673c671a56 227 /* Clear OAR2 register */
ebrus 0:0a673c671a56 228 I2Cx->OAR2 = (uint32_t)tmpreg;
ebrus 0:0a673c671a56 229 /* Configure I2Cx: Own Address1 and acknowledged address */
ebrus 0:0a673c671a56 230 /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
ebrus 0:0a673c671a56 231 /* Set OA1 bits according to I2C_OwnAddress1 value */
ebrus 0:0a673c671a56 232 tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
ebrus 0:0a673c671a56 233 (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
ebrus 0:0a673c671a56 234 /* Write to I2Cx OAR1 */
ebrus 0:0a673c671a56 235 I2Cx->OAR1 = tmpreg;
ebrus 0:0a673c671a56 236 /* Enable Own Address1 acknowledgement */
ebrus 0:0a673c671a56 237 I2Cx->OAR1 |= I2C_OAR1_OA1EN;
ebrus 0:0a673c671a56 238
ebrus 0:0a673c671a56 239 /*---------------------------- I2Cx MODE Configuration ---------------------*/
ebrus 0:0a673c671a56 240 /* Configure I2Cx: mode */
ebrus 0:0a673c671a56 241 /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
ebrus 0:0a673c671a56 242 tmpreg = I2C_InitStruct->I2C_Mode;
ebrus 0:0a673c671a56 243 /* Write to I2Cx CR1 */
ebrus 0:0a673c671a56 244 I2Cx->CR1 |= tmpreg;
ebrus 0:0a673c671a56 245
ebrus 0:0a673c671a56 246 /*---------------------------- I2Cx ACK Configuration ----------------------*/
ebrus 0:0a673c671a56 247 /* Get the I2Cx CR2 value */
ebrus 0:0a673c671a56 248 tmpreg = I2Cx->CR2;
ebrus 0:0a673c671a56 249 /* Clear I2Cx CR2 register */
ebrus 0:0a673c671a56 250 tmpreg &= CR2_CLEAR_MASK;
ebrus 0:0a673c671a56 251 /* Configure I2Cx: acknowledgement */
ebrus 0:0a673c671a56 252 /* Set NACK bit according to I2C_Ack value */
ebrus 0:0a673c671a56 253 tmpreg |= I2C_InitStruct->I2C_Ack;
ebrus 0:0a673c671a56 254 /* Write to I2Cx CR2 */
ebrus 0:0a673c671a56 255 I2Cx->CR2 = tmpreg;
ebrus 0:0a673c671a56 256 }
ebrus 0:0a673c671a56 257
ebrus 0:0a673c671a56 258 /**
ebrus 0:0a673c671a56 259 * @brief Fills each I2C_InitStruct member with its default value.
ebrus 0:0a673c671a56 260 * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
ebrus 0:0a673c671a56 261 * @retval None
ebrus 0:0a673c671a56 262 */
ebrus 0:0a673c671a56 263 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
ebrus 0:0a673c671a56 264 {
ebrus 0:0a673c671a56 265 /*---------------- Reset I2C init structure parameters values --------------*/
ebrus 0:0a673c671a56 266 /* Initialize the I2C_Timing member */
ebrus 0:0a673c671a56 267 I2C_InitStruct->I2C_Timing = 0;
ebrus 0:0a673c671a56 268 /* Initialize the I2C_AnalogFilter member */
ebrus 0:0a673c671a56 269 I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
ebrus 0:0a673c671a56 270 /* Initialize the I2C_DigitalFilter member */
ebrus 0:0a673c671a56 271 I2C_InitStruct->I2C_DigitalFilter = 0;
ebrus 0:0a673c671a56 272 /* Initialize the I2C_Mode member */
ebrus 0:0a673c671a56 273 I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
ebrus 0:0a673c671a56 274 /* Initialize the I2C_OwnAddress1 member */
ebrus 0:0a673c671a56 275 I2C_InitStruct->I2C_OwnAddress1 = 0;
ebrus 0:0a673c671a56 276 /* Initialize the I2C_Ack member */
ebrus 0:0a673c671a56 277 I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
ebrus 0:0a673c671a56 278 /* Initialize the I2C_AcknowledgedAddress member */
ebrus 0:0a673c671a56 279 I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
ebrus 0:0a673c671a56 280 }
ebrus 0:0a673c671a56 281
ebrus 0:0a673c671a56 282 /**
ebrus 0:0a673c671a56 283 * @brief Enables or disables the specified I2C peripheral.
ebrus 0:0a673c671a56 284 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 285 * @param NewState: new state of the I2Cx peripheral.
ebrus 0:0a673c671a56 286 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 287 * @retval None
ebrus 0:0a673c671a56 288 */
ebrus 0:0a673c671a56 289 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 290 {
ebrus 0:0a673c671a56 291 /* Check the parameters */
ebrus 0:0a673c671a56 292 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 293 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 294 if (NewState != DISABLE)
ebrus 0:0a673c671a56 295 {
ebrus 0:0a673c671a56 296 /* Enable the selected I2C peripheral */
ebrus 0:0a673c671a56 297 I2Cx->CR1 |= I2C_CR1_PE;
ebrus 0:0a673c671a56 298 }
ebrus 0:0a673c671a56 299 else
ebrus 0:0a673c671a56 300 {
ebrus 0:0a673c671a56 301 /* Disable the selected I2C peripheral */
ebrus 0:0a673c671a56 302 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
ebrus 0:0a673c671a56 303 }
ebrus 0:0a673c671a56 304 }
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306
ebrus 0:0a673c671a56 307 /**
ebrus 0:0a673c671a56 308 * @brief Enables or disables the specified I2C software reset.
ebrus 0:0a673c671a56 309 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 310 * @retval None
ebrus 0:0a673c671a56 311 */
ebrus 0:0a673c671a56 312 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
ebrus 0:0a673c671a56 313 {
ebrus 0:0a673c671a56 314 /* Check the parameters */
ebrus 0:0a673c671a56 315 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 316
ebrus 0:0a673c671a56 317 /* Disable peripheral */
ebrus 0:0a673c671a56 318 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
ebrus 0:0a673c671a56 319
ebrus 0:0a673c671a56 320 /* Perform a dummy read to delay the disable of peripheral for minimum
ebrus 0:0a673c671a56 321 3 APB clock cycles to perform the software reset functionality */
ebrus 0:0a673c671a56 322 *(__IO uint32_t *)(uint32_t)I2Cx;
ebrus 0:0a673c671a56 323
ebrus 0:0a673c671a56 324 /* Enable peripheral */
ebrus 0:0a673c671a56 325 I2Cx->CR1 |= I2C_CR1_PE;
ebrus 0:0a673c671a56 326 }
ebrus 0:0a673c671a56 327
ebrus 0:0a673c671a56 328 /**
ebrus 0:0a673c671a56 329 * @brief Enables or disables the specified I2C interrupts.
ebrus 0:0a673c671a56 330 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 331 * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
ebrus 0:0a673c671a56 332 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 333 * @arg I2C_IT_ERRI: Error interrupt mask
ebrus 0:0a673c671a56 334 * @arg I2C_IT_TCI: Transfer Complete interrupt mask
ebrus 0:0a673c671a56 335 * @arg I2C_IT_STOPI: Stop Detection interrupt mask
ebrus 0:0a673c671a56 336 * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
ebrus 0:0a673c671a56 337 * @arg I2C_IT_ADDRI: Address Match interrupt mask
ebrus 0:0a673c671a56 338 * @arg I2C_IT_RXI: RX interrupt mask
ebrus 0:0a673c671a56 339 * @arg I2C_IT_TXI: TX interrupt mask
ebrus 0:0a673c671a56 340 * @param NewState: new state of the specified I2C interrupts.
ebrus 0:0a673c671a56 341 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 342 * @retval None
ebrus 0:0a673c671a56 343 */
ebrus 0:0a673c671a56 344 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
ebrus 0:0a673c671a56 345 {
ebrus 0:0a673c671a56 346 /* Check the parameters */
ebrus 0:0a673c671a56 347 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 348 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 349 assert_param(IS_I2C_CONFIG_IT(I2C_IT));
ebrus 0:0a673c671a56 350
ebrus 0:0a673c671a56 351 if (NewState != DISABLE)
ebrus 0:0a673c671a56 352 {
ebrus 0:0a673c671a56 353 /* Enable the selected I2C interrupts */
ebrus 0:0a673c671a56 354 I2Cx->CR1 |= I2C_IT;
ebrus 0:0a673c671a56 355 }
ebrus 0:0a673c671a56 356 else
ebrus 0:0a673c671a56 357 {
ebrus 0:0a673c671a56 358 /* Disable the selected I2C interrupts */
ebrus 0:0a673c671a56 359 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
ebrus 0:0a673c671a56 360 }
ebrus 0:0a673c671a56 361 }
ebrus 0:0a673c671a56 362
ebrus 0:0a673c671a56 363 /**
ebrus 0:0a673c671a56 364 * @brief Enables or disables the I2C Clock stretching.
ebrus 0:0a673c671a56 365 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 366 * @param NewState: new state of the I2Cx Clock stretching.
ebrus 0:0a673c671a56 367 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 368 * @retval None
ebrus 0:0a673c671a56 369 */
ebrus 0:0a673c671a56 370 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 371 {
ebrus 0:0a673c671a56 372 /* Check the parameters */
ebrus 0:0a673c671a56 373 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 374 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 375
ebrus 0:0a673c671a56 376 if (NewState != DISABLE)
ebrus 0:0a673c671a56 377 {
ebrus 0:0a673c671a56 378 /* Enable clock stretching */
ebrus 0:0a673c671a56 379 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
ebrus 0:0a673c671a56 380 }
ebrus 0:0a673c671a56 381 else
ebrus 0:0a673c671a56 382 {
ebrus 0:0a673c671a56 383 /* Disable clock stretching */
ebrus 0:0a673c671a56 384 I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
ebrus 0:0a673c671a56 385 }
ebrus 0:0a673c671a56 386 }
ebrus 0:0a673c671a56 387
ebrus 0:0a673c671a56 388 /**
ebrus 0:0a673c671a56 389 * @brief Enables or disables I2C wakeup from stop mode.
ebrus 0:0a673c671a56 390 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 391 * @param NewState: new state of the I2Cx stop mode.
ebrus 0:0a673c671a56 392 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 393 * @retval None
ebrus 0:0a673c671a56 394 */
ebrus 0:0a673c671a56 395 void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 396 {
ebrus 0:0a673c671a56 397 /* Check the parameters */
ebrus 0:0a673c671a56 398 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 399 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 400
ebrus 0:0a673c671a56 401 if (NewState != DISABLE)
ebrus 0:0a673c671a56 402 {
ebrus 0:0a673c671a56 403 /* Enable wakeup from stop mode */
ebrus 0:0a673c671a56 404 I2Cx->CR1 |= I2C_CR1_WUPEN;
ebrus 0:0a673c671a56 405 }
ebrus 0:0a673c671a56 406 else
ebrus 0:0a673c671a56 407 {
ebrus 0:0a673c671a56 408 /* Disable wakeup from stop mode */
ebrus 0:0a673c671a56 409 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
ebrus 0:0a673c671a56 410 }
ebrus 0:0a673c671a56 411 }
ebrus 0:0a673c671a56 412
ebrus 0:0a673c671a56 413 /**
ebrus 0:0a673c671a56 414 * @brief Enables or disables the I2C own address 2.
ebrus 0:0a673c671a56 415 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 416 * @param NewState: new state of the I2C own address 2.
ebrus 0:0a673c671a56 417 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 418 * @retval None
ebrus 0:0a673c671a56 419 */
ebrus 0:0a673c671a56 420 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 421 {
ebrus 0:0a673c671a56 422 /* Check the parameters */
ebrus 0:0a673c671a56 423 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 424 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 425
ebrus 0:0a673c671a56 426 if (NewState != DISABLE)
ebrus 0:0a673c671a56 427 {
ebrus 0:0a673c671a56 428 /* Enable own address 2 */
ebrus 0:0a673c671a56 429 I2Cx->OAR2 |= I2C_OAR2_OA2EN;
ebrus 0:0a673c671a56 430 }
ebrus 0:0a673c671a56 431 else
ebrus 0:0a673c671a56 432 {
ebrus 0:0a673c671a56 433 /* Disable own address 2 */
ebrus 0:0a673c671a56 434 I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
ebrus 0:0a673c671a56 435 }
ebrus 0:0a673c671a56 436 }
ebrus 0:0a673c671a56 437
ebrus 0:0a673c671a56 438 /**
ebrus 0:0a673c671a56 439 * @brief Configures the I2C slave own address 2 and mask.
ebrus 0:0a673c671a56 440 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 441 * @param Address: specifies the slave address to be programmed.
ebrus 0:0a673c671a56 442 * @param Mask: specifies own address 2 mask to be programmed.
ebrus 0:0a673c671a56 443 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 444 * @arg I2C_OA2_NoMask: no mask.
ebrus 0:0a673c671a56 445 * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
ebrus 0:0a673c671a56 446 * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
ebrus 0:0a673c671a56 447 * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
ebrus 0:0a673c671a56 448 * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
ebrus 0:0a673c671a56 449 * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
ebrus 0:0a673c671a56 450 * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
ebrus 0:0a673c671a56 451 * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
ebrus 0:0a673c671a56 452 * @retval None
ebrus 0:0a673c671a56 453 */
ebrus 0:0a673c671a56 454 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
ebrus 0:0a673c671a56 455 {
ebrus 0:0a673c671a56 456 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 457
ebrus 0:0a673c671a56 458 /* Check the parameters */
ebrus 0:0a673c671a56 459 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 460 assert_param(IS_I2C_OWN_ADDRESS2(Address));
ebrus 0:0a673c671a56 461 assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
ebrus 0:0a673c671a56 462
ebrus 0:0a673c671a56 463 /* Get the old register value */
ebrus 0:0a673c671a56 464 tmpreg = I2Cx->OAR2;
ebrus 0:0a673c671a56 465
ebrus 0:0a673c671a56 466 /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
ebrus 0:0a673c671a56 467 tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
ebrus 0:0a673c671a56 468
ebrus 0:0a673c671a56 469 /* Set I2Cx SADD */
ebrus 0:0a673c671a56 470 tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
ebrus 0:0a673c671a56 471 (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
ebrus 0:0a673c671a56 472
ebrus 0:0a673c671a56 473 /* Store the new register value */
ebrus 0:0a673c671a56 474 I2Cx->OAR2 = tmpreg;
ebrus 0:0a673c671a56 475 }
ebrus 0:0a673c671a56 476
ebrus 0:0a673c671a56 477 /**
ebrus 0:0a673c671a56 478 * @brief Enables or disables the I2C general call mode.
ebrus 0:0a673c671a56 479 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 480 * @param NewState: new state of the I2C general call mode.
ebrus 0:0a673c671a56 481 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 482 * @retval None
ebrus 0:0a673c671a56 483 */
ebrus 0:0a673c671a56 484 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 485 {
ebrus 0:0a673c671a56 486 /* Check the parameters */
ebrus 0:0a673c671a56 487 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 488 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 489
ebrus 0:0a673c671a56 490 if (NewState != DISABLE)
ebrus 0:0a673c671a56 491 {
ebrus 0:0a673c671a56 492 /* Enable general call mode */
ebrus 0:0a673c671a56 493 I2Cx->CR1 |= I2C_CR1_GCEN;
ebrus 0:0a673c671a56 494 }
ebrus 0:0a673c671a56 495 else
ebrus 0:0a673c671a56 496 {
ebrus 0:0a673c671a56 497 /* Disable general call mode */
ebrus 0:0a673c671a56 498 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
ebrus 0:0a673c671a56 499 }
ebrus 0:0a673c671a56 500 }
ebrus 0:0a673c671a56 501
ebrus 0:0a673c671a56 502 /**
ebrus 0:0a673c671a56 503 * @brief Enables or disables the I2C slave byte control.
ebrus 0:0a673c671a56 504 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 505 * @param NewState: new state of the I2C slave byte control.
ebrus 0:0a673c671a56 506 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 507 * @retval None
ebrus 0:0a673c671a56 508 */
ebrus 0:0a673c671a56 509 void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 510 {
ebrus 0:0a673c671a56 511 /* Check the parameters */
ebrus 0:0a673c671a56 512 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 513 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 514
ebrus 0:0a673c671a56 515 if (NewState != DISABLE)
ebrus 0:0a673c671a56 516 {
ebrus 0:0a673c671a56 517 /* Enable slave byte control */
ebrus 0:0a673c671a56 518 I2Cx->CR1 |= I2C_CR1_SBC;
ebrus 0:0a673c671a56 519 }
ebrus 0:0a673c671a56 520 else
ebrus 0:0a673c671a56 521 {
ebrus 0:0a673c671a56 522 /* Disable slave byte control */
ebrus 0:0a673c671a56 523 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
ebrus 0:0a673c671a56 524 }
ebrus 0:0a673c671a56 525 }
ebrus 0:0a673c671a56 526
ebrus 0:0a673c671a56 527 /**
ebrus 0:0a673c671a56 528 * @brief Configures the slave address to be transmitted after start generation.
ebrus 0:0a673c671a56 529 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 530 * @param Address: specifies the slave address to be programmed.
ebrus 0:0a673c671a56 531 * @note This function should be called before generating start condition.
ebrus 0:0a673c671a56 532 * @retval None
ebrus 0:0a673c671a56 533 */
ebrus 0:0a673c671a56 534 void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
ebrus 0:0a673c671a56 535 {
ebrus 0:0a673c671a56 536 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 537
ebrus 0:0a673c671a56 538 /* Check the parameters */
ebrus 0:0a673c671a56 539 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 540 assert_param(IS_I2C_SLAVE_ADDRESS(Address));
ebrus 0:0a673c671a56 541
ebrus 0:0a673c671a56 542 /* Get the old register value */
ebrus 0:0a673c671a56 543 tmpreg = I2Cx->CR2;
ebrus 0:0a673c671a56 544
ebrus 0:0a673c671a56 545 /* Reset I2Cx SADD bit [9:0] */
ebrus 0:0a673c671a56 546 tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
ebrus 0:0a673c671a56 547
ebrus 0:0a673c671a56 548 /* Set I2Cx SADD */
ebrus 0:0a673c671a56 549 tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
ebrus 0:0a673c671a56 550
ebrus 0:0a673c671a56 551 /* Store the new register value */
ebrus 0:0a673c671a56 552 I2Cx->CR2 = tmpreg;
ebrus 0:0a673c671a56 553 }
ebrus 0:0a673c671a56 554
ebrus 0:0a673c671a56 555 /**
ebrus 0:0a673c671a56 556 * @brief Enables or disables the I2C 10-bit addressing mode for the master.
ebrus 0:0a673c671a56 557 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 558 * @param NewState: new state of the I2C 10-bit addressing mode.
ebrus 0:0a673c671a56 559 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 560 * @note This function should be called before generating start condition.
ebrus 0:0a673c671a56 561 * @retval None
ebrus 0:0a673c671a56 562 */
ebrus 0:0a673c671a56 563 void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 564 {
ebrus 0:0a673c671a56 565 /* Check the parameters */
ebrus 0:0a673c671a56 566 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 567 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 568
ebrus 0:0a673c671a56 569 if (NewState != DISABLE)
ebrus 0:0a673c671a56 570 {
ebrus 0:0a673c671a56 571 /* Enable 10-bit addressing mode */
ebrus 0:0a673c671a56 572 I2Cx->CR2 |= I2C_CR2_ADD10;
ebrus 0:0a673c671a56 573 }
ebrus 0:0a673c671a56 574 else
ebrus 0:0a673c671a56 575 {
ebrus 0:0a673c671a56 576 /* Disable 10-bit addressing mode */
ebrus 0:0a673c671a56 577 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
ebrus 0:0a673c671a56 578 }
ebrus 0:0a673c671a56 579 }
ebrus 0:0a673c671a56 580
ebrus 0:0a673c671a56 581 /**
ebrus 0:0a673c671a56 582 * @}
ebrus 0:0a673c671a56 583 */
ebrus 0:0a673c671a56 584
ebrus 0:0a673c671a56 585
ebrus 0:0a673c671a56 586 /** @defgroup I2C_Group2 Communications handling functions
ebrus 0:0a673c671a56 587 * @brief Communications handling functions
ebrus 0:0a673c671a56 588 *
ebrus 0:0a673c671a56 589 @verbatim
ebrus 0:0a673c671a56 590 ===============================================================================
ebrus 0:0a673c671a56 591 ##### Communications handling functions #####
ebrus 0:0a673c671a56 592 ===============================================================================
ebrus 0:0a673c671a56 593 [..] This section provides a set of functions that handles I2C communication.
ebrus 0:0a673c671a56 594
ebrus 0:0a673c671a56 595 [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
ebrus 0:0a673c671a56 596 mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
ebrus 0:0a673c671a56 597
ebrus 0:0a673c671a56 598 [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
ebrus 0:0a673c671a56 599 this configuration should be done before generating start condition in master
ebrus 0:0a673c671a56 600 mode.
ebrus 0:0a673c671a56 601
ebrus 0:0a673c671a56 602 [..] When switching from master write operation to read operation in 10Bit addressing
ebrus 0:0a673c671a56 603 mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
ebrus 0:0a673c671a56 604 Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
ebrus 0:0a673c671a56 605
ebrus 0:0a673c671a56 606 [..] In master mode, when transferring more than 255 bytes Reload mode should be used
ebrus 0:0a673c671a56 607 to handle communication. In the first phase of transfer, Nbytes should be set to
ebrus 0:0a673c671a56 608 255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
ebrus 0:0a673c671a56 609 function should be called to handle remaining communication.
ebrus 0:0a673c671a56 610
ebrus 0:0a673c671a56 611 [..] In master mode, when software end mode is selected when all data is transferred
ebrus 0:0a673c671a56 612 TC flag is set I2C_TransferHandling() function should be called to generate STOP
ebrus 0:0a673c671a56 613 or generate ReStart.
ebrus 0:0a673c671a56 614
ebrus 0:0a673c671a56 615 @endverbatim
ebrus 0:0a673c671a56 616 * @{
ebrus 0:0a673c671a56 617 */
ebrus 0:0a673c671a56 618
ebrus 0:0a673c671a56 619 /**
ebrus 0:0a673c671a56 620 * @brief Enables or disables the I2C automatic end mode (stop condition is
ebrus 0:0a673c671a56 621 * automatically sent when nbytes data are transferred).
ebrus 0:0a673c671a56 622 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 623 * @param NewState: new state of the I2C automatic end mode.
ebrus 0:0a673c671a56 624 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 625 * @note This function has effect if Reload mode is disabled.
ebrus 0:0a673c671a56 626 * @retval None
ebrus 0:0a673c671a56 627 */
ebrus 0:0a673c671a56 628 void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 629 {
ebrus 0:0a673c671a56 630 /* Check the parameters */
ebrus 0:0a673c671a56 631 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 632 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 633
ebrus 0:0a673c671a56 634 if (NewState != DISABLE)
ebrus 0:0a673c671a56 635 {
ebrus 0:0a673c671a56 636 /* Enable Auto end mode */
ebrus 0:0a673c671a56 637 I2Cx->CR2 |= I2C_CR2_AUTOEND;
ebrus 0:0a673c671a56 638 }
ebrus 0:0a673c671a56 639 else
ebrus 0:0a673c671a56 640 {
ebrus 0:0a673c671a56 641 /* Disable Auto end mode */
ebrus 0:0a673c671a56 642 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
ebrus 0:0a673c671a56 643 }
ebrus 0:0a673c671a56 644 }
ebrus 0:0a673c671a56 645
ebrus 0:0a673c671a56 646 /**
ebrus 0:0a673c671a56 647 * @brief Enables or disables the I2C nbytes reload mode.
ebrus 0:0a673c671a56 648 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 649 * @param NewState: new state of the nbytes reload mode.
ebrus 0:0a673c671a56 650 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 651 * @retval None
ebrus 0:0a673c671a56 652 */
ebrus 0:0a673c671a56 653 void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 654 {
ebrus 0:0a673c671a56 655 /* Check the parameters */
ebrus 0:0a673c671a56 656 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 657 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 658
ebrus 0:0a673c671a56 659 if (NewState != DISABLE)
ebrus 0:0a673c671a56 660 {
ebrus 0:0a673c671a56 661 /* Enable Auto Reload mode */
ebrus 0:0a673c671a56 662 I2Cx->CR2 |= I2C_CR2_RELOAD;
ebrus 0:0a673c671a56 663 }
ebrus 0:0a673c671a56 664 else
ebrus 0:0a673c671a56 665 {
ebrus 0:0a673c671a56 666 /* Disable Auto Reload mode */
ebrus 0:0a673c671a56 667 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
ebrus 0:0a673c671a56 668 }
ebrus 0:0a673c671a56 669 }
ebrus 0:0a673c671a56 670
ebrus 0:0a673c671a56 671 /**
ebrus 0:0a673c671a56 672 * @brief Configures the number of bytes to be transmitted/received.
ebrus 0:0a673c671a56 673 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 674 * @param Number_Bytes: specifies the number of bytes to be programmed.
ebrus 0:0a673c671a56 675 * @retval None
ebrus 0:0a673c671a56 676 */
ebrus 0:0a673c671a56 677 void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
ebrus 0:0a673c671a56 678 {
ebrus 0:0a673c671a56 679 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 680
ebrus 0:0a673c671a56 681 /* Check the parameters */
ebrus 0:0a673c671a56 682 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 683
ebrus 0:0a673c671a56 684 /* Get the old register value */
ebrus 0:0a673c671a56 685 tmpreg = I2Cx->CR2;
ebrus 0:0a673c671a56 686
ebrus 0:0a673c671a56 687 /* Reset I2Cx Nbytes bit [7:0] */
ebrus 0:0a673c671a56 688 tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
ebrus 0:0a673c671a56 689
ebrus 0:0a673c671a56 690 /* Set I2Cx Nbytes */
ebrus 0:0a673c671a56 691 tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
ebrus 0:0a673c671a56 692
ebrus 0:0a673c671a56 693 /* Store the new register value */
ebrus 0:0a673c671a56 694 I2Cx->CR2 = tmpreg;
ebrus 0:0a673c671a56 695 }
ebrus 0:0a673c671a56 696
ebrus 0:0a673c671a56 697 /**
ebrus 0:0a673c671a56 698 * @brief Configures the type of transfer request for the master.
ebrus 0:0a673c671a56 699 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 700 * @param I2C_Direction: specifies the transfer request direction to be programmed.
ebrus 0:0a673c671a56 701 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 702 * @arg I2C_Direction_Transmitter: Master request a write transfer
ebrus 0:0a673c671a56 703 * @arg I2C_Direction_Receiver: Master request a read transfer
ebrus 0:0a673c671a56 704 * @retval None
ebrus 0:0a673c671a56 705 */
ebrus 0:0a673c671a56 706 void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
ebrus 0:0a673c671a56 707 {
ebrus 0:0a673c671a56 708 /* Check the parameters */
ebrus 0:0a673c671a56 709 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 710 assert_param(IS_I2C_DIRECTION(I2C_Direction));
ebrus 0:0a673c671a56 711
ebrus 0:0a673c671a56 712 /* Test on the direction to set/reset the read/write bit */
ebrus 0:0a673c671a56 713 if (I2C_Direction == I2C_Direction_Transmitter)
ebrus 0:0a673c671a56 714 {
ebrus 0:0a673c671a56 715 /* Request a write Transfer */
ebrus 0:0a673c671a56 716 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
ebrus 0:0a673c671a56 717 }
ebrus 0:0a673c671a56 718 else
ebrus 0:0a673c671a56 719 {
ebrus 0:0a673c671a56 720 /* Request a read Transfer */
ebrus 0:0a673c671a56 721 I2Cx->CR2 |= I2C_CR2_RD_WRN;
ebrus 0:0a673c671a56 722 }
ebrus 0:0a673c671a56 723 }
ebrus 0:0a673c671a56 724
ebrus 0:0a673c671a56 725 /**
ebrus 0:0a673c671a56 726 * @brief Generates I2Cx communication START condition.
ebrus 0:0a673c671a56 727 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 728 * @param NewState: new state of the I2C START condition generation.
ebrus 0:0a673c671a56 729 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 730 * @retval None
ebrus 0:0a673c671a56 731 */
ebrus 0:0a673c671a56 732 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 733 {
ebrus 0:0a673c671a56 734 /* Check the parameters */
ebrus 0:0a673c671a56 735 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 736 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 737
ebrus 0:0a673c671a56 738 if (NewState != DISABLE)
ebrus 0:0a673c671a56 739 {
ebrus 0:0a673c671a56 740 /* Generate a START condition */
ebrus 0:0a673c671a56 741 I2Cx->CR2 |= I2C_CR2_START;
ebrus 0:0a673c671a56 742 }
ebrus 0:0a673c671a56 743 else
ebrus 0:0a673c671a56 744 {
ebrus 0:0a673c671a56 745 /* Disable the START condition generation */
ebrus 0:0a673c671a56 746 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
ebrus 0:0a673c671a56 747 }
ebrus 0:0a673c671a56 748 }
ebrus 0:0a673c671a56 749
ebrus 0:0a673c671a56 750 /**
ebrus 0:0a673c671a56 751 * @brief Generates I2Cx communication STOP condition.
ebrus 0:0a673c671a56 752 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 753 * @param NewState: new state of the I2C STOP condition generation.
ebrus 0:0a673c671a56 754 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 755 * @retval None
ebrus 0:0a673c671a56 756 */
ebrus 0:0a673c671a56 757 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 758 {
ebrus 0:0a673c671a56 759 /* Check the parameters */
ebrus 0:0a673c671a56 760 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 761 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 762
ebrus 0:0a673c671a56 763 if (NewState != DISABLE)
ebrus 0:0a673c671a56 764 {
ebrus 0:0a673c671a56 765 /* Generate a STOP condition */
ebrus 0:0a673c671a56 766 I2Cx->CR2 |= I2C_CR2_STOP;
ebrus 0:0a673c671a56 767 }
ebrus 0:0a673c671a56 768 else
ebrus 0:0a673c671a56 769 {
ebrus 0:0a673c671a56 770 /* Disable the STOP condition generation */
ebrus 0:0a673c671a56 771 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
ebrus 0:0a673c671a56 772 }
ebrus 0:0a673c671a56 773 }
ebrus 0:0a673c671a56 774
ebrus 0:0a673c671a56 775 /**
ebrus 0:0a673c671a56 776 * @brief Enables or disables the I2C 10-bit header only mode with read direction.
ebrus 0:0a673c671a56 777 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 778 * @param NewState: new state of the I2C 10-bit header only mode.
ebrus 0:0a673c671a56 779 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 780 * @note This mode can be used only when switching from master transmitter mode
ebrus 0:0a673c671a56 781 * to master receiver mode.
ebrus 0:0a673c671a56 782 * @retval None
ebrus 0:0a673c671a56 783 */
ebrus 0:0a673c671a56 784 void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 785 {
ebrus 0:0a673c671a56 786 /* Check the parameters */
ebrus 0:0a673c671a56 787 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 788 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 789
ebrus 0:0a673c671a56 790 if (NewState != DISABLE)
ebrus 0:0a673c671a56 791 {
ebrus 0:0a673c671a56 792 /* Enable 10-bit header only mode */
ebrus 0:0a673c671a56 793 I2Cx->CR2 |= I2C_CR2_HEAD10R;
ebrus 0:0a673c671a56 794 }
ebrus 0:0a673c671a56 795 else
ebrus 0:0a673c671a56 796 {
ebrus 0:0a673c671a56 797 /* Disable 10-bit header only mode */
ebrus 0:0a673c671a56 798 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
ebrus 0:0a673c671a56 799 }
ebrus 0:0a673c671a56 800 }
ebrus 0:0a673c671a56 801
ebrus 0:0a673c671a56 802 /**
ebrus 0:0a673c671a56 803 * @brief Generates I2C communication Acknowledge.
ebrus 0:0a673c671a56 804 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 805 * @param NewState: new state of the Acknowledge.
ebrus 0:0a673c671a56 806 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 807 * @retval None
ebrus 0:0a673c671a56 808 */
ebrus 0:0a673c671a56 809 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 810 {
ebrus 0:0a673c671a56 811 /* Check the parameters */
ebrus 0:0a673c671a56 812 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 813 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 814
ebrus 0:0a673c671a56 815 if (NewState != DISABLE)
ebrus 0:0a673c671a56 816 {
ebrus 0:0a673c671a56 817 /* Enable ACK generation */
ebrus 0:0a673c671a56 818 I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
ebrus 0:0a673c671a56 819 }
ebrus 0:0a673c671a56 820 else
ebrus 0:0a673c671a56 821 {
ebrus 0:0a673c671a56 822 /* Enable NACK generation */
ebrus 0:0a673c671a56 823 I2Cx->CR2 |= I2C_CR2_NACK;
ebrus 0:0a673c671a56 824 }
ebrus 0:0a673c671a56 825 }
ebrus 0:0a673c671a56 826
ebrus 0:0a673c671a56 827 /**
ebrus 0:0a673c671a56 828 * @brief Returns the I2C slave matched address .
ebrus 0:0a673c671a56 829 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 830 * @retval The value of the slave matched address .
ebrus 0:0a673c671a56 831 */
ebrus 0:0a673c671a56 832 uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
ebrus 0:0a673c671a56 833 {
ebrus 0:0a673c671a56 834 /* Check the parameters */
ebrus 0:0a673c671a56 835 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 836
ebrus 0:0a673c671a56 837 /* Return the slave matched address in the SR1 register */
ebrus 0:0a673c671a56 838 return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
ebrus 0:0a673c671a56 839 }
ebrus 0:0a673c671a56 840
ebrus 0:0a673c671a56 841 /**
ebrus 0:0a673c671a56 842 * @brief Returns the I2C slave received request.
ebrus 0:0a673c671a56 843 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 844 * @retval The value of the received request.
ebrus 0:0a673c671a56 845 */
ebrus 0:0a673c671a56 846 uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
ebrus 0:0a673c671a56 847 {
ebrus 0:0a673c671a56 848 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 849 uint16_t direction = 0;
ebrus 0:0a673c671a56 850
ebrus 0:0a673c671a56 851 /* Check the parameters */
ebrus 0:0a673c671a56 852 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 853
ebrus 0:0a673c671a56 854 /* Return the slave matched address in the SR1 register */
ebrus 0:0a673c671a56 855 tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
ebrus 0:0a673c671a56 856
ebrus 0:0a673c671a56 857 /* If write transfer is requested */
ebrus 0:0a673c671a56 858 if (tmpreg == 0)
ebrus 0:0a673c671a56 859 {
ebrus 0:0a673c671a56 860 /* write transfer is requested */
ebrus 0:0a673c671a56 861 direction = I2C_Direction_Transmitter;
ebrus 0:0a673c671a56 862 }
ebrus 0:0a673c671a56 863 else
ebrus 0:0a673c671a56 864 {
ebrus 0:0a673c671a56 865 /* Read transfer is requested */
ebrus 0:0a673c671a56 866 direction = I2C_Direction_Receiver;
ebrus 0:0a673c671a56 867 }
ebrus 0:0a673c671a56 868 return direction;
ebrus 0:0a673c671a56 869 }
ebrus 0:0a673c671a56 870
ebrus 0:0a673c671a56 871 /**
ebrus 0:0a673c671a56 872 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
ebrus 0:0a673c671a56 873 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 874 * @param Address: specifies the slave address to be programmed.
ebrus 0:0a673c671a56 875 * @param Number_Bytes: specifies the number of bytes to be programmed.
ebrus 0:0a673c671a56 876 * This parameter must be a value between 0 and 255.
ebrus 0:0a673c671a56 877 * @param ReloadEndMode: new state of the I2C START condition generation.
ebrus 0:0a673c671a56 878 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 879 * @arg I2C_Reload_Mode: Enable Reload mode .
ebrus 0:0a673c671a56 880 * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
ebrus 0:0a673c671a56 881 * @arg I2C_SoftEnd_Mode: Enable Software end mode.
ebrus 0:0a673c671a56 882 * @param StartStopMode: new state of the I2C START condition generation.
ebrus 0:0a673c671a56 883 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 884 * @arg I2C_No_StartStop: Don't Generate stop and start condition.
ebrus 0:0a673c671a56 885 * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
ebrus 0:0a673c671a56 886 * @arg I2C_Generate_Start_Read: Generate Restart for read request.
ebrus 0:0a673c671a56 887 * @arg I2C_Generate_Start_Write: Generate Restart for write request.
ebrus 0:0a673c671a56 888 * @retval None
ebrus 0:0a673c671a56 889 */
ebrus 0:0a673c671a56 890 void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
ebrus 0:0a673c671a56 891 {
ebrus 0:0a673c671a56 892 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 893
ebrus 0:0a673c671a56 894 /* Check the parameters */
ebrus 0:0a673c671a56 895 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 896 assert_param(IS_I2C_SLAVE_ADDRESS(Address));
ebrus 0:0a673c671a56 897 assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
ebrus 0:0a673c671a56 898 assert_param(IS_START_STOP_MODE(StartStopMode));
ebrus 0:0a673c671a56 899
ebrus 0:0a673c671a56 900 /* Get the CR2 register value */
ebrus 0:0a673c671a56 901 tmpreg = I2Cx->CR2;
ebrus 0:0a673c671a56 902
ebrus 0:0a673c671a56 903 /* clear tmpreg specific bits */
ebrus 0:0a673c671a56 904 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
ebrus 0:0a673c671a56 905
ebrus 0:0a673c671a56 906 /* update tmpreg */
ebrus 0:0a673c671a56 907 tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
ebrus 0:0a673c671a56 908 (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
ebrus 0:0a673c671a56 909
ebrus 0:0a673c671a56 910 /* update CR2 register */
ebrus 0:0a673c671a56 911 I2Cx->CR2 = tmpreg;
ebrus 0:0a673c671a56 912 }
ebrus 0:0a673c671a56 913
ebrus 0:0a673c671a56 914 /**
ebrus 0:0a673c671a56 915 * @}
ebrus 0:0a673c671a56 916 */
ebrus 0:0a673c671a56 917
ebrus 0:0a673c671a56 918
ebrus 0:0a673c671a56 919 /** @defgroup I2C_Group3 SMBUS management functions
ebrus 0:0a673c671a56 920 * @brief SMBUS management functions
ebrus 0:0a673c671a56 921 *
ebrus 0:0a673c671a56 922 @verbatim
ebrus 0:0a673c671a56 923 ===============================================================================
ebrus 0:0a673c671a56 924 ##### SMBUS management functions #####
ebrus 0:0a673c671a56 925 ===============================================================================
ebrus 0:0a673c671a56 926 [..] This section provides a set of functions that handles SMBus communication
ebrus 0:0a673c671a56 927 and timeouts detection.
ebrus 0:0a673c671a56 928
ebrus 0:0a673c671a56 929 [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
ebrus 0:0a673c671a56 930 function and setting I2C_Mode member of I2C_InitTypeDef() structure to
ebrus 0:0a673c671a56 931 I2C_Mode_SMBusDevice.
ebrus 0:0a673c671a56 932
ebrus 0:0a673c671a56 933 [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
ebrus 0:0a673c671a56 934 function and setting I2C_Mode member of I2C_InitTypeDef() structure to
ebrus 0:0a673c671a56 935 I2C_Mode_SMBusHost.
ebrus 0:0a673c671a56 936
ebrus 0:0a673c671a56 937 [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
ebrus 0:0a673c671a56 938 function.
ebrus 0:0a673c671a56 939
ebrus 0:0a673c671a56 940 [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
ebrus 0:0a673c671a56 941 configured (in accordance to SMBus specification) using I2C_TimeoutBConfig()
ebrus 0:0a673c671a56 942 function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
ebrus 0:0a673c671a56 943 the detection.
ebrus 0:0a673c671a56 944
ebrus 0:0a673c671a56 945 [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
ebrus 0:0a673c671a56 946 function followed by the call of I2C_ClockTimeoutCmd(). When adding to this
ebrus 0:0a673c671a56 947 procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition
ebrus 0:0a673c671a56 948 (both SCL and SDA high) is detected also.
ebrus 0:0a673c671a56 949
ebrus 0:0a673c671a56 950 @endverbatim
ebrus 0:0a673c671a56 951 * @{
ebrus 0:0a673c671a56 952 */
ebrus 0:0a673c671a56 953
ebrus 0:0a673c671a56 954 /**
ebrus 0:0a673c671a56 955 * @brief Enables or disables I2C SMBus alert.
ebrus 0:0a673c671a56 956 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 957 * @param NewState: new state of the I2Cx SMBus alert.
ebrus 0:0a673c671a56 958 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 959 * @retval None
ebrus 0:0a673c671a56 960 */
ebrus 0:0a673c671a56 961 void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 962 {
ebrus 0:0a673c671a56 963 /* Check the parameters */
ebrus 0:0a673c671a56 964 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 965 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 966
ebrus 0:0a673c671a56 967 if (NewState != DISABLE)
ebrus 0:0a673c671a56 968 {
ebrus 0:0a673c671a56 969 /* Enable SMBus alert */
ebrus 0:0a673c671a56 970 I2Cx->CR1 |= I2C_CR1_ALERTEN;
ebrus 0:0a673c671a56 971 }
ebrus 0:0a673c671a56 972 else
ebrus 0:0a673c671a56 973 {
ebrus 0:0a673c671a56 974 /* Disable SMBus alert */
ebrus 0:0a673c671a56 975 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
ebrus 0:0a673c671a56 976 }
ebrus 0:0a673c671a56 977 }
ebrus 0:0a673c671a56 978
ebrus 0:0a673c671a56 979 /**
ebrus 0:0a673c671a56 980 * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).
ebrus 0:0a673c671a56 981 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 982 * @param NewState: new state of the I2Cx clock Timeout.
ebrus 0:0a673c671a56 983 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 984 * @retval None
ebrus 0:0a673c671a56 985 */
ebrus 0:0a673c671a56 986 void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 987 {
ebrus 0:0a673c671a56 988 /* Check the parameters */
ebrus 0:0a673c671a56 989 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 990 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 991
ebrus 0:0a673c671a56 992 if (NewState != DISABLE)
ebrus 0:0a673c671a56 993 {
ebrus 0:0a673c671a56 994 /* Enable Clock Timeout */
ebrus 0:0a673c671a56 995 I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
ebrus 0:0a673c671a56 996 }
ebrus 0:0a673c671a56 997 else
ebrus 0:0a673c671a56 998 {
ebrus 0:0a673c671a56 999 /* Disable Clock Timeout */
ebrus 0:0a673c671a56 1000 I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
ebrus 0:0a673c671a56 1001 }
ebrus 0:0a673c671a56 1002 }
ebrus 0:0a673c671a56 1003
ebrus 0:0a673c671a56 1004 /**
ebrus 0:0a673c671a56 1005 * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
ebrus 0:0a673c671a56 1006 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1007 * @param NewState: new state of the I2Cx Extended clock Timeout.
ebrus 0:0a673c671a56 1008 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1009 * @retval None
ebrus 0:0a673c671a56 1010 */
ebrus 0:0a673c671a56 1011 void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 1012 {
ebrus 0:0a673c671a56 1013 /* Check the parameters */
ebrus 0:0a673c671a56 1014 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1015 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1016
ebrus 0:0a673c671a56 1017 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1018 {
ebrus 0:0a673c671a56 1019 /* Enable Clock Timeout */
ebrus 0:0a673c671a56 1020 I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
ebrus 0:0a673c671a56 1021 }
ebrus 0:0a673c671a56 1022 else
ebrus 0:0a673c671a56 1023 {
ebrus 0:0a673c671a56 1024 /* Disable Clock Timeout */
ebrus 0:0a673c671a56 1025 I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
ebrus 0:0a673c671a56 1026 }
ebrus 0:0a673c671a56 1027 }
ebrus 0:0a673c671a56 1028
ebrus 0:0a673c671a56 1029 /**
ebrus 0:0a673c671a56 1030 * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
ebrus 0:0a673c671a56 1031 * high detection).
ebrus 0:0a673c671a56 1032 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1033 * @param NewState: new state of the I2Cx Idle clock Timeout.
ebrus 0:0a673c671a56 1034 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1035 * @retval None
ebrus 0:0a673c671a56 1036 */
ebrus 0:0a673c671a56 1037 void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 1038 {
ebrus 0:0a673c671a56 1039 /* Check the parameters */
ebrus 0:0a673c671a56 1040 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1041 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1042
ebrus 0:0a673c671a56 1043 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1044 {
ebrus 0:0a673c671a56 1045 /* Enable Clock Timeout */
ebrus 0:0a673c671a56 1046 I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
ebrus 0:0a673c671a56 1047 }
ebrus 0:0a673c671a56 1048 else
ebrus 0:0a673c671a56 1049 {
ebrus 0:0a673c671a56 1050 /* Disable Clock Timeout */
ebrus 0:0a673c671a56 1051 I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
ebrus 0:0a673c671a56 1052 }
ebrus 0:0a673c671a56 1053 }
ebrus 0:0a673c671a56 1054
ebrus 0:0a673c671a56 1055 /**
ebrus 0:0a673c671a56 1056 * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
ebrus 0:0a673c671a56 1057 * idle SCL and SDA high when TIDLE = 1).
ebrus 0:0a673c671a56 1058 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1059 * @param Timeout: specifies the TimeoutA to be programmed.
ebrus 0:0a673c671a56 1060 * @retval None
ebrus 0:0a673c671a56 1061 */
ebrus 0:0a673c671a56 1062 void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
ebrus 0:0a673c671a56 1063 {
ebrus 0:0a673c671a56 1064 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 1065
ebrus 0:0a673c671a56 1066 /* Check the parameters */
ebrus 0:0a673c671a56 1067 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1068 assert_param(IS_I2C_TIMEOUT(Timeout));
ebrus 0:0a673c671a56 1069
ebrus 0:0a673c671a56 1070 /* Get the old register value */
ebrus 0:0a673c671a56 1071 tmpreg = I2Cx->TIMEOUTR;
ebrus 0:0a673c671a56 1072
ebrus 0:0a673c671a56 1073 /* Reset I2Cx TIMEOUTA bit [11:0] */
ebrus 0:0a673c671a56 1074 tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
ebrus 0:0a673c671a56 1075
ebrus 0:0a673c671a56 1076 /* Set I2Cx TIMEOUTA */
ebrus 0:0a673c671a56 1077 tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
ebrus 0:0a673c671a56 1078
ebrus 0:0a673c671a56 1079 /* Store the new register value */
ebrus 0:0a673c671a56 1080 I2Cx->TIMEOUTR = tmpreg;
ebrus 0:0a673c671a56 1081 }
ebrus 0:0a673c671a56 1082
ebrus 0:0a673c671a56 1083 /**
ebrus 0:0a673c671a56 1084 * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).
ebrus 0:0a673c671a56 1085 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1086 * @param Timeout: specifies the TimeoutB to be programmed.
ebrus 0:0a673c671a56 1087 * @retval None
ebrus 0:0a673c671a56 1088 */
ebrus 0:0a673c671a56 1089 void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
ebrus 0:0a673c671a56 1090 {
ebrus 0:0a673c671a56 1091 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 1092
ebrus 0:0a673c671a56 1093 /* Check the parameters */
ebrus 0:0a673c671a56 1094 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1095 assert_param(IS_I2C_TIMEOUT(Timeout));
ebrus 0:0a673c671a56 1096
ebrus 0:0a673c671a56 1097 /* Get the old register value */
ebrus 0:0a673c671a56 1098 tmpreg = I2Cx->TIMEOUTR;
ebrus 0:0a673c671a56 1099
ebrus 0:0a673c671a56 1100 /* Reset I2Cx TIMEOUTB bit [11:0] */
ebrus 0:0a673c671a56 1101 tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
ebrus 0:0a673c671a56 1102
ebrus 0:0a673c671a56 1103 /* Set I2Cx TIMEOUTB */
ebrus 0:0a673c671a56 1104 tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
ebrus 0:0a673c671a56 1105
ebrus 0:0a673c671a56 1106 /* Store the new register value */
ebrus 0:0a673c671a56 1107 I2Cx->TIMEOUTR = tmpreg;
ebrus 0:0a673c671a56 1108 }
ebrus 0:0a673c671a56 1109
ebrus 0:0a673c671a56 1110 /**
ebrus 0:0a673c671a56 1111 * @brief Enables or disables I2C PEC calculation.
ebrus 0:0a673c671a56 1112 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1113 * @param NewState: new state of the I2Cx PEC calculation.
ebrus 0:0a673c671a56 1114 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1115 * @retval None
ebrus 0:0a673c671a56 1116 */
ebrus 0:0a673c671a56 1117 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 1118 {
ebrus 0:0a673c671a56 1119 /* Check the parameters */
ebrus 0:0a673c671a56 1120 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1121 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1122
ebrus 0:0a673c671a56 1123 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1124 {
ebrus 0:0a673c671a56 1125 /* Enable PEC calculation */
ebrus 0:0a673c671a56 1126 I2Cx->CR1 |= I2C_CR1_PECEN;
ebrus 0:0a673c671a56 1127 }
ebrus 0:0a673c671a56 1128 else
ebrus 0:0a673c671a56 1129 {
ebrus 0:0a673c671a56 1130 /* Disable PEC calculation */
ebrus 0:0a673c671a56 1131 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
ebrus 0:0a673c671a56 1132 }
ebrus 0:0a673c671a56 1133 }
ebrus 0:0a673c671a56 1134
ebrus 0:0a673c671a56 1135 /**
ebrus 0:0a673c671a56 1136 * @brief Enables or disables I2C PEC transmission/reception request.
ebrus 0:0a673c671a56 1137 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1138 * @param NewState: new state of the I2Cx PEC request.
ebrus 0:0a673c671a56 1139 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1140 * @retval None
ebrus 0:0a673c671a56 1141 */
ebrus 0:0a673c671a56 1142 void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
ebrus 0:0a673c671a56 1143 {
ebrus 0:0a673c671a56 1144 /* Check the parameters */
ebrus 0:0a673c671a56 1145 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1146 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1147
ebrus 0:0a673c671a56 1148 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1149 {
ebrus 0:0a673c671a56 1150 /* Enable PEC transmission/reception request */
ebrus 0:0a673c671a56 1151 I2Cx->CR1 |= I2C_CR2_PECBYTE;
ebrus 0:0a673c671a56 1152 }
ebrus 0:0a673c671a56 1153 else
ebrus 0:0a673c671a56 1154 {
ebrus 0:0a673c671a56 1155 /* Disable PEC transmission/reception request */
ebrus 0:0a673c671a56 1156 I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
ebrus 0:0a673c671a56 1157 }
ebrus 0:0a673c671a56 1158 }
ebrus 0:0a673c671a56 1159
ebrus 0:0a673c671a56 1160 /**
ebrus 0:0a673c671a56 1161 * @brief Returns the I2C PEC.
ebrus 0:0a673c671a56 1162 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1163 * @retval The value of the PEC .
ebrus 0:0a673c671a56 1164 */
ebrus 0:0a673c671a56 1165 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
ebrus 0:0a673c671a56 1166 {
ebrus 0:0a673c671a56 1167 /* Check the parameters */
ebrus 0:0a673c671a56 1168 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1169
ebrus 0:0a673c671a56 1170 /* Return the slave matched address in the SR1 register */
ebrus 0:0a673c671a56 1171 return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
ebrus 0:0a673c671a56 1172 }
ebrus 0:0a673c671a56 1173
ebrus 0:0a673c671a56 1174 /**
ebrus 0:0a673c671a56 1175 * @}
ebrus 0:0a673c671a56 1176 */
ebrus 0:0a673c671a56 1177
ebrus 0:0a673c671a56 1178
ebrus 0:0a673c671a56 1179 /** @defgroup I2C_Group4 I2C registers management functions
ebrus 0:0a673c671a56 1180 * @brief I2C registers management functions
ebrus 0:0a673c671a56 1181 *
ebrus 0:0a673c671a56 1182 @verbatim
ebrus 0:0a673c671a56 1183 ===============================================================================
ebrus 0:0a673c671a56 1184 ##### I2C registers management functions #####
ebrus 0:0a673c671a56 1185 ===============================================================================
ebrus 0:0a673c671a56 1186 [..] This section provides a functions that allow user the management of
ebrus 0:0a673c671a56 1187 I2C registers.
ebrus 0:0a673c671a56 1188
ebrus 0:0a673c671a56 1189 @endverbatim
ebrus 0:0a673c671a56 1190 * @{
ebrus 0:0a673c671a56 1191 */
ebrus 0:0a673c671a56 1192
ebrus 0:0a673c671a56 1193 /**
ebrus 0:0a673c671a56 1194 * @brief Reads the specified I2C register and returns its value.
ebrus 0:0a673c671a56 1195 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1196 * @param I2C_Register: specifies the register to read.
ebrus 0:0a673c671a56 1197 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1198 * @arg I2C_Register_CR1: CR1 register.
ebrus 0:0a673c671a56 1199 * @arg I2C_Register_CR2: CR2 register.
ebrus 0:0a673c671a56 1200 * @arg I2C_Register_OAR1: OAR1 register.
ebrus 0:0a673c671a56 1201 * @arg I2C_Register_OAR2: OAR2 register.
ebrus 0:0a673c671a56 1202 * @arg I2C_Register_TIMINGR: TIMING register.
ebrus 0:0a673c671a56 1203 * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
ebrus 0:0a673c671a56 1204 * @arg I2C_Register_ISR: ISR register.
ebrus 0:0a673c671a56 1205 * @arg I2C_Register_ICR: ICR register.
ebrus 0:0a673c671a56 1206 * @arg I2C_Register_PECR: PECR register.
ebrus 0:0a673c671a56 1207 * @arg I2C_Register_RXDR: RXDR register.
ebrus 0:0a673c671a56 1208 * @arg I2C_Register_TXDR: TXDR register.
ebrus 0:0a673c671a56 1209 * @retval The value of the read register.
ebrus 0:0a673c671a56 1210 */
ebrus 0:0a673c671a56 1211 uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
ebrus 0:0a673c671a56 1212 {
ebrus 0:0a673c671a56 1213 __IO uint32_t tmp = 0;
ebrus 0:0a673c671a56 1214
ebrus 0:0a673c671a56 1215 /* Check the parameters */
ebrus 0:0a673c671a56 1216 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1217 assert_param(IS_I2C_REGISTER(I2C_Register));
ebrus 0:0a673c671a56 1218
ebrus 0:0a673c671a56 1219 tmp = (uint32_t)I2Cx;
ebrus 0:0a673c671a56 1220 tmp += I2C_Register;
ebrus 0:0a673c671a56 1221
ebrus 0:0a673c671a56 1222 /* Return the selected register value */
ebrus 0:0a673c671a56 1223 return (*(__IO uint32_t *) tmp);
ebrus 0:0a673c671a56 1224 }
ebrus 0:0a673c671a56 1225
ebrus 0:0a673c671a56 1226 /**
ebrus 0:0a673c671a56 1227 * @}
ebrus 0:0a673c671a56 1228 */
ebrus 0:0a673c671a56 1229
ebrus 0:0a673c671a56 1230 /** @defgroup I2C_Group5 Data transfers management functions
ebrus 0:0a673c671a56 1231 * @brief Data transfers management functions
ebrus 0:0a673c671a56 1232 *
ebrus 0:0a673c671a56 1233 @verbatim
ebrus 0:0a673c671a56 1234 ===============================================================================
ebrus 0:0a673c671a56 1235 ##### Data transfers management functions #####
ebrus 0:0a673c671a56 1236 ===============================================================================
ebrus 0:0a673c671a56 1237 [..] This subsection provides a set of functions allowing to manage
ebrus 0:0a673c671a56 1238 the I2C data transfers.
ebrus 0:0a673c671a56 1239
ebrus 0:0a673c671a56 1240 [..] The read access of the I2C_RXDR register can be done using
ebrus 0:0a673c671a56 1241 the I2C_ReceiveData() function and returns the received value.
ebrus 0:0a673c671a56 1242 Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
ebrus 0:0a673c671a56 1243 function and stores the written data into TXDR.
ebrus 0:0a673c671a56 1244 @endverbatim
ebrus 0:0a673c671a56 1245 * @{
ebrus 0:0a673c671a56 1246 */
ebrus 0:0a673c671a56 1247
ebrus 0:0a673c671a56 1248 /**
ebrus 0:0a673c671a56 1249 * @brief Sends a data byte through the I2Cx peripheral.
ebrus 0:0a673c671a56 1250 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1251 * @param Data: Byte to be transmitted..
ebrus 0:0a673c671a56 1252 * @retval None
ebrus 0:0a673c671a56 1253 */
ebrus 0:0a673c671a56 1254 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
ebrus 0:0a673c671a56 1255 {
ebrus 0:0a673c671a56 1256 /* Check the parameters */
ebrus 0:0a673c671a56 1257 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1258
ebrus 0:0a673c671a56 1259 /* Write in the DR register the data to be sent */
ebrus 0:0a673c671a56 1260 I2Cx->TXDR = (uint8_t)Data;
ebrus 0:0a673c671a56 1261 }
ebrus 0:0a673c671a56 1262
ebrus 0:0a673c671a56 1263 /**
ebrus 0:0a673c671a56 1264 * @brief Returns the most recent received data by the I2Cx peripheral.
ebrus 0:0a673c671a56 1265 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1266 * @retval The value of the received data.
ebrus 0:0a673c671a56 1267 */
ebrus 0:0a673c671a56 1268 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
ebrus 0:0a673c671a56 1269 {
ebrus 0:0a673c671a56 1270 /* Check the parameters */
ebrus 0:0a673c671a56 1271 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1272
ebrus 0:0a673c671a56 1273 /* Return the data in the DR register */
ebrus 0:0a673c671a56 1274 return (uint8_t)I2Cx->RXDR;
ebrus 0:0a673c671a56 1275 }
ebrus 0:0a673c671a56 1276
ebrus 0:0a673c671a56 1277 /**
ebrus 0:0a673c671a56 1278 * @}
ebrus 0:0a673c671a56 1279 */
ebrus 0:0a673c671a56 1280
ebrus 0:0a673c671a56 1281
ebrus 0:0a673c671a56 1282 /** @defgroup I2C_Group6 DMA transfers management functions
ebrus 0:0a673c671a56 1283 * @brief DMA transfers management functions
ebrus 0:0a673c671a56 1284 *
ebrus 0:0a673c671a56 1285 @verbatim
ebrus 0:0a673c671a56 1286 ===============================================================================
ebrus 0:0a673c671a56 1287 ##### DMA transfers management functions #####
ebrus 0:0a673c671a56 1288 ===============================================================================
ebrus 0:0a673c671a56 1289 [..] This section provides two functions that can be used only in DMA mode.
ebrus 0:0a673c671a56 1290 [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel
ebrus 0:0a673c671a56 1291 requests:
ebrus 0:0a673c671a56 1292 (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
ebrus 0:0a673c671a56 1293 (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
ebrus 0:0a673c671a56 1294 [..] In this Mode it is advised to use the following function:
ebrus 0:0a673c671a56 1295 (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
ebrus 0:0a673c671a56 1296 @endverbatim
ebrus 0:0a673c671a56 1297 * @{
ebrus 0:0a673c671a56 1298 */
ebrus 0:0a673c671a56 1299
ebrus 0:0a673c671a56 1300 /**
ebrus 0:0a673c671a56 1301 * @brief Enables or disables the I2C DMA interface.
ebrus 0:0a673c671a56 1302 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1303 * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
ebrus 0:0a673c671a56 1304 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 1305 * @arg I2C_DMAReq_Tx: Tx DMA transfer request
ebrus 0:0a673c671a56 1306 * @arg I2C_DMAReq_Rx: Rx DMA transfer request
ebrus 0:0a673c671a56 1307 * @param NewState: new state of the selected I2C DMA transfer request.
ebrus 0:0a673c671a56 1308 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 1309 * @retval None
ebrus 0:0a673c671a56 1310 */
ebrus 0:0a673c671a56 1311 void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
ebrus 0:0a673c671a56 1312 {
ebrus 0:0a673c671a56 1313 /* Check the parameters */
ebrus 0:0a673c671a56 1314 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1315 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 1316 assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
ebrus 0:0a673c671a56 1317
ebrus 0:0a673c671a56 1318 if (NewState != DISABLE)
ebrus 0:0a673c671a56 1319 {
ebrus 0:0a673c671a56 1320 /* Enable the selected I2C DMA requests */
ebrus 0:0a673c671a56 1321 I2Cx->CR1 |= I2C_DMAReq;
ebrus 0:0a673c671a56 1322 }
ebrus 0:0a673c671a56 1323 else
ebrus 0:0a673c671a56 1324 {
ebrus 0:0a673c671a56 1325 /* Disable the selected I2C DMA requests */
ebrus 0:0a673c671a56 1326 I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
ebrus 0:0a673c671a56 1327 }
ebrus 0:0a673c671a56 1328 }
ebrus 0:0a673c671a56 1329 /**
ebrus 0:0a673c671a56 1330 * @}
ebrus 0:0a673c671a56 1331 */
ebrus 0:0a673c671a56 1332
ebrus 0:0a673c671a56 1333
ebrus 0:0a673c671a56 1334 /** @defgroup I2C_Group7 Interrupts and flags management functions
ebrus 0:0a673c671a56 1335 * @brief Interrupts and flags management functions
ebrus 0:0a673c671a56 1336 *
ebrus 0:0a673c671a56 1337 @verbatim
ebrus 0:0a673c671a56 1338 ===============================================================================
ebrus 0:0a673c671a56 1339 ##### Interrupts and flags management functions #####
ebrus 0:0a673c671a56 1340 ===============================================================================
ebrus 0:0a673c671a56 1341 [..] This section provides functions allowing to configure the I2C Interrupts
ebrus 0:0a673c671a56 1342 sources and check or clear the flags or pending bits status.
ebrus 0:0a673c671a56 1343 The user should identify which mode will be used in his application to manage
ebrus 0:0a673c671a56 1344 the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6) .
ebrus 0:0a673c671a56 1345
ebrus 0:0a673c671a56 1346 *** Polling Mode ***
ebrus 0:0a673c671a56 1347 ====================
ebrus 0:0a673c671a56 1348 [..] In Polling Mode, the I2C communication can be managed by 15 flags:
ebrus 0:0a673c671a56 1349 (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
ebrus 0:0a673c671a56 1350 (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
ebrus 0:0a673c671a56 1351 (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
ebrus 0:0a673c671a56 1352 (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
ebrus 0:0a673c671a56 1353 (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
ebrus 0:0a673c671a56 1354 (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
ebrus 0:0a673c671a56 1355 (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
ebrus 0:0a673c671a56 1356 (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
ebrus 0:0a673c671a56 1357 (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
ebrus 0:0a673c671a56 1358 (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
ebrus 0:0a673c671a56 1359 (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
ebrus 0:0a673c671a56 1360 (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
ebrus 0:0a673c671a56 1361 (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
ebrus 0:0a673c671a56 1362 (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
ebrus 0:0a673c671a56 1363 (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
ebrus 0:0a673c671a56 1364
ebrus 0:0a673c671a56 1365 [..] In this Mode it is advised to use the following functions:
ebrus 0:0a673c671a56 1366 (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ebrus 0:0a673c671a56 1367 (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
ebrus 0:0a673c671a56 1368
ebrus 0:0a673c671a56 1369 [..]
ebrus 0:0a673c671a56 1370 (@)Do not use the BUSY flag to handle each data transmission or reception.It is
ebrus 0:0a673c671a56 1371 better to use the TXIS and RXNE flags instead.
ebrus 0:0a673c671a56 1372
ebrus 0:0a673c671a56 1373 *** Interrupt Mode ***
ebrus 0:0a673c671a56 1374 ======================
ebrus 0:0a673c671a56 1375 [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
ebrus 0:0a673c671a56 1376 and 15 pending bits:
ebrus 0:0a673c671a56 1377 [..] Interrupt Source:
ebrus 0:0a673c671a56 1378 (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
ebrus 0:0a673c671a56 1379 (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
ebrus 0:0a673c671a56 1380 (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
ebrus 0:0a673c671a56 1381 (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
ebrus 0:0a673c671a56 1382 (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
ebrus 0:0a673c671a56 1383 (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
ebrus 0:0a673c671a56 1384 (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
ebrus 0:0a673c671a56 1385
ebrus 0:0a673c671a56 1386 [..] Pending Bits:
ebrus 0:0a673c671a56 1387 (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
ebrus 0:0a673c671a56 1388 (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
ebrus 0:0a673c671a56 1389 (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
ebrus 0:0a673c671a56 1390 (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
ebrus 0:0a673c671a56 1391 (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
ebrus 0:0a673c671a56 1392 (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
ebrus 0:0a673c671a56 1393 (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
ebrus 0:0a673c671a56 1394 (#) I2C_IT_BERR: to indicate the status of Bus error flag.
ebrus 0:0a673c671a56 1395 (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
ebrus 0:0a673c671a56 1396 (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
ebrus 0:0a673c671a56 1397 (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
ebrus 0:0a673c671a56 1398 (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
ebrus 0:0a673c671a56 1399 (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
ebrus 0:0a673c671a56 1400
ebrus 0:0a673c671a56 1401 [..] In this Mode it is advised to use the following functions:
ebrus 0:0a673c671a56 1402 (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
ebrus 0:0a673c671a56 1403 (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
ebrus 0:0a673c671a56 1404
ebrus 0:0a673c671a56 1405 @endverbatim
ebrus 0:0a673c671a56 1406 * @{
ebrus 0:0a673c671a56 1407 */
ebrus 0:0a673c671a56 1408
ebrus 0:0a673c671a56 1409 /**
ebrus 0:0a673c671a56 1410 * @brief Checks whether the specified I2C flag is set or not.
ebrus 0:0a673c671a56 1411 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1412 * @param I2C_FLAG: specifies the flag to check.
ebrus 0:0a673c671a56 1413 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1414 * @arg I2C_FLAG_TXE: Transmit data register empty
ebrus 0:0a673c671a56 1415 * @arg I2C_FLAG_TXIS: Transmit interrupt status
ebrus 0:0a673c671a56 1416 * @arg I2C_FLAG_RXNE: Receive data register not empty
ebrus 0:0a673c671a56 1417 * @arg I2C_FLAG_ADDR: Address matched (slave mode)
ebrus 0:0a673c671a56 1418 * @arg I2C_FLAG_NACKF: NACK received flag
ebrus 0:0a673c671a56 1419 * @arg I2C_FLAG_STOPF: STOP detection flag
ebrus 0:0a673c671a56 1420 * @arg I2C_FLAG_TC: Transfer complete (master mode)
ebrus 0:0a673c671a56 1421 * @arg I2C_FLAG_TCR: Transfer complete reload
ebrus 0:0a673c671a56 1422 * @arg I2C_FLAG_BERR: Bus error
ebrus 0:0a673c671a56 1423 * @arg I2C_FLAG_ARLO: Arbitration lost
ebrus 0:0a673c671a56 1424 * @arg I2C_FLAG_OVR: Overrun/Underrun
ebrus 0:0a673c671a56 1425 * @arg I2C_FLAG_PECERR: PEC error in reception
ebrus 0:0a673c671a56 1426 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
ebrus 0:0a673c671a56 1427 * @arg I2C_FLAG_ALERT: SMBus Alert
ebrus 0:0a673c671a56 1428 * @arg I2C_FLAG_BUSY: Bus busy
ebrus 0:0a673c671a56 1429 * @retval The new state of I2C_FLAG (SET or RESET).
ebrus 0:0a673c671a56 1430 */
ebrus 0:0a673c671a56 1431 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
ebrus 0:0a673c671a56 1432 {
ebrus 0:0a673c671a56 1433 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 1434 FlagStatus bitstatus = RESET;
ebrus 0:0a673c671a56 1435
ebrus 0:0a673c671a56 1436 /* Check the parameters */
ebrus 0:0a673c671a56 1437 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1438 assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
ebrus 0:0a673c671a56 1439
ebrus 0:0a673c671a56 1440 /* Get the ISR register value */
ebrus 0:0a673c671a56 1441 tmpreg = I2Cx->ISR;
ebrus 0:0a673c671a56 1442
ebrus 0:0a673c671a56 1443 /* Get flag status */
ebrus 0:0a673c671a56 1444 tmpreg &= I2C_FLAG;
ebrus 0:0a673c671a56 1445
ebrus 0:0a673c671a56 1446 if(tmpreg != 0)
ebrus 0:0a673c671a56 1447 {
ebrus 0:0a673c671a56 1448 /* I2C_FLAG is set */
ebrus 0:0a673c671a56 1449 bitstatus = SET;
ebrus 0:0a673c671a56 1450 }
ebrus 0:0a673c671a56 1451 else
ebrus 0:0a673c671a56 1452 {
ebrus 0:0a673c671a56 1453 /* I2C_FLAG is reset */
ebrus 0:0a673c671a56 1454 bitstatus = RESET;
ebrus 0:0a673c671a56 1455 }
ebrus 0:0a673c671a56 1456 return bitstatus;
ebrus 0:0a673c671a56 1457 }
ebrus 0:0a673c671a56 1458
ebrus 0:0a673c671a56 1459 /**
ebrus 0:0a673c671a56 1460 * @brief Clears the I2Cx's pending flags.
ebrus 0:0a673c671a56 1461 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1462 * @param I2C_FLAG: specifies the flag to clear.
ebrus 0:0a673c671a56 1463 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 1464 * @arg I2C_FLAG_ADDR: Address matched (slave mode)
ebrus 0:0a673c671a56 1465 * @arg I2C_FLAG_NACKF: NACK received flag
ebrus 0:0a673c671a56 1466 * @arg I2C_FLAG_STOPF: STOP detection flag
ebrus 0:0a673c671a56 1467 * @arg I2C_FLAG_BERR: Bus error
ebrus 0:0a673c671a56 1468 * @arg I2C_FLAG_ARLO: Arbitration lost
ebrus 0:0a673c671a56 1469 * @arg I2C_FLAG_OVR: Overrun/Underrun
ebrus 0:0a673c671a56 1470 * @arg I2C_FLAG_PECERR: PEC error in reception
ebrus 0:0a673c671a56 1471 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
ebrus 0:0a673c671a56 1472 * @arg I2C_FLAG_ALERT: SMBus Alert
ebrus 0:0a673c671a56 1473 * @retval The new state of I2C_FLAG (SET or RESET).
ebrus 0:0a673c671a56 1474 */
ebrus 0:0a673c671a56 1475 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
ebrus 0:0a673c671a56 1476 {
ebrus 0:0a673c671a56 1477 /* Check the parameters */
ebrus 0:0a673c671a56 1478 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1479 assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
ebrus 0:0a673c671a56 1480
ebrus 0:0a673c671a56 1481 /* Clear the selected flag */
ebrus 0:0a673c671a56 1482 I2Cx->ICR = I2C_FLAG;
ebrus 0:0a673c671a56 1483 }
ebrus 0:0a673c671a56 1484
ebrus 0:0a673c671a56 1485 /**
ebrus 0:0a673c671a56 1486 * @brief Checks whether the specified I2C interrupt has occurred or not.
ebrus 0:0a673c671a56 1487 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1488 * @param I2C_IT: specifies the interrupt source to check.
ebrus 0:0a673c671a56 1489 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 1490 * @arg I2C_IT_TXIS: Transmit interrupt status
ebrus 0:0a673c671a56 1491 * @arg I2C_IT_RXNE: Receive data register not empty
ebrus 0:0a673c671a56 1492 * @arg I2C_IT_ADDR: Address matched (slave mode)
ebrus 0:0a673c671a56 1493 * @arg I2C_IT_NACKF: NACK received flag
ebrus 0:0a673c671a56 1494 * @arg I2C_IT_STOPF: STOP detection flag
ebrus 0:0a673c671a56 1495 * @arg I2C_IT_TC: Transfer complete (master mode)
ebrus 0:0a673c671a56 1496 * @arg I2C_IT_TCR: Transfer complete reload
ebrus 0:0a673c671a56 1497 * @arg I2C_IT_BERR: Bus error
ebrus 0:0a673c671a56 1498 * @arg I2C_IT_ARLO: Arbitration lost
ebrus 0:0a673c671a56 1499 * @arg I2C_IT_OVR: Overrun/Underrun
ebrus 0:0a673c671a56 1500 * @arg I2C_IT_PECERR: PEC error in reception
ebrus 0:0a673c671a56 1501 * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
ebrus 0:0a673c671a56 1502 * @arg I2C_IT_ALERT: SMBus Alert
ebrus 0:0a673c671a56 1503 * @retval The new state of I2C_IT (SET or RESET).
ebrus 0:0a673c671a56 1504 */
ebrus 0:0a673c671a56 1505 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
ebrus 0:0a673c671a56 1506 {
ebrus 0:0a673c671a56 1507 uint32_t tmpreg = 0;
ebrus 0:0a673c671a56 1508 ITStatus bitstatus = RESET;
ebrus 0:0a673c671a56 1509 uint32_t enablestatus = 0;
ebrus 0:0a673c671a56 1510
ebrus 0:0a673c671a56 1511 /* Check the parameters */
ebrus 0:0a673c671a56 1512 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1513 assert_param(IS_I2C_GET_IT(I2C_IT));
ebrus 0:0a673c671a56 1514
ebrus 0:0a673c671a56 1515 /* Check if the interrupt source is enabled or not */
ebrus 0:0a673c671a56 1516 /* If Error interrupt */
ebrus 0:0a673c671a56 1517 if((uint32_t)(I2C_IT & ERROR_IT_MASK))
ebrus 0:0a673c671a56 1518 {
ebrus 0:0a673c671a56 1519 enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
ebrus 0:0a673c671a56 1520 }
ebrus 0:0a673c671a56 1521 /* If TC interrupt */
ebrus 0:0a673c671a56 1522 else if((uint32_t)(I2C_IT & TC_IT_MASK))
ebrus 0:0a673c671a56 1523 {
ebrus 0:0a673c671a56 1524 enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
ebrus 0:0a673c671a56 1525 }
ebrus 0:0a673c671a56 1526 else
ebrus 0:0a673c671a56 1527 {
ebrus 0:0a673c671a56 1528 enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
ebrus 0:0a673c671a56 1529 }
ebrus 0:0a673c671a56 1530
ebrus 0:0a673c671a56 1531 /* Get the ISR register value */
ebrus 0:0a673c671a56 1532 tmpreg = I2Cx->ISR;
ebrus 0:0a673c671a56 1533
ebrus 0:0a673c671a56 1534 /* Get flag status */
ebrus 0:0a673c671a56 1535 tmpreg &= I2C_IT;
ebrus 0:0a673c671a56 1536
ebrus 0:0a673c671a56 1537 /* Check the status of the specified I2C flag */
ebrus 0:0a673c671a56 1538 if((tmpreg != RESET) && enablestatus)
ebrus 0:0a673c671a56 1539 {
ebrus 0:0a673c671a56 1540 /* I2C_IT is set */
ebrus 0:0a673c671a56 1541 bitstatus = SET;
ebrus 0:0a673c671a56 1542 }
ebrus 0:0a673c671a56 1543 else
ebrus 0:0a673c671a56 1544 {
ebrus 0:0a673c671a56 1545 /* I2C_IT is reset */
ebrus 0:0a673c671a56 1546 bitstatus = RESET;
ebrus 0:0a673c671a56 1547 }
ebrus 0:0a673c671a56 1548
ebrus 0:0a673c671a56 1549 /* Return the I2C_IT status */
ebrus 0:0a673c671a56 1550 return bitstatus;
ebrus 0:0a673c671a56 1551 }
ebrus 0:0a673c671a56 1552
ebrus 0:0a673c671a56 1553 /**
ebrus 0:0a673c671a56 1554 * @brief Clears the I2Cx's interrupt pending bits.
ebrus 0:0a673c671a56 1555 * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
ebrus 0:0a673c671a56 1556 * @param I2C_IT: specifies the interrupt pending bit to clear.
ebrus 0:0a673c671a56 1557 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 1558 * @arg I2C_IT_ADDR: Address matched (slave mode)
ebrus 0:0a673c671a56 1559 * @arg I2C_IT_NACKF: NACK received flag
ebrus 0:0a673c671a56 1560 * @arg I2C_IT_STOPF: STOP detection flag
ebrus 0:0a673c671a56 1561 * @arg I2C_IT_BERR: Bus error
ebrus 0:0a673c671a56 1562 * @arg I2C_IT_ARLO: Arbitration lost
ebrus 0:0a673c671a56 1563 * @arg I2C_IT_OVR: Overrun/Underrun
ebrus 0:0a673c671a56 1564 * @arg I2C_IT_PECERR: PEC error in reception
ebrus 0:0a673c671a56 1565 * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
ebrus 0:0a673c671a56 1566 * @arg I2C_IT_ALERT: SMBus Alert
ebrus 0:0a673c671a56 1567 * @retval The new state of I2C_IT (SET or RESET).
ebrus 0:0a673c671a56 1568 */
ebrus 0:0a673c671a56 1569 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
ebrus 0:0a673c671a56 1570 {
ebrus 0:0a673c671a56 1571 /* Check the parameters */
ebrus 0:0a673c671a56 1572 assert_param(IS_I2C_ALL_PERIPH(I2Cx));
ebrus 0:0a673c671a56 1573 assert_param(IS_I2C_CLEAR_IT(I2C_IT));
ebrus 0:0a673c671a56 1574
ebrus 0:0a673c671a56 1575 /* Clear the selected flag */
ebrus 0:0a673c671a56 1576 I2Cx->ICR = I2C_IT;
ebrus 0:0a673c671a56 1577 }
ebrus 0:0a673c671a56 1578
ebrus 0:0a673c671a56 1579 /**
ebrus 0:0a673c671a56 1580 * @}
ebrus 0:0a673c671a56 1581 */
ebrus 0:0a673c671a56 1582
ebrus 0:0a673c671a56 1583 /**
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ebrus 0:0a673c671a56 1595 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/