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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_flash.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_flash.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file contains all the functions prototypes for the FLASH
ebrus 0:0a673c671a56 8 * firmware library.
ebrus 0:0a673c671a56 9 ******************************************************************************
ebrus 0:0a673c671a56 10 * @attention
ebrus 0:0a673c671a56 11 *
ebrus 0:0a673c671a56 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 13 *
ebrus 0:0a673c671a56 14 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 15 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 16 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 17 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 20 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 22 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 23 * without specific prior written permission.
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 *
ebrus 0:0a673c671a56 36 ******************************************************************************
ebrus 0:0a673c671a56 37 */
ebrus 0:0a673c671a56 38
ebrus 0:0a673c671a56 39 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 40 #ifndef __STM32F30x_FLASH_H
ebrus 0:0a673c671a56 41 #define __STM32F30x_FLASH_H
ebrus 0:0a673c671a56 42
ebrus 0:0a673c671a56 43 #ifdef __cplusplus
ebrus 0:0a673c671a56 44 extern "C" {
ebrus 0:0a673c671a56 45 #endif
ebrus 0:0a673c671a56 46
ebrus 0:0a673c671a56 47 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 48 #include "stm32f30x.h"
ebrus 0:0a673c671a56 49
ebrus 0:0a673c671a56 50 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 51 * @{
ebrus 0:0a673c671a56 52 */
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 /** @addtogroup FLASH
ebrus 0:0a673c671a56 55 * @{
ebrus 0:0a673c671a56 56 */
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 /* Exported types ------------------------------------------------------------*/
ebrus 0:0a673c671a56 59 /**
ebrus 0:0a673c671a56 60 * @brief FLASH Status
ebrus 0:0a673c671a56 61 */
ebrus 0:0a673c671a56 62 typedef enum
ebrus 0:0a673c671a56 63 {
ebrus 0:0a673c671a56 64 FLASH_BUSY = 1,
ebrus 0:0a673c671a56 65 FLASH_ERROR_WRP,
ebrus 0:0a673c671a56 66 FLASH_ERROR_PROGRAM,
ebrus 0:0a673c671a56 67 FLASH_COMPLETE,
ebrus 0:0a673c671a56 68 FLASH_TIMEOUT
ebrus 0:0a673c671a56 69 }FLASH_Status;
ebrus 0:0a673c671a56 70
ebrus 0:0a673c671a56 71 /* Exported constants --------------------------------------------------------*/
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73 /** @defgroup FLASH_Exported_Constants
ebrus 0:0a673c671a56 74 * @{
ebrus 0:0a673c671a56 75 */
ebrus 0:0a673c671a56 76
ebrus 0:0a673c671a56 77 /** @defgroup Flash_Latency
ebrus 0:0a673c671a56 78 * @{
ebrus 0:0a673c671a56 79 */
ebrus 0:0a673c671a56 80 #define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
ebrus 0:0a673c671a56 81 #define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
ebrus 0:0a673c671a56 82 #define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
ebrus 0:0a673c671a56 83
ebrus 0:0a673c671a56 84 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
ebrus 0:0a673c671a56 85 ((LATENCY) == FLASH_Latency_1) || \
ebrus 0:0a673c671a56 86 ((LATENCY) == FLASH_Latency_2))
ebrus 0:0a673c671a56 87 /**
ebrus 0:0a673c671a56 88 * @}
ebrus 0:0a673c671a56 89 */
ebrus 0:0a673c671a56 90
ebrus 0:0a673c671a56 91 /** @defgroup FLASH_Interrupts
ebrus 0:0a673c671a56 92 * @{
ebrus 0:0a673c671a56 93 */
ebrus 0:0a673c671a56 94
ebrus 0:0a673c671a56 95 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
ebrus 0:0a673c671a56 96 #define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
ebrus 0:0a673c671a56 97 #define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
ebrus 0:0a673c671a56 98 /**
ebrus 0:0a673c671a56 99 * @}
ebrus 0:0a673c671a56 100 */
ebrus 0:0a673c671a56 101 /** @defgroup FLASH_Address
ebrus 0:0a673c671a56 102 * @{
ebrus 0:0a673c671a56 103 */
ebrus 0:0a673c671a56 104
ebrus 0:0a673c671a56 105 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
ebrus 0:0a673c671a56 106
ebrus 0:0a673c671a56 107 /**
ebrus 0:0a673c671a56 108 * @}
ebrus 0:0a673c671a56 109 */
ebrus 0:0a673c671a56 110
ebrus 0:0a673c671a56 111 /** @defgroup FLASH_OB_DATA_ADDRESS
ebrus 0:0a673c671a56 112 * @{
ebrus 0:0a673c671a56 113 */
ebrus 0:0a673c671a56 114 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 /**
ebrus 0:0a673c671a56 117 * @}
ebrus 0:0a673c671a56 118 */
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120 /** @defgroup Option_Bytes_Write_Protection
ebrus 0:0a673c671a56 121 * @{
ebrus 0:0a673c671a56 122 */
ebrus 0:0a673c671a56 123
ebrus 0:0a673c671a56 124 #define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
ebrus 0:0a673c671a56 125 #define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
ebrus 0:0a673c671a56 126 #define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
ebrus 0:0a673c671a56 127 #define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
ebrus 0:0a673c671a56 128 #define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
ebrus 0:0a673c671a56 129 #define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
ebrus 0:0a673c671a56 130 #define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
ebrus 0:0a673c671a56 131 #define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
ebrus 0:0a673c671a56 132 #define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
ebrus 0:0a673c671a56 133 #define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
ebrus 0:0a673c671a56 134 #define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
ebrus 0:0a673c671a56 135 #define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
ebrus 0:0a673c671a56 136 #define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
ebrus 0:0a673c671a56 137 #define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
ebrus 0:0a673c671a56 138 #define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
ebrus 0:0a673c671a56 139 #define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
ebrus 0:0a673c671a56 140 #define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
ebrus 0:0a673c671a56 141 #define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
ebrus 0:0a673c671a56 142 #define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
ebrus 0:0a673c671a56 143 #define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
ebrus 0:0a673c671a56 144 #define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
ebrus 0:0a673c671a56 145 #define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
ebrus 0:0a673c671a56 146 #define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
ebrus 0:0a673c671a56 147 #define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
ebrus 0:0a673c671a56 148 #define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
ebrus 0:0a673c671a56 149 #define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
ebrus 0:0a673c671a56 150 #define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
ebrus 0:0a673c671a56 151 #define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
ebrus 0:0a673c671a56 152 #define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
ebrus 0:0a673c671a56 153 #define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
ebrus 0:0a673c671a56 154 #define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
ebrus 0:0a673c671a56 155 #define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
ebrus 0:0a673c671a56 156
ebrus 0:0a673c671a56 157 #define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
ebrus 0:0a673c671a56 158
ebrus 0:0a673c671a56 159 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
ebrus 0:0a673c671a56 160
ebrus 0:0a673c671a56 161 /**
ebrus 0:0a673c671a56 162 * @}
ebrus 0:0a673c671a56 163 */
ebrus 0:0a673c671a56 164
ebrus 0:0a673c671a56 165 /** @defgroup Option_Bytes_Read_Protection
ebrus 0:0a673c671a56 166 * @{
ebrus 0:0a673c671a56 167 */
ebrus 0:0a673c671a56 168
ebrus 0:0a673c671a56 169 /**
ebrus 0:0a673c671a56 170 * @brief Read Protection Level
ebrus 0:0a673c671a56 171 */
ebrus 0:0a673c671a56 172 #define OB_RDP_Level_0 ((uint8_t)0xAA)
ebrus 0:0a673c671a56 173 #define OB_RDP_Level_1 ((uint8_t)0xBB)
ebrus 0:0a673c671a56 174 /*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
ebrus 0:0a673c671a56 175 it's no more possible to go back to level 1 or 0 */
ebrus 0:0a673c671a56 176
ebrus 0:0a673c671a56 177 #define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
ebrus 0:0a673c671a56 178 ((LEVEL) == OB_RDP_Level_1))/*||\
ebrus 0:0a673c671a56 179 ((LEVEL) == OB_RDP_Level_2))*/
ebrus 0:0a673c671a56 180 /**
ebrus 0:0a673c671a56 181 * @}
ebrus 0:0a673c671a56 182 */
ebrus 0:0a673c671a56 183
ebrus 0:0a673c671a56 184 /** @defgroup Option_Bytes_IWatchdog
ebrus 0:0a673c671a56 185 * @{
ebrus 0:0a673c671a56 186 */
ebrus 0:0a673c671a56 187
ebrus 0:0a673c671a56 188 #define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
ebrus 0:0a673c671a56 189 #define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
ebrus 0:0a673c671a56 190 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
ebrus 0:0a673c671a56 191
ebrus 0:0a673c671a56 192 /**
ebrus 0:0a673c671a56 193 * @}
ebrus 0:0a673c671a56 194 */
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 /** @defgroup Option_Bytes_nRST_STOP
ebrus 0:0a673c671a56 197 * @{
ebrus 0:0a673c671a56 198 */
ebrus 0:0a673c671a56 199
ebrus 0:0a673c671a56 200 #define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
ebrus 0:0a673c671a56 201 #define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
ebrus 0:0a673c671a56 202 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
ebrus 0:0a673c671a56 203
ebrus 0:0a673c671a56 204 /**
ebrus 0:0a673c671a56 205 * @}
ebrus 0:0a673c671a56 206 */
ebrus 0:0a673c671a56 207
ebrus 0:0a673c671a56 208 /** @defgroup Option_Bytes_nRST_STDBY
ebrus 0:0a673c671a56 209 * @{
ebrus 0:0a673c671a56 210 */
ebrus 0:0a673c671a56 211
ebrus 0:0a673c671a56 212 #define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
ebrus 0:0a673c671a56 213 #define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
ebrus 0:0a673c671a56 214 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
ebrus 0:0a673c671a56 215
ebrus 0:0a673c671a56 216 /**
ebrus 0:0a673c671a56 217 * @}
ebrus 0:0a673c671a56 218 */
ebrus 0:0a673c671a56 219 /** @defgroup Option_Bytes_BOOT1
ebrus 0:0a673c671a56 220 * @{
ebrus 0:0a673c671a56 221 */
ebrus 0:0a673c671a56 222
ebrus 0:0a673c671a56 223 #define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
ebrus 0:0a673c671a56 224 #define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
ebrus 0:0a673c671a56 225 #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
ebrus 0:0a673c671a56 226
ebrus 0:0a673c671a56 227 /**
ebrus 0:0a673c671a56 228 * @}
ebrus 0:0a673c671a56 229 */
ebrus 0:0a673c671a56 230 /** @defgroup Option_Bytes_VDDA_Analog_Monitoring
ebrus 0:0a673c671a56 231 * @{
ebrus 0:0a673c671a56 232 */
ebrus 0:0a673c671a56 233
ebrus 0:0a673c671a56 234 #define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
ebrus 0:0a673c671a56 235 #define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
ebrus 0:0a673c671a56 236
ebrus 0:0a673c671a56 237 #define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
ebrus 0:0a673c671a56 238
ebrus 0:0a673c671a56 239 /**
ebrus 0:0a673c671a56 240 * @}
ebrus 0:0a673c671a56 241 */
ebrus 0:0a673c671a56 242
ebrus 0:0a673c671a56 243 /** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
ebrus 0:0a673c671a56 244 * @{
ebrus 0:0a673c671a56 245 */
ebrus 0:0a673c671a56 246
ebrus 0:0a673c671a56 247 #define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
ebrus 0:0a673c671a56 248 #define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
ebrus 0:0a673c671a56 249
ebrus 0:0a673c671a56 250 #define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
ebrus 0:0a673c671a56 251
ebrus 0:0a673c671a56 252 /**
ebrus 0:0a673c671a56 253 * @}
ebrus 0:0a673c671a56 254 */
ebrus 0:0a673c671a56 255
ebrus 0:0a673c671a56 256 /** @defgroup FLASH_Flags
ebrus 0:0a673c671a56 257 * @{
ebrus 0:0a673c671a56 258 */
ebrus 0:0a673c671a56 259
ebrus 0:0a673c671a56 260 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
ebrus 0:0a673c671a56 261 #define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
ebrus 0:0a673c671a56 262 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
ebrus 0:0a673c671a56 263 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
ebrus 0:0a673c671a56 264
ebrus 0:0a673c671a56 265 #define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
ebrus 0:0a673c671a56 266
ebrus 0:0a673c671a56 267 #define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
ebrus 0:0a673c671a56 268 ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
ebrus 0:0a673c671a56 269 /**
ebrus 0:0a673c671a56 270 * @}
ebrus 0:0a673c671a56 271 */
ebrus 0:0a673c671a56 272 /** @defgroup Timeout_definition
ebrus 0:0a673c671a56 273 * @{
ebrus 0:0a673c671a56 274 */
ebrus 0:0a673c671a56 275 #define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
ebrus 0:0a673c671a56 276
ebrus 0:0a673c671a56 277 /**
ebrus 0:0a673c671a56 278 * @}
ebrus 0:0a673c671a56 279 */
ebrus 0:0a673c671a56 280
ebrus 0:0a673c671a56 281 /**
ebrus 0:0a673c671a56 282 * @}
ebrus 0:0a673c671a56 283 */
ebrus 0:0a673c671a56 284
ebrus 0:0a673c671a56 285 /* Exported macro ------------------------------------------------------------*/
ebrus 0:0a673c671a56 286 /* Exported functions --------------------------------------------------------*/
ebrus 0:0a673c671a56 287
ebrus 0:0a673c671a56 288 /* FLASH Interface configuration functions ************************************/
ebrus 0:0a673c671a56 289 void FLASH_SetLatency(uint32_t FLASH_Latency);
ebrus 0:0a673c671a56 290 void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
ebrus 0:0a673c671a56 291 void FLASH_PrefetchBufferCmd(FunctionalState NewState);
ebrus 0:0a673c671a56 292
ebrus 0:0a673c671a56 293 /* FLASH Memory Programming functions *****************************************/
ebrus 0:0a673c671a56 294 void FLASH_Unlock(void);
ebrus 0:0a673c671a56 295 void FLASH_Lock(void);
ebrus 0:0a673c671a56 296 FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
ebrus 0:0a673c671a56 297 FLASH_Status FLASH_EraseAllPages(void);
ebrus 0:0a673c671a56 298 FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
ebrus 0:0a673c671a56 299 FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
ebrus 0:0a673c671a56 300
ebrus 0:0a673c671a56 301 /* Option Bytes Programming functions *****************************************/
ebrus 0:0a673c671a56 302 void FLASH_OB_Unlock(void);
ebrus 0:0a673c671a56 303 void FLASH_OB_Lock(void);
ebrus 0:0a673c671a56 304 void FLASH_OB_Launch(void);
ebrus 0:0a673c671a56 305 FLASH_Status FLASH_OB_Erase(void);
ebrus 0:0a673c671a56 306 FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
ebrus 0:0a673c671a56 307 FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
ebrus 0:0a673c671a56 308 FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
ebrus 0:0a673c671a56 309 FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
ebrus 0:0a673c671a56 310 FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
ebrus 0:0a673c671a56 311 FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
ebrus 0:0a673c671a56 312 FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
ebrus 0:0a673c671a56 313 FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
ebrus 0:0a673c671a56 314 uint8_t FLASH_OB_GetUser(void);
ebrus 0:0a673c671a56 315 uint32_t FLASH_OB_GetWRP(void);
ebrus 0:0a673c671a56 316 FlagStatus FLASH_OB_GetRDP(void);
ebrus 0:0a673c671a56 317
ebrus 0:0a673c671a56 318 /* Interrupts and flags management functions **********************************/
ebrus 0:0a673c671a56 319 void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
ebrus 0:0a673c671a56 320 FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
ebrus 0:0a673c671a56 321 void FLASH_ClearFlag(uint32_t FLASH_FLAG);
ebrus 0:0a673c671a56 322 FLASH_Status FLASH_GetStatus(void);
ebrus 0:0a673c671a56 323 FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
ebrus 0:0a673c671a56 324
ebrus 0:0a673c671a56 325 #ifdef __cplusplus
ebrus 0:0a673c671a56 326 }
ebrus 0:0a673c671a56 327 #endif
ebrus 0:0a673c671a56 328
ebrus 0:0a673c671a56 329 #endif /* __STM32F30x_FLASH_H */
ebrus 0:0a673c671a56 330
ebrus 0:0a673c671a56 331 /**
ebrus 0:0a673c671a56 332 * @}
ebrus 0:0a673c671a56 333 */
ebrus 0:0a673c671a56 334
ebrus 0:0a673c671a56 335 /**
ebrus 0:0a673c671a56 336 * @}
ebrus 0:0a673c671a56 337 */
ebrus 0:0a673c671a56 338
ebrus 0:0a673c671a56 339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/