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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dma.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_dma.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file contains all the functions prototypes for the DMA firmware
ebrus 0:0a673c671a56 8 * library.
ebrus 0:0a673c671a56 9 ******************************************************************************
ebrus 0:0a673c671a56 10 * @attention
ebrus 0:0a673c671a56 11 *
ebrus 0:0a673c671a56 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 13 *
ebrus 0:0a673c671a56 14 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 15 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 16 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 17 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 20 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 22 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 23 * without specific prior written permission.
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 *
ebrus 0:0a673c671a56 36 ******************************************************************************
ebrus 0:0a673c671a56 37 */
ebrus 0:0a673c671a56 38
ebrus 0:0a673c671a56 39 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 40 #ifndef __STM32F30x_DMA_H
ebrus 0:0a673c671a56 41 #define __STM32F30x_DMA_H
ebrus 0:0a673c671a56 42
ebrus 0:0a673c671a56 43 #ifdef __cplusplus
ebrus 0:0a673c671a56 44 extern "C" {
ebrus 0:0a673c671a56 45 #endif
ebrus 0:0a673c671a56 46
ebrus 0:0a673c671a56 47 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 48 #include "stm32f30x.h"
ebrus 0:0a673c671a56 49
ebrus 0:0a673c671a56 50 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 51 * @{
ebrus 0:0a673c671a56 52 */
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 /** @addtogroup DMA
ebrus 0:0a673c671a56 55 * @{
ebrus 0:0a673c671a56 56 */
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 /* Exported types ------------------------------------------------------------*/
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 /**
ebrus 0:0a673c671a56 61 * @brief DMA Init structures definition
ebrus 0:0a673c671a56 62 */
ebrus 0:0a673c671a56 63 typedef struct
ebrus 0:0a673c671a56 64 {
ebrus 0:0a673c671a56 65 uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
ebrus 0:0a673c671a56 66
ebrus 0:0a673c671a56 67 uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
ebrus 0:0a673c671a56 68
ebrus 0:0a673c671a56 69 uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
ebrus 0:0a673c671a56 70 This parameter can be a value of @ref DMA_data_transfer_direction */
ebrus 0:0a673c671a56 71
ebrus 0:0a673c671a56 72 uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
ebrus 0:0a673c671a56 73 The data unit is equal to the configuration set in DMA_PeripheralDataSize
ebrus 0:0a673c671a56 74 or DMA_MemoryDataSize members depending in the transfer direction. */
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
ebrus 0:0a673c671a56 77 This parameter can be a value of @ref DMA_peripheral_incremented_mode */
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
ebrus 0:0a673c671a56 80 This parameter can be a value of @ref DMA_memory_incremented_mode */
ebrus 0:0a673c671a56 81
ebrus 0:0a673c671a56 82 uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
ebrus 0:0a673c671a56 83 This parameter can be a value of @ref DMA_peripheral_data_size */
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85 uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
ebrus 0:0a673c671a56 86 This parameter can be a value of @ref DMA_memory_data_size */
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
ebrus 0:0a673c671a56 89 This parameter can be a value of @ref DMA_circular_normal_mode
ebrus 0:0a673c671a56 90 @note: The circular buffer mode cannot be used if the memory-to-memory
ebrus 0:0a673c671a56 91 data transfer is configured on the selected Channel */
ebrus 0:0a673c671a56 92
ebrus 0:0a673c671a56 93 uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
ebrus 0:0a673c671a56 94 This parameter can be a value of @ref DMA_priority_level */
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96 uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
ebrus 0:0a673c671a56 97 This parameter can be a value of @ref DMA_memory_to_memory */
ebrus 0:0a673c671a56 98 }DMA_InitTypeDef;
ebrus 0:0a673c671a56 99
ebrus 0:0a673c671a56 100 /* Exported constants --------------------------------------------------------*/
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 /** @defgroup DMA_Exported_Constants
ebrus 0:0a673c671a56 103 * @{
ebrus 0:0a673c671a56 104 */
ebrus 0:0a673c671a56 105
ebrus 0:0a673c671a56 106 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
ebrus 0:0a673c671a56 107 ((PERIPH) == DMA1_Channel2) || \
ebrus 0:0a673c671a56 108 ((PERIPH) == DMA1_Channel3) || \
ebrus 0:0a673c671a56 109 ((PERIPH) == DMA1_Channel4) || \
ebrus 0:0a673c671a56 110 ((PERIPH) == DMA1_Channel5) || \
ebrus 0:0a673c671a56 111 ((PERIPH) == DMA1_Channel6) || \
ebrus 0:0a673c671a56 112 ((PERIPH) == DMA1_Channel7) || \
ebrus 0:0a673c671a56 113 ((PERIPH) == DMA2_Channel1) || \
ebrus 0:0a673c671a56 114 ((PERIPH) == DMA2_Channel2) || \
ebrus 0:0a673c671a56 115 ((PERIPH) == DMA2_Channel3) || \
ebrus 0:0a673c671a56 116 ((PERIPH) == DMA2_Channel4) || \
ebrus 0:0a673c671a56 117 ((PERIPH) == DMA2_Channel5))
ebrus 0:0a673c671a56 118
ebrus 0:0a673c671a56 119 /** @defgroup DMA_data_transfer_direction
ebrus 0:0a673c671a56 120 * @{
ebrus 0:0a673c671a56 121 */
ebrus 0:0a673c671a56 122
ebrus 0:0a673c671a56 123 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 124 #define DMA_DIR_PeripheralDST DMA_CCR_DIR
ebrus 0:0a673c671a56 125
ebrus 0:0a673c671a56 126 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
ebrus 0:0a673c671a56 127 ((DIR) == DMA_DIR_PeripheralDST))
ebrus 0:0a673c671a56 128 /**
ebrus 0:0a673c671a56 129 * @}
ebrus 0:0a673c671a56 130 */
ebrus 0:0a673c671a56 131
ebrus 0:0a673c671a56 132
ebrus 0:0a673c671a56 133 /** @defgroup DMA_peripheral_incremented_mode
ebrus 0:0a673c671a56 134 * @{
ebrus 0:0a673c671a56 135 */
ebrus 0:0a673c671a56 136
ebrus 0:0a673c671a56 137 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 138 #define DMA_PeripheralInc_Enable DMA_CCR_PINC
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
ebrus 0:0a673c671a56 141 ((STATE) == DMA_PeripheralInc_Enable))
ebrus 0:0a673c671a56 142 /**
ebrus 0:0a673c671a56 143 * @}
ebrus 0:0a673c671a56 144 */
ebrus 0:0a673c671a56 145
ebrus 0:0a673c671a56 146 /** @defgroup DMA_memory_incremented_mode
ebrus 0:0a673c671a56 147 * @{
ebrus 0:0a673c671a56 148 */
ebrus 0:0a673c671a56 149
ebrus 0:0a673c671a56 150 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 151 #define DMA_MemoryInc_Enable DMA_CCR_MINC
ebrus 0:0a673c671a56 152
ebrus 0:0a673c671a56 153 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
ebrus 0:0a673c671a56 154 ((STATE) == DMA_MemoryInc_Enable))
ebrus 0:0a673c671a56 155 /**
ebrus 0:0a673c671a56 156 * @}
ebrus 0:0a673c671a56 157 */
ebrus 0:0a673c671a56 158
ebrus 0:0a673c671a56 159 /** @defgroup DMA_peripheral_data_size
ebrus 0:0a673c671a56 160 * @{
ebrus 0:0a673c671a56 161 */
ebrus 0:0a673c671a56 162
ebrus 0:0a673c671a56 163 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 164 #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
ebrus 0:0a673c671a56 165 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
ebrus 0:0a673c671a56 166
ebrus 0:0a673c671a56 167 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
ebrus 0:0a673c671a56 168 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
ebrus 0:0a673c671a56 169 ((SIZE) == DMA_PeripheralDataSize_Word))
ebrus 0:0a673c671a56 170 /**
ebrus 0:0a673c671a56 171 * @}
ebrus 0:0a673c671a56 172 */
ebrus 0:0a673c671a56 173
ebrus 0:0a673c671a56 174 /** @defgroup DMA_memory_data_size
ebrus 0:0a673c671a56 175 * @{
ebrus 0:0a673c671a56 176 */
ebrus 0:0a673c671a56 177
ebrus 0:0a673c671a56 178 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 179 #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
ebrus 0:0a673c671a56 180 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
ebrus 0:0a673c671a56 181
ebrus 0:0a673c671a56 182 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
ebrus 0:0a673c671a56 183 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
ebrus 0:0a673c671a56 184 ((SIZE) == DMA_MemoryDataSize_Word))
ebrus 0:0a673c671a56 185 /**
ebrus 0:0a673c671a56 186 * @}
ebrus 0:0a673c671a56 187 */
ebrus 0:0a673c671a56 188
ebrus 0:0a673c671a56 189 /** @defgroup DMA_circular_normal_mode
ebrus 0:0a673c671a56 190 * @{
ebrus 0:0a673c671a56 191 */
ebrus 0:0a673c671a56 192
ebrus 0:0a673c671a56 193 #define DMA_Mode_Normal ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 194 #define DMA_Mode_Circular DMA_CCR_CIRC
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
ebrus 0:0a673c671a56 197 /**
ebrus 0:0a673c671a56 198 * @}
ebrus 0:0a673c671a56 199 */
ebrus 0:0a673c671a56 200
ebrus 0:0a673c671a56 201 /** @defgroup DMA_priority_level
ebrus 0:0a673c671a56 202 * @{
ebrus 0:0a673c671a56 203 */
ebrus 0:0a673c671a56 204
ebrus 0:0a673c671a56 205 #define DMA_Priority_VeryHigh DMA_CCR_PL
ebrus 0:0a673c671a56 206 #define DMA_Priority_High DMA_CCR_PL_1
ebrus 0:0a673c671a56 207 #define DMA_Priority_Medium DMA_CCR_PL_0
ebrus 0:0a673c671a56 208 #define DMA_Priority_Low ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 209
ebrus 0:0a673c671a56 210 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
ebrus 0:0a673c671a56 211 ((PRIORITY) == DMA_Priority_High) || \
ebrus 0:0a673c671a56 212 ((PRIORITY) == DMA_Priority_Medium) || \
ebrus 0:0a673c671a56 213 ((PRIORITY) == DMA_Priority_Low))
ebrus 0:0a673c671a56 214 /**
ebrus 0:0a673c671a56 215 * @}
ebrus 0:0a673c671a56 216 */
ebrus 0:0a673c671a56 217
ebrus 0:0a673c671a56 218 /** @defgroup DMA_memory_to_memory
ebrus 0:0a673c671a56 219 * @{
ebrus 0:0a673c671a56 220 */
ebrus 0:0a673c671a56 221
ebrus 0:0a673c671a56 222 #define DMA_M2M_Disable ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 223 #define DMA_M2M_Enable DMA_CCR_MEM2MEM
ebrus 0:0a673c671a56 224
ebrus 0:0a673c671a56 225 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
ebrus 0:0a673c671a56 226
ebrus 0:0a673c671a56 227 /**
ebrus 0:0a673c671a56 228 * @}
ebrus 0:0a673c671a56 229 */
ebrus 0:0a673c671a56 230
ebrus 0:0a673c671a56 231 /** @defgroup DMA_interrupts_definition
ebrus 0:0a673c671a56 232 * @{
ebrus 0:0a673c671a56 233 */
ebrus 0:0a673c671a56 234
ebrus 0:0a673c671a56 235 #define DMA_IT_TC ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 236 #define DMA_IT_HT ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 237 #define DMA_IT_TE ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 238 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
ebrus 0:0a673c671a56 239
ebrus 0:0a673c671a56 240 #define DMA1_IT_GL1 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 241 #define DMA1_IT_TC1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 242 #define DMA1_IT_HT1 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 243 #define DMA1_IT_TE1 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 244 #define DMA1_IT_GL2 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 245 #define DMA1_IT_TC2 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 246 #define DMA1_IT_HT2 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 247 #define DMA1_IT_TE2 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 248 #define DMA1_IT_GL3 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 249 #define DMA1_IT_TC3 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 250 #define DMA1_IT_HT3 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 251 #define DMA1_IT_TE3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 252 #define DMA1_IT_GL4 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 253 #define DMA1_IT_TC4 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 254 #define DMA1_IT_HT4 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 255 #define DMA1_IT_TE4 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 256 #define DMA1_IT_GL5 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 257 #define DMA1_IT_TC5 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 258 #define DMA1_IT_HT5 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 259 #define DMA1_IT_TE5 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 260 #define DMA1_IT_GL6 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 261 #define DMA1_IT_TC6 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 262 #define DMA1_IT_HT6 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 263 #define DMA1_IT_TE6 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 264 #define DMA1_IT_GL7 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 265 #define DMA1_IT_TC7 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 266 #define DMA1_IT_HT7 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 267 #define DMA1_IT_TE7 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 268
ebrus 0:0a673c671a56 269 #define DMA2_IT_GL1 ((uint32_t)0x10000001)
ebrus 0:0a673c671a56 270 #define DMA2_IT_TC1 ((uint32_t)0x10000002)
ebrus 0:0a673c671a56 271 #define DMA2_IT_HT1 ((uint32_t)0x10000004)
ebrus 0:0a673c671a56 272 #define DMA2_IT_TE1 ((uint32_t)0x10000008)
ebrus 0:0a673c671a56 273 #define DMA2_IT_GL2 ((uint32_t)0x10000010)
ebrus 0:0a673c671a56 274 #define DMA2_IT_TC2 ((uint32_t)0x10000020)
ebrus 0:0a673c671a56 275 #define DMA2_IT_HT2 ((uint32_t)0x10000040)
ebrus 0:0a673c671a56 276 #define DMA2_IT_TE2 ((uint32_t)0x10000080)
ebrus 0:0a673c671a56 277 #define DMA2_IT_GL3 ((uint32_t)0x10000100)
ebrus 0:0a673c671a56 278 #define DMA2_IT_TC3 ((uint32_t)0x10000200)
ebrus 0:0a673c671a56 279 #define DMA2_IT_HT3 ((uint32_t)0x10000400)
ebrus 0:0a673c671a56 280 #define DMA2_IT_TE3 ((uint32_t)0x10000800)
ebrus 0:0a673c671a56 281 #define DMA2_IT_GL4 ((uint32_t)0x10001000)
ebrus 0:0a673c671a56 282 #define DMA2_IT_TC4 ((uint32_t)0x10002000)
ebrus 0:0a673c671a56 283 #define DMA2_IT_HT4 ((uint32_t)0x10004000)
ebrus 0:0a673c671a56 284 #define DMA2_IT_TE4 ((uint32_t)0x10008000)
ebrus 0:0a673c671a56 285 #define DMA2_IT_GL5 ((uint32_t)0x10010000)
ebrus 0:0a673c671a56 286 #define DMA2_IT_TC5 ((uint32_t)0x10020000)
ebrus 0:0a673c671a56 287 #define DMA2_IT_HT5 ((uint32_t)0x10040000)
ebrus 0:0a673c671a56 288 #define DMA2_IT_TE5 ((uint32_t)0x10080000)
ebrus 0:0a673c671a56 289
ebrus 0:0a673c671a56 290 #define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
ebrus 0:0a673c671a56 291
ebrus 0:0a673c671a56 292 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
ebrus 0:0a673c671a56 293 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
ebrus 0:0a673c671a56 294 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
ebrus 0:0a673c671a56 295 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
ebrus 0:0a673c671a56 296 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
ebrus 0:0a673c671a56 297 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
ebrus 0:0a673c671a56 298 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
ebrus 0:0a673c671a56 299 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
ebrus 0:0a673c671a56 300 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
ebrus 0:0a673c671a56 301 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
ebrus 0:0a673c671a56 302 ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
ebrus 0:0a673c671a56 303 ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
ebrus 0:0a673c671a56 304 ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
ebrus 0:0a673c671a56 305 ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
ebrus 0:0a673c671a56 306 ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
ebrus 0:0a673c671a56 307 ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
ebrus 0:0a673c671a56 308 ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
ebrus 0:0a673c671a56 309 ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
ebrus 0:0a673c671a56 310 ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
ebrus 0:0a673c671a56 311 ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
ebrus 0:0a673c671a56 312 ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
ebrus 0:0a673c671a56 313 ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
ebrus 0:0a673c671a56 314 ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
ebrus 0:0a673c671a56 315 ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
ebrus 0:0a673c671a56 316
ebrus 0:0a673c671a56 317 /**
ebrus 0:0a673c671a56 318 * @}
ebrus 0:0a673c671a56 319 */
ebrus 0:0a673c671a56 320
ebrus 0:0a673c671a56 321 /** @defgroup DMA_flags_definition
ebrus 0:0a673c671a56 322 * @{
ebrus 0:0a673c671a56 323 */
ebrus 0:0a673c671a56 324
ebrus 0:0a673c671a56 325 #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
ebrus 0:0a673c671a56 326 #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
ebrus 0:0a673c671a56 327 #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 328 #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
ebrus 0:0a673c671a56 329 #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
ebrus 0:0a673c671a56 330 #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
ebrus 0:0a673c671a56 331 #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
ebrus 0:0a673c671a56 332 #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
ebrus 0:0a673c671a56 333 #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
ebrus 0:0a673c671a56 334 #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
ebrus 0:0a673c671a56 335 #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
ebrus 0:0a673c671a56 336 #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
ebrus 0:0a673c671a56 337 #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
ebrus 0:0a673c671a56 338 #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
ebrus 0:0a673c671a56 339 #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
ebrus 0:0a673c671a56 340 #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
ebrus 0:0a673c671a56 341 #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
ebrus 0:0a673c671a56 342 #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
ebrus 0:0a673c671a56 343 #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
ebrus 0:0a673c671a56 344 #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
ebrus 0:0a673c671a56 345 #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
ebrus 0:0a673c671a56 346 #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
ebrus 0:0a673c671a56 347 #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
ebrus 0:0a673c671a56 348 #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
ebrus 0:0a673c671a56 349 #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
ebrus 0:0a673c671a56 350 #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
ebrus 0:0a673c671a56 351 #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
ebrus 0:0a673c671a56 352 #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 353
ebrus 0:0a673c671a56 354 #define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
ebrus 0:0a673c671a56 355 #define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
ebrus 0:0a673c671a56 356 #define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
ebrus 0:0a673c671a56 357 #define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
ebrus 0:0a673c671a56 358 #define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
ebrus 0:0a673c671a56 359 #define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
ebrus 0:0a673c671a56 360 #define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
ebrus 0:0a673c671a56 361 #define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
ebrus 0:0a673c671a56 362 #define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
ebrus 0:0a673c671a56 363 #define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
ebrus 0:0a673c671a56 364 #define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
ebrus 0:0a673c671a56 365 #define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
ebrus 0:0a673c671a56 366 #define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
ebrus 0:0a673c671a56 367 #define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
ebrus 0:0a673c671a56 368 #define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
ebrus 0:0a673c671a56 369 #define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
ebrus 0:0a673c671a56 370 #define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
ebrus 0:0a673c671a56 371 #define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
ebrus 0:0a673c671a56 372 #define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
ebrus 0:0a673c671a56 373 #define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
ebrus 0:0a673c671a56 374
ebrus 0:0a673c671a56 375 #define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
ebrus 0:0a673c671a56 376
ebrus 0:0a673c671a56 377 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
ebrus 0:0a673c671a56 378 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
ebrus 0:0a673c671a56 379 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
ebrus 0:0a673c671a56 380 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
ebrus 0:0a673c671a56 381 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
ebrus 0:0a673c671a56 382 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
ebrus 0:0a673c671a56 383 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
ebrus 0:0a673c671a56 384 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
ebrus 0:0a673c671a56 385 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
ebrus 0:0a673c671a56 386 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
ebrus 0:0a673c671a56 387 ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
ebrus 0:0a673c671a56 388 ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
ebrus 0:0a673c671a56 389 ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
ebrus 0:0a673c671a56 390 ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
ebrus 0:0a673c671a56 391 ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
ebrus 0:0a673c671a56 392 ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
ebrus 0:0a673c671a56 393 ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
ebrus 0:0a673c671a56 394 ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
ebrus 0:0a673c671a56 395 ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
ebrus 0:0a673c671a56 396 ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
ebrus 0:0a673c671a56 397 ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
ebrus 0:0a673c671a56 398 ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
ebrus 0:0a673c671a56 399 ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
ebrus 0:0a673c671a56 400 ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
ebrus 0:0a673c671a56 401
ebrus 0:0a673c671a56 402 /**
ebrus 0:0a673c671a56 403 * @}
ebrus 0:0a673c671a56 404 */
ebrus 0:0a673c671a56 405
ebrus 0:0a673c671a56 406 /**
ebrus 0:0a673c671a56 407 * @}
ebrus 0:0a673c671a56 408 */
ebrus 0:0a673c671a56 409
ebrus 0:0a673c671a56 410 /* Exported macro ------------------------------------------------------------*/
ebrus 0:0a673c671a56 411 /* Exported functions ------------------------------------------------------- */
ebrus 0:0a673c671a56 412
ebrus 0:0a673c671a56 413 /* Function used to set the DMA configuration to the default reset state ******/
ebrus 0:0a673c671a56 414 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
ebrus 0:0a673c671a56 415
ebrus 0:0a673c671a56 416 /* Initialization and Configuration functions *********************************/
ebrus 0:0a673c671a56 417 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
ebrus 0:0a673c671a56 418 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
ebrus 0:0a673c671a56 419 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
ebrus 0:0a673c671a56 420
ebrus 0:0a673c671a56 421 /* Data Counter functions******************************************************/
ebrus 0:0a673c671a56 422 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
ebrus 0:0a673c671a56 423 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
ebrus 0:0a673c671a56 424
ebrus 0:0a673c671a56 425 /* Interrupts and flags management functions **********************************/
ebrus 0:0a673c671a56 426 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
ebrus 0:0a673c671a56 427 FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
ebrus 0:0a673c671a56 428 void DMA_ClearFlag(uint32_t DMAy_FLAG);
ebrus 0:0a673c671a56 429 ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
ebrus 0:0a673c671a56 430 void DMA_ClearITPendingBit(uint32_t DMAy_IT);
ebrus 0:0a673c671a56 431
ebrus 0:0a673c671a56 432 #ifdef __cplusplus
ebrus 0:0a673c671a56 433 }
ebrus 0:0a673c671a56 434 #endif
ebrus 0:0a673c671a56 435
ebrus 0:0a673c671a56 436 #endif /*__STM32F30x_DMA_H */
ebrus 0:0a673c671a56 437
ebrus 0:0a673c671a56 438 /**
ebrus 0:0a673c671a56 439 * @}
ebrus 0:0a673c671a56 440 */
ebrus 0:0a673c671a56 441
ebrus 0:0a673c671a56 442 /**
ebrus 0:0a673c671a56 443 * @}
ebrus 0:0a673c671a56 444 */
ebrus 0:0a673c671a56 445
ebrus 0:0a673c671a56 446 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/