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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_dbgmcu.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_dbgmcu.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 8 * functionalities of the Debug MCU (DBGMCU) peripheral:
ebrus 0:0a673c671a56 9 * + Device and Revision ID management
ebrus 0:0a673c671a56 10 * + Peripherals Configuration
ebrus 0:0a673c671a56 11 ******************************************************************************
ebrus 0:0a673c671a56 12 * @attention
ebrus 0:0a673c671a56 13 *
ebrus 0:0a673c671a56 14 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 15 *
ebrus 0:0a673c671a56 16 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 17 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 18 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 20 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 21 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 22 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 24 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 25 * without specific prior written permission.
ebrus 0:0a673c671a56 26 *
ebrus 0:0a673c671a56 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 37 *
ebrus 0:0a673c671a56 38 ******************************************************************************
ebrus 0:0a673c671a56 39 */
ebrus 0:0a673c671a56 40
ebrus 0:0a673c671a56 41 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 42 #include "stm32f30x_dbgmcu.h"
ebrus 0:0a673c671a56 43
ebrus 0:0a673c671a56 44 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 45 * @{
ebrus 0:0a673c671a56 46 */
ebrus 0:0a673c671a56 47
ebrus 0:0a673c671a56 48 /** @defgroup DBGMCU
ebrus 0:0a673c671a56 49 * @brief DBGMCU driver modules
ebrus 0:0a673c671a56 50 * @{
ebrus 0:0a673c671a56 51 */
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 54 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 55 #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 58 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 59 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 60 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 61
ebrus 0:0a673c671a56 62 /** @defgroup DBGMCU_Private_Functions
ebrus 0:0a673c671a56 63 * @{
ebrus 0:0a673c671a56 64 */
ebrus 0:0a673c671a56 65
ebrus 0:0a673c671a56 66 /** @defgroup DBGMCU_Group1 Device and Revision ID management functions
ebrus 0:0a673c671a56 67 * @brief Device and Revision ID management functions
ebrus 0:0a673c671a56 68 *
ebrus 0:0a673c671a56 69 @verbatim
ebrus 0:0a673c671a56 70 ==============================================================================
ebrus 0:0a673c671a56 71 ##### Device and Revision ID management functions #####
ebrus 0:0a673c671a56 72 ==============================================================================
ebrus 0:0a673c671a56 73
ebrus 0:0a673c671a56 74 @endverbatim
ebrus 0:0a673c671a56 75 * @{
ebrus 0:0a673c671a56 76 */
ebrus 0:0a673c671a56 77
ebrus 0:0a673c671a56 78 /**
ebrus 0:0a673c671a56 79 * @brief Returns the device revision identifier.
ebrus 0:0a673c671a56 80 * @param None
ebrus 0:0a673c671a56 81 * @retval Device revision identifier
ebrus 0:0a673c671a56 82 */
ebrus 0:0a673c671a56 83 uint32_t DBGMCU_GetREVID(void)
ebrus 0:0a673c671a56 84 {
ebrus 0:0a673c671a56 85 return(DBGMCU->IDCODE >> 16);
ebrus 0:0a673c671a56 86 }
ebrus 0:0a673c671a56 87
ebrus 0:0a673c671a56 88 /**
ebrus 0:0a673c671a56 89 * @brief Returns the device identifier.
ebrus 0:0a673c671a56 90 * @param None
ebrus 0:0a673c671a56 91 * @retval Device identifier
ebrus 0:0a673c671a56 92 */
ebrus 0:0a673c671a56 93 uint32_t DBGMCU_GetDEVID(void)
ebrus 0:0a673c671a56 94 {
ebrus 0:0a673c671a56 95 return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
ebrus 0:0a673c671a56 96 }
ebrus 0:0a673c671a56 97
ebrus 0:0a673c671a56 98 /**
ebrus 0:0a673c671a56 99 * @}
ebrus 0:0a673c671a56 100 */
ebrus 0:0a673c671a56 101
ebrus 0:0a673c671a56 102 /** @defgroup DBGMCU_Group2 Peripherals Configuration functions
ebrus 0:0a673c671a56 103 * @brief Peripherals Configuration
ebrus 0:0a673c671a56 104 *
ebrus 0:0a673c671a56 105 @verbatim
ebrus 0:0a673c671a56 106 ==============================================================================
ebrus 0:0a673c671a56 107 ##### Peripherals Configuration functions #####
ebrus 0:0a673c671a56 108 ==============================================================================
ebrus 0:0a673c671a56 109
ebrus 0:0a673c671a56 110 @endverbatim
ebrus 0:0a673c671a56 111 * @{
ebrus 0:0a673c671a56 112 */
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 /**
ebrus 0:0a673c671a56 115 * @brief Configures low power mode behavior when the MCU is in Debug mode.
ebrus 0:0a673c671a56 116 * @param DBGMCU_Periph: specifies the low power mode.
ebrus 0:0a673c671a56 117 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 118 * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
ebrus 0:0a673c671a56 119 * @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
ebrus 0:0a673c671a56 120 * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
ebrus 0:0a673c671a56 121 * @param NewState: new state of the specified low power mode in Debug mode.
ebrus 0:0a673c671a56 122 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 123 * @retval None
ebrus 0:0a673c671a56 124 */
ebrus 0:0a673c671a56 125 void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
ebrus 0:0a673c671a56 126 {
ebrus 0:0a673c671a56 127 /* Check the parameters */
ebrus 0:0a673c671a56 128 assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
ebrus 0:0a673c671a56 129 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 130 if (NewState != DISABLE)
ebrus 0:0a673c671a56 131 {
ebrus 0:0a673c671a56 132 DBGMCU->CR |= DBGMCU_Periph;
ebrus 0:0a673c671a56 133 }
ebrus 0:0a673c671a56 134 else
ebrus 0:0a673c671a56 135 {
ebrus 0:0a673c671a56 136 DBGMCU->CR &= ~DBGMCU_Periph;
ebrus 0:0a673c671a56 137 }
ebrus 0:0a673c671a56 138 }
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 /**
ebrus 0:0a673c671a56 141 * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
ebrus 0:0a673c671a56 142 * @param DBGMCU_Periph: specifies the APB1 peripheral.
ebrus 0:0a673c671a56 143 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 144 * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
ebrus 0:0a673c671a56 145 * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
ebrus 0:0a673c671a56 146 * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
ebrus 0:0a673c671a56 147 * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
ebrus 0:0a673c671a56 148 * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
ebrus 0:0a673c671a56 149 * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
ebrus 0:0a673c671a56 150 * Core is halted.
ebrus 0:0a673c671a56 151 * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
ebrus 0:0a673c671a56 152 * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
ebrus 0:0a673c671a56 153 * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
ebrus 0:0a673c671a56 154 * Core is halted.
ebrus 0:0a673c671a56 155 * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
ebrus 0:0a673c671a56 156 * Core is halted.
ebrus 0:0a673c671a56 157 * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
ebrus 0:0a673c671a56 158 * @param NewState: new state of the specified APB1 peripheral in Debug mode.
ebrus 0:0a673c671a56 159 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 160 * @retval None
ebrus 0:0a673c671a56 161 */
ebrus 0:0a673c671a56 162 void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
ebrus 0:0a673c671a56 163 {
ebrus 0:0a673c671a56 164 /* Check the parameters */
ebrus 0:0a673c671a56 165 assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
ebrus 0:0a673c671a56 166 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 167
ebrus 0:0a673c671a56 168 if (NewState != DISABLE)
ebrus 0:0a673c671a56 169 {
ebrus 0:0a673c671a56 170 DBGMCU->APB1FZ |= DBGMCU_Periph;
ebrus 0:0a673c671a56 171 }
ebrus 0:0a673c671a56 172 else
ebrus 0:0a673c671a56 173 {
ebrus 0:0a673c671a56 174 DBGMCU->APB1FZ &= ~DBGMCU_Periph;
ebrus 0:0a673c671a56 175 }
ebrus 0:0a673c671a56 176 }
ebrus 0:0a673c671a56 177
ebrus 0:0a673c671a56 178 /**
ebrus 0:0a673c671a56 179 * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
ebrus 0:0a673c671a56 180 * @param DBGMCU_Periph: specifies the APB2 peripheral.
ebrus 0:0a673c671a56 181 * This parameter can be any combination of the following values:
ebrus 0:0a673c671a56 182 * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
ebrus 0:0a673c671a56 183 * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
ebrus 0:0a673c671a56 184 * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
ebrus 0:0a673c671a56 185 * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
ebrus 0:0a673c671a56 186 * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
ebrus 0:0a673c671a56 187 * @param NewState: new state of the specified APB2 peripheral in Debug mode.
ebrus 0:0a673c671a56 188 * This parameter can be: ENABLE or DISABLE.
ebrus 0:0a673c671a56 189 * @retval None
ebrus 0:0a673c671a56 190 */
ebrus 0:0a673c671a56 191 void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
ebrus 0:0a673c671a56 192 {
ebrus 0:0a673c671a56 193 /* Check the parameters */
ebrus 0:0a673c671a56 194 assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
ebrus 0:0a673c671a56 195 assert_param(IS_FUNCTIONAL_STATE(NewState));
ebrus 0:0a673c671a56 196
ebrus 0:0a673c671a56 197 if (NewState != DISABLE)
ebrus 0:0a673c671a56 198 {
ebrus 0:0a673c671a56 199 DBGMCU->APB2FZ |= DBGMCU_Periph;
ebrus 0:0a673c671a56 200 }
ebrus 0:0a673c671a56 201 else
ebrus 0:0a673c671a56 202 {
ebrus 0:0a673c671a56 203 DBGMCU->APB2FZ &= ~DBGMCU_Periph;
ebrus 0:0a673c671a56 204 }
ebrus 0:0a673c671a56 205 }
ebrus 0:0a673c671a56 206
ebrus 0:0a673c671a56 207 /**
ebrus 0:0a673c671a56 208 * @}
ebrus 0:0a673c671a56 209 */
ebrus 0:0a673c671a56 210
ebrus 0:0a673c671a56 211 /**
ebrus 0:0a673c671a56 212 * @}
ebrus 0:0a673c671a56 213 */
ebrus 0:0a673c671a56 214
ebrus 0:0a673c671a56 215 /**
ebrus 0:0a673c671a56 216 * @}
ebrus 0:0a673c671a56 217 */
ebrus 0:0a673c671a56 218
ebrus 0:0a673c671a56 219 /**
ebrus 0:0a673c671a56 220 * @}
ebrus 0:0a673c671a56 221 */
ebrus 0:0a673c671a56 222
ebrus 0:0a673c671a56 223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/