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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_comp.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f30x_comp.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 27-February-2014
ebrus 0:0a673c671a56 7 * @brief This file contains all the functions prototypes for the COMP firmware
ebrus 0:0a673c671a56 8 * library.
ebrus 0:0a673c671a56 9 ******************************************************************************
ebrus 0:0a673c671a56 10 * @attention
ebrus 0:0a673c671a56 11 *
ebrus 0:0a673c671a56 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 13 *
ebrus 0:0a673c671a56 14 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 15 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 16 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 17 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 20 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 22 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 23 * without specific prior written permission.
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 *
ebrus 0:0a673c671a56 36 ******************************************************************************
ebrus 0:0a673c671a56 37 */
ebrus 0:0a673c671a56 38
ebrus 0:0a673c671a56 39 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 40 #ifndef __STM32F30x_COMP_H
ebrus 0:0a673c671a56 41 #define __STM32F30x_COMP_H
ebrus 0:0a673c671a56 42
ebrus 0:0a673c671a56 43 #ifdef __cplusplus
ebrus 0:0a673c671a56 44 extern "C" {
ebrus 0:0a673c671a56 45 #endif
ebrus 0:0a673c671a56 46
ebrus 0:0a673c671a56 47 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 48 #include "stm32f30x.h"
ebrus 0:0a673c671a56 49
ebrus 0:0a673c671a56 50 /** @addtogroup STM32F30x_StdPeriph_Driver
ebrus 0:0a673c671a56 51 * @{
ebrus 0:0a673c671a56 52 */
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 /** @addtogroup COMP
ebrus 0:0a673c671a56 55 * @{
ebrus 0:0a673c671a56 56 */
ebrus 0:0a673c671a56 57
ebrus 0:0a673c671a56 58 /* Exported types ------------------------------------------------------------*/
ebrus 0:0a673c671a56 59
ebrus 0:0a673c671a56 60 /**
ebrus 0:0a673c671a56 61 * @brief COMP Init structure definition
ebrus 0:0a673c671a56 62 */
ebrus 0:0a673c671a56 63
ebrus 0:0a673c671a56 64 typedef struct
ebrus 0:0a673c671a56 65 {
ebrus 0:0a673c671a56 66
ebrus 0:0a673c671a56 67 uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
ebrus 0:0a673c671a56 68 This parameter can be a value of @ref COMP_InvertingInput */
ebrus 0:0a673c671a56 69
ebrus 0:0a673c671a56 70 uint32_t COMP_NonInvertingInput; /*!< Selects the non inverting input of the comparator.
ebrus 0:0a673c671a56 71 This parameter can be a value of @ref COMP_NonInvertingInput */
ebrus 0:0a673c671a56 72
ebrus 0:0a673c671a56 73 uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
ebrus 0:0a673c671a56 74 This parameter can be a value of @ref COMP_Output */
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 uint32_t COMP_BlankingSrce; /*!< Selects the output blanking source of the comparator.
ebrus 0:0a673c671a56 77 This parameter can be a value of @ref COMP_BlankingSrce */
ebrus 0:0a673c671a56 78
ebrus 0:0a673c671a56 79 uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
ebrus 0:0a673c671a56 80 This parameter can be a value of @ref COMP_OutputPoloarity */
ebrus 0:0a673c671a56 81
ebrus 0:0a673c671a56 82 uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
ebrus 0:0a673c671a56 83 This parameter can be a value of @ref COMP_Hysteresis */
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85 uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
ebrus 0:0a673c671a56 86 and allows to adjust the speed/consumption.
ebrus 0:0a673c671a56 87 This parameter can be a value of @ref COMP_Mode */
ebrus 0:0a673c671a56 88 }COMP_InitTypeDef;
ebrus 0:0a673c671a56 89
ebrus 0:0a673c671a56 90 /* Exported constants --------------------------------------------------------*/
ebrus 0:0a673c671a56 91
ebrus 0:0a673c671a56 92 /** @defgroup COMP_Exported_Constants
ebrus 0:0a673c671a56 93 * @{
ebrus 0:0a673c671a56 94 */
ebrus 0:0a673c671a56 95
ebrus 0:0a673c671a56 96 /** @defgroup COMP_Selection
ebrus 0:0a673c671a56 97 * @{
ebrus 0:0a673c671a56 98 */
ebrus 0:0a673c671a56 99
ebrus 0:0a673c671a56 100 #define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
ebrus 0:0a673c671a56 101 #define COMP_Selection_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Selection */
ebrus 0:0a673c671a56 102 #define COMP_Selection_COMP3 ((uint32_t)0x00000008) /*!< COMP3 Selection */
ebrus 0:0a673c671a56 103 #define COMP_Selection_COMP4 ((uint32_t)0x0000000C) /*!< COMP4 Selection */
ebrus 0:0a673c671a56 104 #define COMP_Selection_COMP5 ((uint32_t)0x00000010) /*!< COMP5 Selection */
ebrus 0:0a673c671a56 105 #define COMP_Selection_COMP6 ((uint32_t)0x00000014) /*!< COMP6 Selection */
ebrus 0:0a673c671a56 106 #define COMP_Selection_COMP7 ((uint32_t)0x00000018) /*!< COMP7 Selection */
ebrus 0:0a673c671a56 107
ebrus 0:0a673c671a56 108 #define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
ebrus 0:0a673c671a56 109 ((PERIPH) == COMP_Selection_COMP2) || \
ebrus 0:0a673c671a56 110 ((PERIPH) == COMP_Selection_COMP3) || \
ebrus 0:0a673c671a56 111 ((PERIPH) == COMP_Selection_COMP4) || \
ebrus 0:0a673c671a56 112 ((PERIPH) == COMP_Selection_COMP5) || \
ebrus 0:0a673c671a56 113 ((PERIPH) == COMP_Selection_COMP6) || \
ebrus 0:0a673c671a56 114 ((PERIPH) == COMP_Selection_COMP7))
ebrus 0:0a673c671a56 115
ebrus 0:0a673c671a56 116 /**
ebrus 0:0a673c671a56 117 * @}
ebrus 0:0a673c671a56 118 */
ebrus 0:0a673c671a56 119
ebrus 0:0a673c671a56 120 /** @defgroup COMP_InvertingInput
ebrus 0:0a673c671a56 121 * @{
ebrus 0:0a673c671a56 122 */
ebrus 0:0a673c671a56 123
ebrus 0:0a673c671a56 124 #define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
ebrus 0:0a673c671a56 125 #define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMPxINSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
ebrus 0:0a673c671a56 126 #define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMPxINSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
ebrus 0:0a673c671a56 127 #define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
ebrus 0:0a673c671a56 128 #define COMP_InvertingInput_DAC1OUT1 COMP_CSR_COMPxINSEL_2 /*!< DAC1_OUT1 (PA4) connected to comparator inverting input */
ebrus 0:0a673c671a56 129 #define COMP_InvertingInput_DAC1OUT2 ((uint32_t)0x00000050) /*!< DAC1_OUT2 (PA5) connected to comparator inverting input */
ebrus 0:0a673c671a56 130
ebrus 0:0a673c671a56 131 #define COMP_InvertingInput_IO1 ((uint32_t)0x00000060) /*!< I/O1 (PA0 for COMP1, PA2 for COMP2, PD15 for COMP3,
ebrus 0:0a673c671a56 132 PE8 for COMP4, PD13 for COMP5, PD10 for COMP6,
ebrus 0:0a673c671a56 133 PC0 for COMP7) connected to comparator inverting input */
ebrus 0:0a673c671a56 134
ebrus 0:0a673c671a56 135 #define COMP_InvertingInput_IO2 COMP_CSR_COMPxINSEL /*!< I/O2 (PB12 for COMP3, PB2 for COMP4, PB10 for COMP5,
ebrus 0:0a673c671a56 136 PB15 for COMP6) connected to comparator inverting input */
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138 #define COMP_InvertingInput_DAC2OUT1 COMP_CSR_COMPxINSEL_3 /*!< DAC2_OUT1 (PA6) connected to comparator inverting input */
ebrus 0:0a673c671a56 139
ebrus 0:0a673c671a56 140 #define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
ebrus 0:0a673c671a56 141 ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
ebrus 0:0a673c671a56 142 ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
ebrus 0:0a673c671a56 143 ((INPUT) == COMP_InvertingInput_VREFINT) || \
ebrus 0:0a673c671a56 144 ((INPUT) == COMP_InvertingInput_DAC1OUT1) || \
ebrus 0:0a673c671a56 145 ((INPUT) == COMP_InvertingInput_DAC1OUT2) || \
ebrus 0:0a673c671a56 146 ((INPUT) == COMP_InvertingInput_IO1) || \
ebrus 0:0a673c671a56 147 ((INPUT) == COMP_InvertingInput_IO2) || \
ebrus 0:0a673c671a56 148 ((INPUT) == COMP_InvertingInput_DAC2OUT1))
ebrus 0:0a673c671a56 149 /**
ebrus 0:0a673c671a56 150 * @}
ebrus 0:0a673c671a56 151 */
ebrus 0:0a673c671a56 152
ebrus 0:0a673c671a56 153 /** @defgroup COMP_NonInvertingInput
ebrus 0:0a673c671a56 154 * @{
ebrus 0:0a673c671a56 155 */
ebrus 0:0a673c671a56 156
ebrus 0:0a673c671a56 157 #define COMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< I/O1 (PA1 for COMP1, PA7 for COMP2, PB14 for COMP3,
ebrus 0:0a673c671a56 158 PB0 for COMP4, PD12 for COMP5, PD11 for COMP6,
ebrus 0:0a673c671a56 159 PA0 for COMP7) connected to comparator non inverting input */
ebrus 0:0a673c671a56 160
ebrus 0:0a673c671a56 161 #define COMP_NonInvertingInput_IO2 COMP_CSR_COMPxNONINSEL /*!< I/O2 (PA3 for COMP2, PD14 for COMP3, PE7 for COMP4, PB13 for COMP5,
ebrus 0:0a673c671a56 162 PB11 for COMP6, PC1 for COMP7) connected to comparator non inverting input */
ebrus 0:0a673c671a56 163
ebrus 0:0a673c671a56 164 #define IS_COMP_NONINVERTING_INPUT(INPUT) (((INPUT) == COMP_NonInvertingInput_IO1) || \
ebrus 0:0a673c671a56 165 ((INPUT) == COMP_NonInvertingInput_IO2))
ebrus 0:0a673c671a56 166 /**
ebrus 0:0a673c671a56 167 * @}
ebrus 0:0a673c671a56 168 */
ebrus 0:0a673c671a56 169
ebrus 0:0a673c671a56 170 /** @defgroup COMP_Output
ebrus 0:0a673c671a56 171 * @{
ebrus 0:0a673c671a56 172 */
ebrus 0:0a673c671a56 173
ebrus 0:0a673c671a56 174 #define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
ebrus 0:0a673c671a56 175
ebrus 0:0a673c671a56 176 /* Output Redirection common for all comparators COMP1...COMP7 */
ebrus 0:0a673c671a56 177 #define COMP_Output_TIM1BKIN COMP_CSR_COMPxOUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
ebrus 0:0a673c671a56 178 #define COMP_Output_TIM1BKIN2 ((uint32_t)0x00000800) /*!< COMP output connected to TIM1 Break Input 2 (BKIN2) */
ebrus 0:0a673c671a56 179 #define COMP_Output_TIM8BKIN ((uint32_t)0x00000C00) /*!< COMP output connected to TIM8 Break Input (BKIN) */
ebrus 0:0a673c671a56 180 #define COMP_Output_TIM8BKIN2 ((uint32_t)0x00001000) /*!< COMP output connected to TIM8 Break Input 2 (BKIN2) */
ebrus 0:0a673c671a56 181 #define COMP_Output_TIM1BKIN2_TIM8BKIN2 ((uint32_t)0x00001400) /*!< COMP output connected to TIM1 Break Input 2 and TIM8 Break Input 2 */
ebrus 0:0a673c671a56 182
ebrus 0:0a673c671a56 183 /* Output Redirection common for COMP1 and COMP2 */
ebrus 0:0a673c671a56 184 #define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00001800) /*!< COMP output connected to TIM1 OCREF Clear */
ebrus 0:0a673c671a56 185 #define COMP_Output_TIM1IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM1 Input Capture 1 */
ebrus 0:0a673c671a56 186 #define COMP_Output_TIM2IC4 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 4 */
ebrus 0:0a673c671a56 187 #define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM2 OCREF Clear */
ebrus 0:0a673c671a56 188 #define COMP_Output_TIM3IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM3 Input Capture 1 */
ebrus 0:0a673c671a56 189 #define COMP_Output_TIM3OCREFCLR ((uint32_t)0x00002C00) /*!< COMP output connected to TIM3 OCREF Clear */
ebrus 0:0a673c671a56 190
ebrus 0:0a673c671a56 191 /* Output Redirection specific to COMP2 */
ebrus 0:0a673c671a56 192 #define COMP_Output_HRTIM1_FLT6 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT6 */
ebrus 0:0a673c671a56 193 #define COMP_Output_HRTIM1_EE1_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE1_2*/
ebrus 0:0a673c671a56 194 #define COMP_Output_HRTIM1_EE6_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE6_2 */
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 /* Output Redirection specific to COMP3 */
ebrus 0:0a673c671a56 197 #define COMP_Output_TIM4IC1 ((uint32_t)0x00001C00) /*!< COMP output connected to TIM4 Input Capture 1 */
ebrus 0:0a673c671a56 198 #define COMP_Output_TIM3IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM3 Input Capture 2 */
ebrus 0:0a673c671a56 199 #define COMP_Output_TIM15IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 Input Capture 1 */
ebrus 0:0a673c671a56 200 #define COMP_Output_TIM15BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM15 Break Input (BKIN) */
ebrus 0:0a673c671a56 201
ebrus 0:0a673c671a56 202 /* Output Redirection specific to COMP4 */
ebrus 0:0a673c671a56 203 #define COMP_Output_TIM3IC3 ((uint32_t)0x00001800) /*!< COMP output connected to TIM3 Input Capture 3 */
ebrus 0:0a673c671a56 204 #define COMP_Output_TIM8OCREFCLR ((uint32_t)0x00001C00) /*!< COMP output connected to TIM8 OCREF Clear */
ebrus 0:0a673c671a56 205 #define COMP_Output_TIM15IC2 ((uint32_t)0x00002000) /*!< COMP output connected to TIM15 Input Capture 2 */
ebrus 0:0a673c671a56 206 #define COMP_Output_TIM4IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 2 */
ebrus 0:0a673c671a56 207 #define COMP_Output_TIM15OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM15 OCREF Clear */
ebrus 0:0a673c671a56 208
ebrus 0:0a673c671a56 209 #define COMP_Output_HRTIM1_FLT7 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT7 */
ebrus 0:0a673c671a56 210 #define COMP_Output_HRTIM1_EE2_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE2_2*/
ebrus 0:0a673c671a56 211 #define COMP_Output_HRTIM1_EE7_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE7_2 */
ebrus 0:0a673c671a56 212
ebrus 0:0a673c671a56 213 /* Output Redirection specific to COMP5 */
ebrus 0:0a673c671a56 214 #define COMP_Output_TIM2IC1 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 1 */
ebrus 0:0a673c671a56 215 #define COMP_Output_TIM17IC1 ((uint32_t)0x00002000) /*!< COMP output connected to TIM17 Input Capture 1 */
ebrus 0:0a673c671a56 216 #define COMP_Output_TIM4IC3 ((uint32_t)0x00002400) /*!< COMP output connected to TIM4 Input Capture 3 */
ebrus 0:0a673c671a56 217 #define COMP_Output_TIM16BKIN ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Break Input (BKIN) */
ebrus 0:0a673c671a56 218
ebrus 0:0a673c671a56 219 /* Output Redirection specific to COMP6 */
ebrus 0:0a673c671a56 220 #define COMP_Output_TIM2IC2 ((uint32_t)0x00001800) /*!< COMP output connected to TIM2 Input Capture 2 */
ebrus 0:0a673c671a56 221 #define COMP_Output_COMP6TIM2OCREFCLR ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 OCREF Clear */
ebrus 0:0a673c671a56 222 #define COMP_Output_TIM16OCREFCLR ((uint32_t)0x00002400) /*!< COMP output connected to TIM16 OCREF Clear */
ebrus 0:0a673c671a56 223 #define COMP_Output_TIM16IC1 ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 Input Capture 1 */
ebrus 0:0a673c671a56 224 #define COMP_Output_TIM4IC4 ((uint32_t)0x00002C00) /*!< COMP output connected to TIM4 Input Capture 4 */
ebrus 0:0a673c671a56 225
ebrus 0:0a673c671a56 226 #define COMP_Output_HRTIM1_FLT8 ((uint32_t)0x00003000) /*!< COMP output connected to HRTIM1 FLT8 */
ebrus 0:0a673c671a56 227 #define COMP_Output_HRTIM1_EE3_2 ((uint32_t)0x00003400) /*!< COMP output connected to HRTIM1 EE3_2*/
ebrus 0:0a673c671a56 228 #define COMP_Output_HRTIM1_EE8_2 ((uint32_t)0x00003800) /*!< COMP output connected to HRTIM1 EE8_2 */
ebrus 0:0a673c671a56 229
ebrus 0:0a673c671a56 230 /* Output Redirection specific to COMP7 */
ebrus 0:0a673c671a56 231 #define COMP_Output_TIM2IC3 ((uint32_t)0x00002000) /*!< COMP output connected to TIM2 Input Capture 3 */
ebrus 0:0a673c671a56 232 #define COMP_Output_TIM1IC2 ((uint32_t)0x00002400) /*!< COMP output connected to TIM1 Input Capture 2 */
ebrus 0:0a673c671a56 233 #define COMP_Output_TIM17OCREFCLR ((uint32_t)0x00002800) /*!< COMP output connected to TIM16 OCREF Clear */
ebrus 0:0a673c671a56 234 #define COMP_Output_TIM17BKIN ((uint32_t)0x00002C00) /*!< COMP output connected to TIM16 Break Input (BKIN) */
ebrus 0:0a673c671a56 235
ebrus 0:0a673c671a56 236 #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
ebrus 0:0a673c671a56 237 ((OUTPUT) == COMP_Output_TIM1BKIN) || \
ebrus 0:0a673c671a56 238 ((OUTPUT) == COMP_Output_TIM1IC1) || \
ebrus 0:0a673c671a56 239 ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
ebrus 0:0a673c671a56 240 ((OUTPUT) == COMP_Output_TIM2IC4) || \
ebrus 0:0a673c671a56 241 ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
ebrus 0:0a673c671a56 242 ((OUTPUT) == COMP_Output_COMP6TIM2OCREFCLR) || \
ebrus 0:0a673c671a56 243 ((OUTPUT) == COMP_Output_TIM3IC1) || \
ebrus 0:0a673c671a56 244 ((OUTPUT) == COMP_Output_TIM3OCREFCLR) || \
ebrus 0:0a673c671a56 245 ((OUTPUT) == COMP_Output_TIM8BKIN) || \
ebrus 0:0a673c671a56 246 ((OUTPUT) == COMP_Output_TIM1BKIN2) || \
ebrus 0:0a673c671a56 247 ((OUTPUT) == COMP_Output_TIM8BKIN2) || \
ebrus 0:0a673c671a56 248 ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
ebrus 0:0a673c671a56 249 ((OUTPUT) == COMP_Output_TIM1BKIN2_TIM8BKIN2) || \
ebrus 0:0a673c671a56 250 ((OUTPUT) == COMP_Output_TIM3IC2) || \
ebrus 0:0a673c671a56 251 ((OUTPUT) == COMP_Output_TIM4IC1) || \
ebrus 0:0a673c671a56 252 ((OUTPUT) == COMP_Output_TIM15IC1) || \
ebrus 0:0a673c671a56 253 ((OUTPUT) == COMP_Output_TIM15BKIN) || \
ebrus 0:0a673c671a56 254 ((OUTPUT) == COMP_Output_TIM8OCREFCLR) || \
ebrus 0:0a673c671a56 255 ((OUTPUT) == COMP_Output_TIM3IC3) || \
ebrus 0:0a673c671a56 256 ((OUTPUT) == COMP_Output_TIM4IC1) || \
ebrus 0:0a673c671a56 257 ((OUTPUT) == COMP_Output_TIM15IC1) || \
ebrus 0:0a673c671a56 258 ((OUTPUT) == COMP_Output_TIM2IC1) || \
ebrus 0:0a673c671a56 259 ((OUTPUT) == COMP_Output_TIM4IC3) || \
ebrus 0:0a673c671a56 260 ((OUTPUT) == COMP_Output_TIM16BKIN) || \
ebrus 0:0a673c671a56 261 ((OUTPUT) == COMP_Output_TIM17IC1) || \
ebrus 0:0a673c671a56 262 ((OUTPUT) == COMP_Output_TIM2IC2) || \
ebrus 0:0a673c671a56 263 ((OUTPUT) == COMP_Output_TIM16IC1) || \
ebrus 0:0a673c671a56 264 ((OUTPUT) == COMP_Output_TIM4IC4) || \
ebrus 0:0a673c671a56 265 ((OUTPUT) == COMP_Output_TIM16OCREFCLR) || \
ebrus 0:0a673c671a56 266 ((OUTPUT) == COMP_Output_TIM2IC3) || \
ebrus 0:0a673c671a56 267 ((OUTPUT) == COMP_Output_TIM1IC2) || \
ebrus 0:0a673c671a56 268 ((OUTPUT) == COMP_Output_TIM17BKIN) || \
ebrus 0:0a673c671a56 269 ((OUTPUT) == COMP_Output_TIM17OCREFCLR) || \
ebrus 0:0a673c671a56 270 ((OUTPUT) == COMP_Output_HRTIM1_FLT6) || \
ebrus 0:0a673c671a56 271 ((OUTPUT) == COMP_Output_HRTIM1_EE1_2) || \
ebrus 0:0a673c671a56 272 ((OUTPUT) == COMP_Output_HRTIM1_EE6_2) || \
ebrus 0:0a673c671a56 273 ((OUTPUT) == COMP_Output_HRTIM1_FLT7) || \
ebrus 0:0a673c671a56 274 ((OUTPUT) == COMP_Output_HRTIM1_EE2_2) || \
ebrus 0:0a673c671a56 275 ((OUTPUT) == COMP_Output_HRTIM1_EE7_2) || \
ebrus 0:0a673c671a56 276 ((OUTPUT) == COMP_Output_HRTIM1_FLT8) || \
ebrus 0:0a673c671a56 277 ((OUTPUT) == COMP_Output_HRTIM1_EE3_2) || \
ebrus 0:0a673c671a56 278 ((OUTPUT) == COMP_Output_HRTIM1_EE8_2))
ebrus 0:0a673c671a56 279
ebrus 0:0a673c671a56 280 /**
ebrus 0:0a673c671a56 281 * @}
ebrus 0:0a673c671a56 282 */
ebrus 0:0a673c671a56 283
ebrus 0:0a673c671a56 284 /** @defgroup COMP_BlankingSrce
ebrus 0:0a673c671a56 285 * @{
ebrus 0:0a673c671a56 286 */
ebrus 0:0a673c671a56 287
ebrus 0:0a673c671a56 288 /* No blanking source can be selected for all comparators */
ebrus 0:0a673c671a56 289 #define COMP_BlankingSrce_None ((uint32_t)0x00000000) /*!< No blanking source */
ebrus 0:0a673c671a56 290
ebrus 0:0a673c671a56 291 /* Blanking source common for COMP1, COMP2, COMP3 and COMP7 */
ebrus 0:0a673c671a56 292 #define COMP_BlankingSrce_TIM1OC5 COMP_CSR_COMPxBLANKING_0 /*!< TIM1 OC5 selected as blanking source for compartor */
ebrus 0:0a673c671a56 293
ebrus 0:0a673c671a56 294 /* Blanking source common for COMP1 and COMP2 */
ebrus 0:0a673c671a56 295 #define COMP_BlankingSrce_TIM2OC3 COMP_CSR_COMPxBLANKING_1 /*!< TIM2 OC5 selected as blanking source for compartor */
ebrus 0:0a673c671a56 296
ebrus 0:0a673c671a56 297 /* Blanking source common for COMP1, COMP2 and COMP5 */
ebrus 0:0a673c671a56 298 #define COMP_BlankingSrce_TIM3OC3 ((uint32_t)0x000C0000) /*!< TIM2 OC3 selected as blanking source for compartor */
ebrus 0:0a673c671a56 299
ebrus 0:0a673c671a56 300 /* Blanking source common for COMP3 and COMP6 */
ebrus 0:0a673c671a56 301 #define COMP_BlankingSrce_TIM2OC4 ((uint32_t)0x000C0000) /*!< TIM2 OC4 selected as blanking source for compartor */
ebrus 0:0a673c671a56 302
ebrus 0:0a673c671a56 303 /* Blanking source common for COMP4, COMP5, COMP6 and COMP7 */
ebrus 0:0a673c671a56 304 #define COMP_BlankingSrce_TIM8OC5 COMP_CSR_COMPxBLANKING_1 /*!< TIM8 OC5 selected as blanking source for compartor */
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306 /* Blanking source for COMP4 */
ebrus 0:0a673c671a56 307 #define COMP_BlankingSrce_TIM3OC4 COMP_CSR_COMPxBLANKING_0 /*!< TIM3 OC4 selected as blanking source for compartor */
ebrus 0:0a673c671a56 308 #define COMP_BlankingSrce_TIM15OC1 ((uint32_t)0x000C0000) /*!< TIM15 OC1 selected as blanking source for compartor */
ebrus 0:0a673c671a56 309
ebrus 0:0a673c671a56 310 /* Blanking source common for COMP6 and COMP7 */
ebrus 0:0a673c671a56 311 #define COMP_BlankingSrce_TIM15OC2 COMP_CSR_COMPxBLANKING_2 /*!< TIM15 OC2 selected as blanking source for compartor */
ebrus 0:0a673c671a56 312
ebrus 0:0a673c671a56 313 #define IS_COMP_BLANKING_SOURCE(SOURCE) (((SOURCE) == COMP_BlankingSrce_None) || \
ebrus 0:0a673c671a56 314 ((SOURCE) == COMP_BlankingSrce_TIM1OC5) || \
ebrus 0:0a673c671a56 315 ((SOURCE) == COMP_BlankingSrce_TIM2OC3) || \
ebrus 0:0a673c671a56 316 ((SOURCE) == COMP_BlankingSrce_TIM3OC3) || \
ebrus 0:0a673c671a56 317 ((SOURCE) == COMP_BlankingSrce_TIM2OC4) || \
ebrus 0:0a673c671a56 318 ((SOURCE) == COMP_BlankingSrce_TIM8OC5) || \
ebrus 0:0a673c671a56 319 ((SOURCE) == COMP_BlankingSrce_TIM3OC4) || \
ebrus 0:0a673c671a56 320 ((SOURCE) == COMP_BlankingSrce_TIM15OC1) || \
ebrus 0:0a673c671a56 321 ((SOURCE) == COMP_BlankingSrce_TIM15OC2))
ebrus 0:0a673c671a56 322 /**
ebrus 0:0a673c671a56 323 * @}
ebrus 0:0a673c671a56 324 */
ebrus 0:0a673c671a56 325
ebrus 0:0a673c671a56 326 /** @defgroup COMP_OutputPoloarity
ebrus 0:0a673c671a56 327 * @{
ebrus 0:0a673c671a56 328 */
ebrus 0:0a673c671a56 329 #define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
ebrus 0:0a673c671a56 330 #define COMP_OutputPol_Inverted COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
ebrus 0:0a673c671a56 331
ebrus 0:0a673c671a56 332 #define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
ebrus 0:0a673c671a56 333 ((POL) == COMP_OutputPol_Inverted))
ebrus 0:0a673c671a56 334
ebrus 0:0a673c671a56 335 /**
ebrus 0:0a673c671a56 336 * @}
ebrus 0:0a673c671a56 337 */
ebrus 0:0a673c671a56 338
ebrus 0:0a673c671a56 339 /** @defgroup COMP_Hysteresis
ebrus 0:0a673c671a56 340 * @{
ebrus 0:0a673c671a56 341 */
ebrus 0:0a673c671a56 342 /* Please refer to the electrical characteristics in the device datasheet for
ebrus 0:0a673c671a56 343 the hysteresis level */
ebrus 0:0a673c671a56 344 #define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
ebrus 0:0a673c671a56 345 #define COMP_Hysteresis_Low COMP_CSR_COMPxHYST_0 /*!< Hysteresis level low */
ebrus 0:0a673c671a56 346 #define COMP_Hysteresis_Medium COMP_CSR_COMPxHYST_1 /*!< Hysteresis level medium */
ebrus 0:0a673c671a56 347 #define COMP_Hysteresis_High COMP_CSR_COMPxHYST /*!< Hysteresis level high */
ebrus 0:0a673c671a56 348
ebrus 0:0a673c671a56 349 #define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
ebrus 0:0a673c671a56 350 ((HYSTERESIS) == COMP_Hysteresis_Low) || \
ebrus 0:0a673c671a56 351 ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
ebrus 0:0a673c671a56 352 ((HYSTERESIS) == COMP_Hysteresis_High))
ebrus 0:0a673c671a56 353 /**
ebrus 0:0a673c671a56 354 * @}
ebrus 0:0a673c671a56 355 */
ebrus 0:0a673c671a56 356
ebrus 0:0a673c671a56 357 /** @defgroup COMP_Mode
ebrus 0:0a673c671a56 358 * @{
ebrus 0:0a673c671a56 359 */
ebrus 0:0a673c671a56 360 /* Please refer to the electrical characteristics in the device datasheet for
ebrus 0:0a673c671a56 361 the power consumption values */
ebrus 0:0a673c671a56 362 #define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
ebrus 0:0a673c671a56 363 #define COMP_Mode_MediumSpeed COMP_CSR_COMPxMODE_0 /*!< Medium Speed */
ebrus 0:0a673c671a56 364 #define COMP_Mode_LowPower COMP_CSR_COMPxMODE_1 /*!< Low power mode */
ebrus 0:0a673c671a56 365 #define COMP_Mode_UltraLowPower COMP_CSR_COMPxMODE /*!< Ultra-low power mode */
ebrus 0:0a673c671a56 366
ebrus 0:0a673c671a56 367 #define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
ebrus 0:0a673c671a56 368 ((MODE) == COMP_Mode_LowPower) || \
ebrus 0:0a673c671a56 369 ((MODE) == COMP_Mode_MediumSpeed) || \
ebrus 0:0a673c671a56 370 ((MODE) == COMP_Mode_HighSpeed))
ebrus 0:0a673c671a56 371 /**
ebrus 0:0a673c671a56 372 * @}
ebrus 0:0a673c671a56 373 */
ebrus 0:0a673c671a56 374
ebrus 0:0a673c671a56 375 /** @defgroup COMP_OutputLevel
ebrus 0:0a673c671a56 376 * @{
ebrus 0:0a673c671a56 377 */
ebrus 0:0a673c671a56 378 /* When output polarity is not inverted, comparator output is high when
ebrus 0:0a673c671a56 379 the non-inverting input is at a higher voltage than the inverting input */
ebrus 0:0a673c671a56 380 #define COMP_OutputLevel_High COMP_CSR_COMPxOUT
ebrus 0:0a673c671a56 381 /* When output polarity is not inverted, comparator output is low when
ebrus 0:0a673c671a56 382 the non-inverting input is at a lower voltage than the inverting input*/
ebrus 0:0a673c671a56 383 #define COMP_OutputLevel_Low ((uint32_t)0x00000000)
ebrus 0:0a673c671a56 384
ebrus 0:0a673c671a56 385 /**
ebrus 0:0a673c671a56 386 * @}
ebrus 0:0a673c671a56 387 */
ebrus 0:0a673c671a56 388
ebrus 0:0a673c671a56 389 /** @defgroup COMP_WindowMode
ebrus 0:0a673c671a56 390 * @{
ebrus 0:0a673c671a56 391 */
ebrus 0:0a673c671a56 392 #define IS_COMP_WINDOW(WINDOW) (((WINDOW) == COMP_Selection_COMP2) || \
ebrus 0:0a673c671a56 393 ((WINDOW) == COMP_Selection_COMP4) || \
ebrus 0:0a673c671a56 394 ((WINDOW) == COMP_Selection_COMP6))
ebrus 0:0a673c671a56 395 /**
ebrus 0:0a673c671a56 396 * @}
ebrus 0:0a673c671a56 397 */
ebrus 0:0a673c671a56 398
ebrus 0:0a673c671a56 399 /**
ebrus 0:0a673c671a56 400 * @}
ebrus 0:0a673c671a56 401 */
ebrus 0:0a673c671a56 402
ebrus 0:0a673c671a56 403 /* Exported macro ------------------------------------------------------------*/
ebrus 0:0a673c671a56 404 /* Exported functions ------------------------------------------------------- */
ebrus 0:0a673c671a56 405
ebrus 0:0a673c671a56 406 /* Function used to set the COMP configuration to the default reset state ****/
ebrus 0:0a673c671a56 407 void COMP_DeInit(uint32_t COMP_Selection);
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 /* Initialization and Configuration functions *********************************/
ebrus 0:0a673c671a56 410 void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
ebrus 0:0a673c671a56 411 void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
ebrus 0:0a673c671a56 412 void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
ebrus 0:0a673c671a56 413 void COMP_SwitchCmd(uint32_t COMP_Selection, FunctionalState NewState);
ebrus 0:0a673c671a56 414 uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
ebrus 0:0a673c671a56 415
ebrus 0:0a673c671a56 416 /* Window mode control function ***********************************************/
ebrus 0:0a673c671a56 417 void COMP_WindowCmd(uint32_t COMP_Selection, FunctionalState NewState);
ebrus 0:0a673c671a56 418
ebrus 0:0a673c671a56 419 /* COMP configuration locking function ****************************************/
ebrus 0:0a673c671a56 420 void COMP_LockConfig(uint32_t COMP_Selection);
ebrus 0:0a673c671a56 421
ebrus 0:0a673c671a56 422 #ifdef __cplusplus
ebrus 0:0a673c671a56 423 }
ebrus 0:0a673c671a56 424 #endif
ebrus 0:0a673c671a56 425
ebrus 0:0a673c671a56 426 #endif /*__STM32F30x_COMP_H */
ebrus 0:0a673c671a56 427
ebrus 0:0a673c671a56 428 /**
ebrus 0:0a673c671a56 429 * @}
ebrus 0:0a673c671a56 430 */
ebrus 0:0a673c671a56 431
ebrus 0:0a673c671a56 432 /**
ebrus 0:0a673c671a56 433 * @}
ebrus 0:0a673c671a56 434 */
ebrus 0:0a673c671a56 435
ebrus 0:0a673c671a56 436 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/