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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F411RE/stm32f4xx_hal_cortex.c@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file stm32f4xx_hal_cortex.c
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V1.1.0
ebrus 0:0a673c671a56 6 * @date 19-June-2014
ebrus 0:0a673c671a56 7 * @brief CORTEX HAL module driver.
ebrus 0:0a673c671a56 8 * This file provides firmware functions to manage the following
ebrus 0:0a673c671a56 9 * functionalities of the CORTEX:
ebrus 0:0a673c671a56 10 * + Initialization and de-initialization functions
ebrus 0:0a673c671a56 11 * + Peripheral Control functions
ebrus 0:0a673c671a56 12 *
ebrus 0:0a673c671a56 13 @verbatim
ebrus 0:0a673c671a56 14 ==============================================================================
ebrus 0:0a673c671a56 15 ##### How to use this driver #####
ebrus 0:0a673c671a56 16 ==============================================================================
ebrus 0:0a673c671a56 17
ebrus 0:0a673c671a56 18 [..]
ebrus 0:0a673c671a56 19 *** How to configure Interrupts using CORTEX HAL driver ***
ebrus 0:0a673c671a56 20 ===========================================================
ebrus 0:0a673c671a56 21 [..]
ebrus 0:0a673c671a56 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
ebrus 0:0a673c671a56 23 The Cortex-M4 exceptions are managed by CMSIS functions.
ebrus 0:0a673c671a56 24
ebrus 0:0a673c671a56 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
ebrus 0:0a673c671a56 26 function according to the following table.
ebrus 0:0a673c671a56 27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
ebrus 0:0a673c671a56 28 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
ebrus 0:0a673c671a56 29 (#) please refer to programing manual for details in how to configure priority.
ebrus 0:0a673c671a56 30
ebrus 0:0a673c671a56 31 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
ebrus 0:0a673c671a56 32 The pending IRQ priority will be managed only by the sub priority.
ebrus 0:0a673c671a56 33
ebrus 0:0a673c671a56 34 -@- IRQ priority order (sorted by highest to lowest priority):
ebrus 0:0a673c671a56 35 (+@) Lowest pre-emption priority
ebrus 0:0a673c671a56 36 (+@) Lowest sub priority
ebrus 0:0a673c671a56 37 (+@) Lowest hardware priority (IRQ number)
ebrus 0:0a673c671a56 38
ebrus 0:0a673c671a56 39 [..]
ebrus 0:0a673c671a56 40 *** How to configure Systick using CORTEX HAL driver ***
ebrus 0:0a673c671a56 41 ========================================================
ebrus 0:0a673c671a56 42 [..]
ebrus 0:0a673c671a56 43 Setup SysTick Timer for time base.
ebrus 0:0a673c671a56 44
ebrus 0:0a673c671a56 45 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
ebrus 0:0a673c671a56 46 is a CMSIS function that:
ebrus 0:0a673c671a56 47 (++) Configures the SysTick Reload register with value passed as function parameter.
ebrus 0:0a673c671a56 48 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
ebrus 0:0a673c671a56 49 (++) Resets the SysTick Counter register.
ebrus 0:0a673c671a56 50 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
ebrus 0:0a673c671a56 51 (++) Enables the SysTick Interrupt.
ebrus 0:0a673c671a56 52 (++) Starts the SysTick Counter.
ebrus 0:0a673c671a56 53
ebrus 0:0a673c671a56 54 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
ebrus 0:0a673c671a56 55 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
ebrus 0:0a673c671a56 56 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
ebrus 0:0a673c671a56 57 inside the stm32f4xx_hal_cortex.h file.
ebrus 0:0a673c671a56 58
ebrus 0:0a673c671a56 59 (+) You can change the SysTick IRQ priority by calling the
ebrus 0:0a673c671a56 60 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
ebrus 0:0a673c671a56 61 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
ebrus 0:0a673c671a56 62
ebrus 0:0a673c671a56 63 (+) To adjust the SysTick time base, use the following formula:
ebrus 0:0a673c671a56 64
ebrus 0:0a673c671a56 65 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
ebrus 0:0a673c671a56 66 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
ebrus 0:0a673c671a56 67 (++) Reload Value should not exceed 0xFFFFFF
ebrus 0:0a673c671a56 68
ebrus 0:0a673c671a56 69 @endverbatim
ebrus 0:0a673c671a56 70 ******************************************************************************
ebrus 0:0a673c671a56 71 * @attention
ebrus 0:0a673c671a56 72 *
ebrus 0:0a673c671a56 73 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
ebrus 0:0a673c671a56 74 *
ebrus 0:0a673c671a56 75 * Redistribution and use in source and binary forms, with or without modification,
ebrus 0:0a673c671a56 76 * are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 77 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 78 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 80 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 81 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 83 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 84 * without specific prior written permission.
ebrus 0:0a673c671a56 85 *
ebrus 0:0a673c671a56 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 96 *
ebrus 0:0a673c671a56 97 ******************************************************************************
ebrus 0:0a673c671a56 98 */
ebrus 0:0a673c671a56 99
ebrus 0:0a673c671a56 100 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 101 #include "stm32f4xx_hal.h"
ebrus 0:0a673c671a56 102
ebrus 0:0a673c671a56 103 /** @addtogroup STM32F4xx_HAL_Driver
ebrus 0:0a673c671a56 104 * @{
ebrus 0:0a673c671a56 105 */
ebrus 0:0a673c671a56 106
ebrus 0:0a673c671a56 107 /** @defgroup CORTEX
ebrus 0:0a673c671a56 108 * @brief CORTEX HAL module driver
ebrus 0:0a673c671a56 109 * @{
ebrus 0:0a673c671a56 110 */
ebrus 0:0a673c671a56 111
ebrus 0:0a673c671a56 112 #ifdef HAL_CORTEX_MODULE_ENABLED
ebrus 0:0a673c671a56 113
ebrus 0:0a673c671a56 114 /* Private typedef -----------------------------------------------------------*/
ebrus 0:0a673c671a56 115 /* Private define ------------------------------------------------------------*/
ebrus 0:0a673c671a56 116 /* Private macro -------------------------------------------------------------*/
ebrus 0:0a673c671a56 117 /* Private variables ---------------------------------------------------------*/
ebrus 0:0a673c671a56 118 /* Private function prototypes -----------------------------------------------*/
ebrus 0:0a673c671a56 119 /* Private functions ---------------------------------------------------------*/
ebrus 0:0a673c671a56 120
ebrus 0:0a673c671a56 121 /** @defgroup CORTEX_Private_Functions
ebrus 0:0a673c671a56 122 * @{
ebrus 0:0a673c671a56 123 */
ebrus 0:0a673c671a56 124
ebrus 0:0a673c671a56 125
ebrus 0:0a673c671a56 126 /** @defgroup CORTEX_Group1 Initialization and de-initialization functions
ebrus 0:0a673c671a56 127 * @brief Initialization and Configuration functions
ebrus 0:0a673c671a56 128 *
ebrus 0:0a673c671a56 129 @verbatim
ebrus 0:0a673c671a56 130 ==============================================================================
ebrus 0:0a673c671a56 131 ##### Initialization and de-initialization functions #####
ebrus 0:0a673c671a56 132 ==============================================================================
ebrus 0:0a673c671a56 133 [..]
ebrus 0:0a673c671a56 134 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
ebrus 0:0a673c671a56 135 Systick functionalities
ebrus 0:0a673c671a56 136
ebrus 0:0a673c671a56 137 @endverbatim
ebrus 0:0a673c671a56 138 * @{
ebrus 0:0a673c671a56 139 */
ebrus 0:0a673c671a56 140
ebrus 0:0a673c671a56 141
ebrus 0:0a673c671a56 142 /**
ebrus 0:0a673c671a56 143 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
ebrus 0:0a673c671a56 144 * using the required unlock sequence.
ebrus 0:0a673c671a56 145 * @param PriorityGroup: The priority grouping bits length.
ebrus 0:0a673c671a56 146 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 147 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
ebrus 0:0a673c671a56 148 * 4 bits for subpriority
ebrus 0:0a673c671a56 149 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
ebrus 0:0a673c671a56 150 * 3 bits for subpriority
ebrus 0:0a673c671a56 151 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
ebrus 0:0a673c671a56 152 * 2 bits for subpriority
ebrus 0:0a673c671a56 153 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
ebrus 0:0a673c671a56 154 * 1 bits for subpriority
ebrus 0:0a673c671a56 155 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
ebrus 0:0a673c671a56 156 * 0 bits for subpriority
ebrus 0:0a673c671a56 157 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
ebrus 0:0a673c671a56 158 * The pending IRQ priority will be managed only by the subpriority.
ebrus 0:0a673c671a56 159 * @retval None
ebrus 0:0a673c671a56 160 */
ebrus 0:0a673c671a56 161 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
ebrus 0:0a673c671a56 162 {
ebrus 0:0a673c671a56 163 /* Check the parameters */
ebrus 0:0a673c671a56 164 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
ebrus 0:0a673c671a56 165
ebrus 0:0a673c671a56 166 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
ebrus 0:0a673c671a56 167 NVIC_SetPriorityGrouping(PriorityGroup);
ebrus 0:0a673c671a56 168 }
ebrus 0:0a673c671a56 169
ebrus 0:0a673c671a56 170 /**
ebrus 0:0a673c671a56 171 * @brief Sets the priority of an interrupt.
ebrus 0:0a673c671a56 172 * @param IRQn: External interrupt number.
ebrus 0:0a673c671a56 173 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 174 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 175 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
ebrus 0:0a673c671a56 176 * This parameter can be a value between 0 and 15
ebrus 0:0a673c671a56 177 * A lower priority value indicates a higher priority
ebrus 0:0a673c671a56 178 * @param SubPriority: the subpriority level for the IRQ channel.
ebrus 0:0a673c671a56 179 * This parameter can be a value between 0 and 15
ebrus 0:0a673c671a56 180 * A lower priority value indicates a higher priority.
ebrus 0:0a673c671a56 181 * @retval None
ebrus 0:0a673c671a56 182 */
ebrus 0:0a673c671a56 183 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
ebrus 0:0a673c671a56 184 {
ebrus 0:0a673c671a56 185 uint32_t prioritygroup = 0x00;
ebrus 0:0a673c671a56 186
ebrus 0:0a673c671a56 187 /* Check the parameters */
ebrus 0:0a673c671a56 188 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
ebrus 0:0a673c671a56 189 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
ebrus 0:0a673c671a56 190
ebrus 0:0a673c671a56 191 prioritygroup = NVIC_GetPriorityGrouping();
ebrus 0:0a673c671a56 192
ebrus 0:0a673c671a56 193 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
ebrus 0:0a673c671a56 194 }
ebrus 0:0a673c671a56 195
ebrus 0:0a673c671a56 196 /**
ebrus 0:0a673c671a56 197 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
ebrus 0:0a673c671a56 198 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
ebrus 0:0a673c671a56 199 * function should be called before.
ebrus 0:0a673c671a56 200 * @param IRQn External interrupt number.
ebrus 0:0a673c671a56 201 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 202 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 203 * @retval None
ebrus 0:0a673c671a56 204 */
ebrus 0:0a673c671a56 205 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 206 {
ebrus 0:0a673c671a56 207 /* Enable interrupt */
ebrus 0:0a673c671a56 208 NVIC_EnableIRQ(IRQn);
ebrus 0:0a673c671a56 209 }
ebrus 0:0a673c671a56 210
ebrus 0:0a673c671a56 211 /**
ebrus 0:0a673c671a56 212 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
ebrus 0:0a673c671a56 213 * @param IRQn External interrupt number.
ebrus 0:0a673c671a56 214 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 215 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 216 * @retval None
ebrus 0:0a673c671a56 217 */
ebrus 0:0a673c671a56 218 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 219 {
ebrus 0:0a673c671a56 220 /* Disable interrupt */
ebrus 0:0a673c671a56 221 NVIC_DisableIRQ(IRQn);
ebrus 0:0a673c671a56 222 }
ebrus 0:0a673c671a56 223
ebrus 0:0a673c671a56 224 /**
ebrus 0:0a673c671a56 225 * @brief Initiates a system reset request to reset the MCU.
ebrus 0:0a673c671a56 226 * @param None
ebrus 0:0a673c671a56 227 * @retval None
ebrus 0:0a673c671a56 228 */
ebrus 0:0a673c671a56 229 void HAL_NVIC_SystemReset(void)
ebrus 0:0a673c671a56 230 {
ebrus 0:0a673c671a56 231 /* System Reset */
ebrus 0:0a673c671a56 232 NVIC_SystemReset();
ebrus 0:0a673c671a56 233 }
ebrus 0:0a673c671a56 234
ebrus 0:0a673c671a56 235 /**
ebrus 0:0a673c671a56 236 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
ebrus 0:0a673c671a56 237 * Counter is in free running mode to generate periodic interrupts.
ebrus 0:0a673c671a56 238 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
ebrus 0:0a673c671a56 239 * @retval status: - 0 Function succeeded.
ebrus 0:0a673c671a56 240 * - 1 Function failed.
ebrus 0:0a673c671a56 241 */
ebrus 0:0a673c671a56 242 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
ebrus 0:0a673c671a56 243 {
ebrus 0:0a673c671a56 244 return SysTick_Config(TicksNumb);
ebrus 0:0a673c671a56 245 }
ebrus 0:0a673c671a56 246 /**
ebrus 0:0a673c671a56 247 * @}
ebrus 0:0a673c671a56 248 */
ebrus 0:0a673c671a56 249
ebrus 0:0a673c671a56 250 /** @defgroup CORTEX_Group2 Peripheral Control functions
ebrus 0:0a673c671a56 251 * @brief Cortex control functions
ebrus 0:0a673c671a56 252 *
ebrus 0:0a673c671a56 253 @verbatim
ebrus 0:0a673c671a56 254 ==============================================================================
ebrus 0:0a673c671a56 255 ##### Peripheral Control functions #####
ebrus 0:0a673c671a56 256 ==============================================================================
ebrus 0:0a673c671a56 257 [..]
ebrus 0:0a673c671a56 258 This subsection provides a set of functions allowing to control the CORTEX
ebrus 0:0a673c671a56 259 (NVIC, SYSTICK) functionalities.
ebrus 0:0a673c671a56 260
ebrus 0:0a673c671a56 261
ebrus 0:0a673c671a56 262 @endverbatim
ebrus 0:0a673c671a56 263 * @{
ebrus 0:0a673c671a56 264 */
ebrus 0:0a673c671a56 265
ebrus 0:0a673c671a56 266 /**
ebrus 0:0a673c671a56 267 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
ebrus 0:0a673c671a56 268 * @param None
ebrus 0:0a673c671a56 269 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
ebrus 0:0a673c671a56 270 */
ebrus 0:0a673c671a56 271 uint32_t HAL_NVIC_GetPriorityGrouping(void)
ebrus 0:0a673c671a56 272 {
ebrus 0:0a673c671a56 273 /* Get the PRIGROUP[10:8] field value */
ebrus 0:0a673c671a56 274 return NVIC_GetPriorityGrouping();
ebrus 0:0a673c671a56 275 }
ebrus 0:0a673c671a56 276
ebrus 0:0a673c671a56 277 /**
ebrus 0:0a673c671a56 278 * @brief Gets the priority of an interrupt.
ebrus 0:0a673c671a56 279 * @param IRQn: External interrupt number.
ebrus 0:0a673c671a56 280 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 281 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 282 * @param PriorityGroup: the priority grouping bits length.
ebrus 0:0a673c671a56 283 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 284 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
ebrus 0:0a673c671a56 285 * 4 bits for subpriority
ebrus 0:0a673c671a56 286 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
ebrus 0:0a673c671a56 287 * 3 bits for subpriority
ebrus 0:0a673c671a56 288 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
ebrus 0:0a673c671a56 289 * 2 bits for subpriority
ebrus 0:0a673c671a56 290 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
ebrus 0:0a673c671a56 291 * 1 bits for subpriority
ebrus 0:0a673c671a56 292 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
ebrus 0:0a673c671a56 293 * 0 bits for subpriority
ebrus 0:0a673c671a56 294 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
ebrus 0:0a673c671a56 295 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
ebrus 0:0a673c671a56 296 * @retval None
ebrus 0:0a673c671a56 297 */
ebrus 0:0a673c671a56 298 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
ebrus 0:0a673c671a56 299 {
ebrus 0:0a673c671a56 300 /* Check the parameters */
ebrus 0:0a673c671a56 301 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
ebrus 0:0a673c671a56 302 /* Get priority for Cortex-M system or device specific interrupts */
ebrus 0:0a673c671a56 303 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
ebrus 0:0a673c671a56 304 }
ebrus 0:0a673c671a56 305
ebrus 0:0a673c671a56 306 /**
ebrus 0:0a673c671a56 307 * @brief Sets Pending bit of an external interrupt.
ebrus 0:0a673c671a56 308 * @param IRQn External interrupt number
ebrus 0:0a673c671a56 309 * This parameter can be an enumerator of @ref IRQn_Type enumeration
ebrus 0:0a673c671a56 310 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 311 * @retval None
ebrus 0:0a673c671a56 312 */
ebrus 0:0a673c671a56 313 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 314 {
ebrus 0:0a673c671a56 315 /* Set interrupt pending */
ebrus 0:0a673c671a56 316 NVIC_SetPendingIRQ(IRQn);
ebrus 0:0a673c671a56 317 }
ebrus 0:0a673c671a56 318
ebrus 0:0a673c671a56 319 /**
ebrus 0:0a673c671a56 320 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
ebrus 0:0a673c671a56 321 * and returns the pending bit for the specified interrupt).
ebrus 0:0a673c671a56 322 * @param IRQn External interrupt number.
ebrus 0:0a673c671a56 323 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 324 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 325 * @retval status: - 0 Interrupt status is not pending.
ebrus 0:0a673c671a56 326 * - 1 Interrupt status is pending.
ebrus 0:0a673c671a56 327 */
ebrus 0:0a673c671a56 328 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 329 {
ebrus 0:0a673c671a56 330 /* Return 1 if pending else 0 */
ebrus 0:0a673c671a56 331 return NVIC_GetPendingIRQ(IRQn);
ebrus 0:0a673c671a56 332 }
ebrus 0:0a673c671a56 333
ebrus 0:0a673c671a56 334 /**
ebrus 0:0a673c671a56 335 * @brief Clears the pending bit of an external interrupt.
ebrus 0:0a673c671a56 336 * @param IRQn External interrupt number.
ebrus 0:0a673c671a56 337 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 338 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 339 * @retval None
ebrus 0:0a673c671a56 340 */
ebrus 0:0a673c671a56 341 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
ebrus 0:0a673c671a56 342 {
ebrus 0:0a673c671a56 343 /* Clear pending interrupt */
ebrus 0:0a673c671a56 344 NVIC_ClearPendingIRQ(IRQn);
ebrus 0:0a673c671a56 345 }
ebrus 0:0a673c671a56 346
ebrus 0:0a673c671a56 347 /**
ebrus 0:0a673c671a56 348 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
ebrus 0:0a673c671a56 349 * @param IRQn External interrupt number
ebrus 0:0a673c671a56 350 * This parameter can be an enumerator of IRQn_Type enumeration
ebrus 0:0a673c671a56 351 * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f4xx.h file)
ebrus 0:0a673c671a56 352 * @retval status: - 0 Interrupt status is not pending.
ebrus 0:0a673c671a56 353 * - 1 Interrupt status is pending.
ebrus 0:0a673c671a56 354 */
ebrus 0:0a673c671a56 355 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
ebrus 0:0a673c671a56 356 {
ebrus 0:0a673c671a56 357 /* Return 1 if active else 0 */
ebrus 0:0a673c671a56 358 return NVIC_GetActive(IRQn);
ebrus 0:0a673c671a56 359 }
ebrus 0:0a673c671a56 360
ebrus 0:0a673c671a56 361 /**
ebrus 0:0a673c671a56 362 * @brief Configures the SysTick clock source.
ebrus 0:0a673c671a56 363 * @param CLKSource: specifies the SysTick clock source.
ebrus 0:0a673c671a56 364 * This parameter can be one of the following values:
ebrus 0:0a673c671a56 365 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
ebrus 0:0a673c671a56 366 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
ebrus 0:0a673c671a56 367 * @retval None
ebrus 0:0a673c671a56 368 */
ebrus 0:0a673c671a56 369 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
ebrus 0:0a673c671a56 370 {
ebrus 0:0a673c671a56 371 /* Check the parameters */
ebrus 0:0a673c671a56 372 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
ebrus 0:0a673c671a56 373 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
ebrus 0:0a673c671a56 374 {
ebrus 0:0a673c671a56 375 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
ebrus 0:0a673c671a56 376 }
ebrus 0:0a673c671a56 377 else
ebrus 0:0a673c671a56 378 {
ebrus 0:0a673c671a56 379 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
ebrus 0:0a673c671a56 380 }
ebrus 0:0a673c671a56 381 }
ebrus 0:0a673c671a56 382
ebrus 0:0a673c671a56 383 /**
ebrus 0:0a673c671a56 384 * @brief This function handles SYSTICK interrupt request.
ebrus 0:0a673c671a56 385 * @param None
ebrus 0:0a673c671a56 386 * @retval None
ebrus 0:0a673c671a56 387 */
ebrus 0:0a673c671a56 388 void HAL_SYSTICK_IRQHandler(void)
ebrus 0:0a673c671a56 389 {
ebrus 0:0a673c671a56 390 HAL_SYSTICK_Callback();
ebrus 0:0a673c671a56 391 }
ebrus 0:0a673c671a56 392
ebrus 0:0a673c671a56 393 /**
ebrus 0:0a673c671a56 394 * @brief SYSTICK callback.
ebrus 0:0a673c671a56 395 * @param None
ebrus 0:0a673c671a56 396 * @retval None
ebrus 0:0a673c671a56 397 */
ebrus 0:0a673c671a56 398 __weak void HAL_SYSTICK_Callback(void)
ebrus 0:0a673c671a56 399 {
ebrus 0:0a673c671a56 400 /* NOTE : This function Should not be modified, when the callback is needed,
ebrus 0:0a673c671a56 401 the HAL_SYSTICK_Callback could be implemented in the user file
ebrus 0:0a673c671a56 402 */
ebrus 0:0a673c671a56 403 }
ebrus 0:0a673c671a56 404
ebrus 0:0a673c671a56 405 /**
ebrus 0:0a673c671a56 406 * @}
ebrus 0:0a673c671a56 407 */
ebrus 0:0a673c671a56 408
ebrus 0:0a673c671a56 409 /**
ebrus 0:0a673c671a56 410 * @}
ebrus 0:0a673c671a56 411 */
ebrus 0:0a673c671a56 412
ebrus 0:0a673c671a56 413 #endif /* HAL_CORTEX_MODULE_ENABLED */
ebrus 0:0a673c671a56 414 /**
ebrus 0:0a673c671a56 415 * @}
ebrus 0:0a673c671a56 416 */
ebrus 0:0a673c671a56 417
ebrus 0:0a673c671a56 418 /**
ebrus 0:0a673c671a56 419 * @}
ebrus 0:0a673c671a56 420 */
ebrus 0:0a673c671a56 421
ebrus 0:0a673c671a56 422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/