Ermanno Brusadin / mbed-src

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targets/cmsis/TARGET_STM/TARGET_DISCO_F100RB/misc.h@0:0a673c671a56, 2016-07-27 (annotated)

Committer:
ebrus
Date:
Wed Jul 27 18:35:32 2016 +0000
Revision:
0:0a673c671a56
4

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ebrus 0:0a673c671a56 1 /**
ebrus 0:0a673c671a56 2 ******************************************************************************
ebrus 0:0a673c671a56 3 * @file misc.h
ebrus 0:0a673c671a56 4 * @author MCD Application Team
ebrus 0:0a673c671a56 5 * @version V3.6.1
ebrus 0:0a673c671a56 6 * @date 05-March-2012
ebrus 0:0a673c671a56 7 * @brief This file contains all the functions prototypes for the miscellaneous
ebrus 0:0a673c671a56 8 * firmware library functions (add-on to CMSIS functions).
ebrus 0:0a673c671a56 9 *******************************************************************************
ebrus 0:0a673c671a56 10 * Copyright (c) 2014, STMicroelectronics
ebrus 0:0a673c671a56 11 * All rights reserved.
ebrus 0:0a673c671a56 12 *
ebrus 0:0a673c671a56 13 * Redistribution and use in source and binary forms, with or without
ebrus 0:0a673c671a56 14 * modification, are permitted provided that the following conditions are met:
ebrus 0:0a673c671a56 15 *
ebrus 0:0a673c671a56 16 * 1. Redistributions of source code must retain the above copyright notice,
ebrus 0:0a673c671a56 17 * this list of conditions and the following disclaimer.
ebrus 0:0a673c671a56 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
ebrus 0:0a673c671a56 19 * this list of conditions and the following disclaimer in the documentation
ebrus 0:0a673c671a56 20 * and/or other materials provided with the distribution.
ebrus 0:0a673c671a56 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ebrus 0:0a673c671a56 22 * may be used to endorse or promote products derived from this software
ebrus 0:0a673c671a56 23 * without specific prior written permission.
ebrus 0:0a673c671a56 24 *
ebrus 0:0a673c671a56 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ebrus 0:0a673c671a56 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ebrus 0:0a673c671a56 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ebrus 0:0a673c671a56 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ebrus 0:0a673c671a56 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ebrus 0:0a673c671a56 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ebrus 0:0a673c671a56 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ebrus 0:0a673c671a56 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ebrus 0:0a673c671a56 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ebrus 0:0a673c671a56 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ebrus 0:0a673c671a56 35 *******************************************************************************
ebrus 0:0a673c671a56 36 */
ebrus 0:0a673c671a56 37
ebrus 0:0a673c671a56 38 /* Define to prevent recursive inclusion -------------------------------------*/
ebrus 0:0a673c671a56 39 #ifndef __MISC_H
ebrus 0:0a673c671a56 40 #define __MISC_H
ebrus 0:0a673c671a56 41
ebrus 0:0a673c671a56 42 #ifdef __cplusplus
ebrus 0:0a673c671a56 43 extern "C" {
ebrus 0:0a673c671a56 44 #endif
ebrus 0:0a673c671a56 45
ebrus 0:0a673c671a56 46 /* Includes ------------------------------------------------------------------*/
ebrus 0:0a673c671a56 47 #include "stm32f10x.h"
ebrus 0:0a673c671a56 48
ebrus 0:0a673c671a56 49 /** @addtogroup STM32F10x_StdPeriph_Driver
ebrus 0:0a673c671a56 50 * @{
ebrus 0:0a673c671a56 51 */
ebrus 0:0a673c671a56 52
ebrus 0:0a673c671a56 53 /** @addtogroup MISC
ebrus 0:0a673c671a56 54 * @{
ebrus 0:0a673c671a56 55 */
ebrus 0:0a673c671a56 56
ebrus 0:0a673c671a56 57 /** @defgroup MISC_Exported_Types
ebrus 0:0a673c671a56 58 * @{
ebrus 0:0a673c671a56 59 */
ebrus 0:0a673c671a56 60
ebrus 0:0a673c671a56 61 /**
ebrus 0:0a673c671a56 62 * @brief NVIC Init Structure definition
ebrus 0:0a673c671a56 63 */
ebrus 0:0a673c671a56 64
ebrus 0:0a673c671a56 65 typedef struct
ebrus 0:0a673c671a56 66 {
ebrus 0:0a673c671a56 67 uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
ebrus 0:0a673c671a56 68 This parameter can be a value of @ref IRQn_Type
ebrus 0:0a673c671a56 69 (For the complete STM32 Devices IRQ Channels list, please
ebrus 0:0a673c671a56 70 refer to stm32f10x.h file) */
ebrus 0:0a673c671a56 71
ebrus 0:0a673c671a56 72 uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
ebrus 0:0a673c671a56 73 specified in NVIC_IRQChannel. This parameter can be a value
ebrus 0:0a673c671a56 74 between 0 and 15 as described in the table @ref NVIC_Priority_Table */
ebrus 0:0a673c671a56 75
ebrus 0:0a673c671a56 76 uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
ebrus 0:0a673c671a56 77 in NVIC_IRQChannel. This parameter can be a value
ebrus 0:0a673c671a56 78 between 0 and 15 as described in the table @ref NVIC_Priority_Table */
ebrus 0:0a673c671a56 79
ebrus 0:0a673c671a56 80 FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
ebrus 0:0a673c671a56 81 will be enabled or disabled.
ebrus 0:0a673c671a56 82 This parameter can be set either to ENABLE or DISABLE */
ebrus 0:0a673c671a56 83 } NVIC_InitTypeDef;
ebrus 0:0a673c671a56 84
ebrus 0:0a673c671a56 85 /**
ebrus 0:0a673c671a56 86 * @}
ebrus 0:0a673c671a56 87 */
ebrus 0:0a673c671a56 88
ebrus 0:0a673c671a56 89 /** @defgroup NVIC_Priority_Table
ebrus 0:0a673c671a56 90 * @{
ebrus 0:0a673c671a56 91 */
ebrus 0:0a673c671a56 92
ebrus 0:0a673c671a56 93 /**
ebrus 0:0a673c671a56 94 @code
ebrus 0:0a673c671a56 95 The table below gives the allowed values of the pre-emption priority and subpriority according
ebrus 0:0a673c671a56 96 to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
ebrus 0:0a673c671a56 97 ============================================================================================================================
ebrus 0:0a673c671a56 98 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
ebrus 0:0a673c671a56 99 ============================================================================================================================
ebrus 0:0a673c671a56 100 NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
ebrus 0:0a673c671a56 101 | | | 4 bits for subpriority
ebrus 0:0a673c671a56 102 ----------------------------------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 103 NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
ebrus 0:0a673c671a56 104 | | | 3 bits for subpriority
ebrus 0:0a673c671a56 105 ----------------------------------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 106 NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
ebrus 0:0a673c671a56 107 | | | 2 bits for subpriority
ebrus 0:0a673c671a56 108 ----------------------------------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 109 NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
ebrus 0:0a673c671a56 110 | | | 1 bits for subpriority
ebrus 0:0a673c671a56 111 ----------------------------------------------------------------------------------------------------------------------------
ebrus 0:0a673c671a56 112 NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
ebrus 0:0a673c671a56 113 | | | 0 bits for subpriority
ebrus 0:0a673c671a56 114 ============================================================================================================================
ebrus 0:0a673c671a56 115 @endcode
ebrus 0:0a673c671a56 116 */
ebrus 0:0a673c671a56 117
ebrus 0:0a673c671a56 118 /**
ebrus 0:0a673c671a56 119 * @}
ebrus 0:0a673c671a56 120 */
ebrus 0:0a673c671a56 121
ebrus 0:0a673c671a56 122 /** @defgroup MISC_Exported_Constants
ebrus 0:0a673c671a56 123 * @{
ebrus 0:0a673c671a56 124 */
ebrus 0:0a673c671a56 125
ebrus 0:0a673c671a56 126 /** @defgroup Vector_Table_Base
ebrus 0:0a673c671a56 127 * @{
ebrus 0:0a673c671a56 128 */
ebrus 0:0a673c671a56 129
ebrus 0:0a673c671a56 130 #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
ebrus 0:0a673c671a56 131 #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
ebrus 0:0a673c671a56 132 #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
ebrus 0:0a673c671a56 133 ((VECTTAB) == NVIC_VectTab_FLASH))
ebrus 0:0a673c671a56 134 /**
ebrus 0:0a673c671a56 135 * @}
ebrus 0:0a673c671a56 136 */
ebrus 0:0a673c671a56 137
ebrus 0:0a673c671a56 138 /** @defgroup System_Low_Power
ebrus 0:0a673c671a56 139 * @{
ebrus 0:0a673c671a56 140 */
ebrus 0:0a673c671a56 141
ebrus 0:0a673c671a56 142 #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
ebrus 0:0a673c671a56 143 #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
ebrus 0:0a673c671a56 144 #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
ebrus 0:0a673c671a56 145 #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
ebrus 0:0a673c671a56 146 ((LP) == NVIC_LP_SLEEPDEEP) || \
ebrus 0:0a673c671a56 147 ((LP) == NVIC_LP_SLEEPONEXIT))
ebrus 0:0a673c671a56 148 /**
ebrus 0:0a673c671a56 149 * @}
ebrus 0:0a673c671a56 150 */
ebrus 0:0a673c671a56 151
ebrus 0:0a673c671a56 152 /** @defgroup Preemption_Priority_Group
ebrus 0:0a673c671a56 153 * @{
ebrus 0:0a673c671a56 154 */
ebrus 0:0a673c671a56 155
ebrus 0:0a673c671a56 156 #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
ebrus 0:0a673c671a56 157 4 bits for subpriority */
ebrus 0:0a673c671a56 158 #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
ebrus 0:0a673c671a56 159 3 bits for subpriority */
ebrus 0:0a673c671a56 160 #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
ebrus 0:0a673c671a56 161 2 bits for subpriority */
ebrus 0:0a673c671a56 162 #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
ebrus 0:0a673c671a56 163 1 bits for subpriority */
ebrus 0:0a673c671a56 164 #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
ebrus 0:0a673c671a56 165 0 bits for subpriority */
ebrus 0:0a673c671a56 166
ebrus 0:0a673c671a56 167 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
ebrus 0:0a673c671a56 168 ((GROUP) == NVIC_PriorityGroup_1) || \
ebrus 0:0a673c671a56 169 ((GROUP) == NVIC_PriorityGroup_2) || \
ebrus 0:0a673c671a56 170 ((GROUP) == NVIC_PriorityGroup_3) || \
ebrus 0:0a673c671a56 171 ((GROUP) == NVIC_PriorityGroup_4))
ebrus 0:0a673c671a56 172
ebrus 0:0a673c671a56 173 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
ebrus 0:0a673c671a56 174
ebrus 0:0a673c671a56 175 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
ebrus 0:0a673c671a56 176
ebrus 0:0a673c671a56 177 #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
ebrus 0:0a673c671a56 178
ebrus 0:0a673c671a56 179 /**
ebrus 0:0a673c671a56 180 * @}
ebrus 0:0a673c671a56 181 */
ebrus 0:0a673c671a56 182
ebrus 0:0a673c671a56 183 /** @defgroup SysTick_clock_source
ebrus 0:0a673c671a56 184 * @{
ebrus 0:0a673c671a56 185 */
ebrus 0:0a673c671a56 186
ebrus 0:0a673c671a56 187 #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
ebrus 0:0a673c671a56 188 #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
ebrus 0:0a673c671a56 189 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
ebrus 0:0a673c671a56 190 ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
ebrus 0:0a673c671a56 191 /**
ebrus 0:0a673c671a56 192 * @}
ebrus 0:0a673c671a56 193 */
ebrus 0:0a673c671a56 194
ebrus 0:0a673c671a56 195 /**
ebrus 0:0a673c671a56 196 * @}
ebrus 0:0a673c671a56 197 */
ebrus 0:0a673c671a56 198
ebrus 0:0a673c671a56 199 /** @defgroup MISC_Exported_Macros
ebrus 0:0a673c671a56 200 * @{
ebrus 0:0a673c671a56 201 */
ebrus 0:0a673c671a56 202
ebrus 0:0a673c671a56 203 /**
ebrus 0:0a673c671a56 204 * @}
ebrus 0:0a673c671a56 205 */
ebrus 0:0a673c671a56 206
ebrus 0:0a673c671a56 207 /** @defgroup MISC_Exported_Functions
ebrus 0:0a673c671a56 208 * @{
ebrus 0:0a673c671a56 209 */
ebrus 0:0a673c671a56 210
ebrus 0:0a673c671a56 211 void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
ebrus 0:0a673c671a56 212 void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
ebrus 0:0a673c671a56 213 void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
ebrus 0:0a673c671a56 214 void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
ebrus 0:0a673c671a56 215 void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
ebrus 0:0a673c671a56 216
ebrus 0:0a673c671a56 217 #ifdef __cplusplus
ebrus 0:0a673c671a56 218 }
ebrus 0:0a673c671a56 219 #endif
ebrus 0:0a673c671a56 220
ebrus 0:0a673c671a56 221 #endif /* __MISC_H */
ebrus 0:0a673c671a56 222
ebrus 0:0a673c671a56 223 /**
ebrus 0:0a673c671a56 224 * @}
ebrus 0:0a673c671a56 225 */
ebrus 0:0a673c671a56 226
ebrus 0:0a673c671a56 227 /**
ebrus 0:0a673c671a56 228 * @}
ebrus 0:0a673c671a56 229 */
ebrus 0:0a673c671a56 230
ebrus 0:0a673c671a56 231 /**
ebrus 0:0a673c671a56 232 * @}
ebrus 0:0a673c671a56 233 */
ebrus 0:0a673c671a56 234
ebrus 0:0a673c671a56 235 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/