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Dependents: alarm_slave iq_sx126x sx126x_simple_TX_shield_2020a sx126x_simple_RX_shield_2020a ... more
Revision 7:fe8c0186ee50, committed 2018-08-17
- Comitter:
- Wayne Roberts
- Date:
- Fri Aug 17 17:20:24 2018 -0700
- Parent:
- 6:cd4b02a7e65d
- Child:
- 8:66d3e344d61c
- Commit message:
- add lora status register
Changed in this revision
| sx12xx.h | Show annotated file Show diff for this revision Revisions of this file |
--- a/sx12xx.h Thu Aug 16 17:46:01 2018 -0700
+++ b/sx12xx.h Fri Aug 17 17:20:24 2018 -0700
@@ -10,6 +10,7 @@
#define FREQ_STEP 0.95367431640625 // ( ( double )( XTAL_FREQ / ( double )FREQ_DIV ) )
#define MHZ_TO_FRF 1048576 // = (1<<25) / Fxtal_MHz
#define KHZ_TO_FRF 1048.576
+#define HZ_TO_FRF 1.048576 // = (1<<25) / Fxtal_Hz
/***************************************************************/
#define OPCODE_CLEAR_IRQ_STATUS 0x02
@@ -65,6 +66,7 @@
#define REG_ADDR_BITRATE 0x6a1 // 24bit fsk
#define REG_ADDR_FREQDEV 0x6a4 // 18bit fsk
#define REG_ADDR_SHAPECFG 0x6a7 // 5bit
+#define REG_ADDR_FSK_DEMOD_CFO 0x6b0 // 12bit center frequency offset
#define REG_ADDR_FSK_PKTCTRL0 0x6b3 // 8bit
#define REG_ADDR_FSK_PKTCTRL1 0x6b4 // 3bit
#define REG_ADDR_FSK_PREAMBLE_TXLEN 0x6b5 // 16bit
@@ -86,6 +88,7 @@
#define REG_ADDR_LORA_IRQ_MASK 0x70a // 24bit
#define REG_ADDR_LORA_PREAMBLE_SYMBNB 0x73a // 16bit
#define REG_ADDR_LORA_SYNC 0x740 // config22, config23: frame sync peak position
+#define REG_ADDR_LORA_STATUS 0x76b //
#define REG_ADDR_DIGFECTL 0x804 // 6bits
#define REG_ADDR_BWSEL 0x807 // 5bits
@@ -324,6 +327,17 @@
typedef union {
struct {
+ uint32_t est_freq_error :20; // 0..19
+ uint32_t header_crc16_en : 1; // 20
+ uint32_t rf_en_request : 2; // 21,22
+ uint32_t raw_ranging_result_available : 1; // 23
+ uint32_t unused : 8; // 24..31
+ } bits;
+ uint32_t dword;
+} loraStatus1_t; // at 0x76b
+
+typedef union {
+ struct {
uint8_t inv_edge : 1; // 0
uint8_t swap_iq : 1; // 1
uint8_t dig_fe_clear : 1; // 2