sx12xx.h

00001 #include "mbed.h"
00002 #ifndef SX1265_H
00003 #define SX1265_H
00004 
00005 #define XTAL_FREQ_HZ            32000000
00006 #define FREQ_STEP               0.95367431640625 // ( ( double )( XTAL_FREQ / ( double )FREQ_DIV ) )
00007 #define GFSK_BITRATE_NUMERATOR       1024000000
00008 
00009 
00010 #define OPCODE_GET_STATUS               0x0100
00011 #define OPCODE_GET_VERSION              0x0101
00012 #define OPCODE_WRITEREGMEM32            0x0105
00013 #define OPCODE_READREGMEM32             0x0106
00014 #define OPCODE_CLEAR_RX_BUFFER          0x010b
00015 #define OPCODE_WRITE_BUFFER8            0x0109
00016 #define OPCODE_READ_BUFFER8             0x010a
00017 #define OPCODE_GET_ERRORS               0x010d
00018 #define OPCODE_CLEAR_ERRORS             0x010e
00019 #define OPCODE_CALIBRATE                0x010f
00020 #define OPCODE_SET_REGULATOR_MODE       0x0110
00021 #define OPCODE_CALIBRATE_IMAGE          0x0111  // operating band change
00022 #define OPCODE_SET_DIO_AS_RFSWITCH      0x0112
00023 #define OPCODE_CLEAR_IRQ                0x0114
00024 #define OPCODE_SET_SLEEP                0x011b
00025 #define OPCODE_SET_STANDBY              0x011c
00026 #define OPCODE_SET_FS                   0x011d
00027 #define OPCODE_SET_DIOIRQPARAMS         0x0113
00028 #define OPCODE_SET_TCXO_MODE            0x0117
00029 #define OPCODE_GET_DEVEUI               0x0125
00030 #define OPCODE_GET_JOINEUI              0x0126
00031 #define OPCODE_GET_DEVICE_PIN           0x0127
00032 #define OPCODE_RESET_STATS              0x0200
00033 #define OPCODE_GET_STATS                0x0201
00034 #define OPCODE_GET_PACKET_TYPE          0x0202
00035 #define OPCODE_GET_RX_BUFFER_STATUS     0x0203
00036 #define OPCODE_GET_PKT_STATUS           0x0204
00037 #define OPCODE_GET_RSSI_INST            0x0205
00038 #define OPCODE_SET_GFSK_SYNC_WORD       0x0206
00039 #define OPCODE_SET_LORA_PUBLIC_NETWORK  0x0208
00040 #define OPCODE_SET_RX                   0x0209
00041 #define OPCODE_SET_RF_FREQ_HZ           0x020b // 0x00f30058
00042 #define OPCODE_SET_TX                   0x020a
00043 #define OPCODE_AUTO_TX_RX               0x020c
00044 #define OPCODE_SET_CAD_PARAMS           0x020d
00045 #define OPCODE_SET_PACKET_TYPE          0x020e
00046 #define OPCODE_SET_MODULATION           0x020f
00047 #define OPCODE_SET_PACKET_PARAM         0x0210
00048 #define OPCODE_SET_TXPARAMS             0x0211
00049 #define OPCODE_SET_GFSK_PKT_ADDRESS     0x0212
00050 #define OPCODE_SET_RXTX_FALLBACK_MODE   0x0213
00051 #define OPCODE_SET_RX_DUTYCYCLE         0x0214
00052 #define OPCODE_SET_PA_CONFIG            0x0215
00053 #define OPCODE_STOP_TIMEOUT_ON_PREAMBLE 0x0217
00054 #define OPCODE_SET_CAD                  0x0218
00055 #define OPCODE_SET_TXCW                 0x0219
00056 #define OPCODE_SET_TX_PREAMBLE          0x021a
00057 #define OPCODE_SET_LORA_SYNC_TIMEOUT    0x021b
00058 #define OPCODE_SET_GFSK_CRC_PARAMS      0x0224
00059 #define OPCODE_SET_GFSK_WHITENING       0x0225
00060 #define OPCODE_SET_RX_BOSSTED           0x0227
00061 
00062 #define OPCODE_WIFI_SCAN                0x0300
00063 #define OPCODE_GET_WIFI_NB_RESULTS      0x0305
00064 #define OPCODE_WIFI_READ_RESULTS        0x0306
00065 #define OPCODE_WIFI_RESET_CT            0x0307
00066 #define OPCODE_WIFI_READ_CT             0x0308
00067 
00068 #define OPCODE_GNSS_SET_CONSTELLATION   0x0400
00069 #define OPCODE_GNSS_SET_MODE            0x0408
00070 #define OPCODE_GNSS_AUTONOMOUS          0x0409
00071 #define OPCODE_GNSS_ASSISTED            0x040a
00072 #define OPCODE_GNSS_GET_RESULT_SIZE     0x040c
00073 #define OPCODE_GNSS_READ_RESULTS        0x040d
00074 #define OPCODE_GNSS_ALMANAC_FULL_UPDATE 0x040e
00075 #define OPCODE_GNSS_SET_ASSISTED_POS    0x0410
00076 #define OPCODE_GNSS_GET_NBSVDET         0x0417
00077 #define OPCODE_GNSS_GET_SVDET           0x0418
00078 
00079 #define OPCODE_CRYPTO_SET_KEY               0x0502
00080 #define OPCODE_CRYPTO_DIRIVE_STORE_KEY      0x0503
00081 #define OPCODE_CRYPTO_PROCESS_JOIN_ACC      0x0504
00082 #define OPCODE_CRYPTO_COMPUTE_AES_CMAC      0x0505
00083 #define OPCODE_CRYPTO_VERIFY_AES_CMAC       0x0506
00084 #define OPCODE_CRYPTO_AES_ENCRYPT01         0x0507
00085 #define OPCODE_CRYPTO_AES_ENCRYPT           0x0508
00086 #define OPCODE_CRYPTO_AES_DECRYPT           0x0509
00087 #define OPCODE_CRYPTO_STORE_TO_FLASH        0x050a
00088 #define OPCODE_CRYPTO_RESTORE_FROM_FLASH    0x050b
00089 #define OPCODE_CRYPTO_SET_PARAM             0x050d
00090 #define OPCODE_CRYPTO_GET_PARAM             0x050e
00091 
00092 /* for 0x0112 command: */
00093 #define DIO_en_IDX        0
00094 #define DIO_stby_IDX      1
00095 #define DIO_rx_IDX        2
00096 #define DIO_tx_IDX        3
00097 #define DIO_txhp_IDX      4
00098 #define DIO_gnss_IDX      6
00099 #define DIO_wifi_IDX      7
00100 
00101 #define DIO5_BIT         0x01
00102 #define DIO6_BIT         0x02
00103 #define DIO7_BIT         0x04
00104 #define DIO8_BIT         0x08
00105 #define DIO10_BIT        0x10
00106 
00107 enum {
00108     /* 0x00 */ TCXO_VOLTS_1v6 = 0,
00109     /* 0x01 */ TCXO_VOLTS_1v8,
00110     /* 0x02 */ TCXO_VOLTS_1V8,
00111     /* 0x03 */ TCXO_VOLTS_2v2,
00112     /* 0x04 */ TCXO_VOLTS_2v4,
00113     /* 0x05 */ TCXO_VOLTS_2v7,
00114     /* 0x06 */ TCXO_VOLTS_3v0,
00115     /* 0x07 */ TCXO_VOLTS_3v3,
00116 };
00117 
00118 /* valid memory ranges:
00119  * 000c1000 - 000c2000  1024 dwords
00120  * 00800000 - 00810000  16384 dwords
00121  *
00122  * 00f00000 - 00f00050  20 dwords
00123  * 00f01000 - 00f01048  18 dwords
00124  * 00f02000 - 00f02014  5 dwords
00125  * 00f02018 - 00f02024  3 dwords
00126  * 00f03000 - 00f03034  13 dwords
00127  * 00f04000 - 00f04018  6 dwords
00128  * 00f04020 - 00f04040  8 dwords
00129  * 00f0f000 - 00f0f004  1 dwords
00130  * 00f0f008 - 00f0f010  2 dwords
00131  * 00f10000 - 00f11ffc  (lockup)
00132  * 00f11000 - 00f11058  22 dwords
00133  * 00f12000 - 00f1200c  3 dwords
00134  * 00f12010 - 00f12040  12 dwords
00135  * 00f13000 - 00f15034  2061 dwords
00136  * 00f16000 - 00f16014  5 dwords
00137  * 00f17000 - 00f17058  22 dwords
00138  * 00f18000 - 00f18020  8 dwords
00139  * 00f19000 - 00f190a4  41 dwords
00140  * 00f1a000 - 00f1a034  13 dwords
00141  * 00f1f000 - 00f1f004  1 dwords
00142  * 00f1f00c - 00f1f014  2 dwords
00143  * 00f20000 - 00f20020  8 dwords
00144  * 00f20100 - 00f2013c  15 dwords
00145  * 00f20200 - 00f20250  20 dwords
00146  * 00f20300 - 00f20390  36 dwords
00147  * 00f20400 - 00f204c0  48 dwords
00148  * 00f20500 - 00f2050c  3 dwords
00149  * 00f20540 - 00f20598  22 dwords
00150  * 00f30000 - 00f300cc  51 dwords
00151  */
00152 
00153 /* 800000->8000xx: cmd buffer
00154  */
00155 #define REG_ADDR_REGULATOR_MODE         0x0080036c
00156 #define REG_ADDR_GNSS_CONST             0x008003b8
00157 #define REG_ADDR_GNSS_MODE              0x008004b4
00158 #define REG_ADDR_GNSS_ASSIST_LAT        0x008008ec 
00159 #define REG_ADDR_GNSS_ASSIST_LON        0x008008f0 
00160 #define REG_ADDR_TCXO                   0x00f0003c
00161 #define REG_ADDR_DIO5                   0x00f03018 
00162 #define REG_ADDR_DIO6                   0x00f0301c 
00163 #define REG_ADDR_DIO7                   0x00f03020 
00164 #define REG_ADDR_DIO8                   0x00f03024 
00165 #define REG_ADDR_DIO10                  0x00f0302c 
00166 #define REG_ADDR_COUNTER                0x00f04014
00167 #define REG_ADDR_GFSK_BWF               0x00f20124 
00168 #define REG_ADDR_GFSK_CFG0              0x00f20314 
00169 #define REG_ADDR_GFSK_BITRATE           0x00f20338
00170 #define REG_ADDR_GFSK_FDEV              0x00f2033c
00171 #define REG_ADDR_GFSK_CFG1              0x00f2034c  // gfsk preambleDetect, gfsk preambleLength
00172 #define REG_ADDR_GFSK_CFG2              0x00f20350  // gfsk sync word length (in bits)
00173 #define REG_ADDR_GFSK_SYNC_LO           0x00f20354  // gfsk sync word lo
00174 #define REG_ADDR_GFSK_SYNC_HI           0x00f20358  // gfsk sync word hi
00175 #define REG_ADDR_GFSK_CFG3              0x00f2035c  // gfsk fixlen/varlen
00176 #define REG_ADDR_GFSK_PAYLOAD_LENGTH_A  0x00f20360  // lowest 8bits  todo:tx-or-rx?
00177 #define REG_ADDR_GFSK_PAYLOAD_LENGTH_B  0x00f20368  // payload-length-bits[27:20], addrComp:[17:16]
00178 #define REG_ADDR_GFSK_CFG5              0x00f20370  // gfsk whitening, crcType
00179 #define REG_ADDR_GFSK_CRC_POLY          0x00f20374
00180 #define REG_ADDR_GFSK_CRC_INIT          0x00f20378
00181 #define REG_ADDR_LORA_CONFIG0           0x00f20414
00182 #define REG_ADDR_LORA_CONFIGC           0x00f2041c
00183 #define REG_ADDR_LORA_CONFIGA           0x00f20420
00184 #define REG_ADDR_LORA_CONFIGB           0x00f20428
00185 #define REG_ADDR_LORA_SYNC              0x00f20460
00186 #define REG_ADDR_RFFREQ                 0x00f30058
00187 #define REG_ADDR_TX_PARAMS_A            0x00f30074
00188 #define REG_ADDR_TX_PARAMS_B            0x00f30078
00189 #define REG_ADDR_TX_PARAMS_C            0x00f30080
00190 #define REG_ADDR_TX_PARAMS_D            0x00f30088
00191 //#define REG_ADDR_             0x
00192 //
00193 
00194 #define GFSK_CRC_OFF            0x01
00195 #define GFSK_CRC_1_BYTE         0x00
00196 #define GFSK_CRC_2_BYTE         0x02
00197 #define GFSK_CRC_1_BYTE_INV     0x04
00198 #define GFSK_CRC_2_BYTE_INV     0x06
00199 
00200 #define GFSK_BT_OFF             0x00
00201 #define GFSK_BT_0_3             0x08
00202 #define GFSK_BT_0_5             0x09
00203 #define GFSK_BT_0_7             0x0a
00204 #define GFSK_BT_1_0             0x0b
00205 
00206 #define GFSK_RX_BW_4800         0x1f
00207 #define GFSK_RX_BW_5800         0x17
00208 #define GFSK_RX_BW_7300         0x0f
00209 #define GFSK_RX_BW_9700         0x1e
00210 #define GFSK_RX_BW_11700        0x16
00211 #define GFSK_RX_BW_14600        0x0e
00212 #define GFSK_RX_BW_19500        0x1d
00213 #define GFSK_RX_BW_23400        0x15
00214 #define GFSK_RX_BW_29300        0x0d
00215 #define GFSK_RX_BW_39000        0x1c
00216 #define GFSK_RX_BW_46900        0x14
00217 #define GFSK_RX_BW_58600        0x0c
00218 #define GFSK_RX_BW_78200        0x1b
00219 #define GFSK_RX_BW_93800        0x13
00220 #define GFSK_RX_BW_117300       0x0b
00221 #define GFSK_RX_BW_156200       0x1a
00222 #define GFSK_RX_BW_187200       0x12
00223 #define GFSK_RX_BW_234300       0x0a
00224 #define GFSK_RX_BW_312000       0x19
00225 #define GFSK_RX_BW_373600       0x11
00226 #define GFSK_RX_BW_467000       0x09
00227 
00228 #define GFSK_PBLDET_LENGTH_OFF  0x00
00229 #define GFSK_PBLDET_LENGTH_8    0x04
00230 #define GFSK_PBLDET_LENGTH_16   0x05
00231 #define GFSK_PBLDET_LENGTH_24   0x06
00232 #define GFSK_PBLDET_LENGTH_32   0x07
00233 
00234 enum {
00235     /* 0 */ LORA_BW_7_8KHz = 0,
00236     /* 1 */ LORA_BW_15_6KHz,
00237     /* 2 */ LORA_BW_31_25KHz,
00238     /* 3 */ LORA_BW_62_5KHz,
00239     /* 4 */ LORA_BW_125KHz,
00240     /* 5 */ LORA_BW_250KHz,
00241     /* 6 */ LORA_BW_500KHz,
00242     /* 7 */ LORA_BW_1000KHz,
00243 };
00244 
00245 typedef union {
00246     struct {
00247         uint8_t lf_rc  : 1; // 0
00248         uint8_t hf_rc  : 1; // 1
00249         uint8_t pll    : 1; // 2
00250         uint8_t adc    : 1; // 3
00251         uint8_t img    : 1; // 4
00252         uint8_t pll_tx : 1; // 5
00253         uint8_t rfu    : 2; // 6,7
00254     } bits;
00255     uint8_t octet;
00256 } calibParams_t;  // for opcode 0x010f
00257 
00258 
00259 typedef union {
00260     struct __attribute__((packed)) {
00261         uint8_t dcdc_en    : 1; // 0
00262         uint32_t _todo_    :31; // 1 -> 31
00263     } bits;
00264     uint32_t dword;
00265 } regulatorMode_t;  // 0x0080036c
00266 
00267 typedef union {
00268     struct __attribute__((packed)) {
00269         uint8_t gps        : 1; // 0
00270         uint8_t beidou     : 1; // 1
00271         uint32_t _todo_    :30; // 2 -> 31
00272     } bits;
00273     uint32_t dword;
00274 } gnssConstellation_t;  // 0x008003b8
00275 
00276 typedef union {
00277     struct __attribute__((packed)) {
00278         uint8_t todo              : 1; // 0
00279         uint8_t gnss_scan_single  : 1; // 1     0=dual-scanning
00280         uint32_t _todo_           :30; // 2 -> 31
00281     } bits;
00282     uint32_t dword;
00283 } gnssMode_t;  // 0x008004b4
00284 
00285 typedef union {
00286     struct __attribute__((packed)) {
00287         uint16_t todo           :16; // 0 -> 15
00288         uint8_t volts           : 3; // 16,17,18
00289         uint32_t _todo_         :13; // 19 -> 31
00290     } bits;
00291     uint32_t dword;
00292 } tcxo_t;  // 0x00f0003c
00293 
00294 typedef union {
00295     struct __attribute__((packed)) {
00296         uint8_t todo           : 1; // 0
00297         uint8_t enable         : 1; // 1
00298         uint32_t _todo_        :30; // 2 -> 31
00299     } bits;
00300     uint32_t dword;
00301 } dioEnable_t;  // 0x00f030xx 
00302 
00303 typedef union {
00304     struct __attribute__((packed)) {
00305         uint32_t todo           : 20; // 0 -> 19
00306         uint8_t bwf_lo          : 3; // 20,21,22        /* ? receiver bandwidth exponent ? */
00307         uint8_t _todo_          : 1; // 23
00308         uint8_t bwf_hi          : 2; // 24,25        /* ? receiver bandwidth mantissa ? */
00309         uint8_t todo_           : 6; // 26,27,28,29,30,31
00310     } bits;
00311     uint32_t dword;
00312 } gfskBW_t;  // 0x00f20124 
00313 
00314 typedef union {
00315     struct __attribute__((packed)) {
00316         uint8_t modem_sf        : 4; // 0,1,2,3
00317         uint8_t modem_bw        : 4; // 4,5,6,7
00318         uint8_t coding_rate     : 4; // 8,9,10,11        TODO:not all 4 bits
00319         uint8_t ppm_offset      : 1; // 12      LowDatarateOptimize
00320         uint8_t todo_a          : 3; // 13,14,15
00321         uint8_t crc_on          : 1; // 16
00322         uint8_t implicit_header : 1; // 17
00323         uint8_t todo_b          : 6; // 18,19,20,21,22,23
00324         uint8_t payload_length  : 8; // 24,25,26,27,28,29,30,31
00325     } bits;
00326     uint32_t dword;
00327 } loraConfig0_t;  // at 0x00f20414
00328 
00329 typedef union {
00330     struct {
00331         uint16_t preamble_length  : 16; // 0 -> 15
00332         uint16_t todo             : 16; // 16 -> 31
00333     } bits;
00334     uint32_t dword;
00335 } loraConfigC_t;  // at 0x00f2041c
00336 
00337 typedef union {
00338     struct {
00339         uint8_t todo_a        : 8; // 0,1,2,3,4,5,6,7
00340         uint8_t todo_b        : 2; // 8,9
00341         uint8_t invertIQ      : 1; // 10
00342         uint32_t todo_c       :21; // 11,12,13,14  15,16,17,18  19,20,21,22  23,24,25,26   27,28,29,30  31
00343     } bits;
00344     uint32_t dword;
00345 } loraConfigA_t;  // at 0xf20420
00346 
00347 typedef union {
00348     struct {
00349         uint8_t todo_a        : 1; // 0
00350         uint8_t invertIQ      : 1; // 1
00351         uint32_t todo_b       :30; // 2,3,4,5  6,7,8,9  10,11,12,13  14,15,16,17  18,19,20,21  22,23,24,25  26,27,28,29  30,31
00352     } bits;
00353     uint32_t dword;
00354 } loraConfigB_t;  // at 0x00f20428
00355 
00356 typedef union {
00357     struct {
00358         uint8_t ppg_a        : 4; // 0,1,2,3
00359         uint8_t todo         : 4; // 4,5,6,7
00360         uint8_t ppg_b        : 4; // 8,9,10,11
00361         uint8_t todo_        : 4; // 12,13,14,15
00362         uint16_t _todo       :16; // 16 -> 31
00363     } bits;
00364     uint32_t dword;
00365 } loraSync_t;  // at 0x00f20460
00366 
00367 typedef union {
00368     struct {
00369         uint32_t todo_        :20; // 0,1,2,3  4,5,6,7   8,9,10,11  12,13,14,15   16,17,18,19
00370         uint8_t bt            : 4; // 20,21,22,23       (0=0.3  1=0.5  2=0.7  3=1.0)
00371         uint8_t shaping_en    : 1; // 24
00372         uint8_t todo          : 7; // 25,26,27,28,29,30,31
00373     } bits;
00374     uint32_t dword;
00375 } gfskConfig0_t;  // at 0x00f20314 
00376 
00377 typedef union {
00378     struct {
00379         uint16_t preamble_length    :16; // 0,1,2,3  4,5,6,7   8,9,10,11  12,13,14,15
00380         uint8_t preamble_det_len    : 4; // 16,17,18,19   0=8bit  1=16bit  2=24bit  3=32bit
00381         uint8_t preamble_det_enable : 1; // 20
00382         uint16_t todo               :11; // 21,22,23,24  25,26,27,28, 29,30,31
00383     } bits;
00384     uint32_t dword;
00385 } gfskConfig1_t;  // at 0x00f2034c
00386 
00387 typedef union {
00388     struct __attribute__((packed)) {
00389         uint32_t _todo              :20; // 0,1,2,3  4,5,6,7   8,9,10,11  12,13,14,15  16,17,18,19
00390         uint8_t sync_word_length    : 7; // 20,21,22,23,24,25,26   length in bits
00391         uint16_t todo               : 5; // 27,28,29,30,31
00392     } bits;
00393     uint32_t dword;
00394 } gfskConfig2_t;  // at 0x00f20350
00395 
00396 typedef union {
00397     struct {
00398         uint8_t variable_length     : 1; // 0
00399         uint32_t todo               :31; // 1 -> 31
00400     } bits;
00401     uint32_t dword;
00402 } gfskConfig3_t;  // at 0x00f2035c
00403 
00404 typedef union {
00405     struct __attribute__((packed)) {
00406         uint8_t todo                : 8; // 0 -> 7
00407         uint8_t node_adrs           : 8; // 8 -> 15
00408         uint8_t addr_comp           : 2; // 16,17
00409         uint8_t _todo               : 2; // 18,19
00410         uint8_t payload_length      : 8; // 20,21,22,23  24,25,26,27
00411         uint8_t todo_               : 4; // 28,29,30,31
00412     } bits;
00413     uint32_t dword;
00414 } gfskConfig4_t;  // at 0x00f20368
00415 
00416 typedef union {
00417     struct {
00418         uint8_t crc_off             : 1; // 0
00419         uint8_t todo                : 3; // 1,2,3
00420         uint8_t crc_size            : 1; // 4       0=one-byte   1=two-byte
00421         uint8_t _todo               : 3; // 5,6,7
00422         uint8_t crc_invert          : 1; // 8
00423         uint8_t _todo_              : 7; // 9,10,11,12  13,14,15
00424         uint8_t whitening_enable    : 1; // 16
00425         uint16_t todo_              :15; // 17,18,19,20  21,22,23,24  25,26,27,28  29,30,31
00426     } bits;
00427     uint32_t dword;
00428 } gfskConfig5_t;  // at 0x00f20370  
00429 
00430 typedef union {
00431     struct {
00432         uint8_t _todo              : 8; // 0 -> 7
00433         uint8_t RegPASupply        : 1; // 8
00434         uint32_t todo_             :23; // 9 -> 31
00435     } bits;
00436     uint32_t dword;
00437 } txParamsA_t;  // at 0x00f30074
00438 
00439 typedef union {
00440     struct {
00441         uint8_t _todo              : 1; // 0
00442         uint8_t PaSel              : 1; // 1
00443         uint8_t __todo             : 2; // 2,3
00444         uint8_t PaHPSel            : 3; // 4,5,6
00445         uint8_t todo               : 1; // 7
00446         uint8_t PaDutyCycle        : 3; // 8,9,10
00447         uint32_t todo_             :21; // 11 -> 31
00448     } bits;
00449     uint32_t dword;
00450 } txParamsB_t;  // at 0x00f30078
00451 
00452 typedef union {
00453     struct __attribute__((packed)) {
00454         uint8_t todo                : 8; // 0 -> 7
00455         uint8_t pa_ramp_time        : 3; // 8,9,10
00456         uint8_t _todo               : 1; // 11
00457         uint8_t tx_dbm              : 5; // 12,13,14,15,16
00458         uint16_t todo_              :15; // 17 -> 31
00459     } bits;
00460     uint32_t dword;
00461 } txParamsC_t;  // at 0x00f30080
00462 
00463 typedef union {
00464     struct {
00465         uint32_t todo_       :28; // 0 -> 27
00466         uint8_t PaSel        : 1; // 28
00467         uint8_t todo         : 3; // 29,30,31
00468     } bits;
00469     uint32_t dword;
00470 } txParamsD_t;  // at 0x00f30088
00471 
00472 enum {
00473     /* 0 */ CMD_FAIL = 0,
00474     /* 1 */ CMD_PERR,
00475     /* 2 */ CMD_OK,
00476     /* 3 */ CMD_DAT
00477 };
00478 
00479 enum {
00480     /* 0 */ PACKET_TYPE_NONE = 0,
00481     /* 1 */ PACKET_TYPE_GFSK,
00482     /* 2 */ PACKET_TYPE_LORA,
00483 };
00484 
00485 typedef union {
00486     struct {
00487         uint32_t ___              : 2;    // 0,1
00488         uint32_t TxDone           : 1;    // 2
00489         uint32_t RxDone           : 1;    // 3
00490         uint32_t PreambleDetected : 1;    // 4
00491         uint32_t SyncHeaderValid  : 1;    // 5
00492         uint32_t HeaderErr        : 1;    // 6
00493         uint32_t Err              : 1;    // 7
00494         uint32_t CadDone          : 1;    // 8
00495         uint32_t CadDetected      : 1;    // 9
00496         uint32_t Timeout          : 1;    // 10
00497         uint32_t __               : 8;    // 11,12,13,14,15,16,17,18
00498         uint32_t GNSSDone         : 1;    // 19
00499         uint32_t WifiDone         : 1;    // 20
00500         uint32_t lowBat           : 1;    // 21
00501         uint32_t CmdErr           : 1;    // 22
00502         uint32_t Error            : 1;    // 23
00503         uint32_t FskLenError      : 1;    // 24
00504         uint32_t FskAddrError     : 1;    // 25
00505         uint32_t _                : 6;    // 26,27,28,29,30,31
00506     } bits;
00507     uint32_t dword;
00508 } irq_t;
00509 
00510 typedef union {
00511     struct {
00512         uint16_t bootloader    : 1;    // 0
00513         uint16_t chipMode      : 3;    // 1,2,3
00514         uint16_t resetStatus   : 4;    // 4,5,6,7
00515         uint16_t intActive     : 1;    // 8
00516         uint16_t cmdStatus     : 3;    // 9,10,11
00517         uint16_t rfu           : 4;    // 12,13,14,15
00518     } bits;
00519     uint16_t word;
00520 } stat_t;
00521 
00522 typedef union {
00523     struct {
00524         uint16_t lf_rc_calib    : 1;    // 0
00525         uint16_t hf_rc_calib    : 1;    // 1
00526         uint16_t adc_calib      : 1;    // 2
00527         uint16_t pll_calib      : 1;    // 3
00528         uint16_t img_calib      : 1;    // 4
00529         uint16_t hf_xosc_start_  : 1;    // 5
00530         uint16_t lf_xosc_start  : 1;    // 6
00531         uint16_t pll_lock       : 1;    // 7
00532         uint16_t rx_adc_offset  : 1;    // 8
00533         uint16_t rfu            : 7;    // 9,10,11,12,13,14,15
00534     } bits;
00535     uint16_t word;
00536 } ErrorStat_t;
00537 
00538 typedef union {
00539     struct {
00540         uint8_t signal   : 2;    // 0,1
00541         uint8_t datarate : 6;    // 2,3,4,5,6,7
00542     } bits;
00543     uint16_t octet;
00544 } wifiType_t;
00545 
00546 typedef union {
00547     struct {
00548         uint8_t channelID       : 4;    // 0,1,2,3
00549         uint8_t macValidationID : 4;    // 4,5,6,7
00550     } bits;
00551     uint16_t octet;
00552 } wifiChanInfo_t;
00553 
00554 typedef enum {
00555     CHIPMODE_NONE = 0,
00556     CHIPMODE_RX,
00557     CHIPMODE_TX
00558 } chipMote_e;
00559 
00560 class SX1265 {
00561     public:
00562         SX1265(SPI&, PinName nss, PinName busy, PinName dio9, PinName nrst, uint32_t default_irqs = 0x3ffffff, unsigned tcxoTimeout = 2048, uint8_t tcxoVolts = TCXO_VOLTS_2v7);
00563         static Callback<void()> dio9_topHalf;    // low latency ISR context
00564         uint16_t xfer(uint16_t opcode, uint16_t writeLen, uint16_t readLen, uint8_t* buf);
00565         uint32_t service(void);
00566         void hw_reset(void);
00567         const char *cmdStatus_toString(uint8_t);
00568         uint8_t setMHz(float);
00569         float getMHz(void);
00570         void to_big_endian16(uint16_t in, uint8_t *out);
00571         void to_big_endian32(uint32_t in, uint8_t *out);
00572         void to_big_endian24(uint32_t in, uint8_t *out);
00573         uint32_t from_big_endian32(const uint8_t *in);
00574         //int memRegRead(uint32_t addr, uint16_t len_dwords, uint8_t *dest);
00575         int memRegRead(uint32_t addr, uint16_t len_dwords, uint32_t *dest);
00576         uint8_t getPacketType(void);
00577         void setPacketType(uint8_t);
00578         void start_tx(uint8_t pktLen);  // tx_buf must be filled prior to calling
00579 
00580         Timer t;
00581         ErrorStat_t errorStat;
00582 
00583         //! RF transmit packet buffer
00584         uint8_t tx_buf[256];    // lora fifo size
00585         
00586         //! RF receive packet buffer
00587         uint8_t rx_buf[256];    // lora fifo size
00588 
00589         Callback<void()> chipModeChange; // read chipMode_e chipMode
00590         Callback<void()> txDone; // user context
00591         void (*cadDone)(bool detected); // user context
00592         void (*rxDone)(uint8_t size, float rssi, float snr); // user context
00593         void (*timeout)(bool tx); // user context
00594         unsigned txTimeout;
00595         uint16_t err_opcode;
00596         uint8_t rx_buf_offset;
00597         chipMote_e chipMode;
00598 
00599         void GetPaConfig(uint8_t*); /* for read-modify-write */
00600         void GetLoRaModulationParameters(uint8_t*); /* for read-modify-write */
00601         void GetLoRaPacketParameters(uint8_t*); /* for read-modify-write */
00602         void GetGfskModulationParameters(uint8_t*); /* for read-modify-write */
00603         void GetGfskPacketParameters(uint8_t*); /* for read-modify-write */
00604 
00605     private:
00606         SPI& spi;
00607         DigitalOut nss;
00608         DigitalIn busy;
00609         InterruptIn dio9;
00610         DigitalInOut nrst;
00611         static void dio9isr(void);
00612         bool sleeping;
00613         uint16_t prev_opcode;
00614         uint16_t this_opcode;
00615         bool inService;
00616         void enable_default_irqs_(void);
00617 
00618     public:
00619         uint32_t default_irqs;
00620 
00621     private:
00622         unsigned tcxoStartDelay;
00623         uint8_t tcxoVolts;
00624         uint8_t rxArgs[3];
00625 };
00626 
00627 #endif /* SX1265_H */
00628