main.cpp

00001 #include "sx12xx.h"
00002 
00003 RawSerial pc(USBTX, USBRX);
00004 
00005 #ifdef TARGET_FF_ARDUINO
00006     SPI spi(D11, D12, D13); // mosi, miso, sclk
00007                    //spi, nss, busy, dio1
00008     SX126x radio(spi, D7, D3, D5);
00009  
00010     DigitalOut antswPower(D8);
00011     AnalogIn xtalSel(A3);
00012  
00013     DigitalIn chipType(A2);
00014  
00015     #define PINNAME_NRST            A0
00016  
00017     #define LED_ON      1
00018     #define LED_OFF     0
00019     DigitalOut tx_led(A4);
00020     DigitalOut rx_led(A5);
00021  
00022     void chipModeChange()
00023     {
00024         if (radio.chipMode == CHIPMODE_NONE) {
00025             tx_led = LED_OFF;
00026             rx_led = LED_OFF;
00027         } else if (radio.chipMode == CHIPMODE_TX) {
00028             tx_led = LED_ON;
00029             rx_led = LED_OFF;
00030         } else if (radio.chipMode == CHIPMODE_RX) {
00031             tx_led = LED_OFF;
00032             rx_led = LED_ON;
00033         }
00034     }
00035 #endif /* TARGET_FF_ARDUINO */
00036 
00037 volatile bool tx_done;
00038 
00039 void txDoneBottom()
00040 {
00041     printf("txDone\r\n");
00042     tx_done = true;
00043 }
00044 
00045 PacketParams_t pp;
00046 
00047 void startTx()
00048 {
00049     uint8_t buf[2];
00050 
00051     buf[0] = 0; // TX base address
00052     buf[1] = 0; // RX base address
00053     radio.xfer(OPCODE_SET_BUFFER_BASE_ADDR, 2, 0, buf);
00054 
00055     tx_done = false;
00056     radio.start_tx(pp.gfsk.PayloadLength);
00057 }
00058 
00059 unsigned lfsr;
00060 #define LFSR_INIT       0x1ff
00061 
00062 uint8_t get_pn9_byte()
00063 {
00064     uint8_t ret = 0;
00065     int xor_out;
00066 
00067     xor_out = ((lfsr >> 5) & 0xf) ^ (lfsr & 0xf);   // four bits at a time
00068     lfsr = (lfsr >> 4) | (xor_out << 5);    // four bits at a time
00069 
00070     ret |= (lfsr >> 5) & 0x0f;
00071 
00072     xor_out = ((lfsr >> 5) & 0xf) ^ (lfsr & 0xf);   // four bits at a time
00073     lfsr = (lfsr >> 4) | (xor_out << 5);    // four bits at a time
00074 
00075     ret |= ((lfsr >> 1) & 0xf0);
00076 
00077     return ret;
00078 }
00079 
00080 uint8_t I[2];
00081 uint8_t Q[2];
00082 
00083 void rx_callback()
00084 {
00085     uint8_t ch = pc.getc();
00086 
00087     pc.putc(ch);
00088 
00089     switch (ch) {
00090         case 'q':
00091             radio.writeReg(REG_ADDR_MODCFG+1, ++I[0], 1);
00092             printf("I[0]:%02x\r\n", I[0]);
00093             break;
00094         case 'a':
00095             radio.writeReg(REG_ADDR_MODCFG+1, --I[0], 1);
00096             printf("I[0]:%02x\r\n", I[0]);
00097             break;
00098 
00099         case 'w':
00100             radio.writeReg(REG_ADDR_MODCFG+2, ++Q[0], 1);
00101             printf("Q[0]:%02x\r\n", Q[0]);
00102             break;
00103         case 's':
00104             radio.writeReg(REG_ADDR_MODCFG+2, --Q[0], 1);
00105             printf("Q[0]:%02x\r\n", Q[0]);
00106             break;
00107 
00108         case 'e':
00109             radio.writeReg(REG_ADDR_MODCFG+3, ++I[1], 1);
00110             printf("I[1]:%02x\r\n", I[1]);
00111             break;
00112         case 'd':
00113             radio.writeReg(REG_ADDR_MODCFG+3, --I[1], 1);
00114             printf("I[1]:%02x\r\n", I[1]);
00115             break;
00116 
00117         case 'r':
00118             radio.writeReg(REG_ADDR_MODCFG+4, ++Q[1], 1);
00119             printf("Q[1]:%02x\r\n", Q[1]);
00120             break;
00121         case 'f':
00122             radio.writeReg(REG_ADDR_MODCFG+4, --Q[1], 1);
00123             printf("Q[1]:%02x\r\n", Q[1]);
00124             break;
00125 
00126         default:
00127             break;
00128     } // ..switch (ch)
00129 }
00130 
00131 void
00132 init_syncaddr(uint8_t syncNum)
00133 {
00134     uint32_t sa;
00135 
00136     sa = get_pn9_byte();
00137     sa <<= 8;
00138     sa += get_pn9_byte();
00139     sa <<= 8;
00140     sa += get_pn9_byte();
00141     sa <<= 8;
00142     sa += get_pn9_byte();
00143 
00144     printf("sa %08lx\r\n", sa);
00145     radio.writeReg(REG_ADDR_SYNCADDR, sa, 4);
00146 
00147     sa = get_pn9_byte();
00148     sa <<= 8;
00149     sa += get_pn9_byte();
00150     sa <<= 8;
00151     sa += get_pn9_byte();
00152     sa <<= 8;
00153     sa += get_pn9_byte();
00154 
00155     printf("sa %08lx\r\n", sa);
00156     radio.writeReg(REG_ADDR_SYNCADDR+4, sa, 4);
00157 }
00158  
00159 int main()
00160 {
00161     modCfg_t modCfg;
00162     uint8_t buf[8];
00163     unsigned svcCnt = 0;
00164     unsigned preambleLen = 32;
00165     ModulationParams_t mp;
00166     uint32_t u32;
00167     unsigned bps = 1200;
00168     bool crcOn = true;
00169     unsigned i, fdev_hz;
00170 
00171     printf("\r\nreset\r\n");
00172 
00173     lfsr = LFSR_INIT;
00174 
00175     radio.hw_reset(PINNAME_NRST);
00176 
00177     init_syncaddr(1);
00178 
00179     radio.txDone = txDoneBottom;
00180 //    radio.rxDone = rx_done;
00181 //    radio.timeout = timeout_callback;
00182     radio.chipModeChange = chipModeChange;
00183 //    radio.dio1_topHalf = dio1_top_half;
00184  
00185     radio.SetDIO2AsRfSwitchCtrl(1);
00186 
00187  
00188     //if (radio.getPacketType() != PACKET_TYPE_GFSK)
00189         radio.setPacketType(PACKET_TYPE_GFSK);
00190 
00191     /*************************************************************/
00192     pp.gfsk.PreambleLengthHi = preambleLen >> 8;
00193     pp.gfsk.PreambleLengthLo = preambleLen;
00194     pp.gfsk.PreambleDetectorLength = GFSK_PREAMBLE_DETECTOR_LENGTH_16BITS;
00195     pp.gfsk.SyncWordLength = 24; // 0xC194C1
00196     pp.gfsk.AddrComp = 0;
00197     pp.gfsk.PacketType = HEADER_TYPE_VARIABLE_LENGTH     ;
00198     if (crcOn)
00199         pp.gfsk.CRCType = GFSK_CRC_2_BYTE;
00200     else
00201         pp.gfsk.CRCType = GFSK_CRC_OFF;
00202  
00203     pp.gfsk.PayloadLength = 192;
00204  
00205     radio.xfer(OPCODE_SET_PACKET_PARAMS, 8, 0, pp.buf);
00206     /*************************************************************/
00207  
00208     u32  = 32 * (XTAL_FREQ_HZ / bps);
00209     mp.gfsk.bitrateHi = u32 >> 16; // param1
00210     mp.gfsk.bitrateMid = u32 >> 8; // param2
00211     mp.gfsk.bitrateLo = u32;       // param3
00212     mp.gfsk.PulseShape = GFSK_SHAPE_BT1_0; // param4
00213     // param5:
00214 /*    if (bw_hz < 5800)
00215         mp.gfsk.bandwidth = GFSK_RX_BW_4800;
00216     else if (bw_hz < 7300)
00217         mp.gfsk.bandwidth = GFSK_RX_BW_5800;
00218     else if (bw_hz < 9700)
00219         mp.gfsk.bandwidth = GFSK_RX_BW_7300;
00220     else if (bw_hz < 11700)
00221         mp.gfsk.bandwidth = GFSK_RX_BW_9700;
00222     else if (bw_hz < 14600)
00223         mp.gfsk.bandwidth = GFSK_RX_BW_11700;
00224     else if (bw_hz < 19500)
00225         mp.gfsk.bandwidth = GFSK_RX_BW_14600;
00226     else if (bw_hz < 23400)
00227         mp.gfsk.bandwidth = GFSK_RX_BW_19500;
00228     else if (bw_hz < 29300)
00229         mp.gfsk.bandwidth = GFSK_RX_BW_23400;
00230     else if (bw_hz < 39000)
00231         mp.gfsk.bandwidth = GFSK_RX_BW_29300;
00232     else if (bw_hz < 46900)
00233         mp.gfsk.bandwidth = GFSK_RX_BW_39000;
00234     else if (bw_hz < 58600)
00235         mp.gfsk.bandwidth = GFSK_RX_BW_46900;
00236     else if (bw_hz < 78200)
00237         mp.gfsk.bandwidth = GFSK_RX_BW_58600;
00238     els`e if (bw_hz < 93800)
00239         mp.gfsk.bandwidth = GFSK_RX_BW_78200;
00240     else if (bw_hz < 117300)
00241         mp.gfsk.bandwidth = GFSK_RX_BW_93800;
00242     else if (bw_hz < 156200)
00243         mp.gfsk.bandwidth = GFSK_RX_BW_117300;
00244     else if (bw_hz < 187200)
00245         mp.gfsk.bandwidth = GFSK_RX_BW_156200;
00246     else if (bw_hz < 234300)
00247         mp.gfsk.bandwidth = GFSK_RX_BW_187200;
00248     else if (bw_hz < 312000)
00249         mp.gfsk.bandwidth = GFSK_RX_BW_234300;
00250     else if (bw_hz < 373600)
00251         mp.gfsk.bandwidth = GFSK_RX_BW_312000;
00252     else if (bw_hz < 467000)
00253         mp.gfsk.bandwidth = GFSK_RX_BW_373600;
00254     else
00255         mp.gfsk.bandwidth = GFSK_RX_BW_467000;*/
00256  
00257     mp.gfsk.bandwidth = GFSK_RX_BW_11700;
00258     /*
00259     fdev_hz = 10000;
00260 
00261     u32 = fdev_hz / FREQ_STEP;
00262     mp.gfsk.fdevHi = u32 >> 16; // param6
00263     mp.gfsk.fdevMid = u32 >> 8;    // param7
00264     mp.gfsk.fdevLo = u32; // param8
00265     */
00266     mp.gfsk.fdevHi = 0; // param6
00267     mp.gfsk.fdevMid = 0;    // param7
00268     mp.gfsk.fdevLo = 0; // param8
00269  
00270     radio.xfer(OPCODE_SET_MODULATION_PARAMS, 8, 0, mp.buf);
00271     /*************************************************************/
00272 
00273     I[0] = radio.readReg(REG_ADDR_MODCFG+1, 1),
00274     Q[0] = radio.readReg(REG_ADDR_MODCFG+2, 1),
00275     I[1] = radio.readReg(REG_ADDR_MODCFG+3, 1),
00276     Q[1] = radio.readReg(REG_ADDR_MODCFG+3, 1),
00277 
00278     modCfg.octet = radio.readReg(REG_ADDR_MODCFG, 1);
00279     modCfg.bits.mod_type = 0;
00280     radio.writeReg(REG_ADDR_MODCFG, modCfg.octet, 1);
00281 
00282     /*************************************************************/
00283 
00284     radio.setMHz(915.0);
00285     radio.set_tx_dbm(true, 14);
00286 
00287     {
00288         IrqFlags_t irqEnable;
00289         irqEnable.word = 0;
00290         irqEnable.bits.TxDone = 1;
00291         irqEnable.bits.Timeout = 1;
00292 
00293         buf[0] = irqEnable.word >> 8;    // enable bits
00294         buf[1] = irqEnable.word; // enable bits
00295         buf[2] = irqEnable.word >> 8;     // dio1
00296         buf[3] = irqEnable.word;  // dio1
00297         buf[4] = 0; // dio2
00298         buf[5] = 0; // dio2
00299         buf[6] = 0; // dio3
00300         buf[7] = 0; // dio3
00301         radio.xfer(OPCODE_SET_DIO_IRQ_PARAMS, 8, 0, buf);
00302     }
00303 
00304     for (i = 0; i < pp.gfsk.PayloadLength; i++) {
00305         radio.tx_buf[i] = get_pn9_byte();
00306     }
00307 
00308     antswPower = 1;
00309 
00310     startTx();
00311 
00312     for (;;) {
00313         if (pc.readable())
00314             rx_callback();
00315 
00316         radio.service();
00317 
00318         if (!tx_done) {
00319             //
00320         } else {
00321             wait(0.02);
00322 
00323             for (i = 0; i < pp.gfsk.PayloadLength; i++) {
00324                 radio.tx_buf[i] = get_pn9_byte();
00325             }
00326 
00327             printf("modCfg:%02x\t\t", modCfg.octet);
00328             printf("I:%02x  Q:%02x\t\t\tI:%02x  Q:%02x\r\n",
00329                 (uint8_t)radio.readReg(REG_ADDR_MODCFG+1, 1),
00330                 (uint8_t)radio.readReg(REG_ADDR_MODCFG+2, 1),
00331                 (uint8_t)radio.readReg(REG_ADDR_MODCFG+3, 1),
00332                 (uint8_t)radio.readReg(REG_ADDR_MODCFG+4, 1)
00333             );
00334             startTx();
00335         }
00336     } // ..for (;;)
00337 }
00338