Jim Cooke / Mbed 2 deprecated Hat_Board_v5_1

Slight Mod

Dependencies:   mbed-dsp mbed

Fork of Hat_Board_v5 by John Scharf

SI_LIS.h@5:ef42f4648198, 2014-04-03 (annotated)

Committer:
drnow
Date:
Thu Apr 03 10:56:37 2014 +0000
Revision:
5:ef42f4648198
Parent:
2:3a8cd127b72a 
Slight mod;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
drnow 0:34bad5aca893 1
drnow 0:34bad5aca893 2 #ifndef SI_LIS_h
drnow 0:34bad5aca893 3 #define SI_LIS_h
drnow 0:34bad5aca893 4
drnow 0:34bad5aca893 5 #include "mbed.h"
drnow 0:34bad5aca893 6
drnow 0:34bad5aca893 7 #define IR_ADDRESS 0x5A
drnow 0:34bad5aca893 8 #define LIS_Addr 0x18
drnow 0:34bad5aca893 9 #define HW_KEY_VAL0 0x17 //Value to write into the HW Key register
drnow 0:34bad5aca893 10
drnow 0:34bad5aca893 11 // Register Addresses
drnow 0:34bad5aca893 12
drnow 0:34bad5aca893 13 #define PART_ID 0x00
drnow 0:34bad5aca893 14 #define REV_ID 0x01
drnow 0:34bad5aca893 15 #define SEQ_ID 0x02 //Si114x-A11 (MAJOR_SEQ=1, MINOR_SEQ=1)
drnow 0:34bad5aca893 16 #define INT_CFG 0x03
drnow 0:34bad5aca893 17 #define IRQ_ENABLE 0x04
drnow 0:34bad5aca893 18 #define IRQ_MODE1 0x05
drnow 0:34bad5aca893 19 #define IRQ_MODE2 0x06
drnow 0:34bad5aca893 20 #define HW_KEY 0x07
drnow 0:34bad5aca893 21
drnow 0:34bad5aca893 22 #define MEAS_RATE 0x08
drnow 0:34bad5aca893 23 #define ALS_RATE 0x09
drnow 0:34bad5aca893 24 #define PS_RATE 0x0A
drnow 0:34bad5aca893 25
drnow 0:34bad5aca893 26 #define ALS_LOW_TH0 0x0B
drnow 0:34bad5aca893 27 #define ALS_LOW_TH1 0x0C
drnow 0:34bad5aca893 28 #define ALS_HI_TH0 0x0D
drnow 0:34bad5aca893 29 #define ALS_HI_TH1 0x0E
drnow 0:34bad5aca893 30
drnow 0:34bad5aca893 31 #define PS_LED21 0x0F
drnow 0:34bad5aca893 32 #define PS_LED3 0x10
drnow 0:34bad5aca893 33
drnow 0:34bad5aca893 34 #define PS1_TH0 0x11
drnow 0:34bad5aca893 35 #define PS1_TH1 0x12
drnow 0:34bad5aca893 36 #define PS2_TH0 0x13
drnow 0:34bad5aca893 37 #define PS2_TH1 0x14
drnow 0:34bad5aca893 38 #define PS3_TH0 0x15
drnow 0:34bad5aca893 39
drnow 0:34bad5aca893 40 #define PS3_TH1 0x16
drnow 0:34bad5aca893 41 #define PARAM_WR 0x17
drnow 0:34bad5aca893 42 #define COMMAND 0x18
drnow 0:34bad5aca893 43
drnow 0:34bad5aca893 44 #define RESPONSE 0x20
drnow 0:34bad5aca893 45 #define IRQ_STATUS 0x21
drnow 0:34bad5aca893 46
drnow 0:34bad5aca893 47 #define ALS_VIS_DATA0 0x22
drnow 0:34bad5aca893 48 #define ALS_VIS_DATA1 0x23
drnow 0:34bad5aca893 49 #define ALS_IR_DATA0 0x24
drnow 0:34bad5aca893 50 #define ALS_IR_DATA1 0x25
drnow 0:34bad5aca893 51
drnow 0:34bad5aca893 52 #define PS1_DATA0 0x26
drnow 0:34bad5aca893 53 #define PS1_DATA1 0x27
drnow 0:34bad5aca893 54 #define PS2_DATA0 0x28
drnow 0:34bad5aca893 55 #define PS2_DATA1 0x29
drnow 0:34bad5aca893 56 #define PS3_DATA0 0x2A
drnow 0:34bad5aca893 57 #define PS3_DATA1 0x2B
drnow 0:34bad5aca893 58
drnow 0:34bad5aca893 59
drnow 0:34bad5aca893 60 #define AUX_DATA0 0x2C
drnow 0:34bad5aca893 61 #define AUX_DATA1 0x2D
drnow 0:34bad5aca893 62
drnow 0:34bad5aca893 63 #define PARAM_RD 0x2E
drnow 0:34bad5aca893 64 #define CHIP_STAT 0x30
drnow 0:34bad5aca893 65 #define ANA_IN_KEY 0x3B
drnow 0:34bad5aca893 66
drnow 0:34bad5aca893 67 // Command Register Values
drnow 0:34bad5aca893 68
drnow 0:34bad5aca893 69 #define PARAM_QUERY 0x80 //Value is ORed with Parameter Offset
drnow 0:34bad5aca893 70 #define PARAM_SET 0xA0 //Value is ORed with Parameter Offset
drnow 0:34bad5aca893 71 #define PARAM_AND 0xC0 //Value is ORed with Parameter Offset
drnow 0:34bad5aca893 72 #define PARAM_OR 0xE0 //Value is ORed with Parameter Offset
drnow 0:34bad5aca893 73 #define NOP 0x00
drnow 0:34bad5aca893 74 #define RESET 0x01
drnow 0:34bad5aca893 75 #define BUSADDR 0x02
drnow 0:34bad5aca893 76 #define PS_FORCE 0x05
drnow 0:34bad5aca893 77 #define ALS_FORCE 0x06
drnow 0:34bad5aca893 78 #define PSALS_FORCE 0x07
drnow 0:34bad5aca893 79 #define PS_PAUSE 0x09
drnow 0:34bad5aca893 80 #define ALS_PAUSE 0x0A
drnow 0:34bad5aca893 81 #define PSALS_PAUSE 0x0B
drnow 0:34bad5aca893 82 #define PS_AUTO 0x0D
drnow 0:34bad5aca893 83 #define ALS_AUTO 0x0E
drnow 0:34bad5aca893 84 #define PSALS_AUTO 0x0F
drnow 0:34bad5aca893 85
drnow 0:34bad5aca893 86 // Ram Addresses
drnow 0:34bad5aca893 87
drnow 0:34bad5aca893 88 #define I2C_ADDR 0x00
drnow 0:34bad5aca893 89 #define CHLIST 0x01
drnow 0:34bad5aca893 90 #define PSLED12_SELECT 0x02
drnow 0:34bad5aca893 91 #define PSLED3_SELECT 0x03
drnow 0:34bad5aca893 92 #define FILTER_EN 0x04
drnow 0:34bad5aca893 93 #define PS_ENCODING 0x05
drnow 0:34bad5aca893 94 #define ALS_ENCODING 0x06
drnow 0:34bad5aca893 95 #define PS1_ADCMUX 0x07
drnow 0:34bad5aca893 96 #define PS2_ADCMUX 0x08
drnow 0:34bad5aca893 97 #define PS3_ADCMUX 0x09
drnow 0:34bad5aca893 98 #define PS_ADC_COUNTER 0x0A
drnow 0:34bad5aca893 99 #define PS_ADC_GAIN 0x0B
drnow 0:34bad5aca893 100 #define PS_ADC_MISC 0x0C
drnow 0:34bad5aca893 101 #define ALS1_ADCMUX 0x0D
drnow 0:34bad5aca893 102 #define ALS2_ADCMUX 0x0E
drnow 0:34bad5aca893 103 #define ALS3_ADCMUX 0x0F
drnow 0:34bad5aca893 104 #define ALS_VIS_ADC_COUNTER 0x10
drnow 0:34bad5aca893 105 #define ALS_VIS_ADC_GAIN 0x11
drnow 0:34bad5aca893 106 #define ALS_VIS_ADC_MISC 0x12
drnow 0:34bad5aca893 107 #define ALS_HYST 0x16
drnow 0:34bad5aca893 108 #define PS_HYST 0x17
drnow 0:34bad5aca893 109 #define PS_HISTORY 0x18
drnow 0:34bad5aca893 110 #define ALS_HISTORY 0x19
drnow 0:34bad5aca893 111 #define ADC_OFFSET 0x1A
drnow 0:34bad5aca893 112 #define SLEEP_CTRL 0x1B
drnow 0:34bad5aca893 113 #define LED_REC 0x1C
drnow 0:34bad5aca893 114 #define ALS_IR_ADC_COUNTER 0x1D
drnow 0:34bad5aca893 115 #define ALS_IR_ADC_GAIN 0x1E
drnow 0:34bad5aca893 116 #define ALS_IR_ADC_MISC 0x1F
drnow 0:34bad5aca893 117
drnow 0:34bad5aca893 118 // Measurement Channel List
drnow 0:34bad5aca893 119
drnow 0:34bad5aca893 120 #define PS1_TASK 0x01
drnow 0:34bad5aca893 121 #define PS2_TASK 0x02
drnow 0:34bad5aca893 122 #define PS3_TASK 0x04
drnow 0:34bad5aca893 123 #define ALS_VIS_TASK 0x10
drnow 0:34bad5aca893 124 #define ALS_IR_TASK 0x20
drnow 0:34bad5aca893 125 #define AUX_TASK 0x40
drnow 0:34bad5aca893 126
drnow 0:34bad5aca893 127 // SI1142 Sensor.
drnow 0:34bad5aca893 128
drnow 0:34bad5aca893 129 // Restart device.
drnow 0:34bad5aca893 130 void restart(void);
drnow 0:34bad5aca893 131
drnow 0:34bad5aca893 132 // Wait for the device to respond, then send it a specific command.
drnow 0:34bad5aca893 133 void command(char cmd);
drnow 0:34bad5aca893 134
drnow 0:34bad5aca893 135 // Send a test command.
drnow 0:34bad5aca893 136 void command_test();
drnow 0:34bad5aca893 137
drnow 0:34bad5aca893 138 // Send a non-RESET command.
drnow 0:34bad5aca893 139 int command2(char cmd);
drnow 0:34bad5aca893 140
drnow 0:34bad5aca893 141 // Send a non-RESET command another way.
drnow 0:34bad5aca893 142 void command3(char cmd);
drnow 0:34bad5aca893 143
drnow 0:34bad5aca893 144 /**
drnow 0:34bad5aca893 145 * Read a register from the device.
drnow 0:34bad5aca893 146 */
drnow 0:34bad5aca893 147 char read_reg(/*unsigned*/ char address, int num_data);
drnow 0:34bad5aca893 148
drnow 0:34bad5aca893 149 // Read 4 registers in a row
drnow 0:34bad5aca893 150 char read_reg2(/*unsigned*/ char address);
drnow 0:34bad5aca893 151
drnow 2:3a8cd127b72a 152 // Write to a register on Si1142.
drnow 0:34bad5aca893 153 void write_reg(char address, char num_data);
drnow 0:34bad5aca893 154
drnow 2:3a8cd127b72a 155 void Init_Accel ();
drnow 0:34bad5aca893 156
drnow 0:34bad5aca893 157 void Get_Accel_Register (char Reg_Num);
drnow 0:34bad5aca893 158
drnow 1:2efeed26d93a 159 void Get_Accel_Reg_6 (char Reg_Num); // Read 6 registers
drnow 1:2efeed26d93a 160
drnow 0:34bad5aca893 161 #endif