Peter Drescher / SPI_TFT_old

Library to control a QVGA TFT connected to SPI. You can use printf to print text The lib can handle different fonts, draw lines, circles, rect and bmp

SPI_TFT.cpp@13:d525819cb601, 2012-09-11 (annotated)

Committer:
dreschpe
Date:
Tue Sep 11 20:44:49 2012 +0000
Revision:
13:d525819cb601
Parent:
12:b2dd49f04d5d 
Switch back to io mode CS. The automatic spi cs can cause problems with interrupts or RTOS.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dreschpe 4:e1e45f8a7664 1 /* mbed library for 240*320 pixel display TFT based on HX8347D LCD Controller
dreschpe 4:e1e45f8a7664 2 * Copyright (c) 2011 Peter Drescher - DC2PD
dreschpe 4:e1e45f8a7664 3 *
dreschpe 4:e1e45f8a7664 4 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
dreschpe 4:e1e45f8a7664 5 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
dreschpe 4:e1e45f8a7664 6 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
dreschpe 4:e1e45f8a7664 7 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
dreschpe 4:e1e45f8a7664 8 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
dreschpe 4:e1e45f8a7664 9 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
dreschpe 4:e1e45f8a7664 10 * THE SOFTWARE.
dreschpe 4:e1e45f8a7664 11 */
dreschpe 12:b2dd49f04d5d 12
dreschpe 12:b2dd49f04d5d 13
dreschpe 12:b2dd49f04d5d 14 // fix bmp padding for Bitmap function
dreschpe 12:b2dd49f04d5d 15 // speed up pixel
dreschpe 10:1e868317ff49 16 // 30.12.11 fix cls
dreschpe 12:b2dd49f04d5d 17 // 11.03.12 use DMA to speed up
dreschpe 12:b2dd49f04d5d 18 // 15.03.12 use SSEL for TFT CS to enable DMA Register writes
dreschpe 12:b2dd49f04d5d 19 // 06.04.12 fix SSEL CS problem
dreschpe 12:b2dd49f04d5d 20 // 06.04.12 use direct access to the spi register to speed up the library.
dreschpe 13:d525819cb601 21 // 11.09.12 switch back to using io pin as cs to avoid problems with SSEL CS.
dreschpe 4:e1e45f8a7664 22
dreschpe 4:e1e45f8a7664 23 #include "SPI_TFT.h"
dreschpe 4:e1e45f8a7664 24 #include "mbed.h"
dreschpe 4:e1e45f8a7664 25
dreschpe 4:e1e45f8a7664 26
dreschpe 4:e1e45f8a7664 27 #define BPP 16 // Bits per pixel
dreschpe 4:e1e45f8a7664 28
dreschpe 12:b2dd49f04d5d 29
dreschpe 12:b2dd49f04d5d 30 //extern Serial pc;
dreschpe 12:b2dd49f04d5d 31 //extern DigitalOut xx; // debug !!
dreschpe 4:e1e45f8a7664 32
dreschpe 4:e1e45f8a7664 33 SPI_TFT::SPI_TFT(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName reset, const char *name)
dreschpe 13:d525819cb601 34 : _spi(mosi, miso, sclk), _cs(cs), _reset(reset),GraphicsDisplay(name) {
dreschpe 4:e1e45f8a7664 35 tft_reset();
dreschpe 4:e1e45f8a7664 36 orientation = 0;
dreschpe 4:e1e45f8a7664 37 char_x = 0;
dreschpe 12:b2dd49f04d5d 38 if (mosi == p11 || mosi == P0_18) spi_port = 0; // we must know the used SPI port to setup the DMA
dreschpe 12:b2dd49f04d5d 39 else spi_port = 1;
dreschpe 4:e1e45f8a7664 40 }
dreschpe 4:e1e45f8a7664 41
dreschpe 4:e1e45f8a7664 42 int SPI_TFT::width() {
dreschpe 4:e1e45f8a7664 43 if (orientation == 0 || orientation == 2) return 240;
dreschpe 4:e1e45f8a7664 44 else return 320;
dreschpe 4:e1e45f8a7664 45 }
dreschpe 4:e1e45f8a7664 46
dreschpe 4:e1e45f8a7664 47
dreschpe 4:e1e45f8a7664 48 int SPI_TFT::height() {
dreschpe 4:e1e45f8a7664 49 if (orientation == 0 || orientation == 2) return 320;
dreschpe 4:e1e45f8a7664 50 else return 240;
dreschpe 4:e1e45f8a7664 51 }
dreschpe 4:e1e45f8a7664 52
dreschpe 4:e1e45f8a7664 53
dreschpe 4:e1e45f8a7664 54 void SPI_TFT::set_orientation(unsigned int o) {
dreschpe 4:e1e45f8a7664 55 orientation = o;
dreschpe 4:e1e45f8a7664 56 switch (orientation) {
dreschpe 4:e1e45f8a7664 57 case 0:
dreschpe 12:b2dd49f04d5d 58 wr_reg(0x16, 0x08);
dreschpe 4:e1e45f8a7664 59 break;
dreschpe 4:e1e45f8a7664 60 case 1:
dreschpe 12:b2dd49f04d5d 61 wr_reg(0x16, 0x68);
dreschpe 4:e1e45f8a7664 62 break;
dreschpe 4:e1e45f8a7664 63 case 2:
dreschpe 12:b2dd49f04d5d 64 wr_reg(0x16, 0xC8);
dreschpe 4:e1e45f8a7664 65 break;
dreschpe 4:e1e45f8a7664 66 case 3:
dreschpe 12:b2dd49f04d5d 67 wr_reg(0x16, 0xA8);
dreschpe 4:e1e45f8a7664 68 break;
dreschpe 4:e1e45f8a7664 69 }
dreschpe 12:b2dd49f04d5d 70 WindowMax();
dreschpe 4:e1e45f8a7664 71 }
dreschpe 4:e1e45f8a7664 72
dreschpe 4:e1e45f8a7664 73
dreschpe 12:b2dd49f04d5d 74 // write command to tft register
dreschpe 4:e1e45f8a7664 75
dreschpe 12:b2dd49f04d5d 76 void SPI_TFT::wr_cmd(unsigned char cmd) {
dreschpe 12:b2dd49f04d5d 77 unsigned short spi_d;
dreschpe 12:b2dd49f04d5d 78 spi_d = 0x7000 | cmd ;
dreschpe 13:d525819cb601 79 _cs = 0;
dreschpe 12:b2dd49f04d5d 80 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 81 LPC_SSP0->DR = spi_d;
dreschpe 13:d525819cb601 82 // we have to wait for SPI IDLE to set CS back to high
dreschpe 12:b2dd49f04d5d 83 do {
dreschpe 12:b2dd49f04d5d 84 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle
dreschpe 12:b2dd49f04d5d 85 } else {
dreschpe 12:b2dd49f04d5d 86 LPC_SSP1->DR = spi_d;
dreschpe 12:b2dd49f04d5d 87 do {
dreschpe 12:b2dd49f04d5d 88 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
dreschpe 12:b2dd49f04d5d 89 }
dreschpe 13:d525819cb601 90 _cs = 1;
dreschpe 4:e1e45f8a7664 91 }
dreschpe 4:e1e45f8a7664 92
dreschpe 4:e1e45f8a7664 93
dreschpe 4:e1e45f8a7664 94
dreschpe 12:b2dd49f04d5d 95 void SPI_TFT::wr_dat(unsigned char dat) {
dreschpe 12:b2dd49f04d5d 96 unsigned short spi_d;
dreschpe 12:b2dd49f04d5d 97 spi_d = 0x7200 | dat;
dreschpe 13:d525819cb601 98 _cs = 0;
dreschpe 12:b2dd49f04d5d 99 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 100 LPC_SSP0->DR = spi_d;
dreschpe 13:d525819cb601 101 // we have to wait for SPI IDLE to set CS back to high
dreschpe 12:b2dd49f04d5d 102 do {
dreschpe 12:b2dd49f04d5d 103 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle
dreschpe 12:b2dd49f04d5d 104 } else {
dreschpe 12:b2dd49f04d5d 105 LPC_SSP1->DR = spi_d;
dreschpe 12:b2dd49f04d5d 106 do {
dreschpe 12:b2dd49f04d5d 107 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
dreschpe 12:b2dd49f04d5d 108 }
dreschpe 13:d525819cb601 109 _cs = 1;
dreschpe 4:e1e45f8a7664 110 }
dreschpe 4:e1e45f8a7664 111
dreschpe 4:e1e45f8a7664 112
dreschpe 4:e1e45f8a7664 113
dreschpe 12:b2dd49f04d5d 114 // the HX8347-D controller do not use the MISO (SDO) Signal.
dreschpe 13:d525819cb601 115 // This is a bug - ?
dreschpe 13:d525819cb601 116 // A read will return 0 at the moment
dreschpe 12:b2dd49f04d5d 117
dreschpe 12:b2dd49f04d5d 118 unsigned short SPI_TFT::rd_dat (void) {
dreschpe 12:b2dd49f04d5d 119 unsigned short val = 0;
dreschpe 12:b2dd49f04d5d 120
dreschpe 13:d525819cb601 121 //val = _spi.write(0x73ff); /* Dummy read 1 */
dreschpe 13:d525819cb601 122 //val = _spi.write(0x0000); /* Read D8..D15 */
dreschpe 12:b2dd49f04d5d 123 return (val);
dreschpe 12:b2dd49f04d5d 124 }
dreschpe 12:b2dd49f04d5d 125
dreschpe 12:b2dd49f04d5d 126 void SPI_TFT::wr_reg (unsigned char reg, unsigned char val) {
dreschpe 12:b2dd49f04d5d 127 wr_cmd(reg);
dreschpe 12:b2dd49f04d5d 128 wr_dat(val);
dreschpe 12:b2dd49f04d5d 129 }
dreschpe 12:b2dd49f04d5d 130
dreschpe 4:e1e45f8a7664 131 unsigned short SPI_TFT::rd_reg (unsigned char reg) {
dreschpe 4:e1e45f8a7664 132 wr_cmd(reg);
dreschpe 4:e1e45f8a7664 133 return(rd_dat());
dreschpe 4:e1e45f8a7664 134 }
dreschpe 4:e1e45f8a7664 135
dreschpe 4:e1e45f8a7664 136 void SPI_TFT::tft_reset() {
dreschpe 13:d525819cb601 137 //static unsigned short driverCode;
dreschpe 12:b2dd49f04d5d 138 _spi.format(16,3); // 16 bit spi mode 3
dreschpe 12:b2dd49f04d5d 139 _spi.frequency(48000000); // 48 Mhz SPI clock
dreschpe 13:d525819cb601 140 _cs = 1; // cs high
dreschpe 12:b2dd49f04d5d 141 _reset = 0; // display reset
dreschpe 13:d525819cb601 142 //
dreschpe 13:d525819cb601 143 // if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 144 // Set up SSEL0 for CS
dreschpe 13:d525819cb601 145 // LPC_PINCON->PINSEL1 |= (1UL << 1);
dreschpe 13:d525819cb601 146 // } else {
dreschpe 13:d525819cb601 147 // // Set up SSEL1
dreschpe 13:d525819cb601 148 // LPC_PINCON->PINSEL0 |= (1UL << 13);
dreschpe 13:d525819cb601 149 // }
dreschpe 4:e1e45f8a7664 150 wait_us(50);
dreschpe 4:e1e45f8a7664 151 _reset = 1; // end reset
dreschpe 4:e1e45f8a7664 152 wait_ms(5);
dreschpe 4:e1e45f8a7664 153
dreschpe 4:e1e45f8a7664 154 /* Start Initial Sequence ----------------------------------------------------*/
dreschpe 12:b2dd49f04d5d 155 wr_reg(0xEA, 0x00); /* Reset Power Control 1 */
dreschpe 12:b2dd49f04d5d 156 wr_reg(0xEB, 0x20); /* Power Control 2 */
dreschpe 12:b2dd49f04d5d 157 wr_reg(0xEC, 0x0C); /* Power Control 3 */
dreschpe 12:b2dd49f04d5d 158 wr_reg(0xED, 0xC4); /* Power Control 4 */
dreschpe 12:b2dd49f04d5d 159 wr_reg(0xE8, 0x40); /* Source OPON_N */
dreschpe 12:b2dd49f04d5d 160 wr_reg(0xE9, 0x38); /* Source OPON_I */
dreschpe 12:b2dd49f04d5d 161 wr_reg(0xF1, 0x01); /* */
dreschpe 12:b2dd49f04d5d 162 wr_reg(0xF2, 0x10); /* */
dreschpe 12:b2dd49f04d5d 163 wr_reg(0x27, 0xA3); /* Display Control 2 */
dreschpe 4:e1e45f8a7664 164
dreschpe 4:e1e45f8a7664 165 /* Power On sequence ---------------------------------------------------------*/
dreschpe 12:b2dd49f04d5d 166 wr_reg(0x1B, 0x1B); /* Power Control 2 */
dreschpe 12:b2dd49f04d5d 167 wr_reg(0x1A, 0x01); /* Power Control 1 */
dreschpe 12:b2dd49f04d5d 168 wr_reg(0x24, 0x2F); /* Vcom Control 2 */
dreschpe 12:b2dd49f04d5d 169 wr_reg(0x25, 0x57); /* Vcom Control 3 */
dreschpe 12:b2dd49f04d5d 170 wr_reg(0x23, 0x8D); /* Vcom Control 1 */
dreschpe 4:e1e45f8a7664 171
dreschpe 4:e1e45f8a7664 172 /* Gamma settings -----------------------------------------------------------*/
dreschpe 4:e1e45f8a7664 173 wr_reg(0x40,0x00); //
dreschpe 4:e1e45f8a7664 174 wr_reg(0x41,0x00); //
dreschpe 4:e1e45f8a7664 175 wr_reg(0x42,0x01); //
dreschpe 4:e1e45f8a7664 176 wr_reg(0x43,0x13); //
dreschpe 4:e1e45f8a7664 177 wr_reg(0x44,0x10); //
dreschpe 4:e1e45f8a7664 178 wr_reg(0x45,0x26); //
dreschpe 4:e1e45f8a7664 179 wr_reg(0x46,0x08); //
dreschpe 4:e1e45f8a7664 180 wr_reg(0x47,0x51); //
dreschpe 4:e1e45f8a7664 181 wr_reg(0x48,0x02); //
dreschpe 4:e1e45f8a7664 182 wr_reg(0x49,0x12); //
dreschpe 4:e1e45f8a7664 183 wr_reg(0x4A,0x18); //
dreschpe 4:e1e45f8a7664 184 wr_reg(0x4B,0x19); //
dreschpe 4:e1e45f8a7664 185 wr_reg(0x4C,0x14); //
dreschpe 4:e1e45f8a7664 186 wr_reg(0x50,0x19); //
dreschpe 4:e1e45f8a7664 187 wr_reg(0x51,0x2F); //
dreschpe 4:e1e45f8a7664 188 wr_reg(0x52,0x2C); //
dreschpe 4:e1e45f8a7664 189 wr_reg(0x53,0x3E); //
dreschpe 4:e1e45f8a7664 190 wr_reg(0x54,0x3F); //
dreschpe 4:e1e45f8a7664 191 wr_reg(0x55,0x3F); //
dreschpe 4:e1e45f8a7664 192 wr_reg(0x56,0x2E); //
dreschpe 4:e1e45f8a7664 193 wr_reg(0x57,0x77); //
dreschpe 4:e1e45f8a7664 194 wr_reg(0x58,0x0B); //
dreschpe 4:e1e45f8a7664 195 wr_reg(0x59,0x06); //
dreschpe 4:e1e45f8a7664 196 wr_reg(0x5A,0x07); //
dreschpe 4:e1e45f8a7664 197 wr_reg(0x5B,0x0D); //
dreschpe 4:e1e45f8a7664 198 wr_reg(0x5C,0x1D); //
dreschpe 4:e1e45f8a7664 199 wr_reg(0x5D,0xCC); //
dreschpe 4:e1e45f8a7664 200
dreschpe 4:e1e45f8a7664 201 /* Power + Osc ---------------------------------------------------------------*/
dreschpe 4:e1e45f8a7664 202 wr_reg(0x18, 0x0036); /* OSC Control 1 */
dreschpe 4:e1e45f8a7664 203 wr_reg(0x19, 0x0001); /* OSC Control 2 */
dreschpe 4:e1e45f8a7664 204 wr_reg(0x01, 0x0000); /* Display Mode Control */
dreschpe 4:e1e45f8a7664 205 wr_reg(0x1F, 0x0088); /* Power Control 6 */
dreschpe 4:e1e45f8a7664 206 wait_ms(5); /* Delay 5 ms */
dreschpe 4:e1e45f8a7664 207 wr_reg(0x1F, 0x0080); /* Power Control 6 */
dreschpe 4:e1e45f8a7664 208 wait_ms(5); /* Delay 5 ms */
dreschpe 4:e1e45f8a7664 209 wr_reg(0x1F, 0x0090); /* Power Control 6 */
dreschpe 4:e1e45f8a7664 210 wait_ms(5); /* Delay 5 ms */
dreschpe 4:e1e45f8a7664 211 wr_reg(0x1F, 0x00D0); /* Power Control 6 */
dreschpe 4:e1e45f8a7664 212 wait_ms(5); /* Delay 5 ms */
dreschpe 4:e1e45f8a7664 213
dreschpe 4:e1e45f8a7664 214 wr_reg(0x17, 0x0005); /* Colmod 16Bit/Pixel */
dreschpe 4:e1e45f8a7664 215
dreschpe 4:e1e45f8a7664 216 wr_reg(0x36, 0x0000); /* Panel Characteristic */
dreschpe 4:e1e45f8a7664 217 wr_reg(0x28, 0x0038); /* Display Control 3 */
dreschpe 4:e1e45f8a7664 218 wait_ms(40);
dreschpe 4:e1e45f8a7664 219 wr_reg(0x28, 0x003C); /* Display Control 3 */
dreschpe 4:e1e45f8a7664 220 switch (orientation) {
dreschpe 4:e1e45f8a7664 221 case 0:
dreschpe 4:e1e45f8a7664 222 wr_reg(0x16, 0x0008);
dreschpe 4:e1e45f8a7664 223 break;
dreschpe 4:e1e45f8a7664 224 case 1:
dreschpe 4:e1e45f8a7664 225 wr_reg(0x16, 0x0068);
dreschpe 4:e1e45f8a7664 226 break;
dreschpe 4:e1e45f8a7664 227 case 2:
dreschpe 4:e1e45f8a7664 228 wr_reg(0x16, 0x00C8);
dreschpe 4:e1e45f8a7664 229 break;
dreschpe 4:e1e45f8a7664 230 case 3:
dreschpe 4:e1e45f8a7664 231 wr_reg(0x16, 0x00A8);
dreschpe 4:e1e45f8a7664 232 break;
dreschpe 4:e1e45f8a7664 233 }
dreschpe 4:e1e45f8a7664 234
dreschpe 12:b2dd49f04d5d 235 // setup DMA channel 0
dreschpe 12:b2dd49f04d5d 236 // Power up the GPDMA.
dreschpe 12:b2dd49f04d5d 237 LPC_SC->PCONP |= (1UL << 29);
dreschpe 12:b2dd49f04d5d 238 LPC_GPDMA->DMACConfig = 1; // enable DMA controller
dreschpe 12:b2dd49f04d5d 239 // Reset the Interrupt status
dreschpe 12:b2dd49f04d5d 240 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 241 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 242 LPC_GPDMACH0->DMACCLLI = 0;
dreschpe 12:b2dd49f04d5d 243
dreschpe 4:e1e45f8a7664 244 WindowMax ();
dreschpe 4:e1e45f8a7664 245 }
dreschpe 4:e1e45f8a7664 246
dreschpe 4:e1e45f8a7664 247
dreschpe 4:e1e45f8a7664 248 void SPI_TFT::pixel(int x, int y, int color) {
dreschpe 12:b2dd49f04d5d 249 unsigned char u,l;
dreschpe 4:e1e45f8a7664 250 wr_reg(0x03, (x >> 0));
dreschpe 4:e1e45f8a7664 251 wr_reg(0x02, (x >> 8));
dreschpe 4:e1e45f8a7664 252 wr_reg(0x07, (y >> 0));
dreschpe 4:e1e45f8a7664 253 wr_reg(0x06, (y >> 8));
dreschpe 4:e1e45f8a7664 254 wr_cmd(0x22);
dreschpe 12:b2dd49f04d5d 255 u = color >> 8;
dreschpe 12:b2dd49f04d5d 256 l = color & 0xff;
dreschpe 13:d525819cb601 257 _cs = 0;
dreschpe 12:b2dd49f04d5d 258 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 259 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 260 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 261 LPC_SSP0->DR = u; // high byte
dreschpe 12:b2dd49f04d5d 262 LPC_SSP0->DR = l; // low byte
dreschpe 12:b2dd49f04d5d 263 LPC_SSP0->CR0 |= 0x08UL; // set back to 16 bit
dreschpe 13:d525819cb601 264 // we have to wait for SPI IDLE to set CS back to high
dreschpe 12:b2dd49f04d5d 265 do {
dreschpe 12:b2dd49f04d5d 266 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle
dreschpe 12:b2dd49f04d5d 267 } else {
dreschpe 12:b2dd49f04d5d 268 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 269 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 270 LPC_SSP1->DR = u;
dreschpe 12:b2dd49f04d5d 271 LPC_SSP1->DR = l;
dreschpe 12:b2dd49f04d5d 272 LPC_SSP1->CR0 |= 0x08UL; // set back to 16 bit
dreschpe 13:d525819cb601 273 // we have to wait for SPI IDLE to set CS back to high
dreschpe 12:b2dd49f04d5d 274 do {
dreschpe 12:b2dd49f04d5d 275 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
dreschpe 12:b2dd49f04d5d 276 }
dreschpe 13:d525819cb601 277 _cs = 1;
dreschpe 4:e1e45f8a7664 278 }
dreschpe 4:e1e45f8a7664 279
dreschpe 4:e1e45f8a7664 280
dreschpe 4:e1e45f8a7664 281 void SPI_TFT::window (unsigned int x, unsigned int y, unsigned int w, unsigned int h) {
dreschpe 12:b2dd49f04d5d 282 wr_reg(0x03, x );
dreschpe 4:e1e45f8a7664 283 wr_reg(0x02, (x >> 8));
dreschpe 12:b2dd49f04d5d 284 wr_reg(0x05, x+w-1 );
dreschpe 4:e1e45f8a7664 285 wr_reg(0x04, (x+w-1 >> 8));
dreschpe 12:b2dd49f04d5d 286 wr_reg(0x07, y );
dreschpe 4:e1e45f8a7664 287 wr_reg(0x06, ( y >> 8));
dreschpe 12:b2dd49f04d5d 288 wr_reg(0x09, ( y+h-1 ));
dreschpe 4:e1e45f8a7664 289 wr_reg(0x08, ( y+h-1 >> 8));
dreschpe 4:e1e45f8a7664 290 }
dreschpe 4:e1e45f8a7664 291
dreschpe 4:e1e45f8a7664 292
dreschpe 4:e1e45f8a7664 293 void SPI_TFT::WindowMax (void) {
dreschpe 4:e1e45f8a7664 294 window (0, 0, width(), height());
dreschpe 4:e1e45f8a7664 295 }
dreschpe 4:e1e45f8a7664 296
dreschpe 4:e1e45f8a7664 297
dreschpe 4:e1e45f8a7664 298 void SPI_TFT::cls (void) {
dreschpe 12:b2dd49f04d5d 299 //unsigned int i
dreschpe 12:b2dd49f04d5d 300
dreschpe 12:b2dd49f04d5d 301 int pixel = ( width() * height());
dreschpe 12:b2dd49f04d5d 302 int dma_count;
dreschpe 12:b2dd49f04d5d 303 int color = _background;
dreschpe 10:1e868317ff49 304 WindowMax();
dreschpe 4:e1e45f8a7664 305 wr_cmd(0x22);
dreschpe 12:b2dd49f04d5d 306
dreschpe 12:b2dd49f04d5d 307 // The SSEL signal is held low until the spi FIFO is emty.
dreschpe 12:b2dd49f04d5d 308 // We have to lower the SPI clock for the 8 bit start to get the spi running
dreschpe 12:b2dd49f04d5d 309 // until the next data word
dreschpe 13:d525819cb601 310
dreschpe 12:b2dd49f04d5d 311 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color;
dreschpe 12:b2dd49f04d5d 312
dreschpe 13:d525819cb601 313 _cs = 0;
dreschpe 12:b2dd49f04d5d 314 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 315 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 316 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 317 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 318 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 319 LPC_SSP0->DR = 0x72; // start byte
dreschpe 12:b2dd49f04d5d 320 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 12:b2dd49f04d5d 321 } else {
dreschpe 12:b2dd49f04d5d 322 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 323 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 324 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 325 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 326 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 327 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 13:d525819cb601 328 }
dreschpe 12:b2dd49f04d5d 329
dreschpe 12:b2dd49f04d5d 330 // start DMA
dreschpe 12:b2dd49f04d5d 331 do {
dreschpe 12:b2dd49f04d5d 332 if (pixel > 4095) {
dreschpe 12:b2dd49f04d5d 333 dma_count = 4095;
dreschpe 12:b2dd49f04d5d 334 pixel = pixel - 4095;
dreschpe 12:b2dd49f04d5d 335 } else {
dreschpe 12:b2dd49f04d5d 336 dma_count = pixel;
dreschpe 12:b2dd49f04d5d 337 pixel = 0;
dreschpe 12:b2dd49f04d5d 338 }
dreschpe 12:b2dd49f04d5d 339 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 340 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 341 LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt
dreschpe 12:b2dd49f04d5d 342 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 343 LPC_GPDMA->DMACSoftSReq = 0x1; // DMA request
dreschpe 12:b2dd49f04d5d 344
dreschpe 12:b2dd49f04d5d 345 do {
dreschpe 12:b2dd49f04d5d 346 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 347
dreschpe 12:b2dd49f04d5d 348 } while (pixel > 0);
dreschpe 12:b2dd49f04d5d 349 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 350 do {
dreschpe 12:b2dd49f04d5d 351 } while ((0x0010 & LPC_SSP0->SR) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 352 /* disable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 353 LPC_SSP0->DMACR = 0x0;
dreschpe 12:b2dd49f04d5d 354 } else {
dreschpe 12:b2dd49f04d5d 355 do {
dreschpe 12:b2dd49f04d5d 356 } while ((0x0010 & LPC_SSP1->SR) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 357 /* disable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 358 LPC_SSP1->DMACR = 0x0;
dreschpe 12:b2dd49f04d5d 359 }
dreschpe 13:d525819cb601 360 _cs = 1;
dreschpe 4:e1e45f8a7664 361 }
dreschpe 4:e1e45f8a7664 362
dreschpe 4:e1e45f8a7664 363
dreschpe 4:e1e45f8a7664 364 void SPI_TFT::circle(int x0, int y0, int r, int color) {
dreschpe 4:e1e45f8a7664 365
dreschpe 4:e1e45f8a7664 366 int draw_x0, draw_y0;
dreschpe 4:e1e45f8a7664 367 int draw_x1, draw_y1;
dreschpe 4:e1e45f8a7664 368 int draw_x2, draw_y2;
dreschpe 4:e1e45f8a7664 369 int draw_x3, draw_y3;
dreschpe 4:e1e45f8a7664 370 int draw_x4, draw_y4;
dreschpe 4:e1e45f8a7664 371 int draw_x5, draw_y5;
dreschpe 4:e1e45f8a7664 372 int draw_x6, draw_y6;
dreschpe 4:e1e45f8a7664 373 int draw_x7, draw_y7;
dreschpe 4:e1e45f8a7664 374 int xx, yy;
dreschpe 4:e1e45f8a7664 375 int di;
dreschpe 9:9dc5dfdda734 376 //WindowMax();
dreschpe 4:e1e45f8a7664 377 if (r == 0) { /* no radius */
dreschpe 4:e1e45f8a7664 378 return;
dreschpe 4:e1e45f8a7664 379 }
dreschpe 4:e1e45f8a7664 380
dreschpe 4:e1e45f8a7664 381 draw_x0 = draw_x1 = x0;
dreschpe 4:e1e45f8a7664 382 draw_y0 = draw_y1 = y0 + r;
dreschpe 4:e1e45f8a7664 383 if (draw_y0 < height()) {
dreschpe 4:e1e45f8a7664 384 pixel(draw_x0, draw_y0, color); /* 90 degree */
dreschpe 4:e1e45f8a7664 385 }
dreschpe 4:e1e45f8a7664 386
dreschpe 4:e1e45f8a7664 387 draw_x2 = draw_x3 = x0;
dreschpe 4:e1e45f8a7664 388 draw_y2 = draw_y3 = y0 - r;
dreschpe 4:e1e45f8a7664 389 if (draw_y2 >= 0) {
dreschpe 4:e1e45f8a7664 390 pixel(draw_x2, draw_y2, color); /* 270 degree */
dreschpe 4:e1e45f8a7664 391 }
dreschpe 4:e1e45f8a7664 392
dreschpe 4:e1e45f8a7664 393 draw_x4 = draw_x6 = x0 + r;
dreschpe 4:e1e45f8a7664 394 draw_y4 = draw_y6 = y0;
dreschpe 4:e1e45f8a7664 395 if (draw_x4 < width()) {
dreschpe 4:e1e45f8a7664 396 pixel(draw_x4, draw_y4, color); /* 0 degree */
dreschpe 4:e1e45f8a7664 397 }
dreschpe 4:e1e45f8a7664 398
dreschpe 4:e1e45f8a7664 399 draw_x5 = draw_x7 = x0 - r;
dreschpe 4:e1e45f8a7664 400 draw_y5 = draw_y7 = y0;
dreschpe 4:e1e45f8a7664 401 if (draw_x5>=0) {
dreschpe 4:e1e45f8a7664 402 pixel(draw_x5, draw_y5, color); /* 180 degree */
dreschpe 4:e1e45f8a7664 403 }
dreschpe 4:e1e45f8a7664 404
dreschpe 4:e1e45f8a7664 405 if (r == 1) {
dreschpe 4:e1e45f8a7664 406 return;
dreschpe 4:e1e45f8a7664 407 }
dreschpe 4:e1e45f8a7664 408
dreschpe 4:e1e45f8a7664 409 di = 3 - 2*r;
dreschpe 4:e1e45f8a7664 410 xx = 0;
dreschpe 4:e1e45f8a7664 411 yy = r;
dreschpe 4:e1e45f8a7664 412 while (xx < yy) {
dreschpe 4:e1e45f8a7664 413
dreschpe 4:e1e45f8a7664 414 if (di < 0) {
dreschpe 4:e1e45f8a7664 415 di += 4*xx + 6;
dreschpe 4:e1e45f8a7664 416 } else {
dreschpe 4:e1e45f8a7664 417 di += 4*(xx - yy) + 10;
dreschpe 4:e1e45f8a7664 418 yy--;
dreschpe 4:e1e45f8a7664 419 draw_y0--;
dreschpe 4:e1e45f8a7664 420 draw_y1--;
dreschpe 4:e1e45f8a7664 421 draw_y2++;
dreschpe 4:e1e45f8a7664 422 draw_y3++;
dreschpe 4:e1e45f8a7664 423 draw_x4--;
dreschpe 4:e1e45f8a7664 424 draw_x5++;
dreschpe 4:e1e45f8a7664 425 draw_x6--;
dreschpe 4:e1e45f8a7664 426 draw_x7++;
dreschpe 4:e1e45f8a7664 427 }
dreschpe 4:e1e45f8a7664 428 xx++;
dreschpe 4:e1e45f8a7664 429 draw_x0++;
dreschpe 4:e1e45f8a7664 430 draw_x1--;
dreschpe 4:e1e45f8a7664 431 draw_x2++;
dreschpe 4:e1e45f8a7664 432 draw_x3--;
dreschpe 4:e1e45f8a7664 433 draw_y4++;
dreschpe 4:e1e45f8a7664 434 draw_y5++;
dreschpe 4:e1e45f8a7664 435 draw_y6--;
dreschpe 4:e1e45f8a7664 436 draw_y7--;
dreschpe 4:e1e45f8a7664 437
dreschpe 4:e1e45f8a7664 438 if ( (draw_x0 <= width()) && (draw_y0>=0) ) {
dreschpe 4:e1e45f8a7664 439 pixel(draw_x0, draw_y0, color);
dreschpe 4:e1e45f8a7664 440 }
dreschpe 4:e1e45f8a7664 441
dreschpe 4:e1e45f8a7664 442 if ( (draw_x1 >= 0) && (draw_y1 >= 0) ) {
dreschpe 4:e1e45f8a7664 443 pixel(draw_x1, draw_y1, color);
dreschpe 4:e1e45f8a7664 444 }
dreschpe 4:e1e45f8a7664 445
dreschpe 4:e1e45f8a7664 446 if ( (draw_x2 <= width()) && (draw_y2 <= height()) ) {
dreschpe 4:e1e45f8a7664 447 pixel(draw_x2, draw_y2, color);
dreschpe 4:e1e45f8a7664 448 }
dreschpe 4:e1e45f8a7664 449
dreschpe 4:e1e45f8a7664 450 if ( (draw_x3 >=0 ) && (draw_y3 <= height()) ) {
dreschpe 4:e1e45f8a7664 451 pixel(draw_x3, draw_y3, color);
dreschpe 4:e1e45f8a7664 452 }
dreschpe 4:e1e45f8a7664 453
dreschpe 4:e1e45f8a7664 454 if ( (draw_x4 <= width()) && (draw_y4 >= 0) ) {
dreschpe 4:e1e45f8a7664 455 pixel(draw_x4, draw_y4, color);
dreschpe 4:e1e45f8a7664 456 }
dreschpe 4:e1e45f8a7664 457
dreschpe 4:e1e45f8a7664 458 if ( (draw_x5 >= 0) && (draw_y5 >= 0) ) {
dreschpe 4:e1e45f8a7664 459 pixel(draw_x5, draw_y5, color);
dreschpe 4:e1e45f8a7664 460 }
dreschpe 4:e1e45f8a7664 461 if ( (draw_x6 <=width()) && (draw_y6 <= height()) ) {
dreschpe 4:e1e45f8a7664 462 pixel(draw_x6, draw_y6, color);
dreschpe 4:e1e45f8a7664 463 }
dreschpe 4:e1e45f8a7664 464 if ( (draw_x7 >= 0) && (draw_y7 <= height()) ) {
dreschpe 4:e1e45f8a7664 465 pixel(draw_x7, draw_y7, color);
dreschpe 4:e1e45f8a7664 466 }
dreschpe 4:e1e45f8a7664 467 }
dreschpe 4:e1e45f8a7664 468 return;
dreschpe 4:e1e45f8a7664 469 }
dreschpe 4:e1e45f8a7664 470
dreschpe 5:2db1b8070d94 471 void SPI_TFT::fillcircle(int x, int y, int r, int color) {
dreschpe 4:e1e45f8a7664 472 int i;
dreschpe 5:2db1b8070d94 473 for (i = 0; i <= r; i++)
dreschpe 4:e1e45f8a7664 474 circle(x,y,i,color);
dreschpe 4:e1e45f8a7664 475 }
dreschpe 4:e1e45f8a7664 476
dreschpe 4:e1e45f8a7664 477
dreschpe 4:e1e45f8a7664 478
dreschpe 4:e1e45f8a7664 479 void SPI_TFT::hline(int x0, int x1, int y, int color) {
dreschpe 4:e1e45f8a7664 480 int w;
dreschpe 4:e1e45f8a7664 481 w = x1 - x0 + 1;
dreschpe 4:e1e45f8a7664 482 window(x0,y,w,1);
dreschpe 4:e1e45f8a7664 483 wr_cmd(0x22);
dreschpe 13:d525819cb601 484 _cs = 0;
dreschpe 12:b2dd49f04d5d 485 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 486 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 487 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 488 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 489 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 490 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 491 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 12:b2dd49f04d5d 492 } else {
dreschpe 12:b2dd49f04d5d 493 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 494 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 495 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 496 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 497 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 498 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 4:e1e45f8a7664 499 }
dreschpe 12:b2dd49f04d5d 500
dreschpe 12:b2dd49f04d5d 501 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 502 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 503 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color;
dreschpe 12:b2dd49f04d5d 504 LPC_GPDMACH0->DMACCControl = w | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt
dreschpe 12:b2dd49f04d5d 505 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 506 LPC_GPDMA->DMACSoftSReq = 0x1; // start DMA
dreschpe 12:b2dd49f04d5d 507 do {
dreschpe 12:b2dd49f04d5d 508 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 509 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 510 do {
dreschpe 12:b2dd49f04d5d 511 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 512 } else {
dreschpe 12:b2dd49f04d5d 513 do {
dreschpe 12:b2dd49f04d5d 514 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 515 }
dreschpe 13:d525819cb601 516 _cs = 1;
dreschpe 9:9dc5dfdda734 517 WindowMax();
dreschpe 4:e1e45f8a7664 518 return;
dreschpe 4:e1e45f8a7664 519 }
dreschpe 4:e1e45f8a7664 520
dreschpe 4:e1e45f8a7664 521 void SPI_TFT::vline(int x, int y0, int y1, int color) {
dreschpe 4:e1e45f8a7664 522 int h;
dreschpe 4:e1e45f8a7664 523 h = y1 - y0 + 1;
dreschpe 4:e1e45f8a7664 524 window(x,y0,1,h);
dreschpe 4:e1e45f8a7664 525 wr_cmd(0x22);
dreschpe 13:d525819cb601 526 _cs = 0;
dreschpe 12:b2dd49f04d5d 527 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 528 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 529 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 530 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 531 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 532 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 533 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 13:d525819cb601 534 } else {
dreschpe 12:b2dd49f04d5d 535 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 536 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 537 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 538 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 539 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 540 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 4:e1e45f8a7664 541 }
dreschpe 12:b2dd49f04d5d 542
dreschpe 12:b2dd49f04d5d 543 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 544 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 545 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color;
dreschpe 12:b2dd49f04d5d 546 LPC_GPDMACH0->DMACCControl = h | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt
dreschpe 12:b2dd49f04d5d 547 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 548 LPC_GPDMA->DMACSoftSReq = 0x1;
dreschpe 12:b2dd49f04d5d 549 do {
dreschpe 12:b2dd49f04d5d 550 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 551
dreschpe 12:b2dd49f04d5d 552 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 553 do {
dreschpe 12:b2dd49f04d5d 554 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 555 } else {
dreschpe 12:b2dd49f04d5d 556 do {
dreschpe 12:b2dd49f04d5d 557 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 558 }
dreschpe 13:d525819cb601 559 _cs = 1;
dreschpe 9:9dc5dfdda734 560 WindowMax();
dreschpe 4:e1e45f8a7664 561 return;
dreschpe 4:e1e45f8a7664 562 }
dreschpe 4:e1e45f8a7664 563
dreschpe 4:e1e45f8a7664 564
dreschpe 4:e1e45f8a7664 565
dreschpe 4:e1e45f8a7664 566 void SPI_TFT::line(int x0, int y0, int x1, int y1, int color) {
dreschpe 9:9dc5dfdda734 567 //WindowMax();
dreschpe 4:e1e45f8a7664 568 int dx = 0, dy = 0;
dreschpe 4:e1e45f8a7664 569 int dx_sym = 0, dy_sym = 0;
dreschpe 4:e1e45f8a7664 570 int dx_x2 = 0, dy_x2 = 0;
dreschpe 4:e1e45f8a7664 571 int di = 0;
dreschpe 4:e1e45f8a7664 572
dreschpe 4:e1e45f8a7664 573 dx = x1-x0;
dreschpe 4:e1e45f8a7664 574 dy = y1-y0;
dreschpe 4:e1e45f8a7664 575
dreschpe 4:e1e45f8a7664 576 if (dx == 0) { /* vertical line */
dreschpe 4:e1e45f8a7664 577 if (y1 > y0) vline(x0,y0,y1,color);
dreschpe 4:e1e45f8a7664 578 else vline(x0,y1,y0,color);
dreschpe 4:e1e45f8a7664 579 return;
dreschpe 4:e1e45f8a7664 580 }
dreschpe 4:e1e45f8a7664 581
dreschpe 4:e1e45f8a7664 582 if (dx > 0) {
dreschpe 4:e1e45f8a7664 583 dx_sym = 1;
dreschpe 4:e1e45f8a7664 584 } else {
dreschpe 4:e1e45f8a7664 585 dx_sym = -1;
dreschpe 4:e1e45f8a7664 586 }
dreschpe 4:e1e45f8a7664 587 if (dy == 0) { /* horizontal line */
dreschpe 4:e1e45f8a7664 588 if (x1 > x0) hline(x0,x1,y0,color);
dreschpe 4:e1e45f8a7664 589 else hline(x1,x0,y0,color);
dreschpe 4:e1e45f8a7664 590 return;
dreschpe 4:e1e45f8a7664 591 }
dreschpe 4:e1e45f8a7664 592
dreschpe 4:e1e45f8a7664 593 if (dy > 0) {
dreschpe 4:e1e45f8a7664 594 dy_sym = 1;
dreschpe 4:e1e45f8a7664 595 } else {
dreschpe 4:e1e45f8a7664 596 dy_sym = -1;
dreschpe 4:e1e45f8a7664 597 }
dreschpe 4:e1e45f8a7664 598
dreschpe 4:e1e45f8a7664 599 dx = dx_sym*dx;
dreschpe 4:e1e45f8a7664 600 dy = dy_sym*dy;
dreschpe 4:e1e45f8a7664 601
dreschpe 4:e1e45f8a7664 602 dx_x2 = dx*2;
dreschpe 4:e1e45f8a7664 603 dy_x2 = dy*2;
dreschpe 4:e1e45f8a7664 604
dreschpe 4:e1e45f8a7664 605 if (dx >= dy) {
dreschpe 4:e1e45f8a7664 606 di = dy_x2 - dx;
dreschpe 4:e1e45f8a7664 607 while (x0 != x1) {
dreschpe 4:e1e45f8a7664 608
dreschpe 4:e1e45f8a7664 609 pixel(x0, y0, color);
dreschpe 4:e1e45f8a7664 610 x0 += dx_sym;
dreschpe 4:e1e45f8a7664 611 if (di<0) {
dreschpe 4:e1e45f8a7664 612 di += dy_x2;
dreschpe 4:e1e45f8a7664 613 } else {
dreschpe 4:e1e45f8a7664 614 di += dy_x2 - dx_x2;
dreschpe 4:e1e45f8a7664 615 y0 += dy_sym;
dreschpe 4:e1e45f8a7664 616 }
dreschpe 4:e1e45f8a7664 617 }
dreschpe 4:e1e45f8a7664 618 pixel(x0, y0, color);
dreschpe 4:e1e45f8a7664 619 } else {
dreschpe 4:e1e45f8a7664 620 di = dx_x2 - dy;
dreschpe 4:e1e45f8a7664 621 while (y0 != y1) {
dreschpe 4:e1e45f8a7664 622 pixel(x0, y0, color);
dreschpe 4:e1e45f8a7664 623 y0 += dy_sym;
dreschpe 4:e1e45f8a7664 624 if (di < 0) {
dreschpe 4:e1e45f8a7664 625 di += dx_x2;
dreschpe 4:e1e45f8a7664 626 } else {
dreschpe 4:e1e45f8a7664 627 di += dx_x2 - dy_x2;
dreschpe 4:e1e45f8a7664 628 x0 += dx_sym;
dreschpe 4:e1e45f8a7664 629 }
dreschpe 4:e1e45f8a7664 630 }
dreschpe 4:e1e45f8a7664 631 pixel(x0, y0, color);
dreschpe 4:e1e45f8a7664 632 }
dreschpe 4:e1e45f8a7664 633 return;
dreschpe 4:e1e45f8a7664 634 }
dreschpe 4:e1e45f8a7664 635
dreschpe 4:e1e45f8a7664 636
dreschpe 4:e1e45f8a7664 637 void SPI_TFT::rect(int x0, int y0, int x1, int y1, int color) {
dreschpe 4:e1e45f8a7664 638
dreschpe 4:e1e45f8a7664 639 if (x1 > x0) hline(x0,x1,y0,color);
dreschpe 4:e1e45f8a7664 640 else hline(x1,x0,y0,color);
dreschpe 4:e1e45f8a7664 641
dreschpe 4:e1e45f8a7664 642 if (y1 > y0) vline(x0,y0,y1,color);
dreschpe 4:e1e45f8a7664 643 else vline(x0,y1,y0,color);
dreschpe 4:e1e45f8a7664 644
dreschpe 4:e1e45f8a7664 645 if (x1 > x0) hline(x0,x1,y1,color);
dreschpe 4:e1e45f8a7664 646 else hline(x1,x0,y1,color);
dreschpe 4:e1e45f8a7664 647
dreschpe 4:e1e45f8a7664 648 if (y1 > y0) vline(x1,y0,y1,color);
dreschpe 4:e1e45f8a7664 649 else vline(x1,y1,y0,color);
dreschpe 4:e1e45f8a7664 650
dreschpe 4:e1e45f8a7664 651 return;
dreschpe 4:e1e45f8a7664 652 }
dreschpe 4:e1e45f8a7664 653
dreschpe 4:e1e45f8a7664 654
dreschpe 4:e1e45f8a7664 655
dreschpe 4:e1e45f8a7664 656 void SPI_TFT::fillrect(int x0, int y0, int x1, int y1, int color) {
dreschpe 4:e1e45f8a7664 657
dreschpe 4:e1e45f8a7664 658 int h = y1 - y0 + 1;
dreschpe 4:e1e45f8a7664 659 int w = x1 - x0 + 1;
dreschpe 4:e1e45f8a7664 660 int pixel = h * w;
dreschpe 12:b2dd49f04d5d 661 int dma_count;
dreschpe 4:e1e45f8a7664 662 window(x0,y0,w,h);
dreschpe 4:e1e45f8a7664 663 wr_cmd(0x22);
dreschpe 13:d525819cb601 664 _cs = 0;
dreschpe 12:b2dd49f04d5d 665 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 666 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 667 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 668 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 669 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 670 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 671 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 13:d525819cb601 672 } else {
dreschpe 12:b2dd49f04d5d 673 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 674 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 675 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 676 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 677 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 678 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 4:e1e45f8a7664 679 }
dreschpe 12:b2dd49f04d5d 680
dreschpe 12:b2dd49f04d5d 681 do {
dreschpe 12:b2dd49f04d5d 682 if (pixel > 4095) {
dreschpe 12:b2dd49f04d5d 683 dma_count = 4095;
dreschpe 12:b2dd49f04d5d 684 pixel = pixel - 4095;
dreschpe 12:b2dd49f04d5d 685 } else {
dreschpe 12:b2dd49f04d5d 686 dma_count = pixel;
dreschpe 12:b2dd49f04d5d 687 pixel = 0;
dreschpe 12:b2dd49f04d5d 688 }
dreschpe 12:b2dd49f04d5d 689 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 690 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 691 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)&color;
dreschpe 12:b2dd49f04d5d 692 LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) ; // 16 bit transfer , no address increment, interrupt
dreschpe 12:b2dd49f04d5d 693 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 694 LPC_GPDMA->DMACSoftSReq = 0x1;
dreschpe 12:b2dd49f04d5d 695 do {
dreschpe 12:b2dd49f04d5d 696 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 697
dreschpe 12:b2dd49f04d5d 698 } while (pixel > 0);
dreschpe 12:b2dd49f04d5d 699
dreschpe 12:b2dd49f04d5d 700 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 701 do {
dreschpe 12:b2dd49f04d5d 702 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 703 } else {
dreschpe 12:b2dd49f04d5d 704 do {
dreschpe 12:b2dd49f04d5d 705 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 706 }
dreschpe 13:d525819cb601 707 _cs = 1;
dreschpe 9:9dc5dfdda734 708 WindowMax();
dreschpe 4:e1e45f8a7664 709 return;
dreschpe 4:e1e45f8a7664 710 }
dreschpe 4:e1e45f8a7664 711
dreschpe 4:e1e45f8a7664 712
dreschpe 6:fc33e4a5713e 713 void SPI_TFT::locate(int x, int y) {
dreschpe 6:fc33e4a5713e 714 char_x = x;
dreschpe 6:fc33e4a5713e 715 char_y = y;
dreschpe 4:e1e45f8a7664 716 }
dreschpe 4:e1e45f8a7664 717
dreschpe 4:e1e45f8a7664 718
dreschpe 4:e1e45f8a7664 719
dreschpe 4:e1e45f8a7664 720 int SPI_TFT::columns() {
dreschpe 4:e1e45f8a7664 721 return width() / font[1];
dreschpe 4:e1e45f8a7664 722 }
dreschpe 4:e1e45f8a7664 723
dreschpe 4:e1e45f8a7664 724
dreschpe 4:e1e45f8a7664 725
dreschpe 4:e1e45f8a7664 726 int SPI_TFT::rows() {
dreschpe 4:e1e45f8a7664 727 return height() / font[2];
dreschpe 4:e1e45f8a7664 728 }
dreschpe 4:e1e45f8a7664 729
dreschpe 4:e1e45f8a7664 730
dreschpe 4:e1e45f8a7664 731
dreschpe 4:e1e45f8a7664 732 int SPI_TFT::_putc(int value) {
dreschpe 6:fc33e4a5713e 733 if (value == '\n') { // new line
dreschpe 4:e1e45f8a7664 734 char_x = 0;
dreschpe 6:fc33e4a5713e 735 char_y = char_y + font[2];
dreschpe 6:fc33e4a5713e 736 if (char_y >= height() - font[2]) {
dreschpe 6:fc33e4a5713e 737 char_y = 0;
dreschpe 4:e1e45f8a7664 738 }
dreschpe 4:e1e45f8a7664 739 } else {
dreschpe 6:fc33e4a5713e 740 character(char_x, char_y, value);
dreschpe 12:b2dd49f04d5d 741 }
dreschpe 4:e1e45f8a7664 742 return value;
dreschpe 4:e1e45f8a7664 743 }
dreschpe 4:e1e45f8a7664 744
dreschpe 4:e1e45f8a7664 745
dreschpe 4:e1e45f8a7664 746
dreschpe 4:e1e45f8a7664 747
dreschpe 6:fc33e4a5713e 748 void SPI_TFT::character(int x, int y, int c) {
dreschpe 12:b2dd49f04d5d 749 unsigned int hor,vert,offset,bpl,j,i,b,p;
dreschpe 4:e1e45f8a7664 750 unsigned char* zeichen;
dreschpe 4:e1e45f8a7664 751 unsigned char z,w;
dreschpe 12:b2dd49f04d5d 752 unsigned int pixel;
dreschpe 12:b2dd49f04d5d 753 unsigned int dma_count,dma_off;
dreschpe 12:b2dd49f04d5d 754 uint16_t *buffer;
dreschpe 4:e1e45f8a7664 755
dreschpe 4:e1e45f8a7664 756 if ((c < 31) || (c > 127)) return; // test char range
dreschpe 4:e1e45f8a7664 757
dreschpe 4:e1e45f8a7664 758 // read font parameter from start of array
dreschpe 4:e1e45f8a7664 759 offset = font[0]; // bytes / char
dreschpe 4:e1e45f8a7664 760 hor = font[1]; // get hor size of font
dreschpe 4:e1e45f8a7664 761 vert = font[2]; // get vert size of font
dreschpe 4:e1e45f8a7664 762 bpl = font[3]; // bytes per line
dreschpe 4:e1e45f8a7664 763
dreschpe 4:e1e45f8a7664 764 if (char_x + hor > width()) {
dreschpe 4:e1e45f8a7664 765 char_x = 0;
dreschpe 6:fc33e4a5713e 766 char_y = char_y + vert;
dreschpe 12:b2dd49f04d5d 767 if (char_y >= height() - font[2]) {
dreschpe 6:fc33e4a5713e 768 char_y = 0;
dreschpe 4:e1e45f8a7664 769 }
dreschpe 4:e1e45f8a7664 770 }
dreschpe 6:fc33e4a5713e 771 window(char_x, char_y,hor,vert); // char box
dreschpe 4:e1e45f8a7664 772 wr_cmd(0x22);
dreschpe 12:b2dd49f04d5d 773
dreschpe 12:b2dd49f04d5d 774 pixel = hor * vert; // calculate buffer size
dreschpe 12:b2dd49f04d5d 775
dreschpe 12:b2dd49f04d5d 776 buffer = (uint16_t *) malloc (2*pixel); // we need a buffer for the 16 bit
dreschpe 12:b2dd49f04d5d 777 if (buffer == NULL) {
dreschpe 12:b2dd49f04d5d 778 //led = 1;
dreschpe 12:b2dd49f04d5d 779 //pc.printf("Malloc error !\n\r");
dreschpe 12:b2dd49f04d5d 780 return; // error no memory
dreschpe 12:b2dd49f04d5d 781 }
dreschpe 12:b2dd49f04d5d 782
dreschpe 4:e1e45f8a7664 783 zeichen = &font[((c -32) * offset) + 4]; // start of char bitmap
dreschpe 4:e1e45f8a7664 784 w = zeichen[0]; // width of actual char
dreschpe 12:b2dd49f04d5d 785 p = 0;
dreschpe 12:b2dd49f04d5d 786 // construct the char into the buffer
dreschpe 4:e1e45f8a7664 787 for (j=0; j<vert; j++) { // vert line
dreschpe 4:e1e45f8a7664 788 for (i=0; i<hor; i++) { // horz line
dreschpe 4:e1e45f8a7664 789 z = zeichen[bpl * i + ((j & 0xF8) >> 3)+1];
dreschpe 4:e1e45f8a7664 790 b = 1 << (j & 0x07);
dreschpe 4:e1e45f8a7664 791 if (( z & b ) == 0x00) {
dreschpe 12:b2dd49f04d5d 792 buffer[p] = _background;
dreschpe 4:e1e45f8a7664 793 } else {
dreschpe 12:b2dd49f04d5d 794 buffer[p] = _foreground;
dreschpe 4:e1e45f8a7664 795 }
dreschpe 12:b2dd49f04d5d 796 p++;
dreschpe 4:e1e45f8a7664 797 }
dreschpe 4:e1e45f8a7664 798 }
dreschpe 12:b2dd49f04d5d 799
dreschpe 12:b2dd49f04d5d 800
dreschpe 12:b2dd49f04d5d 801 // copy the buffer with DMA SPI to display
dreschpe 12:b2dd49f04d5d 802 dma_off = 0; // offset for DMA transfer
dreschpe 13:d525819cb601 803 _cs = 0;
dreschpe 12:b2dd49f04d5d 804 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 805 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 806 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 807 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 808 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 809 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 810 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 12:b2dd49f04d5d 811 } else {
dreschpe 12:b2dd49f04d5d 812 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 813 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 814 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 815 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 816 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 817 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 12:b2dd49f04d5d 818 }
dreschpe 12:b2dd49f04d5d 819
dreschpe 12:b2dd49f04d5d 820 // start DMA
dreschpe 12:b2dd49f04d5d 821 do {
dreschpe 12:b2dd49f04d5d 822 if (pixel > 4095) { // this is a giant font !
dreschpe 12:b2dd49f04d5d 823 dma_count = 4095;
dreschpe 12:b2dd49f04d5d 824 pixel = pixel - 4095;
dreschpe 12:b2dd49f04d5d 825 } else {
dreschpe 12:b2dd49f04d5d 826 dma_count = pixel;
dreschpe 12:b2dd49f04d5d 827 pixel = 0;
dreschpe 12:b2dd49f04d5d 828 }
dreschpe 12:b2dd49f04d5d 829 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 830 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 831 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t) (buffer + dma_off);
dreschpe 12:b2dd49f04d5d 832 LPC_GPDMACH0->DMACCControl = dma_count | (1UL << 18) | (1UL << 21) | (1UL << 31) | DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt
dreschpe 12:b2dd49f04d5d 833 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 834 LPC_GPDMA->DMACSoftSReq = 0x1;
dreschpe 12:b2dd49f04d5d 835 do {
dreschpe 12:b2dd49f04d5d 836 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 837 dma_off = dma_off + dma_count;
dreschpe 12:b2dd49f04d5d 838 } while (pixel > 0);
dreschpe 12:b2dd49f04d5d 839
dreschpe 12:b2dd49f04d5d 840 free ((uint16_t *) buffer);
dreschpe 12:b2dd49f04d5d 841
dreschpe 12:b2dd49f04d5d 842 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 843 do {
dreschpe 12:b2dd49f04d5d 844 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI0 not idle
dreschpe 12:b2dd49f04d5d 845 /* disable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 846 LPC_SSP0->DMACR = 0x0;
dreschpe 12:b2dd49f04d5d 847 } else {
dreschpe 12:b2dd49f04d5d 848 do {
dreschpe 12:b2dd49f04d5d 849 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI1 not idle
dreschpe 12:b2dd49f04d5d 850 /* disable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 851 LPC_SSP1->DMACR = 0x0;
dreschpe 12:b2dd49f04d5d 852 }
dreschpe 13:d525819cb601 853 _cs = 1;
dreschpe 9:9dc5dfdda734 854 WindowMax();
dreschpe 4:e1e45f8a7664 855 if ((w + 2) < hor) { // x offset to next char
dreschpe 4:e1e45f8a7664 856 char_x += w + 2;
dreschpe 4:e1e45f8a7664 857 } else char_x += hor;
dreschpe 12:b2dd49f04d5d 858
dreschpe 4:e1e45f8a7664 859 }
dreschpe 4:e1e45f8a7664 860
dreschpe 4:e1e45f8a7664 861
dreschpe 4:e1e45f8a7664 862 void SPI_TFT::set_font(unsigned char* f) {
dreschpe 4:e1e45f8a7664 863 font = f;
dreschpe 4:e1e45f8a7664 864 }
dreschpe 4:e1e45f8a7664 865
dreschpe 4:e1e45f8a7664 866
dreschpe 4:e1e45f8a7664 867
dreschpe 4:e1e45f8a7664 868 void SPI_TFT::Bitmap(unsigned int x, unsigned int y, unsigned int w, unsigned int h,unsigned char *bitmap) {
dreschpe 12:b2dd49f04d5d 869 unsigned int j;
dreschpe 12:b2dd49f04d5d 870 int padd;
dreschpe 4:e1e45f8a7664 871 unsigned short *bitmap_ptr = (unsigned short *)bitmap;
dreschpe 12:b2dd49f04d5d 872 // the lines are padded to multiple of 4 bytes in a bitmap
dreschpe 6:fc33e4a5713e 873 padd = -1;
dreschpe 6:fc33e4a5713e 874 do {
dreschpe 6:fc33e4a5713e 875 padd ++;
dreschpe 6:fc33e4a5713e 876 } while (2*(w + padd)%4 != 0);
dreschpe 4:e1e45f8a7664 877 window(x, y, w, h);
dreschpe 4:e1e45f8a7664 878 wr_cmd(0x22);
dreschpe 13:d525819cb601 879 _cs = 0;
dreschpe 12:b2dd49f04d5d 880 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 881 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 882 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 883 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 884 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 885 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 886 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 12:b2dd49f04d5d 887 } else {
dreschpe 12:b2dd49f04d5d 888 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 889 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 890 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 891 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 892 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 893 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 12:b2dd49f04d5d 894 }
dreschpe 6:fc33e4a5713e 895 bitmap_ptr += ((h - 1)* (w + padd));
dreschpe 4:e1e45f8a7664 896 for (j = 0; j < h; j++) { //Lines
dreschpe 12:b2dd49f04d5d 897 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 898 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 899 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)bitmap_ptr;
dreschpe 12:b2dd49f04d5d 900 LPC_GPDMACH0->DMACCControl = w | (1UL << 18) | (1UL << 21) | (1UL << 31) | DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt
dreschpe 12:b2dd49f04d5d 901 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 902 LPC_GPDMA->DMACSoftSReq = 0x1;
dreschpe 12:b2dd49f04d5d 903 do {
dreschpe 12:b2dd49f04d5d 904 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 905
dreschpe 12:b2dd49f04d5d 906 bitmap_ptr -= w;
dreschpe 6:fc33e4a5713e 907 bitmap_ptr -= padd;
dreschpe 4:e1e45f8a7664 908 }
dreschpe 12:b2dd49f04d5d 909
dreschpe 12:b2dd49f04d5d 910 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 911 do {
dreschpe 12:b2dd49f04d5d 912 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 913 } else {
dreschpe 12:b2dd49f04d5d 914 do {
dreschpe 12:b2dd49f04d5d 915 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 916 }
dreschpe 13:d525819cb601 917 _cs = 1;
dreschpe 9:9dc5dfdda734 918 WindowMax();
dreschpe 5:2db1b8070d94 919 }
dreschpe 5:2db1b8070d94 920
dreschpe 5:2db1b8070d94 921
dreschpe 5:2db1b8070d94 922 int SPI_TFT::BMP_16(unsigned int x, unsigned int y, const char *Name_BMP) {
dreschpe 5:2db1b8070d94 923
dreschpe 5:2db1b8070d94 924 #define OffsetPixelWidth 18
dreschpe 5:2db1b8070d94 925 #define OffsetPixelHeigh 22
dreschpe 5:2db1b8070d94 926 #define OffsetFileSize 34
dreschpe 5:2db1b8070d94 927 #define OffsetPixData 10
dreschpe 5:2db1b8070d94 928 #define OffsetBPP 28
dreschpe 5:2db1b8070d94 929
dreschpe 5:2db1b8070d94 930 char filename[50];
dreschpe 5:2db1b8070d94 931 unsigned char BMP_Header[54];
dreschpe 5:2db1b8070d94 932 unsigned short BPP_t;
dreschpe 5:2db1b8070d94 933 unsigned int PixelWidth,PixelHeigh,start_data;
dreschpe 5:2db1b8070d94 934 unsigned int i,off;
dreschpe 5:2db1b8070d94 935 int padd,j;
dreschpe 5:2db1b8070d94 936 unsigned short *line;
dreschpe 5:2db1b8070d94 937
dreschpe 5:2db1b8070d94 938 // get the filename
dreschpe 5:2db1b8070d94 939 LocalFileSystem local("local");
dreschpe 5:2db1b8070d94 940 sprintf(&filename[0],"/local/");
dreschpe 5:2db1b8070d94 941 i=7;
dreschpe 5:2db1b8070d94 942 while (*Name_BMP!='\0') {
dreschpe 5:2db1b8070d94 943 filename[i++]=*Name_BMP++;
dreschpe 5:2db1b8070d94 944 }
dreschpe 12:b2dd49f04d5d 945
dreschpe 12:b2dd49f04d5d 946 fprintf(stderr, "filename : %s \n\r",filename);
dreschpe 12:b2dd49f04d5d 947
dreschpe 5:2db1b8070d94 948 FILE *Image = fopen((const char *)&filename[0], "r"); // open the bmp file
dreschpe 5:2db1b8070d94 949 if (!Image) {
dreschpe 5:2db1b8070d94 950 return(0); // error file not found !
dreschpe 5:2db1b8070d94 951 }
dreschpe 5:2db1b8070d94 952
dreschpe 5:2db1b8070d94 953 fread(&BMP_Header[0],1,54,Image); // get the BMP Header
dreschpe 5:2db1b8070d94 954
dreschpe 5:2db1b8070d94 955 if (BMP_Header[0] != 0x42 || BMP_Header[1] != 0x4D) { // check magic byte
dreschpe 5:2db1b8070d94 956 fclose(Image);
dreschpe 5:2db1b8070d94 957 return(-1); // error no BMP file
dreschpe 5:2db1b8070d94 958 }
dreschpe 5:2db1b8070d94 959
dreschpe 5:2db1b8070d94 960 BPP_t = BMP_Header[OffsetBPP] + (BMP_Header[OffsetBPP + 1] << 8);
dreschpe 5:2db1b8070d94 961 if (BPP_t != 0x0010) {
dreschpe 5:2db1b8070d94 962 fclose(Image);
dreschpe 5:2db1b8070d94 963 return(-2); // error no 16 bit BMP
dreschpe 5:2db1b8070d94 964 }
dreschpe 5:2db1b8070d94 965
dreschpe 5:2db1b8070d94 966 PixelHeigh = BMP_Header[OffsetPixelHeigh] + (BMP_Header[OffsetPixelHeigh + 1] << 8) + (BMP_Header[OffsetPixelHeigh + 2] << 16) + (BMP_Header[OffsetPixelHeigh + 3] << 24);
dreschpe 5:2db1b8070d94 967 PixelWidth = BMP_Header[OffsetPixelWidth] + (BMP_Header[OffsetPixelWidth + 1] << 8) + (BMP_Header[OffsetPixelWidth + 2] << 16) + (BMP_Header[OffsetPixelWidth + 3] << 24);
dreschpe 5:2db1b8070d94 968 if (PixelHeigh > height() + y || PixelWidth > width() + x) {
dreschpe 5:2db1b8070d94 969 fclose(Image);
dreschpe 5:2db1b8070d94 970 return(-3); // to big
dreschpe 5:2db1b8070d94 971 }
dreschpe 5:2db1b8070d94 972
dreschpe 5:2db1b8070d94 973 start_data = BMP_Header[OffsetPixData] + (BMP_Header[OffsetPixData + 1] << 8) + (BMP_Header[OffsetPixData + 2] << 16) + (BMP_Header[OffsetPixData + 3] << 24);
dreschpe 12:b2dd49f04d5d 974
dreschpe 12:b2dd49f04d5d 975 line = (unsigned short *) malloc (2 * PixelWidth); // we need a buffer for a line
dreschpe 5:2db1b8070d94 976 if (line == NULL) {
dreschpe 5:2db1b8070d94 977 return(-4); // error no memory
dreschpe 5:2db1b8070d94 978 }
dreschpe 5:2db1b8070d94 979
dreschpe 12:b2dd49f04d5d 980 // the bmp lines are padded to multiple of 4 bytes
dreschpe 5:2db1b8070d94 981 padd = -1;
dreschpe 5:2db1b8070d94 982 do {
dreschpe 5:2db1b8070d94 983 padd ++;
dreschpe 5:2db1b8070d94 984 } while ((PixelWidth * 2 + padd)%4 != 0);
dreschpe 5:2db1b8070d94 985
dreschpe 12:b2dd49f04d5d 986 window(x, y,PixelWidth+1,PixelHeigh);
dreschpe 5:2db1b8070d94 987 wr_cmd(0x22);
dreschpe 13:d525819cb601 988 _cs = 0;
dreschpe 5:2db1b8070d94 989 for (j = PixelHeigh - 1; j >= 0; j--) { //Lines bottom up
dreschpe 5:2db1b8070d94 990 off = j * (PixelWidth * 2 + padd) + start_data; // start of line
dreschpe 5:2db1b8070d94 991 fseek(Image, off ,SEEK_SET);
dreschpe 5:2db1b8070d94 992 fread(line,1,PixelWidth * 2,Image); // read a line - slow !
dreschpe 12:b2dd49f04d5d 993 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 994 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP0->DR; // we send to SSP0
dreschpe 12:b2dd49f04d5d 995 /* Enable SSP0 for DMA. */
dreschpe 12:b2dd49f04d5d 996 LPC_SSP0->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 997 LPC_SSP0->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 998 LPC_SSP0->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 999 LPC_SSP0->CR0 |= 0x08UL; // set to 16 bit
dreschpe 13:d525819cb601 1000 } else {
dreschpe 12:b2dd49f04d5d 1001 LPC_GPDMACH0->DMACCDestAddr = (uint32_t)&LPC_SSP1->DR; // we send to SSP1
dreschpe 12:b2dd49f04d5d 1002 /* Enable SSP1 for DMA. */
dreschpe 12:b2dd49f04d5d 1003 LPC_SSP1->DMACR = 0x2;
dreschpe 12:b2dd49f04d5d 1004 LPC_SSP1->CR0 &= ~(0x08UL); // set to 8 bit
dreschpe 12:b2dd49f04d5d 1005 LPC_SSP1->DR = 0x72; // start Data
dreschpe 12:b2dd49f04d5d 1006 LPC_SSP1->CR0 |= 0x08UL; // set to 16 bit
dreschpe 13:d525819cb601 1007 }
dreschpe 12:b2dd49f04d5d 1008
dreschpe 12:b2dd49f04d5d 1009 LPC_GPDMA->DMACIntTCClear = 0x1;
dreschpe 12:b2dd49f04d5d 1010 LPC_GPDMA->DMACIntErrClr = 0x1;
dreschpe 12:b2dd49f04d5d 1011 LPC_GPDMACH0->DMACCSrcAddr = (uint32_t)line;
dreschpe 12:b2dd49f04d5d 1012 LPC_GPDMACH0->DMACCControl = PixelWidth | (1UL << 18) | (1UL << 21) | (1UL << 31) | DMA_CHANNEL_SRC_INC ; // 16 bit transfer , address increment, interrupt
dreschpe 12:b2dd49f04d5d 1013 LPC_GPDMACH0->DMACCConfig = DMA_CHANNEL_ENABLE | DMA_TRANSFER_TYPE_M2P ;
dreschpe 12:b2dd49f04d5d 1014 LPC_GPDMA->DMACSoftSReq = 0x1;
dreschpe 12:b2dd49f04d5d 1015 do {
dreschpe 12:b2dd49f04d5d 1016 } while ((LPC_GPDMA->DMACRawIntTCStat & 0x01) == 0); // DMA is running
dreschpe 12:b2dd49f04d5d 1017
dreschpe 5:2db1b8070d94 1018 }
dreschpe 12:b2dd49f04d5d 1019
dreschpe 12:b2dd49f04d5d 1020 if (spi_port == 0) { // TFT on SSP0
dreschpe 12:b2dd49f04d5d 1021 do {
dreschpe 12:b2dd49f04d5d 1022 } while ((LPC_SSP0->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 1023 } else {
dreschpe 12:b2dd49f04d5d 1024 do {
dreschpe 12:b2dd49f04d5d 1025 } while ((LPC_SSP1->SR & 0x10) == 0x10); // SPI FIFO not empty
dreschpe 12:b2dd49f04d5d 1026 }
dreschpe 13:d525819cb601 1027 _cs = 1;
dreschpe 5:2db1b8070d94 1028 free (line);
dreschpe 5:2db1b8070d94 1029 fclose(Image);
dreschpe 9:9dc5dfdda734 1030 WindowMax();
dreschpe 5:2db1b8070d94 1031 return(1);
dreschpe 4:e1e45f8a7664 1032 }