lpc17xx_gpdma.h

00001 /***********************************************************************//**
00002  * @file        lpc17xx_gpdma.h
00003  * @brief        Contains all macro definitions and function prototypes
00004  *                 support for GPDMA firmware library on LPC17xx
00005  * @version        2.0
00006  * @date        21. May. 2010
00007  * @author        NXP MCU SW Application Team
00008  **************************************************************************
00009  * Software that is described herein is for illustrative purposes only
00010  * which provides customers with programming information regarding the
00011  * products. This software is supplied "AS IS" without any warranties.
00012  * NXP Semiconductors assumes no responsibility or liability for the
00013  * use of the software, conveys no license or title under any patent,
00014  * copyright, or mask work right to the product. NXP Semiconductors
00015  * reserves the right to make changes in the software without
00016  * notification. NXP Semiconductors also make no representation or
00017  * warranty that such application will be suitable for the specified
00018  * use without further testing or modification.
00019  **************************************************************************/
00020 
00021 /* Peripheral group ----------------------------------------------------------- */
00022 /** @defgroup GPDMA GPDMA
00023  * @ingroup LPC1700CMSIS_FwLib_Drivers
00024  * @{
00025  */
00026 
00027 #ifndef LPC17XX_GPDMA_H_
00028 #define LPC17XX_GPDMA_H_
00029 
00030 /* Includes ------------------------------------------------------------------- */
00031 #include "LPC17xx.h"
00032 #include "lpc_types.h"
00033 
00034 
00035 #ifdef __cplusplus
00036 extern "C"
00037 {
00038 #endif
00039 
00040 /* Public Macros -------------------------------------------------------------- */
00041 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
00042  * @{
00043  */
00044 
00045 /** DMA Connection number definitions */
00046 #define GPDMA_CONN_SSP0_Tx             ((0UL))         /**< SSP0 Tx */
00047 #define GPDMA_CONN_SSP0_Rx             ((1UL))         /**< SSP0 Rx */
00048 #define GPDMA_CONN_SSP1_Tx             ((2UL))         /**< SSP1 Tx */
00049 #define GPDMA_CONN_SSP1_Rx             ((3UL))         /**< SSP1 Rx */
00050 #define GPDMA_CONN_ADC                 ((4UL))         /**< ADC */
00051 #define GPDMA_CONN_I2S_Channel_0     ((5UL))         /**< I2S channel 0 */
00052 #define GPDMA_CONN_I2S_Channel_1     ((6UL))         /**< I2S channel 1 */
00053 #define GPDMA_CONN_DAC                 ((7UL))         /**< DAC */
00054 #define GPDMA_CONN_UART0_Tx            ((8UL))         /**< UART0 Tx */
00055 #define GPDMA_CONN_UART0_Rx            ((9UL))         /**< UART0 Rx */
00056 #define GPDMA_CONN_UART1_Tx            ((10UL))         /**< UART1 Tx */
00057 #define GPDMA_CONN_UART1_Rx            ((11UL))         /**< UART1 Rx */
00058 #define GPDMA_CONN_UART2_Tx            ((12UL))         /**< UART2 Tx */
00059 #define GPDMA_CONN_UART2_Rx            ((13UL))         /**< UART2 Rx */
00060 #define GPDMA_CONN_UART3_Tx            ((14UL))         /**< UART3 Tx */
00061 #define GPDMA_CONN_UART3_Rx            ((15UL))         /**< UART3 Rx */
00062 #define GPDMA_CONN_MAT0_0             ((16UL))         /**< MAT0.0 */
00063 #define GPDMA_CONN_MAT0_1             ((17UL))         /**< MAT0.1 */
00064 #define GPDMA_CONN_MAT1_0             ((18UL))         /**< MAT1.0 */
00065 #define GPDMA_CONN_MAT1_1           ((19UL))         /**< MAT1.1 */
00066 #define GPDMA_CONN_MAT2_0           ((20UL))         /**< MAT2.0 */
00067 #define GPDMA_CONN_MAT2_1           ((21UL))         /**< MAT2.1 */
00068 #define GPDMA_CONN_MAT3_0             ((22UL))         /**< MAT3.0 */
00069 #define GPDMA_CONN_MAT3_1           ((23UL))         /**< MAT3.1 */
00070 
00071 /** GPDMA Transfer type definitions */
00072 #define GPDMA_TRANSFERTYPE_M2M         ((0UL))     /**< Memory to memory - DMA control */
00073 #define GPDMA_TRANSFERTYPE_M2P         ((1UL))     /**< Memory to peripheral - DMA control */
00074 #define GPDMA_TRANSFERTYPE_P2M         ((2UL))     /**< Peripheral to memory - DMA control */
00075 #define GPDMA_TRANSFERTYPE_P2P         ((3UL))     /**< Source peripheral to destination peripheral - DMA control */
00076 
00077 /** Burst size in Source and Destination definitions */
00078 #define GPDMA_BSIZE_1     ((0UL)) /**< Burst size = 1 */
00079 #define GPDMA_BSIZE_4     ((1UL)) /**< Burst size = 4 */
00080 #define GPDMA_BSIZE_8     ((2UL)) /**< Burst size = 8 */
00081 #define GPDMA_BSIZE_16     ((3UL)) /**< Burst size = 16 */
00082 #define GPDMA_BSIZE_32     ((4UL)) /**< Burst size = 32 */
00083 #define GPDMA_BSIZE_64     ((5UL)) /**< Burst size = 64 */
00084 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
00085 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
00086 
00087 /** Width in Source transfer width and Destination transfer width definitions */
00088 #define GPDMA_WIDTH_BYTE         ((0UL)) /**< Width = 1 byte */
00089 #define GPDMA_WIDTH_HALFWORD     ((1UL)) /**< Width = 2 bytes */
00090 #define GPDMA_WIDTH_WORD         ((2UL)) /**< Width = 4 bytes */
00091 
00092 /** DMA Request Select Mode definitions */
00093 #define GPDMA_REQSEL_UART     ((0UL)) /**< UART TX/RX is selected */
00094 #define GPDMA_REQSEL_TIMER     ((1UL)) /**< Timer match is selected */
00095 
00096 /**
00097  * @}
00098  */
00099 
00100 
00101 /* Private Macros ------------------------------------------------------------- */
00102 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
00103  * @{
00104  */
00105 
00106 /* --------------------- BIT DEFINITIONS -------------------------------------- */
00107 /*********************************************************************//**
00108  * Macro defines for DMA Interrupt Status register
00109  **********************************************************************/
00110 #define GPDMA_DMACIntStat_Ch(n)            (((1UL<<n)&0xFF))
00111 #define GPDMA_DMACIntStat_BITMASK        ((0xFF))
00112 
00113 /*********************************************************************//**
00114  * Macro defines for DMA Interrupt Terminal Count Request Status register
00115  **********************************************************************/
00116 #define GPDMA_DMACIntTCStat_Ch(n)        (((1UL<<n)&0xFF))
00117 #define GPDMA_DMACIntTCStat_BITMASK        ((0xFF))
00118 
00119 /*********************************************************************//**
00120  * Macro defines for DMA Interrupt Terminal Count Request Clear register
00121  **********************************************************************/
00122 #define GPDMA_DMACIntTCClear_Ch(n)        (((1UL<<n)&0xFF))
00123 #define GPDMA_DMACIntTCClear_BITMASK    ((0xFF))
00124 
00125 /*********************************************************************//**
00126  * Macro defines for DMA Interrupt Error Status register
00127  **********************************************************************/
00128 #define GPDMA_DMACIntErrStat_Ch(n)        (((1UL<<n)&0xFF))
00129 #define GPDMA_DMACIntErrStat_BITMASK    ((0xFF))
00130 
00131 /*********************************************************************//**
00132  * Macro defines for DMA Interrupt Error Clear register
00133  **********************************************************************/
00134 #define GPDMA_DMACIntErrClr_Ch(n)        (((1UL<<n)&0xFF))
00135 #define GPDMA_DMACIntErrClr_BITMASK        ((0xFF))
00136 
00137 /*********************************************************************//**
00138  * Macro defines for DMA Raw Interrupt Terminal Count Status register
00139  **********************************************************************/
00140 #define GPDMA_DMACRawIntTCStat_Ch(n)    (((1UL<<n)&0xFF))
00141 #define GPDMA_DMACRawIntTCStat_BITMASK    ((0xFF))
00142 
00143 /*********************************************************************//**
00144  * Macro defines for DMA Raw Error Interrupt Status register
00145  **********************************************************************/
00146 #define GPDMA_DMACRawIntErrStat_Ch(n)    (((1UL<<n)&0xFF))
00147 #define GPDMA_DMACRawIntErrStat_BITMASK    ((0xFF))
00148 
00149 /*********************************************************************//**
00150  * Macro defines for DMA Enabled Channel register
00151  **********************************************************************/
00152 #define GPDMA_DMACEnbldChns_Ch(n)        (((1UL<<n)&0xFF))
00153 #define GPDMA_DMACEnbldChns_BITMASK        ((0xFF))
00154 
00155 /*********************************************************************//**
00156  * Macro defines for DMA Software Burst Request register
00157  **********************************************************************/
00158 #define    GPDMA_DMACSoftBReq_Src(n)        (((1UL<<n)&0xFFFF))
00159 #define GPDMA_DMACSoftBReq_BITMASK        ((0xFFFF))
00160 
00161 /*********************************************************************//**
00162  * Macro defines for DMA Software Single Request register
00163  **********************************************************************/
00164 #define GPDMA_DMACSoftSReq_Src(n)         (((1UL<<n)&0xFFFF))
00165 #define GPDMA_DMACSoftSReq_BITMASK        ((0xFFFF))
00166 
00167 /*********************************************************************//**
00168  * Macro defines for DMA Software Last Burst Request register
00169  **********************************************************************/
00170 #define GPDMA_DMACSoftLBReq_Src(n)        (((1UL<<n)&0xFFFF))
00171 #define GPDMA_DMACSoftLBReq_BITMASK        ((0xFFFF))
00172 
00173 /*********************************************************************//**
00174  * Macro defines for DMA Software Last Single Request register
00175  **********************************************************************/
00176 #define GPDMA_DMACSoftLSReq_Src(n)         (((1UL<<n)&0xFFFF))
00177 #define GPDMA_DMACSoftLSReq_BITMASK        ((0xFFFF))
00178 
00179 /*********************************************************************//**
00180  * Macro defines for DMA Configuration register
00181  **********************************************************************/
00182 #define GPDMA_DMACConfig_E                ((0x01))     /**< DMA Controller enable*/
00183 #define GPDMA_DMACConfig_M                ((0x02))     /**< AHB Master endianness configuration*/
00184 #define GPDMA_DMACConfig_BITMASK        ((0x03))
00185 
00186 /*********************************************************************//**
00187  * Macro defines for DMA Synchronization register
00188  **********************************************************************/
00189 #define GPDMA_DMACSync_Src(n)            (((1UL<<n)&0xFFFF))
00190 #define GPDMA_DMACSync_BITMASK            ((0xFFFF))
00191 
00192 /*********************************************************************//**
00193  * Macro defines for DMA Request Select register
00194  **********************************************************************/
00195 #define GPDMA_DMAReqSel_Input(n)        (((1UL<<(n-8))&0xFF))
00196 #define GPDMA_DMAReqSel_BITMASK            ((0xFF))
00197 
00198 /*********************************************************************//**
00199  * Macro defines for DMA Channel Linked List Item registers
00200  **********************************************************************/
00201 /** DMA Channel Linked List Item registers bit mask*/
00202 #define GPDMA_DMACCxLLI_BITMASK         ((0xFFFFFFFC))
00203 
00204 /*********************************************************************//**
00205  * Macro defines for DMA channel control registers
00206  **********************************************************************/
00207 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0))     /**< Transfer size*/
00208 #define GPDMA_DMACCxControl_SBSize(n)        (((n&0x07)<<12))     /**< Source burst size*/
00209 #define GPDMA_DMACCxControl_DBSize(n)        (((n&0x07)<<15))     /**< Destination burst size*/
00210 #define GPDMA_DMACCxControl_SWidth(n)        (((n&0x07)<<18))     /**< Source transfer width*/
00211 #define GPDMA_DMACCxControl_DWidth(n)        (((n&0x07)<<21))     /**< Destination transfer width*/
00212 #define GPDMA_DMACCxControl_SI                ((1UL<<26))         /**< Source increment*/
00213 #define GPDMA_DMACCxControl_DI                ((1UL<<27))         /**< Destination increment*/
00214 #define GPDMA_DMACCxControl_Prot1            ((1UL<<28))         /**< Indicates that the access is in user mode or privileged mode*/
00215 #define GPDMA_DMACCxControl_Prot2            ((1UL<<29))         /**< Indicates that the access is bufferable or not bufferable*/
00216 #define GPDMA_DMACCxControl_Prot3            ((1UL<<30))         /**< Indicates that the access is cacheable or not cacheable*/
00217 #define GPDMA_DMACCxControl_I                ((1UL<<31))         /**< Terminal count interrupt enable bit */
00218 /** DMA channel control registers bit mask */
00219 #define GPDMA_DMACCxControl_BITMASK            ((0xFCFFFFFF))
00220 
00221 /*********************************************************************//**
00222  * Macro defines for DMA Channel Configuration registers
00223  **********************************************************************/
00224 #define GPDMA_DMACCxConfig_E                     ((1UL<<0))            /**< DMA control enable*/
00225 #define GPDMA_DMACCxConfig_SrcPeripheral(n)     (((n&0x1F)<<1))     /**< Source peripheral*/
00226 #define GPDMA_DMACCxConfig_DestPeripheral(n)     (((n&0x1F)<<6))     /**< Destination peripheral*/
00227 #define GPDMA_DMACCxConfig_TransferType(n)         (((n&0x7)<<11))     /**< This value indicates the type of transfer*/
00228 #define GPDMA_DMACCxConfig_IE                     ((1UL<<14))            /**< Interrupt error mask*/
00229 #define GPDMA_DMACCxConfig_ITC                     ((1UL<<15))         /**< Terminal count interrupt mask*/
00230 #define GPDMA_DMACCxConfig_L                     ((1UL<<16))         /**< Lock*/
00231 #define GPDMA_DMACCxConfig_A                     ((1UL<<17))         /**< Active*/
00232 #define GPDMA_DMACCxConfig_H                     ((1UL<<18))         /**< Halt*/
00233 /** DMA Channel Configuration registers bit mask */
00234 #define GPDMA_DMACCxConfig_BITMASK                ((0x7FFFF))
00235 
00236 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
00237 /* Macros check GPDMA channel */
00238 #define PARAM_GPDMA_CHANNEL(n)    ((n>=0) && (n<=7))
00239 
00240 /* Macros check GPDMA connection type */
00241 #define PARAM_GPDMA_CONN(n)        ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
00242 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
00243 || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
00244 || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
00245 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
00246 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
00247 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
00248 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
00249 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
00250 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
00251 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
00252 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
00253 
00254 /* Macros check GPDMA burst size type */
00255 #define PARAM_GPDMA_BSIZE(n)    ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
00256 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
00257 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
00258 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
00259 
00260 /* Macros check GPDMA width type */
00261 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
00262 || (n==GPDMA_WIDTH_WORD))
00263 
00264 /* Macros check GPDMA status type */
00265 #define PARAM_GPDMA_STAT(n)    ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
00266 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
00267 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
00268 
00269 /* Macros check GPDMA transfer type */
00270 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
00271 ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
00272 
00273 /* Macros check GPDMA state clear type */
00274 #define PARAM_GPDMA_STATCLR(n)    ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
00275 
00276 /* Macros check GPDMA request select type */
00277 #define PARAM_GPDMA_REQSEL(n)    ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
00278 /**
00279  * @}
00280  */
00281 
00282 
00283 /* Public Types --------------------------------------------------------------- */
00284 /** @defgroup GPDMA_Public_Types GPDMA Public Types
00285  * @{
00286  */
00287 
00288 /**
00289  * @brief GPDMA Status enumeration
00290  */
00291 typedef enum {
00292     GPDMA_STAT_INT,            /**< GPDMA Interrupt Status */
00293     GPDMA_STAT_INTTC,        /**< GPDMA Interrupt Terminal Count Request Status */
00294     GPDMA_STAT_INTERR,        /**< GPDMA Interrupt Error Status */
00295     GPDMA_STAT_RAWINTTC,    /**< GPDMA Raw Interrupt Terminal Count Status */
00296     GPDMA_STAT_RAWINTERR,    /**< GPDMA Raw Error Interrupt Status */
00297     GPDMA_STAT_ENABLED_CH    /**< GPDMA Enabled Channel Status */
00298 } GPDMA_Status_Type;
00299 
00300 /**
00301  * @brief GPDMA Interrupt clear status enumeration
00302  */
00303 typedef enum{
00304     GPDMA_STATCLR_INTTC,    /**< GPDMA Interrupt Terminal Count Request Clear */
00305     GPDMA_STATCLR_INTERR    /**< GPDMA Interrupt Error Clear */
00306 }GPDMA_StateClear_Type;
00307 
00308 /**
00309  * @brief GPDMA Channel configuration structure type definition
00310  */
00311 typedef struct {
00312     uint32_t ChannelNum;     /**< DMA channel number, should be in
00313                                 range from 0 to 7.
00314                                 Note: DMA channel 0 has the highest priority
00315                                 and DMA channel 7 the lowest priority.
00316                                 */
00317     uint32_t TransferSize;    /**< Length/Size of transfer */
00318     uint32_t TransferWidth;    /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
00319     uint32_t SrcMemAddr;    /**< Physical Source Address, used in case TransferType is chosen as
00320                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
00321     uint32_t DstMemAddr;    /**< Physical Destination Address, used in case TransferType is chosen as
00322                                  GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
00323     uint32_t TransferType;    /**< Transfer Type, should be one of the following:
00324                             - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
00325                             - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
00326                             - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
00327                             - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
00328                             */
00329     uint32_t SrcConn;        /**< Peripheral Source Connection type, used in case TransferType is chosen as
00330                             GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
00331                             following:
00332                              - GPDMA_CONN_SSP0_Tx: SSP0, Tx
00333                              - GPDMA_CONN_SSP0_Rx: SSP0, Rx
00334                              - GPDMA_CONN_SSP1_Tx: SSP1, Tx
00335                              - GPDMA_CONN_SSP1_Rx: SSP1, Rx
00336                              - GPDMA_CONN_ADC: ADC
00337                              - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
00338                              - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
00339                              - GPDMA_CONN_DAC: DAC
00340                              - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
00341                              - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
00342                              - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
00343                              - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
00344                              - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
00345                              - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
00346                              - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
00347                              - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
00348                              */
00349     uint32_t DstConn;        /**< Peripheral Destination Connection type, used in case TransferType is chosen as
00350                             GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
00351                             following:
00352                              - GPDMA_CONN_SSP0_Tx: SSP0, Tx
00353                              - GPDMA_CONN_SSP0_Rx: SSP0, Rx
00354                              - GPDMA_CONN_SSP1_Tx: SSP1, Tx
00355                              - GPDMA_CONN_SSP1_Rx: SSP1, Rx
00356                              - GPDMA_CONN_ADC: ADC
00357                              - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
00358                              - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
00359                              - GPDMA_CONN_DAC: DAC
00360                              - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
00361                              - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
00362                              - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
00363                              - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
00364                              - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
00365                              - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
00366                              - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
00367                              - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
00368                              */
00369     uint32_t DMALLI;        /**< Linker List Item structure data address
00370                             if there's no Linker List, set as '0'
00371                             */
00372 } GPDMA_Channel_CFG_Type;
00373 
00374 /**
00375  * @brief GPDMA Linker List Item structure type definition
00376  */
00377 typedef struct {
00378     uint32_t SrcAddr;    /**< Source Address */
00379     uint32_t DstAddr;    /**< Destination address */
00380     uint32_t NextLLI;    /**< Next LLI address, otherwise set to '0' */
00381     uint32_t Control;    /**< GPDMA Control of this LLI */
00382 } GPDMA_LLI_Type;
00383 
00384 
00385 /**
00386  * @}
00387  */
00388 
00389 /* Public Functions ----------------------------------------------------------- */
00390 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions
00391  * @{
00392  */
00393 
00394 void GPDMA_Init(void);
00395 //Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
00396 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
00397 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
00398 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
00399 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
00400 //void GPDMA_IntHandler(void);
00401 
00402 /**
00403  * @}
00404  */
00405 
00406 
00407 #ifdef __cplusplus
00408 }
00409 #endif
00410 
00411 #endif /* LPC17XX_GPDMA_H_ */
00412 
00413 /**
00414  * @}
00415  */
00416 
00417 /* --------------------------------- End Of File ------------------------------ */