Diogo Almeida / lora_receiver_embedios

Para o mario

Dependencies:   mbed SoftSerial USBDevice Buffer

lora_receiver/main.cpp@0:fdd8efebefc3, 2018-12-13 (annotated)

Committer:
diogo966
Date:
Thu Dec 13 23:17:28 2018 +0000
Revision:
0:fdd8efebefc3
Lora_receiver_embebidos2018

Who changed what in which revision?

UserRevisionLine numberNew contents of line
diogo966 0:fdd8efebefc3 1 /*
diogo966 0:fdd8efebefc3 2 * Copyright (c) 2017 Helmut Tschemernjak
diogo966 0:fdd8efebefc3 3 * 30826 Garbsen (Hannover) Germany
diogo966 0:fdd8efebefc3 4 * Licensed under the Apache License, Version 2.0);
diogo966 0:fdd8efebefc3 5 */
diogo966 0:fdd8efebefc3 6 #include "main.h"
diogo966 0:fdd8efebefc3 7 #include "USBSerial.h"
diogo966 0:fdd8efebefc3 8 //#include "BufferedSerial.h"
diogo966 0:fdd8efebefc3 9 DigitalOut myled(LED4);
diogo966 0:fdd8efebefc3 10 BufferedSerial *ser;
diogo966 0:fdd8efebefc3 11 USBSerial usb_serial;
diogo966 0:fdd8efebefc3 12 char Buffer_2[8][30];
diogo966 0:fdd8efebefc3 13 int x_y;
diogo966 0:fdd8efebefc3 14
diogo966 0:fdd8efebefc3 15
diogo966 0:fdd8efebefc3 16 int main() {
diogo966 0:fdd8efebefc3 17 SystemClock_Config();
diogo966 0:fdd8efebefc3 18 ser = new BufferedSerial(USBTX, USBRX);
diogo966 0:fdd8efebefc3 19 ser->baud(115200*2);
diogo966 0:fdd8efebefc3 20 ser->format(8);
diogo966 0:fdd8efebefc3 21
diogo966 0:fdd8efebefc3 22 wait(5);
diogo966 0:fdd8efebefc3 23 while(1){
diogo966 0:fdd8efebefc3 24 x_y=Receiver();
diogo966 0:fdd8efebefc3 25
diogo966 0:fdd8efebefc3 26 if (x_y==-3){
diogo966 0:fdd8efebefc3 27 usb_serial.printf("Saiu");
diogo966 0:fdd8efebefc3 28 myled=1;
diogo966 0:fdd8efebefc3 29
diogo966 0:fdd8efebefc3 30 }
diogo966 0:fdd8efebefc3 31 }
diogo966 0:fdd8efebefc3 32
diogo966 0:fdd8efebefc3 33 }
diogo966 0:fdd8efebefc3 34
diogo966 0:fdd8efebefc3 35
diogo966 0:fdd8efebefc3 36
diogo966 0:fdd8efebefc3 37
diogo966 0:fdd8efebefc3 38
diogo966 0:fdd8efebefc3 39 void mode_buffer(uint8_t buf,int xx){
diogo966 0:fdd8efebefc3 40 for(int yy=0;yy<29;yy++){
diogo966 0:fdd8efebefc3 41 //Buffer_2[xx][yy] = buf[yy];
diogo966 0:fdd8efebefc3 42 }
diogo966 0:fdd8efebefc3 43
diogo966 0:fdd8efebefc3 44 }
diogo966 0:fdd8efebefc3 45
diogo966 0:fdd8efebefc3 46
diogo966 0:fdd8efebefc3 47 void SystemClock_Config(void)
diogo966 0:fdd8efebefc3 48 {
diogo966 0:fdd8efebefc3 49 #ifdef B_L072Z_LRWAN1_LORA
diogo966 0:fdd8efebefc3 50 /*
diogo966 0:fdd8efebefc3 51 * The L072Z_LRWAN1_LORA clock setup is somewhat differnt from the Nucleo board.
diogo966 0:fdd8efebefc3 52 * It has no LSE.
diogo966 0:fdd8efebefc3 53 */
diogo966 0:fdd8efebefc3 54 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
diogo966 0:fdd8efebefc3 55 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
diogo966 0:fdd8efebefc3 56
diogo966 0:fdd8efebefc3 57 /* Enable HSE Oscillator and Activate PLL with HSE as source */
diogo966 0:fdd8efebefc3 58 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
diogo966 0:fdd8efebefc3 59 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
diogo966 0:fdd8efebefc3 60 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
diogo966 0:fdd8efebefc3 61 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
diogo966 0:fdd8efebefc3 62 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
diogo966 0:fdd8efebefc3 63 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
diogo966 0:fdd8efebefc3 64 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_6;
diogo966 0:fdd8efebefc3 65 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_3;
diogo966 0:fdd8efebefc3 66
diogo966 0:fdd8efebefc3 67 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
diogo966 0:fdd8efebefc3 68 // Error_Handler();
diogo966 0:fdd8efebefc3 69 }
diogo966 0:fdd8efebefc3 70
diogo966 0:fdd8efebefc3 71 /* Set Voltage scale1 as MCU will run at 32MHz */
diogo966 0:fdd8efebefc3 72 __HAL_RCC_PWR_CLK_ENABLE();
diogo966 0:fdd8efebefc3 73 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
diogo966 0:fdd8efebefc3 74
diogo966 0:fdd8efebefc3 75 /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
diogo966 0:fdd8efebefc3 76 while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
diogo966 0:fdd8efebefc3 77
diogo966 0:fdd8efebefc3 78 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
diogo966 0:fdd8efebefc3 79 clocks dividers */
diogo966 0:fdd8efebefc3 80 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
diogo966 0:fdd8efebefc3 81 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
diogo966 0:fdd8efebefc3 82 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
diogo966 0:fdd8efebefc3 83 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
diogo966 0:fdd8efebefc3 84 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
diogo966 0:fdd8efebefc3 85 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
diogo966 0:fdd8efebefc3 86 // Error_Handler();
diogo966 0:fdd8efebefc3 87 }
diogo966 0:fdd8efebefc3 88 #endif
diogo966 0:fdd8efebefc3 89 }
diogo966 0:fdd8efebefc3 90
diogo966 0:fdd8efebefc3 91 void dump(const char *title, const void *data, int len, bool dwords)
diogo966 0:fdd8efebefc3 92 {
diogo966 0:fdd8efebefc3 93 dprintf("dump(\"%s\", 0x%x, %d bytes)", title, data, len);
diogo966 0:fdd8efebefc3 94
diogo966 0:fdd8efebefc3 95 int i, j, cnt;
diogo966 0:fdd8efebefc3 96 unsigned char *u;
diogo966 0:fdd8efebefc3 97 const int width = 16;
diogo966 0:fdd8efebefc3 98 const int seppos = 7;
diogo966 0:fdd8efebefc3 99
diogo966 0:fdd8efebefc3 100 cnt = 0;
diogo966 0:fdd8efebefc3 101 u = (unsigned char *)data;
diogo966 0:fdd8efebefc3 102 while (len > 0) {
diogo966 0:fdd8efebefc3 103 ser->printf("%08x: ", (unsigned int)data + cnt);
diogo966 0:fdd8efebefc3 104 if (dwords) {
diogo966 0:fdd8efebefc3 105 unsigned int *ip = ( unsigned int *)u;
diogo966 0:fdd8efebefc3 106 ser->printf(" 0x%08x\r\n", *ip);
diogo966 0:fdd8efebefc3 107 u+= 4;
diogo966 0:fdd8efebefc3 108 len -= 4;
diogo966 0:fdd8efebefc3 109 cnt += 4;
diogo966 0:fdd8efebefc3 110 continue;
diogo966 0:fdd8efebefc3 111 }
diogo966 0:fdd8efebefc3 112 cnt += width;
diogo966 0:fdd8efebefc3 113 j = len < width ? len : width;
diogo966 0:fdd8efebefc3 114 for (i = 0; i < j; i++) {
diogo966 0:fdd8efebefc3 115 ser->printf("%2.2x ", *(u + i));
diogo966 0:fdd8efebefc3 116 if (i == seppos)
diogo966 0:fdd8efebefc3 117 ser->putc(' ');
diogo966 0:fdd8efebefc3 118 }
diogo966 0:fdd8efebefc3 119 ser->putc(' ');
diogo966 0:fdd8efebefc3 120 if (j < width) {
diogo966 0:fdd8efebefc3 121 i = width - j;
diogo966 0:fdd8efebefc3 122 if (i > seppos + 1)
diogo966 0:fdd8efebefc3 123 ser->putc(' ');
diogo966 0:fdd8efebefc3 124 while (i--) {
diogo966 0:fdd8efebefc3 125 printf("%s", " ");
diogo966 0:fdd8efebefc3 126 }
diogo966 0:fdd8efebefc3 127 }
diogo966 0:fdd8efebefc3 128 for (i = 0; i < j; i++) {
diogo966 0:fdd8efebefc3 129 int c = *(u + i);
diogo966 0:fdd8efebefc3 130 if (c >= ' ' && c <= '~')
diogo966 0:fdd8efebefc3 131 ser->putc(c);
diogo966 0:fdd8efebefc3 132 else
diogo966 0:fdd8efebefc3 133 ser->putc('.');
diogo966 0:fdd8efebefc3 134 if (i == seppos)
diogo966 0:fdd8efebefc3 135 ser->putc(' ');
diogo966 0:fdd8efebefc3 136 }
diogo966 0:fdd8efebefc3 137 len -= width;
diogo966 0:fdd8efebefc3 138 u += width;
diogo966 0:fdd8efebefc3 139 ser->printf("\r\n");
diogo966 0:fdd8efebefc3 140 }
diogo966 0:fdd8efebefc3 141 ser->printf("--\r\n");
diogo966 0:fdd8efebefc3 142 }