Revision 72:38012a7efba1, committed 2016-01-20

Comitter:

dheerajmpai23

Date:

Wed Jan 20 10:58:47 2016 +0000

Parent:

71:9193fbdaa3e1

Commit message:

Adding The changes as follows:; 1.BBRAM_CHECKFUNCTION; 2.Register Checking Function; 3.Indivisual Register Checking Function;

Changed in this revision

diff -r 9193fbdaa3e1 -r 38012a7efba1 adf.h
--- a/adf.h	Tue Jan 19 10:30:46 2016 +0000
+++ b/adf.h	Wed Jan 20 10:58:47 2016 +0000
@@ -1,4 +1,5 @@
 //without reset feature , with state checks.
+//have made the changes --> BBRAM_CHECK and REGISTER_CHECK
 InterruptIn IRQ(ADF_IRQ);
 //Ticker ticker;
  
@@ -9,7 +10,7 @@
 bool finish_write_data;
 uint8_t signal = 0x00;
 unsigned char bbram_buffer[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x37,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x56,0x10,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00};
- 
+unsigned char bbram_buffer_1[66]={0x19,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x00,0xF4,0xC2,0x10,0xC0,0x00,0x30,0x31,0x07,0x00,0x01,0x00,0x7F,0x00,0x0B,0x20/**24**/,0x00,0x00,0x40,0x0C,0x00,0x05,0x00,0x00,0x18,0x12,0x34,0x70,0xE0/*37**/,0x10,0xC4,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00}; //After Changes
 //int initialise_card();
 //int disk_initialize();
  
@@ -46,6 +47,9 @@
 #define CMD_PHY_OFF 0xB0
 #define CMD_PHY_TX 0xB5
 #define CMD_CONFIG_DEV 0xBB
+
+#define SPI_MEMR_RD 0x28
+
  
 #define check_status {\
     unsigned char stat=0;\
@@ -55,7 +59,43 @@
     gCS_ADF=1;\
     status = stat;\
 }
- 
+
+bool bbram_err=false;
+int err_idx=-1;
+#define bbram_check gCS_ADF=0;\
+    spi.write(0x39);\
+    spi.write(0x00);\
+    for(int i=0;i<64;i++){\
+        if(spi.write(0xFF)!=bbram_buffer_1[i+2]){\
+            printf("bbram_err");\
+            bbram_err=true;\
+            err_idx=i;\
+            break;\
+        }\
+    }\
+    gCS_ADF=1;\
+    
+    
+bool reg_err=false;
+#define reg_check_ram(addr1,addr2,reg) reg_err=false;\
+    gCS_ADF=0;\
+        spi.write(addr1);\
+        spi.write(addr2);\
+        if(spi.write(0xFF)!=reg)\
+            reg_err=true;\
+    gCS_ADF=1;\
+
+bool reg_wrt_err=false;
+#define reg_check\
+    reg_wrt_err=false;\
+    reg_check_ram(SPI_MEMR_RD,0x24,0x20)\
+    reg_wrt_err=reg_err;\
+    reg_check_ram(SPI_MEMR_RD,0x36,0x70)\
+    reg_wrt_err=(reg_wrt_err || reg_err);\
+    reg_check_ram(SPI_MEMR_RD,0x37,0xE0)\
+    reg_wrt_err=(reg_wrt_err || reg_err);\
+
+
 // all three arguments are int
 #define assrt_phy_off(return_this) {\
     int cmd_err_cnt = 0;\
@@ -156,7 +196,7 @@
  
 //for reseting the transmission call assert function after b5 and b1. after b1 assert_phi_on and after b5 assert_phi_tx. 
 //----------------------------------------------------------------------------
- 
+//Check_BBRAM Registers You are altering them here
 # define initiate {\
     SPI_mutex.lock();\
     gCS_ADF=0;\
@@ -371,4 +411,5 @@
         }\
     }\
     gPC.puts("after while loop\r\n");\
-}
\ No newline at end of file
+}
+