loragw_reg.h

00001 /*
00002  / _____)             _              | |
00003 ( (____  _____ ____ _| |_ _____  ____| |__
00004  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
00005  _____) ) ____| | | || |_| ____( (___| | | |
00006 (______/|_____)_|_|_| \__)_____)\____)_| |_|
00007   (C)2017 Semtech-Cycleo
00008 
00009 Description:
00010     Functions used to handle a single LoRa concentrator.
00011     Registers are addressed by name.
00012     Multi-bytes registers are handled automatically.
00013     Read-modify-write is handled automatically.
00014 
00015 
00016 */
00017 
00018 
00019 #ifndef _LORAGW_REG_H
00020 #define _LORAGW_REG_H
00021 
00022 /* -------------------------------------------------------------------------- */
00023 /* --- DEPENDANCIES --------------------------------------------------------- */
00024 
00025 #include <stdint.h>        /* C99 types */
00026 #include <stdbool.h>    /* bool type */
00027 
00028 /* -------------------------------------------------------------------------- */
00029 /* --- INTERNAL SHARED TYPES ------------------------------------------------ */
00030 
00031 struct lgw_reg_s {
00032     int8_t  page;        /*!< page containing the register (-1 for all pages) */
00033     uint8_t addr;        /*!< base address of the register (7 bit) */
00034     uint8_t offs;        /*!< position of the register LSB (between 0 to 7) */
00035     bool    sign;        /*!< 1 indicates the register is signed (2 complem.) */
00036     uint8_t leng;        /*!< number of bits in the register */
00037     bool    rdon;        /*!< 1 indicates a read-only register */
00038     int32_t dflt;        /*!< register default value */
00039 };
00040 
00041 /* -------------------------------------------------------------------------- */
00042 /* --- INTERNAL SHARED FUNCTIONS -------------------------------------------- */
00043 
00044 int reg_w_align32(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, struct lgw_reg_s r, int32_t reg_value);
00045 int reg_r_align32(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, struct lgw_reg_s r, int32_t *reg_value);
00046 
00047 /* -------------------------------------------------------------------------- */
00048 /* --- PUBLIC CONSTANTS ----------------------------------------------------- */
00049 
00050 #define LGW_REG_SUCCESS  0
00051 #define LGW_REG_ERROR    -1
00052 
00053 /*
00054 auto generated register mapping for C code : 11-Jul-2013 13:20:40
00055 this file contains autogenerated C struct used to access the LORA registers
00056 this file is autogenerated from registers description
00057 293 registers are defined
00058 */
00059 
00060 #define LGW_PAGE_REG 0
00061 #define LGW_SOFT_RESET 1
00062 #define LGW_VERSION 2
00063 #define LGW_RX_DATA_BUF_ADDR 3
00064 #define LGW_RX_DATA_BUF_DATA 4
00065 #define LGW_TX_DATA_BUF_ADDR 5
00066 #define LGW_TX_DATA_BUF_DATA 6
00067 #define LGW_CAPTURE_RAM_ADDR 7
00068 #define LGW_CAPTURE_RAM_DATA 8
00069 #define LGW_MCU_PROM_ADDR 9
00070 #define LGW_MCU_PROM_DATA 10
00071 #define LGW_RX_PACKET_DATA_FIFO_NUM_STORED 11
00072 #define LGW_RX_PACKET_DATA_FIFO_ADDR_POINTER 12
00073 #define LGW_RX_PACKET_DATA_FIFO_STATUS 13
00074 #define LGW_RX_PACKET_DATA_FIFO_PAYLOAD_SIZE 14
00075 #define LGW_MBWSSF_MODEM_ENABLE 15
00076 #define LGW_CONCENTRATOR_MODEM_ENABLE 16
00077 #define LGW_FSK_MODEM_ENABLE 17
00078 #define LGW_GLOBAL_EN 18
00079 #define LGW_CLK32M_EN 19
00080 #define LGW_CLKHS_EN 20
00081 #define LGW_START_BIST0 21
00082 #define LGW_START_BIST1 22
00083 #define LGW_CLEAR_BIST0 23
00084 #define LGW_CLEAR_BIST1 24
00085 #define LGW_BIST0_FINISHED 25
00086 #define LGW_BIST1_FINISHED 26
00087 #define LGW_MCU_AGC_PROG_RAM_BIST_STATUS 27
00088 #define LGW_MCU_ARB_PROG_RAM_BIST_STATUS 28
00089 #define LGW_CAPTURE_RAM_BIST_STATUS 29
00090 #define LGW_CHAN_FIR_RAM0_BIST_STATUS 30
00091 #define LGW_CHAN_FIR_RAM1_BIST_STATUS 31
00092 #define LGW_CORR0_RAM_BIST_STATUS 32
00093 #define LGW_CORR1_RAM_BIST_STATUS 33
00094 #define LGW_CORR2_RAM_BIST_STATUS 34
00095 #define LGW_CORR3_RAM_BIST_STATUS 35
00096 #define LGW_CORR4_RAM_BIST_STATUS 36
00097 #define LGW_CORR5_RAM_BIST_STATUS 37
00098 #define LGW_CORR6_RAM_BIST_STATUS 38
00099 #define LGW_CORR7_RAM_BIST_STATUS 39
00100 #define LGW_MODEM0_RAM0_BIST_STATUS 40
00101 #define LGW_MODEM1_RAM0_BIST_STATUS 41
00102 #define LGW_MODEM2_RAM0_BIST_STATUS 42
00103 #define LGW_MODEM3_RAM0_BIST_STATUS 43
00104 #define LGW_MODEM4_RAM0_BIST_STATUS 44
00105 #define LGW_MODEM5_RAM0_BIST_STATUS 45
00106 #define LGW_MODEM6_RAM0_BIST_STATUS 46
00107 #define LGW_MODEM7_RAM0_BIST_STATUS 47
00108 #define LGW_MODEM0_RAM1_BIST_STATUS 48
00109 #define LGW_MODEM1_RAM1_BIST_STATUS 49
00110 #define LGW_MODEM2_RAM1_BIST_STATUS 50
00111 #define LGW_MODEM3_RAM1_BIST_STATUS 51
00112 #define LGW_MODEM4_RAM1_BIST_STATUS 52
00113 #define LGW_MODEM5_RAM1_BIST_STATUS 53
00114 #define LGW_MODEM6_RAM1_BIST_STATUS 54
00115 #define LGW_MODEM7_RAM1_BIST_STATUS 55
00116 #define LGW_MODEM0_RAM2_BIST_STATUS 56
00117 #define LGW_MODEM1_RAM2_BIST_STATUS 57
00118 #define LGW_MODEM2_RAM2_BIST_STATUS 58
00119 #define LGW_MODEM3_RAM2_BIST_STATUS 59
00120 #define LGW_MODEM4_RAM2_BIST_STATUS 60
00121 #define LGW_MODEM5_RAM2_BIST_STATUS 61
00122 #define LGW_MODEM6_RAM2_BIST_STATUS 62
00123 #define LGW_MODEM7_RAM2_BIST_STATUS 63
00124 #define LGW_MODEM_MBWSSF_RAM0_BIST_STATUS 64
00125 #define LGW_MODEM_MBWSSF_RAM1_BIST_STATUS 65
00126 #define LGW_MODEM_MBWSSF_RAM2_BIST_STATUS 66
00127 #define LGW_MCU_AGC_DATA_RAM_BIST0_STATUS 67
00128 #define LGW_MCU_AGC_DATA_RAM_BIST1_STATUS 68
00129 #define LGW_MCU_ARB_DATA_RAM_BIST0_STATUS 69
00130 #define LGW_MCU_ARB_DATA_RAM_BIST1_STATUS 70
00131 #define LGW_TX_TOP_RAM_BIST0_STATUS 71
00132 #define LGW_TX_TOP_RAM_BIST1_STATUS 72
00133 #define LGW_DATA_MNGT_RAM_BIST0_STATUS 73
00134 #define LGW_DATA_MNGT_RAM_BIST1_STATUS 74
00135 #define LGW_GPIO_SELECT_INPUT 75
00136 #define LGW_GPIO_SELECT_OUTPUT 76
00137 #define LGW_GPIO_MODE 77
00138 #define LGW_GPIO_PIN_REG_IN 78
00139 #define LGW_GPIO_PIN_REG_OUT 79
00140 #define LGW_MCU_AGC_STATUS 80
00141 #define LGW_MCU_ARB_STATUS 81
00142 #define LGW_CHIP_ID 82
00143 #define LGW_EMERGENCY_FORCE_HOST_CTRL 83
00144 #define LGW_RX_INVERT_IQ 84
00145 #define LGW_MODEM_INVERT_IQ 85
00146 #define LGW_MBWSSF_MODEM_INVERT_IQ 86
00147 #define LGW_RX_EDGE_SELECT 87
00148 #define LGW_MISC_RADIO_EN 88
00149 #define LGW_FSK_MODEM_INVERT_IQ 89
00150 #define LGW_FILTER_GAIN 90
00151 #define LGW_RADIO_SELECT 91
00152 #define LGW_IF_FREQ_0 92
00153 #define LGW_IF_FREQ_1 93
00154 #define LGW_IF_FREQ_2 94
00155 #define LGW_IF_FREQ_3 95
00156 #define LGW_IF_FREQ_4 96
00157 #define LGW_IF_FREQ_5 97
00158 #define LGW_IF_FREQ_6 98
00159 #define LGW_IF_FREQ_7 99
00160 #define LGW_IF_FREQ_8 100
00161 #define LGW_IF_FREQ_9 101
00162 #define LGW_CHANN_OVERRIDE_AGC_GAIN 102
00163 #define LGW_CHANN_AGC_GAIN 103
00164 #define LGW_CORR0_DETECT_EN 104
00165 #define LGW_CORR1_DETECT_EN 105
00166 #define LGW_CORR2_DETECT_EN 106
00167 #define LGW_CORR3_DETECT_EN 107
00168 #define LGW_CORR4_DETECT_EN 108
00169 #define LGW_CORR5_DETECT_EN 109
00170 #define LGW_CORR6_DETECT_EN 110
00171 #define LGW_CORR7_DETECT_EN 111
00172 #define LGW_CORR_SAME_PEAKS_OPTION_SF6 112
00173 #define LGW_CORR_SAME_PEAKS_OPTION_SF7 113
00174 #define LGW_CORR_SAME_PEAKS_OPTION_SF8 114
00175 #define LGW_CORR_SAME_PEAKS_OPTION_SF9 115
00176 #define LGW_CORR_SAME_PEAKS_OPTION_SF10 116
00177 #define LGW_CORR_SAME_PEAKS_OPTION_SF11 117
00178 #define LGW_CORR_SAME_PEAKS_OPTION_SF12 118
00179 #define LGW_CORR_SIG_NOISE_RATIO_SF6 119
00180 #define LGW_CORR_SIG_NOISE_RATIO_SF7 120
00181 #define LGW_CORR_SIG_NOISE_RATIO_SF8 121
00182 #define LGW_CORR_SIG_NOISE_RATIO_SF9 122
00183 #define LGW_CORR_SIG_NOISE_RATIO_SF10 123
00184 #define LGW_CORR_SIG_NOISE_RATIO_SF11 124
00185 #define LGW_CORR_SIG_NOISE_RATIO_SF12 125
00186 #define LGW_CORR_NUM_SAME_PEAK 126
00187 #define LGW_CORR_MAC_GAIN 127
00188 #define LGW_ADJUST_MODEM_START_OFFSET_RDX4 128
00189 #define LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4 129
00190 #define LGW_DBG_CORR_SELECT_SF 130
00191 #define LGW_DBG_CORR_SELECT_CHANNEL 131
00192 #define LGW_DBG_DETECT_CPT 132
00193 #define LGW_DBG_SYMB_CPT 133
00194 #define LGW_CHIRP_INVERT_RX 134
00195 #define LGW_DC_NOTCH_EN 135
00196 #define LGW_IMPLICIT_CRC_EN 136
00197 #define LGW_IMPLICIT_CODING_RATE 137
00198 #define LGW_IMPLICIT_PAYLOAD_LENGHT 138
00199 #define LGW_FREQ_TO_TIME_INVERT 139
00200 #define LGW_FREQ_TO_TIME_DRIFT 140
00201 #define LGW_PAYLOAD_FINE_TIMING_GAIN 141
00202 #define LGW_PREAMBLE_FINE_TIMING_GAIN 142
00203 #define LGW_TRACKING_INTEGRAL 143
00204 #define LGW_FRAME_SYNCH_PEAK1_POS 144
00205 #define LGW_FRAME_SYNCH_PEAK2_POS 145
00206 #define LGW_PREAMBLE_SYMB1_NB 146
00207 #define LGW_FRAME_SYNCH_GAIN 147
00208 #define LGW_SYNCH_DETECT_TH 148
00209 #define LGW_LLR_SCALE 149
00210 #define LGW_SNR_AVG_CST 150
00211 #define LGW_PPM_OFFSET 151
00212 #define LGW_MAX_PAYLOAD_LEN 152
00213 #define LGW_ONLY_CRC_EN 153
00214 #define LGW_ZERO_PAD 154
00215 #define LGW_DEC_GAIN_OFFSET 155
00216 #define LGW_CHAN_GAIN_OFFSET 156
00217 #define LGW_FORCE_HOST_RADIO_CTRL 157
00218 #define LGW_FORCE_HOST_FE_CTRL 158
00219 #define LGW_FORCE_DEC_FILTER_GAIN 159
00220 #define LGW_MCU_RST_0 160
00221 #define LGW_MCU_RST_1 161
00222 #define LGW_MCU_SELECT_MUX_0 162
00223 #define LGW_MCU_SELECT_MUX_1 163
00224 #define LGW_MCU_CORRUPTION_DETECTED_0 164
00225 #define LGW_MCU_CORRUPTION_DETECTED_1 165
00226 #define LGW_MCU_SELECT_EDGE_0 166
00227 #define LGW_MCU_SELECT_EDGE_1 167
00228 #define LGW_CHANN_SELECT_RSSI 168
00229 #define LGW_RSSI_BB_DEFAULT_VALUE 169
00230 #define LGW_RSSI_DEC_DEFAULT_VALUE 170
00231 #define LGW_RSSI_CHANN_DEFAULT_VALUE 171
00232 #define LGW_RSSI_BB_FILTER_ALPHA 172
00233 #define LGW_RSSI_DEC_FILTER_ALPHA 173
00234 #define LGW_RSSI_CHANN_FILTER_ALPHA 174
00235 #define LGW_IQ_MISMATCH_A_AMP_COEFF 175
00236 #define LGW_IQ_MISMATCH_A_PHI_COEFF 176
00237 #define LGW_IQ_MISMATCH_B_AMP_COEFF 177
00238 #define LGW_IQ_MISMATCH_B_SEL_I 178
00239 #define LGW_IQ_MISMATCH_B_PHI_COEFF 179
00240 #define LGW_TX_TRIG_IMMEDIATE 180
00241 #define LGW_TX_TRIG_DELAYED 181
00242 #define LGW_TX_TRIG_GPS 182
00243 #define LGW_TX_START_DELAY 183
00244 #define LGW_TX_FRAME_SYNCH_PEAK1_POS 184
00245 #define LGW_TX_FRAME_SYNCH_PEAK2_POS 185
00246 #define LGW_TX_RAMP_DURATION 186
00247 #define LGW_TX_OFFSET_I 187
00248 #define LGW_TX_OFFSET_Q 188
00249 #define LGW_TX_MODE 189
00250 #define LGW_TX_ZERO_PAD 190
00251 #define LGW_TX_EDGE_SELECT 191
00252 #define LGW_TX_EDGE_SELECT_TOP 192
00253 #define LGW_TX_GAIN 193
00254 #define LGW_TX_CHIRP_LOW_PASS 194
00255 #define LGW_TX_FCC_WIDEBAND 195
00256 #define LGW_TX_SWAP_IQ 196
00257 #define LGW_MBWSSF_IMPLICIT_HEADER 197
00258 #define LGW_MBWSSF_IMPLICIT_CRC_EN 198
00259 #define LGW_MBWSSF_IMPLICIT_CODING_RATE 199
00260 #define LGW_MBWSSF_IMPLICIT_PAYLOAD_LENGHT 200
00261 #define LGW_MBWSSF_AGC_FREEZE_ON_DETECT 201
00262 #define LGW_MBWSSF_FRAME_SYNCH_PEAK1_POS 202
00263 #define LGW_MBWSSF_FRAME_SYNCH_PEAK2_POS 203
00264 #define LGW_MBWSSF_PREAMBLE_SYMB1_NB 204
00265 #define LGW_MBWSSF_FRAME_SYNCH_GAIN 205
00266 #define LGW_MBWSSF_SYNCH_DETECT_TH 206
00267 #define LGW_MBWSSF_DETECT_MIN_SINGLE_PEAK 207
00268 #define LGW_MBWSSF_DETECT_TRIG_SAME_PEAK_NB 208
00269 #define LGW_MBWSSF_FREQ_TO_TIME_INVERT 209
00270 #define LGW_MBWSSF_FREQ_TO_TIME_DRIFT 210
00271 #define LGW_MBWSSF_PPM_CORRECTION 211
00272 #define LGW_MBWSSF_PAYLOAD_FINE_TIMING_GAIN 212
00273 #define LGW_MBWSSF_PREAMBLE_FINE_TIMING_GAIN 213
00274 #define LGW_MBWSSF_TRACKING_INTEGRAL 214
00275 #define LGW_MBWSSF_ZERO_PAD 215
00276 #define LGW_MBWSSF_MODEM_BW 216
00277 #define LGW_MBWSSF_RADIO_SELECT 217
00278 #define LGW_MBWSSF_RX_CHIRP_INVERT 218
00279 #define LGW_MBWSSF_LLR_SCALE 219
00280 #define LGW_MBWSSF_SNR_AVG_CST 220
00281 #define LGW_MBWSSF_PPM_OFFSET 221
00282 #define LGW_MBWSSF_RATE_SF 222
00283 #define LGW_MBWSSF_ONLY_CRC_EN 223
00284 #define LGW_MBWSSF_MAX_PAYLOAD_LEN 224
00285 #define LGW_TX_STATUS 225
00286 #define LGW_FSK_CH_BW_EXPO 226
00287 #define LGW_FSK_RSSI_LENGTH 227
00288 #define LGW_FSK_RX_INVERT 228
00289 #define LGW_FSK_PKT_MODE 229
00290 #define LGW_FSK_PSIZE 230
00291 #define LGW_FSK_CRC_EN 231
00292 #define LGW_FSK_DCFREE_ENC 232
00293 #define LGW_FSK_CRC_IBM 233
00294 #define LGW_FSK_ERROR_OSR_TOL 234
00295 #define LGW_FSK_RADIO_SELECT 235
00296 #define LGW_FSK_BR_RATIO 236
00297 #define LGW_FSK_REF_PATTERN_LSB 237
00298 #define LGW_FSK_REF_PATTERN_MSB 238
00299 #define LGW_FSK_PKT_LENGTH 239
00300 #define LGW_FSK_TX_GAUSSIAN_EN 240
00301 #define LGW_FSK_TX_GAUSSIAN_SELECT_BT 241
00302 #define LGW_FSK_TX_PATTERN_EN 242
00303 #define LGW_FSK_TX_PREAMBLE_SEQ 243
00304 #define LGW_FSK_TX_PSIZE 244
00305 #define LGW_FSK_NODE_ADRS 245
00306 #define LGW_FSK_BROADCAST 246
00307 #define LGW_FSK_AUTO_AFC_ON 247
00308 #define LGW_FSK_PATTERN_TIMEOUT_CFG 248
00309 #define LGW_SPI_RADIO_A__DATA 249
00310 #define LGW_SPI_RADIO_A__DATA_READBACK 250
00311 #define LGW_SPI_RADIO_A__ADDR 251
00312 #define LGW_SPI_RADIO_A__CS 252
00313 #define LGW_SPI_RADIO_B__DATA 253
00314 #define LGW_SPI_RADIO_B__DATA_READBACK 254
00315 #define LGW_SPI_RADIO_B__ADDR 255
00316 #define LGW_SPI_RADIO_B__CS 256
00317 #define LGW_RADIO_A_EN 257
00318 #define LGW_RADIO_B_EN 258
00319 #define LGW_RADIO_RST 259
00320 #define LGW_LNA_A_EN 260
00321 #define LGW_PA_A_EN 261
00322 #define LGW_LNA_B_EN 262
00323 #define LGW_PA_B_EN 263
00324 #define LGW_PA_GAIN 264
00325 #define LGW_LNA_A_CTRL_LUT 265
00326 #define LGW_PA_A_CTRL_LUT 266
00327 #define LGW_LNA_B_CTRL_LUT 267
00328 #define LGW_PA_B_CTRL_LUT 268
00329 #define LGW_CAPTURE_SOURCE 269
00330 #define LGW_CAPTURE_START 270
00331 #define LGW_CAPTURE_FORCE_TRIGGER 271
00332 #define LGW_CAPTURE_WRAP 272
00333 #define LGW_CAPTURE_PERIOD 273
00334 #define LGW_MODEM_STATUS 274
00335 #define LGW_VALID_HEADER_COUNTER_0 275
00336 #define LGW_VALID_PACKET_COUNTER_0 276
00337 #define LGW_VALID_HEADER_COUNTER_MBWSSF 277
00338 #define LGW_VALID_HEADER_COUNTER_FSK 278
00339 #define LGW_VALID_PACKET_COUNTER_MBWSSF 279
00340 #define LGW_VALID_PACKET_COUNTER_FSK 280
00341 #define LGW_CHANN_RSSI 281
00342 #define LGW_BB_RSSI 282
00343 #define LGW_DEC_RSSI 283
00344 #define LGW_DBG_MCU_DATA 284
00345 #define LGW_DBG_ARB_MCU_RAM_DATA 285
00346 #define LGW_DBG_AGC_MCU_RAM_DATA 286
00347 #define LGW_NEXT_PACKET_CNT 287
00348 #define LGW_ADDR_CAPTURE_COUNT 288
00349 #define LGW_TIMESTAMP 289
00350 #define LGW_DBG_CHANN0_GAIN 290
00351 #define LGW_DBG_CHANN1_GAIN 291
00352 #define LGW_DBG_CHANN2_GAIN 292
00353 #define LGW_DBG_CHANN3_GAIN 293
00354 #define LGW_DBG_CHANN4_GAIN 294
00355 #define LGW_DBG_CHANN5_GAIN 295
00356 #define LGW_DBG_CHANN6_GAIN 296
00357 #define LGW_DBG_CHANN7_GAIN 297
00358 #define LGW_DBG_DEC_FILT_GAIN 298
00359 #define LGW_SPI_DATA_FIFO_PTR 299
00360 #define LGW_PACKET_DATA_FIFO_PTR 300
00361 #define LGW_DBG_ARB_MCU_RAM_ADDR 301
00362 #define LGW_DBG_AGC_MCU_RAM_ADDR 302
00363 #define LGW_SPI_MASTER_CHIP_SELECT_POLARITY 303
00364 #define LGW_SPI_MASTER_CPOL 304
00365 #define LGW_SPI_MASTER_CPHA 305
00366 #define LGW_SIG_GEN_ANALYSER_MUX_SEL 306
00367 #define LGW_SIG_GEN_EN 307
00368 #define LGW_SIG_ANALYSER_EN 308
00369 #define LGW_SIG_ANALYSER_AVG_LEN 309
00370 #define LGW_SIG_ANALYSER_PRECISION 310
00371 #define LGW_SIG_ANALYSER_VALID_OUT 311
00372 #define LGW_SIG_GEN_FREQ 312
00373 #define LGW_SIG_ANALYSER_FREQ 313
00374 #define LGW_SIG_ANALYSER_I_OUT 314
00375 #define LGW_SIG_ANALYSER_Q_OUT 315
00376 #define LGW_GPS_EN 316
00377 #define LGW_GPS_POL 317
00378 #define LGW_SW_TEST_REG1 318
00379 #define LGW_SW_TEST_REG2 319
00380 #define LGW_SW_TEST_REG3 320
00381 #define LGW_DATA_MNGT_STATUS 321
00382 #define LGW_DATA_MNGT_CPT_FRAME_ALLOCATED 322
00383 #define LGW_DATA_MNGT_CPT_FRAME_FINISHED 323
00384 #define LGW_DATA_MNGT_CPT_FRAME_READEN 324
00385 #define LGW_TX_TRIG_ALL 325
00386 
00387 #define LGW_TOTALREGS 326
00388 
00389 /* -------------------------------------------------------------------------- */
00390 /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */
00391 
00392 /**
00393 @brief Connect LoRa concentrator by opening SPI link
00394 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00395 */
00396 int lgw_connect(void);
00397 
00398 /**
00399 @brief Disconnect LoRa concentrator by closing SPI link
00400 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00401 */
00402 int lgw_disconnect(void);
00403 
00404 /**
00405 @brief Use the soft-reset register to put the concentrator in initial state
00406 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00407 */
00408 int lgw_soft_reset(void);
00409 
00410 /**
00411 @brief Check if the registers are ok, send diagnostics to stdio/stderr/file
00412 @param f file descriptor to to which the check result will be written
00413 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00414 */
00415 int lgw_reg_check(FILE *f);
00416 
00417 /**
00418 @brief LoRa concentrator register write
00419 @param register_id register number in the data structure describing registers
00420 @param reg_value signed value to write to the register (for u32, use cast)
00421 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00422 */
00423 int lgw_reg_w(uint16_t register_id, int32_t reg_value);
00424 
00425 /**
00426 @brief LoRa concentrator register read
00427 @param register_id register number in the data structure describing registers
00428 @param reg_value pointer to a variable where to write register read value
00429 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00430 */
00431 int lgw_reg_r(uint16_t register_id, int32_t *reg_value);
00432 
00433 /**
00434 @brief LoRa concentrator register burst write
00435 @param register_id register number in the data structure describing registers
00436 @param data pointer to byte array that will be sent to the LoRa concentrator
00437 @param size size of the transfer, in byte(s)
00438 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00439 */
00440 int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size);
00441 
00442 /**
00443 @brief LoRa concentrator register burst read
00444 @param register_id register number in the data structure describing registers
00445 @param data pointer to byte array that will be written from the LoRa concentrator
00446 @param size size of the transfer, in byte(s)
00447 @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR)
00448 */
00449 int lgw_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size);
00450 
00451 
00452 #endif
00453 
00454 /* --- EOF ------------------------------------------------------------------ */