Damian Gabino
/
picoGW_mcu
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src/SX1308HAL/inc/loragw_reg.h@0:c76361bd82e8, 2018-04-11 (annotated)
- Committer:
- dgabino
- Date:
- Wed Apr 11 14:42:47 2018 +0000
- Revision:
- 0:c76361bd82e8
Initial commit
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| dgabino | 0:c76361bd82e8 | 1 | /* |
| dgabino | 0:c76361bd82e8 | 2 | / _____) _ | | |
| dgabino | 0:c76361bd82e8 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
| dgabino | 0:c76361bd82e8 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
| dgabino | 0:c76361bd82e8 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
| dgabino | 0:c76361bd82e8 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
| dgabino | 0:c76361bd82e8 | 7 | (C)2017 Semtech-Cycleo |
| dgabino | 0:c76361bd82e8 | 8 | |
| dgabino | 0:c76361bd82e8 | 9 | Description: |
| dgabino | 0:c76361bd82e8 | 10 | Functions used to handle a single LoRa concentrator. |
| dgabino | 0:c76361bd82e8 | 11 | Registers are addressed by name. |
| dgabino | 0:c76361bd82e8 | 12 | Multi-bytes registers are handled automatically. |
| dgabino | 0:c76361bd82e8 | 13 | Read-modify-write is handled automatically. |
| dgabino | 0:c76361bd82e8 | 14 | |
| dgabino | 0:c76361bd82e8 | 15 | |
| dgabino | 0:c76361bd82e8 | 16 | */ |
| dgabino | 0:c76361bd82e8 | 17 | |
| dgabino | 0:c76361bd82e8 | 18 | |
| dgabino | 0:c76361bd82e8 | 19 | #ifndef _LORAGW_REG_H |
| dgabino | 0:c76361bd82e8 | 20 | #define _LORAGW_REG_H |
| dgabino | 0:c76361bd82e8 | 21 | |
| dgabino | 0:c76361bd82e8 | 22 | /* -------------------------------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 23 | /* --- DEPENDANCIES --------------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 24 | |
| dgabino | 0:c76361bd82e8 | 25 | #include <stdint.h> /* C99 types */ |
| dgabino | 0:c76361bd82e8 | 26 | #include <stdbool.h> /* bool type */ |
| dgabino | 0:c76361bd82e8 | 27 | |
| dgabino | 0:c76361bd82e8 | 28 | /* -------------------------------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 29 | /* --- INTERNAL SHARED TYPES ------------------------------------------------ */ |
| dgabino | 0:c76361bd82e8 | 30 | |
| dgabino | 0:c76361bd82e8 | 31 | struct lgw_reg_s { |
| dgabino | 0:c76361bd82e8 | 32 | int8_t page; /*!< page containing the register (-1 for all pages) */ |
| dgabino | 0:c76361bd82e8 | 33 | uint8_t addr; /*!< base address of the register (7 bit) */ |
| dgabino | 0:c76361bd82e8 | 34 | uint8_t offs; /*!< position of the register LSB (between 0 to 7) */ |
| dgabino | 0:c76361bd82e8 | 35 | bool sign; /*!< 1 indicates the register is signed (2 complem.) */ |
| dgabino | 0:c76361bd82e8 | 36 | uint8_t leng; /*!< number of bits in the register */ |
| dgabino | 0:c76361bd82e8 | 37 | bool rdon; /*!< 1 indicates a read-only register */ |
| dgabino | 0:c76361bd82e8 | 38 | int32_t dflt; /*!< register default value */ |
| dgabino | 0:c76361bd82e8 | 39 | }; |
| dgabino | 0:c76361bd82e8 | 40 | |
| dgabino | 0:c76361bd82e8 | 41 | /* -------------------------------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 42 | /* --- INTERNAL SHARED FUNCTIONS -------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 43 | |
| dgabino | 0:c76361bd82e8 | 44 | int reg_w_align32(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, struct lgw_reg_s r, int32_t reg_value); |
| dgabino | 0:c76361bd82e8 | 45 | int reg_r_align32(void *spi_target, uint8_t spi_mux_mode, uint8_t spi_mux_target, struct lgw_reg_s r, int32_t *reg_value); |
| dgabino | 0:c76361bd82e8 | 46 | |
| dgabino | 0:c76361bd82e8 | 47 | /* -------------------------------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 48 | /* --- PUBLIC CONSTANTS ----------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 49 | |
| dgabino | 0:c76361bd82e8 | 50 | #define LGW_REG_SUCCESS 0 |
| dgabino | 0:c76361bd82e8 | 51 | #define LGW_REG_ERROR -1 |
| dgabino | 0:c76361bd82e8 | 52 | |
| dgabino | 0:c76361bd82e8 | 53 | /* |
| dgabino | 0:c76361bd82e8 | 54 | auto generated register mapping for C code : 11-Jul-2013 13:20:40 |
| dgabino | 0:c76361bd82e8 | 55 | this file contains autogenerated C struct used to access the LORA registers |
| dgabino | 0:c76361bd82e8 | 56 | this file is autogenerated from registers description |
| dgabino | 0:c76361bd82e8 | 57 | 293 registers are defined |
| dgabino | 0:c76361bd82e8 | 58 | */ |
| dgabino | 0:c76361bd82e8 | 59 | |
| dgabino | 0:c76361bd82e8 | 60 | #define LGW_PAGE_REG 0 |
| dgabino | 0:c76361bd82e8 | 61 | #define LGW_SOFT_RESET 1 |
| dgabino | 0:c76361bd82e8 | 62 | #define LGW_VERSION 2 |
| dgabino | 0:c76361bd82e8 | 63 | #define LGW_RX_DATA_BUF_ADDR 3 |
| dgabino | 0:c76361bd82e8 | 64 | #define LGW_RX_DATA_BUF_DATA 4 |
| dgabino | 0:c76361bd82e8 | 65 | #define LGW_TX_DATA_BUF_ADDR 5 |
| dgabino | 0:c76361bd82e8 | 66 | #define LGW_TX_DATA_BUF_DATA 6 |
| dgabino | 0:c76361bd82e8 | 67 | #define LGW_CAPTURE_RAM_ADDR 7 |
| dgabino | 0:c76361bd82e8 | 68 | #define LGW_CAPTURE_RAM_DATA 8 |
| dgabino | 0:c76361bd82e8 | 69 | #define LGW_MCU_PROM_ADDR 9 |
| dgabino | 0:c76361bd82e8 | 70 | #define LGW_MCU_PROM_DATA 10 |
| dgabino | 0:c76361bd82e8 | 71 | #define LGW_RX_PACKET_DATA_FIFO_NUM_STORED 11 |
| dgabino | 0:c76361bd82e8 | 72 | #define LGW_RX_PACKET_DATA_FIFO_ADDR_POINTER 12 |
| dgabino | 0:c76361bd82e8 | 73 | #define LGW_RX_PACKET_DATA_FIFO_STATUS 13 |
| dgabino | 0:c76361bd82e8 | 74 | #define LGW_RX_PACKET_DATA_FIFO_PAYLOAD_SIZE 14 |
| dgabino | 0:c76361bd82e8 | 75 | #define LGW_MBWSSF_MODEM_ENABLE 15 |
| dgabino | 0:c76361bd82e8 | 76 | #define LGW_CONCENTRATOR_MODEM_ENABLE 16 |
| dgabino | 0:c76361bd82e8 | 77 | #define LGW_FSK_MODEM_ENABLE 17 |
| dgabino | 0:c76361bd82e8 | 78 | #define LGW_GLOBAL_EN 18 |
| dgabino | 0:c76361bd82e8 | 79 | #define LGW_CLK32M_EN 19 |
| dgabino | 0:c76361bd82e8 | 80 | #define LGW_CLKHS_EN 20 |
| dgabino | 0:c76361bd82e8 | 81 | #define LGW_START_BIST0 21 |
| dgabino | 0:c76361bd82e8 | 82 | #define LGW_START_BIST1 22 |
| dgabino | 0:c76361bd82e8 | 83 | #define LGW_CLEAR_BIST0 23 |
| dgabino | 0:c76361bd82e8 | 84 | #define LGW_CLEAR_BIST1 24 |
| dgabino | 0:c76361bd82e8 | 85 | #define LGW_BIST0_FINISHED 25 |
| dgabino | 0:c76361bd82e8 | 86 | #define LGW_BIST1_FINISHED 26 |
| dgabino | 0:c76361bd82e8 | 87 | #define LGW_MCU_AGC_PROG_RAM_BIST_STATUS 27 |
| dgabino | 0:c76361bd82e8 | 88 | #define LGW_MCU_ARB_PROG_RAM_BIST_STATUS 28 |
| dgabino | 0:c76361bd82e8 | 89 | #define LGW_CAPTURE_RAM_BIST_STATUS 29 |
| dgabino | 0:c76361bd82e8 | 90 | #define LGW_CHAN_FIR_RAM0_BIST_STATUS 30 |
| dgabino | 0:c76361bd82e8 | 91 | #define LGW_CHAN_FIR_RAM1_BIST_STATUS 31 |
| dgabino | 0:c76361bd82e8 | 92 | #define LGW_CORR0_RAM_BIST_STATUS 32 |
| dgabino | 0:c76361bd82e8 | 93 | #define LGW_CORR1_RAM_BIST_STATUS 33 |
| dgabino | 0:c76361bd82e8 | 94 | #define LGW_CORR2_RAM_BIST_STATUS 34 |
| dgabino | 0:c76361bd82e8 | 95 | #define LGW_CORR3_RAM_BIST_STATUS 35 |
| dgabino | 0:c76361bd82e8 | 96 | #define LGW_CORR4_RAM_BIST_STATUS 36 |
| dgabino | 0:c76361bd82e8 | 97 | #define LGW_CORR5_RAM_BIST_STATUS 37 |
| dgabino | 0:c76361bd82e8 | 98 | #define LGW_CORR6_RAM_BIST_STATUS 38 |
| dgabino | 0:c76361bd82e8 | 99 | #define LGW_CORR7_RAM_BIST_STATUS 39 |
| dgabino | 0:c76361bd82e8 | 100 | #define LGW_MODEM0_RAM0_BIST_STATUS 40 |
| dgabino | 0:c76361bd82e8 | 101 | #define LGW_MODEM1_RAM0_BIST_STATUS 41 |
| dgabino | 0:c76361bd82e8 | 102 | #define LGW_MODEM2_RAM0_BIST_STATUS 42 |
| dgabino | 0:c76361bd82e8 | 103 | #define LGW_MODEM3_RAM0_BIST_STATUS 43 |
| dgabino | 0:c76361bd82e8 | 104 | #define LGW_MODEM4_RAM0_BIST_STATUS 44 |
| dgabino | 0:c76361bd82e8 | 105 | #define LGW_MODEM5_RAM0_BIST_STATUS 45 |
| dgabino | 0:c76361bd82e8 | 106 | #define LGW_MODEM6_RAM0_BIST_STATUS 46 |
| dgabino | 0:c76361bd82e8 | 107 | #define LGW_MODEM7_RAM0_BIST_STATUS 47 |
| dgabino | 0:c76361bd82e8 | 108 | #define LGW_MODEM0_RAM1_BIST_STATUS 48 |
| dgabino | 0:c76361bd82e8 | 109 | #define LGW_MODEM1_RAM1_BIST_STATUS 49 |
| dgabino | 0:c76361bd82e8 | 110 | #define LGW_MODEM2_RAM1_BIST_STATUS 50 |
| dgabino | 0:c76361bd82e8 | 111 | #define LGW_MODEM3_RAM1_BIST_STATUS 51 |
| dgabino | 0:c76361bd82e8 | 112 | #define LGW_MODEM4_RAM1_BIST_STATUS 52 |
| dgabino | 0:c76361bd82e8 | 113 | #define LGW_MODEM5_RAM1_BIST_STATUS 53 |
| dgabino | 0:c76361bd82e8 | 114 | #define LGW_MODEM6_RAM1_BIST_STATUS 54 |
| dgabino | 0:c76361bd82e8 | 115 | #define LGW_MODEM7_RAM1_BIST_STATUS 55 |
| dgabino | 0:c76361bd82e8 | 116 | #define LGW_MODEM0_RAM2_BIST_STATUS 56 |
| dgabino | 0:c76361bd82e8 | 117 | #define LGW_MODEM1_RAM2_BIST_STATUS 57 |
| dgabino | 0:c76361bd82e8 | 118 | #define LGW_MODEM2_RAM2_BIST_STATUS 58 |
| dgabino | 0:c76361bd82e8 | 119 | #define LGW_MODEM3_RAM2_BIST_STATUS 59 |
| dgabino | 0:c76361bd82e8 | 120 | #define LGW_MODEM4_RAM2_BIST_STATUS 60 |
| dgabino | 0:c76361bd82e8 | 121 | #define LGW_MODEM5_RAM2_BIST_STATUS 61 |
| dgabino | 0:c76361bd82e8 | 122 | #define LGW_MODEM6_RAM2_BIST_STATUS 62 |
| dgabino | 0:c76361bd82e8 | 123 | #define LGW_MODEM7_RAM2_BIST_STATUS 63 |
| dgabino | 0:c76361bd82e8 | 124 | #define LGW_MODEM_MBWSSF_RAM0_BIST_STATUS 64 |
| dgabino | 0:c76361bd82e8 | 125 | #define LGW_MODEM_MBWSSF_RAM1_BIST_STATUS 65 |
| dgabino | 0:c76361bd82e8 | 126 | #define LGW_MODEM_MBWSSF_RAM2_BIST_STATUS 66 |
| dgabino | 0:c76361bd82e8 | 127 | #define LGW_MCU_AGC_DATA_RAM_BIST0_STATUS 67 |
| dgabino | 0:c76361bd82e8 | 128 | #define LGW_MCU_AGC_DATA_RAM_BIST1_STATUS 68 |
| dgabino | 0:c76361bd82e8 | 129 | #define LGW_MCU_ARB_DATA_RAM_BIST0_STATUS 69 |
| dgabino | 0:c76361bd82e8 | 130 | #define LGW_MCU_ARB_DATA_RAM_BIST1_STATUS 70 |
| dgabino | 0:c76361bd82e8 | 131 | #define LGW_TX_TOP_RAM_BIST0_STATUS 71 |
| dgabino | 0:c76361bd82e8 | 132 | #define LGW_TX_TOP_RAM_BIST1_STATUS 72 |
| dgabino | 0:c76361bd82e8 | 133 | #define LGW_DATA_MNGT_RAM_BIST0_STATUS 73 |
| dgabino | 0:c76361bd82e8 | 134 | #define LGW_DATA_MNGT_RAM_BIST1_STATUS 74 |
| dgabino | 0:c76361bd82e8 | 135 | #define LGW_GPIO_SELECT_INPUT 75 |
| dgabino | 0:c76361bd82e8 | 136 | #define LGW_GPIO_SELECT_OUTPUT 76 |
| dgabino | 0:c76361bd82e8 | 137 | #define LGW_GPIO_MODE 77 |
| dgabino | 0:c76361bd82e8 | 138 | #define LGW_GPIO_PIN_REG_IN 78 |
| dgabino | 0:c76361bd82e8 | 139 | #define LGW_GPIO_PIN_REG_OUT 79 |
| dgabino | 0:c76361bd82e8 | 140 | #define LGW_MCU_AGC_STATUS 80 |
| dgabino | 0:c76361bd82e8 | 141 | #define LGW_MCU_ARB_STATUS 81 |
| dgabino | 0:c76361bd82e8 | 142 | #define LGW_CHIP_ID 82 |
| dgabino | 0:c76361bd82e8 | 143 | #define LGW_EMERGENCY_FORCE_HOST_CTRL 83 |
| dgabino | 0:c76361bd82e8 | 144 | #define LGW_RX_INVERT_IQ 84 |
| dgabino | 0:c76361bd82e8 | 145 | #define LGW_MODEM_INVERT_IQ 85 |
| dgabino | 0:c76361bd82e8 | 146 | #define LGW_MBWSSF_MODEM_INVERT_IQ 86 |
| dgabino | 0:c76361bd82e8 | 147 | #define LGW_RX_EDGE_SELECT 87 |
| dgabino | 0:c76361bd82e8 | 148 | #define LGW_MISC_RADIO_EN 88 |
| dgabino | 0:c76361bd82e8 | 149 | #define LGW_FSK_MODEM_INVERT_IQ 89 |
| dgabino | 0:c76361bd82e8 | 150 | #define LGW_FILTER_GAIN 90 |
| dgabino | 0:c76361bd82e8 | 151 | #define LGW_RADIO_SELECT 91 |
| dgabino | 0:c76361bd82e8 | 152 | #define LGW_IF_FREQ_0 92 |
| dgabino | 0:c76361bd82e8 | 153 | #define LGW_IF_FREQ_1 93 |
| dgabino | 0:c76361bd82e8 | 154 | #define LGW_IF_FREQ_2 94 |
| dgabino | 0:c76361bd82e8 | 155 | #define LGW_IF_FREQ_3 95 |
| dgabino | 0:c76361bd82e8 | 156 | #define LGW_IF_FREQ_4 96 |
| dgabino | 0:c76361bd82e8 | 157 | #define LGW_IF_FREQ_5 97 |
| dgabino | 0:c76361bd82e8 | 158 | #define LGW_IF_FREQ_6 98 |
| dgabino | 0:c76361bd82e8 | 159 | #define LGW_IF_FREQ_7 99 |
| dgabino | 0:c76361bd82e8 | 160 | #define LGW_IF_FREQ_8 100 |
| dgabino | 0:c76361bd82e8 | 161 | #define LGW_IF_FREQ_9 101 |
| dgabino | 0:c76361bd82e8 | 162 | #define LGW_CHANN_OVERRIDE_AGC_GAIN 102 |
| dgabino | 0:c76361bd82e8 | 163 | #define LGW_CHANN_AGC_GAIN 103 |
| dgabino | 0:c76361bd82e8 | 164 | #define LGW_CORR0_DETECT_EN 104 |
| dgabino | 0:c76361bd82e8 | 165 | #define LGW_CORR1_DETECT_EN 105 |
| dgabino | 0:c76361bd82e8 | 166 | #define LGW_CORR2_DETECT_EN 106 |
| dgabino | 0:c76361bd82e8 | 167 | #define LGW_CORR3_DETECT_EN 107 |
| dgabino | 0:c76361bd82e8 | 168 | #define LGW_CORR4_DETECT_EN 108 |
| dgabino | 0:c76361bd82e8 | 169 | #define LGW_CORR5_DETECT_EN 109 |
| dgabino | 0:c76361bd82e8 | 170 | #define LGW_CORR6_DETECT_EN 110 |
| dgabino | 0:c76361bd82e8 | 171 | #define LGW_CORR7_DETECT_EN 111 |
| dgabino | 0:c76361bd82e8 | 172 | #define LGW_CORR_SAME_PEAKS_OPTION_SF6 112 |
| dgabino | 0:c76361bd82e8 | 173 | #define LGW_CORR_SAME_PEAKS_OPTION_SF7 113 |
| dgabino | 0:c76361bd82e8 | 174 | #define LGW_CORR_SAME_PEAKS_OPTION_SF8 114 |
| dgabino | 0:c76361bd82e8 | 175 | #define LGW_CORR_SAME_PEAKS_OPTION_SF9 115 |
| dgabino | 0:c76361bd82e8 | 176 | #define LGW_CORR_SAME_PEAKS_OPTION_SF10 116 |
| dgabino | 0:c76361bd82e8 | 177 | #define LGW_CORR_SAME_PEAKS_OPTION_SF11 117 |
| dgabino | 0:c76361bd82e8 | 178 | #define LGW_CORR_SAME_PEAKS_OPTION_SF12 118 |
| dgabino | 0:c76361bd82e8 | 179 | #define LGW_CORR_SIG_NOISE_RATIO_SF6 119 |
| dgabino | 0:c76361bd82e8 | 180 | #define LGW_CORR_SIG_NOISE_RATIO_SF7 120 |
| dgabino | 0:c76361bd82e8 | 181 | #define LGW_CORR_SIG_NOISE_RATIO_SF8 121 |
| dgabino | 0:c76361bd82e8 | 182 | #define LGW_CORR_SIG_NOISE_RATIO_SF9 122 |
| dgabino | 0:c76361bd82e8 | 183 | #define LGW_CORR_SIG_NOISE_RATIO_SF10 123 |
| dgabino | 0:c76361bd82e8 | 184 | #define LGW_CORR_SIG_NOISE_RATIO_SF11 124 |
| dgabino | 0:c76361bd82e8 | 185 | #define LGW_CORR_SIG_NOISE_RATIO_SF12 125 |
| dgabino | 0:c76361bd82e8 | 186 | #define LGW_CORR_NUM_SAME_PEAK 126 |
| dgabino | 0:c76361bd82e8 | 187 | #define LGW_CORR_MAC_GAIN 127 |
| dgabino | 0:c76361bd82e8 | 188 | #define LGW_ADJUST_MODEM_START_OFFSET_RDX4 128 |
| dgabino | 0:c76361bd82e8 | 189 | #define LGW_ADJUST_MODEM_START_OFFSET_SF12_RDX4 129 |
| dgabino | 0:c76361bd82e8 | 190 | #define LGW_DBG_CORR_SELECT_SF 130 |
| dgabino | 0:c76361bd82e8 | 191 | #define LGW_DBG_CORR_SELECT_CHANNEL 131 |
| dgabino | 0:c76361bd82e8 | 192 | #define LGW_DBG_DETECT_CPT 132 |
| dgabino | 0:c76361bd82e8 | 193 | #define LGW_DBG_SYMB_CPT 133 |
| dgabino | 0:c76361bd82e8 | 194 | #define LGW_CHIRP_INVERT_RX 134 |
| dgabino | 0:c76361bd82e8 | 195 | #define LGW_DC_NOTCH_EN 135 |
| dgabino | 0:c76361bd82e8 | 196 | #define LGW_IMPLICIT_CRC_EN 136 |
| dgabino | 0:c76361bd82e8 | 197 | #define LGW_IMPLICIT_CODING_RATE 137 |
| dgabino | 0:c76361bd82e8 | 198 | #define LGW_IMPLICIT_PAYLOAD_LENGHT 138 |
| dgabino | 0:c76361bd82e8 | 199 | #define LGW_FREQ_TO_TIME_INVERT 139 |
| dgabino | 0:c76361bd82e8 | 200 | #define LGW_FREQ_TO_TIME_DRIFT 140 |
| dgabino | 0:c76361bd82e8 | 201 | #define LGW_PAYLOAD_FINE_TIMING_GAIN 141 |
| dgabino | 0:c76361bd82e8 | 202 | #define LGW_PREAMBLE_FINE_TIMING_GAIN 142 |
| dgabino | 0:c76361bd82e8 | 203 | #define LGW_TRACKING_INTEGRAL 143 |
| dgabino | 0:c76361bd82e8 | 204 | #define LGW_FRAME_SYNCH_PEAK1_POS 144 |
| dgabino | 0:c76361bd82e8 | 205 | #define LGW_FRAME_SYNCH_PEAK2_POS 145 |
| dgabino | 0:c76361bd82e8 | 206 | #define LGW_PREAMBLE_SYMB1_NB 146 |
| dgabino | 0:c76361bd82e8 | 207 | #define LGW_FRAME_SYNCH_GAIN 147 |
| dgabino | 0:c76361bd82e8 | 208 | #define LGW_SYNCH_DETECT_TH 148 |
| dgabino | 0:c76361bd82e8 | 209 | #define LGW_LLR_SCALE 149 |
| dgabino | 0:c76361bd82e8 | 210 | #define LGW_SNR_AVG_CST 150 |
| dgabino | 0:c76361bd82e8 | 211 | #define LGW_PPM_OFFSET 151 |
| dgabino | 0:c76361bd82e8 | 212 | #define LGW_MAX_PAYLOAD_LEN 152 |
| dgabino | 0:c76361bd82e8 | 213 | #define LGW_ONLY_CRC_EN 153 |
| dgabino | 0:c76361bd82e8 | 214 | #define LGW_ZERO_PAD 154 |
| dgabino | 0:c76361bd82e8 | 215 | #define LGW_DEC_GAIN_OFFSET 155 |
| dgabino | 0:c76361bd82e8 | 216 | #define LGW_CHAN_GAIN_OFFSET 156 |
| dgabino | 0:c76361bd82e8 | 217 | #define LGW_FORCE_HOST_RADIO_CTRL 157 |
| dgabino | 0:c76361bd82e8 | 218 | #define LGW_FORCE_HOST_FE_CTRL 158 |
| dgabino | 0:c76361bd82e8 | 219 | #define LGW_FORCE_DEC_FILTER_GAIN 159 |
| dgabino | 0:c76361bd82e8 | 220 | #define LGW_MCU_RST_0 160 |
| dgabino | 0:c76361bd82e8 | 221 | #define LGW_MCU_RST_1 161 |
| dgabino | 0:c76361bd82e8 | 222 | #define LGW_MCU_SELECT_MUX_0 162 |
| dgabino | 0:c76361bd82e8 | 223 | #define LGW_MCU_SELECT_MUX_1 163 |
| dgabino | 0:c76361bd82e8 | 224 | #define LGW_MCU_CORRUPTION_DETECTED_0 164 |
| dgabino | 0:c76361bd82e8 | 225 | #define LGW_MCU_CORRUPTION_DETECTED_1 165 |
| dgabino | 0:c76361bd82e8 | 226 | #define LGW_MCU_SELECT_EDGE_0 166 |
| dgabino | 0:c76361bd82e8 | 227 | #define LGW_MCU_SELECT_EDGE_1 167 |
| dgabino | 0:c76361bd82e8 | 228 | #define LGW_CHANN_SELECT_RSSI 168 |
| dgabino | 0:c76361bd82e8 | 229 | #define LGW_RSSI_BB_DEFAULT_VALUE 169 |
| dgabino | 0:c76361bd82e8 | 230 | #define LGW_RSSI_DEC_DEFAULT_VALUE 170 |
| dgabino | 0:c76361bd82e8 | 231 | #define LGW_RSSI_CHANN_DEFAULT_VALUE 171 |
| dgabino | 0:c76361bd82e8 | 232 | #define LGW_RSSI_BB_FILTER_ALPHA 172 |
| dgabino | 0:c76361bd82e8 | 233 | #define LGW_RSSI_DEC_FILTER_ALPHA 173 |
| dgabino | 0:c76361bd82e8 | 234 | #define LGW_RSSI_CHANN_FILTER_ALPHA 174 |
| dgabino | 0:c76361bd82e8 | 235 | #define LGW_IQ_MISMATCH_A_AMP_COEFF 175 |
| dgabino | 0:c76361bd82e8 | 236 | #define LGW_IQ_MISMATCH_A_PHI_COEFF 176 |
| dgabino | 0:c76361bd82e8 | 237 | #define LGW_IQ_MISMATCH_B_AMP_COEFF 177 |
| dgabino | 0:c76361bd82e8 | 238 | #define LGW_IQ_MISMATCH_B_SEL_I 178 |
| dgabino | 0:c76361bd82e8 | 239 | #define LGW_IQ_MISMATCH_B_PHI_COEFF 179 |
| dgabino | 0:c76361bd82e8 | 240 | #define LGW_TX_TRIG_IMMEDIATE 180 |
| dgabino | 0:c76361bd82e8 | 241 | #define LGW_TX_TRIG_DELAYED 181 |
| dgabino | 0:c76361bd82e8 | 242 | #define LGW_TX_TRIG_GPS 182 |
| dgabino | 0:c76361bd82e8 | 243 | #define LGW_TX_START_DELAY 183 |
| dgabino | 0:c76361bd82e8 | 244 | #define LGW_TX_FRAME_SYNCH_PEAK1_POS 184 |
| dgabino | 0:c76361bd82e8 | 245 | #define LGW_TX_FRAME_SYNCH_PEAK2_POS 185 |
| dgabino | 0:c76361bd82e8 | 246 | #define LGW_TX_RAMP_DURATION 186 |
| dgabino | 0:c76361bd82e8 | 247 | #define LGW_TX_OFFSET_I 187 |
| dgabino | 0:c76361bd82e8 | 248 | #define LGW_TX_OFFSET_Q 188 |
| dgabino | 0:c76361bd82e8 | 249 | #define LGW_TX_MODE 189 |
| dgabino | 0:c76361bd82e8 | 250 | #define LGW_TX_ZERO_PAD 190 |
| dgabino | 0:c76361bd82e8 | 251 | #define LGW_TX_EDGE_SELECT 191 |
| dgabino | 0:c76361bd82e8 | 252 | #define LGW_TX_EDGE_SELECT_TOP 192 |
| dgabino | 0:c76361bd82e8 | 253 | #define LGW_TX_GAIN 193 |
| dgabino | 0:c76361bd82e8 | 254 | #define LGW_TX_CHIRP_LOW_PASS 194 |
| dgabino | 0:c76361bd82e8 | 255 | #define LGW_TX_FCC_WIDEBAND 195 |
| dgabino | 0:c76361bd82e8 | 256 | #define LGW_TX_SWAP_IQ 196 |
| dgabino | 0:c76361bd82e8 | 257 | #define LGW_MBWSSF_IMPLICIT_HEADER 197 |
| dgabino | 0:c76361bd82e8 | 258 | #define LGW_MBWSSF_IMPLICIT_CRC_EN 198 |
| dgabino | 0:c76361bd82e8 | 259 | #define LGW_MBWSSF_IMPLICIT_CODING_RATE 199 |
| dgabino | 0:c76361bd82e8 | 260 | #define LGW_MBWSSF_IMPLICIT_PAYLOAD_LENGHT 200 |
| dgabino | 0:c76361bd82e8 | 261 | #define LGW_MBWSSF_AGC_FREEZE_ON_DETECT 201 |
| dgabino | 0:c76361bd82e8 | 262 | #define LGW_MBWSSF_FRAME_SYNCH_PEAK1_POS 202 |
| dgabino | 0:c76361bd82e8 | 263 | #define LGW_MBWSSF_FRAME_SYNCH_PEAK2_POS 203 |
| dgabino | 0:c76361bd82e8 | 264 | #define LGW_MBWSSF_PREAMBLE_SYMB1_NB 204 |
| dgabino | 0:c76361bd82e8 | 265 | #define LGW_MBWSSF_FRAME_SYNCH_GAIN 205 |
| dgabino | 0:c76361bd82e8 | 266 | #define LGW_MBWSSF_SYNCH_DETECT_TH 206 |
| dgabino | 0:c76361bd82e8 | 267 | #define LGW_MBWSSF_DETECT_MIN_SINGLE_PEAK 207 |
| dgabino | 0:c76361bd82e8 | 268 | #define LGW_MBWSSF_DETECT_TRIG_SAME_PEAK_NB 208 |
| dgabino | 0:c76361bd82e8 | 269 | #define LGW_MBWSSF_FREQ_TO_TIME_INVERT 209 |
| dgabino | 0:c76361bd82e8 | 270 | #define LGW_MBWSSF_FREQ_TO_TIME_DRIFT 210 |
| dgabino | 0:c76361bd82e8 | 271 | #define LGW_MBWSSF_PPM_CORRECTION 211 |
| dgabino | 0:c76361bd82e8 | 272 | #define LGW_MBWSSF_PAYLOAD_FINE_TIMING_GAIN 212 |
| dgabino | 0:c76361bd82e8 | 273 | #define LGW_MBWSSF_PREAMBLE_FINE_TIMING_GAIN 213 |
| dgabino | 0:c76361bd82e8 | 274 | #define LGW_MBWSSF_TRACKING_INTEGRAL 214 |
| dgabino | 0:c76361bd82e8 | 275 | #define LGW_MBWSSF_ZERO_PAD 215 |
| dgabino | 0:c76361bd82e8 | 276 | #define LGW_MBWSSF_MODEM_BW 216 |
| dgabino | 0:c76361bd82e8 | 277 | #define LGW_MBWSSF_RADIO_SELECT 217 |
| dgabino | 0:c76361bd82e8 | 278 | #define LGW_MBWSSF_RX_CHIRP_INVERT 218 |
| dgabino | 0:c76361bd82e8 | 279 | #define LGW_MBWSSF_LLR_SCALE 219 |
| dgabino | 0:c76361bd82e8 | 280 | #define LGW_MBWSSF_SNR_AVG_CST 220 |
| dgabino | 0:c76361bd82e8 | 281 | #define LGW_MBWSSF_PPM_OFFSET 221 |
| dgabino | 0:c76361bd82e8 | 282 | #define LGW_MBWSSF_RATE_SF 222 |
| dgabino | 0:c76361bd82e8 | 283 | #define LGW_MBWSSF_ONLY_CRC_EN 223 |
| dgabino | 0:c76361bd82e8 | 284 | #define LGW_MBWSSF_MAX_PAYLOAD_LEN 224 |
| dgabino | 0:c76361bd82e8 | 285 | #define LGW_TX_STATUS 225 |
| dgabino | 0:c76361bd82e8 | 286 | #define LGW_FSK_CH_BW_EXPO 226 |
| dgabino | 0:c76361bd82e8 | 287 | #define LGW_FSK_RSSI_LENGTH 227 |
| dgabino | 0:c76361bd82e8 | 288 | #define LGW_FSK_RX_INVERT 228 |
| dgabino | 0:c76361bd82e8 | 289 | #define LGW_FSK_PKT_MODE 229 |
| dgabino | 0:c76361bd82e8 | 290 | #define LGW_FSK_PSIZE 230 |
| dgabino | 0:c76361bd82e8 | 291 | #define LGW_FSK_CRC_EN 231 |
| dgabino | 0:c76361bd82e8 | 292 | #define LGW_FSK_DCFREE_ENC 232 |
| dgabino | 0:c76361bd82e8 | 293 | #define LGW_FSK_CRC_IBM 233 |
| dgabino | 0:c76361bd82e8 | 294 | #define LGW_FSK_ERROR_OSR_TOL 234 |
| dgabino | 0:c76361bd82e8 | 295 | #define LGW_FSK_RADIO_SELECT 235 |
| dgabino | 0:c76361bd82e8 | 296 | #define LGW_FSK_BR_RATIO 236 |
| dgabino | 0:c76361bd82e8 | 297 | #define LGW_FSK_REF_PATTERN_LSB 237 |
| dgabino | 0:c76361bd82e8 | 298 | #define LGW_FSK_REF_PATTERN_MSB 238 |
| dgabino | 0:c76361bd82e8 | 299 | #define LGW_FSK_PKT_LENGTH 239 |
| dgabino | 0:c76361bd82e8 | 300 | #define LGW_FSK_TX_GAUSSIAN_EN 240 |
| dgabino | 0:c76361bd82e8 | 301 | #define LGW_FSK_TX_GAUSSIAN_SELECT_BT 241 |
| dgabino | 0:c76361bd82e8 | 302 | #define LGW_FSK_TX_PATTERN_EN 242 |
| dgabino | 0:c76361bd82e8 | 303 | #define LGW_FSK_TX_PREAMBLE_SEQ 243 |
| dgabino | 0:c76361bd82e8 | 304 | #define LGW_FSK_TX_PSIZE 244 |
| dgabino | 0:c76361bd82e8 | 305 | #define LGW_FSK_NODE_ADRS 245 |
| dgabino | 0:c76361bd82e8 | 306 | #define LGW_FSK_BROADCAST 246 |
| dgabino | 0:c76361bd82e8 | 307 | #define LGW_FSK_AUTO_AFC_ON 247 |
| dgabino | 0:c76361bd82e8 | 308 | #define LGW_FSK_PATTERN_TIMEOUT_CFG 248 |
| dgabino | 0:c76361bd82e8 | 309 | #define LGW_SPI_RADIO_A__DATA 249 |
| dgabino | 0:c76361bd82e8 | 310 | #define LGW_SPI_RADIO_A__DATA_READBACK 250 |
| dgabino | 0:c76361bd82e8 | 311 | #define LGW_SPI_RADIO_A__ADDR 251 |
| dgabino | 0:c76361bd82e8 | 312 | #define LGW_SPI_RADIO_A__CS 252 |
| dgabino | 0:c76361bd82e8 | 313 | #define LGW_SPI_RADIO_B__DATA 253 |
| dgabino | 0:c76361bd82e8 | 314 | #define LGW_SPI_RADIO_B__DATA_READBACK 254 |
| dgabino | 0:c76361bd82e8 | 315 | #define LGW_SPI_RADIO_B__ADDR 255 |
| dgabino | 0:c76361bd82e8 | 316 | #define LGW_SPI_RADIO_B__CS 256 |
| dgabino | 0:c76361bd82e8 | 317 | #define LGW_RADIO_A_EN 257 |
| dgabino | 0:c76361bd82e8 | 318 | #define LGW_RADIO_B_EN 258 |
| dgabino | 0:c76361bd82e8 | 319 | #define LGW_RADIO_RST 259 |
| dgabino | 0:c76361bd82e8 | 320 | #define LGW_LNA_A_EN 260 |
| dgabino | 0:c76361bd82e8 | 321 | #define LGW_PA_A_EN 261 |
| dgabino | 0:c76361bd82e8 | 322 | #define LGW_LNA_B_EN 262 |
| dgabino | 0:c76361bd82e8 | 323 | #define LGW_PA_B_EN 263 |
| dgabino | 0:c76361bd82e8 | 324 | #define LGW_PA_GAIN 264 |
| dgabino | 0:c76361bd82e8 | 325 | #define LGW_LNA_A_CTRL_LUT 265 |
| dgabino | 0:c76361bd82e8 | 326 | #define LGW_PA_A_CTRL_LUT 266 |
| dgabino | 0:c76361bd82e8 | 327 | #define LGW_LNA_B_CTRL_LUT 267 |
| dgabino | 0:c76361bd82e8 | 328 | #define LGW_PA_B_CTRL_LUT 268 |
| dgabino | 0:c76361bd82e8 | 329 | #define LGW_CAPTURE_SOURCE 269 |
| dgabino | 0:c76361bd82e8 | 330 | #define LGW_CAPTURE_START 270 |
| dgabino | 0:c76361bd82e8 | 331 | #define LGW_CAPTURE_FORCE_TRIGGER 271 |
| dgabino | 0:c76361bd82e8 | 332 | #define LGW_CAPTURE_WRAP 272 |
| dgabino | 0:c76361bd82e8 | 333 | #define LGW_CAPTURE_PERIOD 273 |
| dgabino | 0:c76361bd82e8 | 334 | #define LGW_MODEM_STATUS 274 |
| dgabino | 0:c76361bd82e8 | 335 | #define LGW_VALID_HEADER_COUNTER_0 275 |
| dgabino | 0:c76361bd82e8 | 336 | #define LGW_VALID_PACKET_COUNTER_0 276 |
| dgabino | 0:c76361bd82e8 | 337 | #define LGW_VALID_HEADER_COUNTER_MBWSSF 277 |
| dgabino | 0:c76361bd82e8 | 338 | #define LGW_VALID_HEADER_COUNTER_FSK 278 |
| dgabino | 0:c76361bd82e8 | 339 | #define LGW_VALID_PACKET_COUNTER_MBWSSF 279 |
| dgabino | 0:c76361bd82e8 | 340 | #define LGW_VALID_PACKET_COUNTER_FSK 280 |
| dgabino | 0:c76361bd82e8 | 341 | #define LGW_CHANN_RSSI 281 |
| dgabino | 0:c76361bd82e8 | 342 | #define LGW_BB_RSSI 282 |
| dgabino | 0:c76361bd82e8 | 343 | #define LGW_DEC_RSSI 283 |
| dgabino | 0:c76361bd82e8 | 344 | #define LGW_DBG_MCU_DATA 284 |
| dgabino | 0:c76361bd82e8 | 345 | #define LGW_DBG_ARB_MCU_RAM_DATA 285 |
| dgabino | 0:c76361bd82e8 | 346 | #define LGW_DBG_AGC_MCU_RAM_DATA 286 |
| dgabino | 0:c76361bd82e8 | 347 | #define LGW_NEXT_PACKET_CNT 287 |
| dgabino | 0:c76361bd82e8 | 348 | #define LGW_ADDR_CAPTURE_COUNT 288 |
| dgabino | 0:c76361bd82e8 | 349 | #define LGW_TIMESTAMP 289 |
| dgabino | 0:c76361bd82e8 | 350 | #define LGW_DBG_CHANN0_GAIN 290 |
| dgabino | 0:c76361bd82e8 | 351 | #define LGW_DBG_CHANN1_GAIN 291 |
| dgabino | 0:c76361bd82e8 | 352 | #define LGW_DBG_CHANN2_GAIN 292 |
| dgabino | 0:c76361bd82e8 | 353 | #define LGW_DBG_CHANN3_GAIN 293 |
| dgabino | 0:c76361bd82e8 | 354 | #define LGW_DBG_CHANN4_GAIN 294 |
| dgabino | 0:c76361bd82e8 | 355 | #define LGW_DBG_CHANN5_GAIN 295 |
| dgabino | 0:c76361bd82e8 | 356 | #define LGW_DBG_CHANN6_GAIN 296 |
| dgabino | 0:c76361bd82e8 | 357 | #define LGW_DBG_CHANN7_GAIN 297 |
| dgabino | 0:c76361bd82e8 | 358 | #define LGW_DBG_DEC_FILT_GAIN 298 |
| dgabino | 0:c76361bd82e8 | 359 | #define LGW_SPI_DATA_FIFO_PTR 299 |
| dgabino | 0:c76361bd82e8 | 360 | #define LGW_PACKET_DATA_FIFO_PTR 300 |
| dgabino | 0:c76361bd82e8 | 361 | #define LGW_DBG_ARB_MCU_RAM_ADDR 301 |
| dgabino | 0:c76361bd82e8 | 362 | #define LGW_DBG_AGC_MCU_RAM_ADDR 302 |
| dgabino | 0:c76361bd82e8 | 363 | #define LGW_SPI_MASTER_CHIP_SELECT_POLARITY 303 |
| dgabino | 0:c76361bd82e8 | 364 | #define LGW_SPI_MASTER_CPOL 304 |
| dgabino | 0:c76361bd82e8 | 365 | #define LGW_SPI_MASTER_CPHA 305 |
| dgabino | 0:c76361bd82e8 | 366 | #define LGW_SIG_GEN_ANALYSER_MUX_SEL 306 |
| dgabino | 0:c76361bd82e8 | 367 | #define LGW_SIG_GEN_EN 307 |
| dgabino | 0:c76361bd82e8 | 368 | #define LGW_SIG_ANALYSER_EN 308 |
| dgabino | 0:c76361bd82e8 | 369 | #define LGW_SIG_ANALYSER_AVG_LEN 309 |
| dgabino | 0:c76361bd82e8 | 370 | #define LGW_SIG_ANALYSER_PRECISION 310 |
| dgabino | 0:c76361bd82e8 | 371 | #define LGW_SIG_ANALYSER_VALID_OUT 311 |
| dgabino | 0:c76361bd82e8 | 372 | #define LGW_SIG_GEN_FREQ 312 |
| dgabino | 0:c76361bd82e8 | 373 | #define LGW_SIG_ANALYSER_FREQ 313 |
| dgabino | 0:c76361bd82e8 | 374 | #define LGW_SIG_ANALYSER_I_OUT 314 |
| dgabino | 0:c76361bd82e8 | 375 | #define LGW_SIG_ANALYSER_Q_OUT 315 |
| dgabino | 0:c76361bd82e8 | 376 | #define LGW_GPS_EN 316 |
| dgabino | 0:c76361bd82e8 | 377 | #define LGW_GPS_POL 317 |
| dgabino | 0:c76361bd82e8 | 378 | #define LGW_SW_TEST_REG1 318 |
| dgabino | 0:c76361bd82e8 | 379 | #define LGW_SW_TEST_REG2 319 |
| dgabino | 0:c76361bd82e8 | 380 | #define LGW_SW_TEST_REG3 320 |
| dgabino | 0:c76361bd82e8 | 381 | #define LGW_DATA_MNGT_STATUS 321 |
| dgabino | 0:c76361bd82e8 | 382 | #define LGW_DATA_MNGT_CPT_FRAME_ALLOCATED 322 |
| dgabino | 0:c76361bd82e8 | 383 | #define LGW_DATA_MNGT_CPT_FRAME_FINISHED 323 |
| dgabino | 0:c76361bd82e8 | 384 | #define LGW_DATA_MNGT_CPT_FRAME_READEN 324 |
| dgabino | 0:c76361bd82e8 | 385 | #define LGW_TX_TRIG_ALL 325 |
| dgabino | 0:c76361bd82e8 | 386 | |
| dgabino | 0:c76361bd82e8 | 387 | #define LGW_TOTALREGS 326 |
| dgabino | 0:c76361bd82e8 | 388 | |
| dgabino | 0:c76361bd82e8 | 389 | /* -------------------------------------------------------------------------- */ |
| dgabino | 0:c76361bd82e8 | 390 | /* --- PUBLIC FUNCTIONS PROTOTYPES ------------------------------------------ */ |
| dgabino | 0:c76361bd82e8 | 391 | |
| dgabino | 0:c76361bd82e8 | 392 | /** |
| dgabino | 0:c76361bd82e8 | 393 | @brief Connect LoRa concentrator by opening SPI link |
| dgabino | 0:c76361bd82e8 | 394 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 395 | */ |
| dgabino | 0:c76361bd82e8 | 396 | int lgw_connect(void); |
| dgabino | 0:c76361bd82e8 | 397 | |
| dgabino | 0:c76361bd82e8 | 398 | /** |
| dgabino | 0:c76361bd82e8 | 399 | @brief Disconnect LoRa concentrator by closing SPI link |
| dgabino | 0:c76361bd82e8 | 400 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 401 | */ |
| dgabino | 0:c76361bd82e8 | 402 | int lgw_disconnect(void); |
| dgabino | 0:c76361bd82e8 | 403 | |
| dgabino | 0:c76361bd82e8 | 404 | /** |
| dgabino | 0:c76361bd82e8 | 405 | @brief Use the soft-reset register to put the concentrator in initial state |
| dgabino | 0:c76361bd82e8 | 406 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 407 | */ |
| dgabino | 0:c76361bd82e8 | 408 | int lgw_soft_reset(void); |
| dgabino | 0:c76361bd82e8 | 409 | |
| dgabino | 0:c76361bd82e8 | 410 | /** |
| dgabino | 0:c76361bd82e8 | 411 | @brief Check if the registers are ok, send diagnostics to stdio/stderr/file |
| dgabino | 0:c76361bd82e8 | 412 | @param f file descriptor to to which the check result will be written |
| dgabino | 0:c76361bd82e8 | 413 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 414 | */ |
| dgabino | 0:c76361bd82e8 | 415 | int lgw_reg_check(FILE *f); |
| dgabino | 0:c76361bd82e8 | 416 | |
| dgabino | 0:c76361bd82e8 | 417 | /** |
| dgabino | 0:c76361bd82e8 | 418 | @brief LoRa concentrator register write |
| dgabino | 0:c76361bd82e8 | 419 | @param register_id register number in the data structure describing registers |
| dgabino | 0:c76361bd82e8 | 420 | @param reg_value signed value to write to the register (for u32, use cast) |
| dgabino | 0:c76361bd82e8 | 421 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 422 | */ |
| dgabino | 0:c76361bd82e8 | 423 | int lgw_reg_w(uint16_t register_id, int32_t reg_value); |
| dgabino | 0:c76361bd82e8 | 424 | |
| dgabino | 0:c76361bd82e8 | 425 | /** |
| dgabino | 0:c76361bd82e8 | 426 | @brief LoRa concentrator register read |
| dgabino | 0:c76361bd82e8 | 427 | @param register_id register number in the data structure describing registers |
| dgabino | 0:c76361bd82e8 | 428 | @param reg_value pointer to a variable where to write register read value |
| dgabino | 0:c76361bd82e8 | 429 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 430 | */ |
| dgabino | 0:c76361bd82e8 | 431 | int lgw_reg_r(uint16_t register_id, int32_t *reg_value); |
| dgabino | 0:c76361bd82e8 | 432 | |
| dgabino | 0:c76361bd82e8 | 433 | /** |
| dgabino | 0:c76361bd82e8 | 434 | @brief LoRa concentrator register burst write |
| dgabino | 0:c76361bd82e8 | 435 | @param register_id register number in the data structure describing registers |
| dgabino | 0:c76361bd82e8 | 436 | @param data pointer to byte array that will be sent to the LoRa concentrator |
| dgabino | 0:c76361bd82e8 | 437 | @param size size of the transfer, in byte(s) |
| dgabino | 0:c76361bd82e8 | 438 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 439 | */ |
| dgabino | 0:c76361bd82e8 | 440 | int lgw_reg_wb(uint16_t register_id, uint8_t *data, uint16_t size); |
| dgabino | 0:c76361bd82e8 | 441 | |
| dgabino | 0:c76361bd82e8 | 442 | /** |
| dgabino | 0:c76361bd82e8 | 443 | @brief LoRa concentrator register burst read |
| dgabino | 0:c76361bd82e8 | 444 | @param register_id register number in the data structure describing registers |
| dgabino | 0:c76361bd82e8 | 445 | @param data pointer to byte array that will be written from the LoRa concentrator |
| dgabino | 0:c76361bd82e8 | 446 | @param size size of the transfer, in byte(s) |
| dgabino | 0:c76361bd82e8 | 447 | @return status of register operation (LGW_REG_SUCCESS/LGW_REG_ERROR) |
| dgabino | 0:c76361bd82e8 | 448 | */ |
| dgabino | 0:c76361bd82e8 | 449 | int lgw_reg_rb(uint16_t register_id, uint8_t *data, uint16_t size); |
| dgabino | 0:c76361bd82e8 | 450 | |
| dgabino | 0:c76361bd82e8 | 451 | |
| dgabino | 0:c76361bd82e8 | 452 | #endif |
| dgabino | 0:c76361bd82e8 | 453 | |
| dgabino | 0:c76361bd82e8 | 454 | /* --- EOF ------------------------------------------------------------------ */ |