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mbed-os/targets/TARGET_NXP/TARGET_LPC43XX/ethernet_api.c@0:6bf0743ece18, 2020-03-28 (annotated)

Committer:
demayer
Date:
Sat Mar 28 15:28:19 2020 +0000
Revision:
0:6bf0743ece18
IMU Thread with an event-queue running parallel to handle tasks like a 5 times blinking LED. Button with interrupt detected.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
demayer 0:6bf0743ece18 1 /* mbed Microcontroller Library
demayer 0:6bf0743ece18 2 * Copyright (c) 2006-2015 ARM Limited
demayer 0:6bf0743ece18 3 *
demayer 0:6bf0743ece18 4 * Licensed under the Apache License, Version 2.0 (the "License");
demayer 0:6bf0743ece18 5 * you may not use this file except in compliance with the License.
demayer 0:6bf0743ece18 6 * You may obtain a copy of the License at
demayer 0:6bf0743ece18 7 *
demayer 0:6bf0743ece18 8 * http://www.apache.org/licenses/LICENSE-2.0
demayer 0:6bf0743ece18 9 *
demayer 0:6bf0743ece18 10 * Unless required by applicable law or agreed to in writing, software
demayer 0:6bf0743ece18 11 * distributed under the License is distributed on an "AS IS" BASIS,
demayer 0:6bf0743ece18 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
demayer 0:6bf0743ece18 13 * See the License for the specific language governing permissions and
demayer 0:6bf0743ece18 14 * limitations under the License.
demayer 0:6bf0743ece18 15 *
demayer 0:6bf0743ece18 16 * Contribution by Nitin Bhaskar(nitin.bhaskar.27.09@gmail.com)
demayer 0:6bf0743ece18 17 */
demayer 0:6bf0743ece18 18 #include "ethernet_api.h"
demayer 0:6bf0743ece18 19
demayer 0:6bf0743ece18 20 #include <string.h>
demayer 0:6bf0743ece18 21 #include "cmsis.h"
demayer 0:6bf0743ece18 22 #include "mbed_interface.h"
demayer 0:6bf0743ece18 23 #include "mbed_toolchain.h"
demayer 0:6bf0743ece18 24 #include "mbed_error.h"
demayer 0:6bf0743ece18 25 #include "pinmap.h"
demayer 0:6bf0743ece18 26
demayer 0:6bf0743ece18 27 #define NEW_LOGIC 0
demayer 0:6bf0743ece18 28 #define NEW_ETH_BUFFER 0
demayer 0:6bf0743ece18 29
demayer 0:6bf0743ece18 30 #if NEW_ETH_BUFFER
demayer 0:6bf0743ece18 31
demayer 0:6bf0743ece18 32 #define NUM_RX_FRAG 4 // Number of Rx Fragments (== packets)
demayer 0:6bf0743ece18 33 #define NUM_TX_FRAG 3 // Number of Tx Fragments (== packets)
demayer 0:6bf0743ece18 34
demayer 0:6bf0743ece18 35 #define ETH_MAX_FLEN 1536 // Maximum Ethernet Frame Size
demayer 0:6bf0743ece18 36 #define ETH_FRAG_SIZE ETH_MAX_FLEN // Packet Fragment size (same as packet length)
demayer 0:6bf0743ece18 37
demayer 0:6bf0743ece18 38 #else
demayer 0:6bf0743ece18 39
demayer 0:6bf0743ece18 40 // Memfree calculation:
demayer 0:6bf0743ece18 41 // (16 * 1024) - ((2 * 4 * NUM_RX) + (2 * 4 * NUM_RX) + (0x300 * NUM_RX) +
demayer 0:6bf0743ece18 42 // (2 * 4 * NUM_TX) + (1 * 4 * NUM_TX) + (0x300 * NUM_TX)) = 8556
demayer 0:6bf0743ece18 43 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
demayer 0:6bf0743ece18 44 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
demayer 0:6bf0743ece18 45 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
demayer 0:6bf0743ece18 46 //#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
demayer 0:6bf0743ece18 47
demayer 0:6bf0743ece18 48 //#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
demayer 0:6bf0743ece18 49 #define ETH_FRAG_SIZE 0x300 /* Packet Fragment size 1536/2 Bytes */
demayer 0:6bf0743ece18 50 #define ETH_MAX_FLEN 0x300 /* Max. Ethernet Frame Size */
demayer 0:6bf0743ece18 51
demayer 0:6bf0743ece18 52 const int ethernet_MTU_SIZE = 0x300;
demayer 0:6bf0743ece18 53
demayer 0:6bf0743ece18 54 #endif
demayer 0:6bf0743ece18 55
demayer 0:6bf0743ece18 56 #define ETHERNET_ADDR_SIZE 6
demayer 0:6bf0743ece18 57
demayer 0:6bf0743ece18 58 /* Descriptors Fields bits */
demayer 0:6bf0743ece18 59 #define TRDES_OWN_BIT (1U<<31) /* Own bit in RDES0 & TDES0 */
demayer 0:6bf0743ece18 60 #define RX_END_RING (1<<15) /* Receive End of Ring bit in RDES1 */
demayer 0:6bf0743ece18 61 #define RX_NXTDESC_FLAG (1<<14) /* Second Address Chained bit in RDES1 */
demayer 0:6bf0743ece18 62 #define TX_LAST_SEGM (1<<29) /* Last Segment bit in TDES0 */
demayer 0:6bf0743ece18 63 #define TX_FIRST_SEGM (1<<28) /* First Segment bit in TDES0 */
demayer 0:6bf0743ece18 64 #define TX_END_RING (1<<21) /* Transmit End of Ring bit in TDES0 */
demayer 0:6bf0743ece18 65 #define TX_NXTDESC_FLAG (1<<20) /* Second Address Chained bit in TDES0 */
demayer 0:6bf0743ece18 66
demayer 0:6bf0743ece18 67 PACKED struct RX_DESC_TypeDef { /* RX Descriptor struct */
demayer 0:6bf0743ece18 68 unsigned int Status;
demayer 0:6bf0743ece18 69 unsigned int Ctrl;
demayer 0:6bf0743ece18 70 unsigned int BufAddr1;
demayer 0:6bf0743ece18 71 unsigned int NextDescAddr;
demayer 0:6bf0743ece18 72 };
demayer 0:6bf0743ece18 73 typedef struct RX_DESC_TypeDef RX_DESC_TypeDef;
demayer 0:6bf0743ece18 74
demayer 0:6bf0743ece18 75 PACKED struct TX_DESC_TypeDef { /* TX Descriptor struct */
demayer 0:6bf0743ece18 76 unsigned int Status;
demayer 0:6bf0743ece18 77 unsigned int Ctrl;
demayer 0:6bf0743ece18 78 unsigned int BufAddr1;
demayer 0:6bf0743ece18 79 unsigned int NextDescAddr;
demayer 0:6bf0743ece18 80 };
demayer 0:6bf0743ece18 81 typedef struct TX_DESC_TypeDef TX_DESC_TypeDef;
demayer 0:6bf0743ece18 82
demayer 0:6bf0743ece18 83 /* ETHMODE RMII SELECT */
demayer 0:6bf0743ece18 84 #define RMII_SELECT 0x04
demayer 0:6bf0743ece18 85 /* define to tell PHY about write operation */
demayer 0:6bf0743ece18 86 #define MII_WRITE (1 << 1)
demayer 0:6bf0743ece18 87 /* define to tell PHY about read operation */
demayer 0:6bf0743ece18 88 #define MII_READ (0 << 1)
demayer 0:6bf0743ece18 89 /* define to enable duplex mode */
demayer 0:6bf0743ece18 90 #define MAC_DUPLEX_MODE (1 << 11)
demayer 0:6bf0743ece18 91
demayer 0:6bf0743ece18 92 /* MAC_FRAME_FILTER register bit defines */
demayer 0:6bf0743ece18 93 #define MAC_FRAME_FILTER_PR (1 << 0) /* Promiscuous Mode */
demayer 0:6bf0743ece18 94 #define MAC_FRAME_FILTER_RA (1UL << 31) /* Receive all */
demayer 0:6bf0743ece18 95
demayer 0:6bf0743ece18 96 /* MAC_CONFIG register bit defines */
demayer 0:6bf0743ece18 97 #define MAC_CONFIG_RE (1 << 2) /* Receiver enable */
demayer 0:6bf0743ece18 98 #define MAC_CONFIG_TE (1 << 3) /* Transmitter Enable */
demayer 0:6bf0743ece18 99
demayer 0:6bf0743ece18 100 /* DMA_OP_MODE register bit defines */
demayer 0:6bf0743ece18 101 #define DMA_OP_MODE_SSR (1 << 1) /* Start/stop receive */
demayer 0:6bf0743ece18 102 #define DMA_OP_MODE_SST (1 << 13) /* Start/Stop Transmission Command */
demayer 0:6bf0743ece18 103
demayer 0:6bf0743ece18 104 /* DMA_INT_EN register bit defines */
demayer 0:6bf0743ece18 105 #define DMA_INT_EN_TIE (1 << 0) /* Transmit interrupt enable */
demayer 0:6bf0743ece18 106 #define DMA_INT_EN_TSE (1 << 1) /* Transmit stopped enable */
demayer 0:6bf0743ece18 107 #define DMA_INT_EN_TUE (1 << 2) /* Transmit buffer unavailable enable */
demayer 0:6bf0743ece18 108 #define DMA_INT_EN_TJE (1 << 3) /* Transmit jabber timeout enable */
demayer 0:6bf0743ece18 109 #define DMA_INT_EN_OVE (1 << 4) /* Overflow interrupt enable */
demayer 0:6bf0743ece18 110 #define DMA_INT_EN_UNE (1 << 5) /* Underflow interrupt enable */
demayer 0:6bf0743ece18 111 #define DMA_INT_EN_RIE (1 << 6) /* Receive interrupt enable */
demayer 0:6bf0743ece18 112 #define DMA_INT_EN_RUE (1 << 7) /* Receive buffer unavailable enable */
demayer 0:6bf0743ece18 113 #define DMA_INT_EN_RSE (1 << 8) /* Received stopped enable */
demayer 0:6bf0743ece18 114 #define DMA_INT_EN_RWE (1 << 9) /* Receive watchdog timeout enable */
demayer 0:6bf0743ece18 115 #define DMA_INT_EN_ETE (1 << 10) /* Early transmit interrupt enable */
demayer 0:6bf0743ece18 116 #define DMA_INT_EN_FBE (1 << 13) /* Fatal bus error enable */
demayer 0:6bf0743ece18 117 #define DMA_INT_EN_ERE (1 << 14) /* Early receive interrupt enable */
demayer 0:6bf0743ece18 118 #define DMA_INT_EN_AIE (1 << 15) /* Abnormal interrupt summary enable */
demayer 0:6bf0743ece18 119 #define DMA_INT_EN_NIE (1 << 16) /* Normal interrupt summary enable */
demayer 0:6bf0743ece18 120
demayer 0:6bf0743ece18 121
demayer 0:6bf0743ece18 122
demayer 0:6bf0743ece18 123 /* PHY Support Register */
demayer 0:6bf0743ece18 124 #define SUPP_SPEED 0x00004000 /* Reduced MII Logic Current Speed */
demayer 0:6bf0743ece18 125 //#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
demayer 0:6bf0743ece18 126 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
demayer 0:6bf0743ece18 127
demayer 0:6bf0743ece18 128 /* MII Management Command Register */
demayer 0:6bf0743ece18 129 #define MCMD_READ 0x00000001 /* MII Read */
demayer 0:6bf0743ece18 130 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
demayer 0:6bf0743ece18 131
demayer 0:6bf0743ece18 132 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
demayer 0:6bf0743ece18 133 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
demayer 0:6bf0743ece18 134
demayer 0:6bf0743ece18 135 /* MII Management Address Register */
demayer 0:6bf0743ece18 136 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
demayer 0:6bf0743ece18 137 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
demayer 0:6bf0743ece18 138
demayer 0:6bf0743ece18 139 /* MII Management Indicators Register */
demayer 0:6bf0743ece18 140 #define MIND_BUSY 0x00000001 /* MII is Busy */
demayer 0:6bf0743ece18 141 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
demayer 0:6bf0743ece18 142 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
demayer 0:6bf0743ece18 143 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
demayer 0:6bf0743ece18 144
demayer 0:6bf0743ece18 145 /* DP83848C PHY Registers */
demayer 0:6bf0743ece18 146 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
demayer 0:6bf0743ece18 147 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
demayer 0:6bf0743ece18 148 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
demayer 0:6bf0743ece18 149 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
demayer 0:6bf0743ece18 150 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
demayer 0:6bf0743ece18 151 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
demayer 0:6bf0743ece18 152 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
demayer 0:6bf0743ece18 153 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
demayer 0:6bf0743ece18 154
demayer 0:6bf0743ece18 155 /* PHY Extended Registers */
demayer 0:6bf0743ece18 156 #define PHY_REG_STS 0x10 /* Status Register */
demayer 0:6bf0743ece18 157 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
demayer 0:6bf0743ece18 158 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
demayer 0:6bf0743ece18 159 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
demayer 0:6bf0743ece18 160 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
demayer 0:6bf0743ece18 161 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
demayer 0:6bf0743ece18 162 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
demayer 0:6bf0743ece18 163 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
demayer 0:6bf0743ece18 164 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
demayer 0:6bf0743ece18 165 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
demayer 0:6bf0743ece18 166 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
demayer 0:6bf0743ece18 167 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
demayer 0:6bf0743ece18 168
demayer 0:6bf0743ece18 169 #define PHY_REG_SCSR 0x1F /* PHY Special Control/Status Register */
demayer 0:6bf0743ece18 170
demayer 0:6bf0743ece18 171 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
demayer 0:6bf0743ece18 172 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
demayer 0:6bf0743ece18 173 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
demayer 0:6bf0743ece18 174 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
demayer 0:6bf0743ece18 175 #define PHY_AUTO_NEG 0x1000 /* Select Auto Negotiation */
demayer 0:6bf0743ece18 176
demayer 0:6bf0743ece18 177 #define DP83848C_DEF_ADR 0x01 /* Default PHY device address */
demayer 0:6bf0743ece18 178 #define DP83848C_ID 0x20005C90 /* PHY Identifier - DP83848C */
demayer 0:6bf0743ece18 179
demayer 0:6bf0743ece18 180 #define LAN8720_ID 0x0007C0F0 /* PHY Identifier - LAN8720 */
demayer 0:6bf0743ece18 181
demayer 0:6bf0743ece18 182 #define PHY_STS_LINK 0x0001 /* PHY Status Link Mask */
demayer 0:6bf0743ece18 183 #define PHY_STS_SPEED 0x0002 /* PHY Status Speed Mask */
demayer 0:6bf0743ece18 184 #define PHY_STS_DUPLEX 0x0004 /* PHY Status Duplex Mask */
demayer 0:6bf0743ece18 185
demayer 0:6bf0743ece18 186 #define PHY_BMCR_RESET 0x8000 /* PHY Reset */
demayer 0:6bf0743ece18 187
demayer 0:6bf0743ece18 188 #define PHY_BMSR_LINK 0x0004 /* PHY BMSR Link valid */
demayer 0:6bf0743ece18 189
demayer 0:6bf0743ece18 190 #define PHY_SCSR_100MBIT 0x0008 /* Speed: 1=100 MBit, 0=10Mbit */
demayer 0:6bf0743ece18 191 #define PHY_SCSR_DUPLEX 0x0010 /* PHY Duplex Mask */
demayer 0:6bf0743ece18 192
demayer 0:6bf0743ece18 193 static int phy_read(unsigned int PhyReg);
demayer 0:6bf0743ece18 194 static int phy_write(unsigned int PhyReg, unsigned short Data);
demayer 0:6bf0743ece18 195
demayer 0:6bf0743ece18 196 static void txdscr_init(void);
demayer 0:6bf0743ece18 197 static void rxdscr_init(void);
demayer 0:6bf0743ece18 198
demayer 0:6bf0743ece18 199 #if defined (__ICCARM__)
demayer 0:6bf0743ece18 200 # define AHBSRAM1
demayer 0:6bf0743ece18 201 #elif defined(TOOLCHAIN_GCC_CR)
demayer 0:6bf0743ece18 202 # define AHBSRAM1 __attribute__((section(".data.$RamPeriph32")))
demayer 0:6bf0743ece18 203 #else
demayer 0:6bf0743ece18 204 # define AHBSRAM1 __attribute__((section("AHBSRAM1"),aligned))
demayer 0:6bf0743ece18 205 #endif
demayer 0:6bf0743ece18 206
demayer 0:6bf0743ece18 207 AHBSRAM1 volatile uint8_t rxbuf[NUM_RX_FRAG][ETH_FRAG_SIZE];
demayer 0:6bf0743ece18 208 AHBSRAM1 volatile uint8_t txbuf[NUM_TX_FRAG][ETH_FRAG_SIZE];
demayer 0:6bf0743ece18 209 AHBSRAM1 volatile RX_DESC_TypeDef rxdesc[NUM_RX_FRAG];
demayer 0:6bf0743ece18 210 AHBSRAM1 volatile TX_DESC_TypeDef txdesc[NUM_TX_FRAG];
demayer 0:6bf0743ece18 211
demayer 0:6bf0743ece18 212 #ifndef min
demayer 0:6bf0743ece18 213 #define min(x, y) (((x)<(y))?(x):(y))
demayer 0:6bf0743ece18 214 #endif
demayer 0:6bf0743ece18 215
demayer 0:6bf0743ece18 216 static uint32_t phy_id = 0;
demayer 0:6bf0743ece18 217 static uint32_t TxDescIndex = 0;
demayer 0:6bf0743ece18 218 static uint32_t RxDescIndex = 0;
demayer 0:6bf0743ece18 219 static uint32_t RxOffset = 0;
demayer 0:6bf0743ece18 220
demayer 0:6bf0743ece18 221 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 222 Ethernet Device initialize
demayer 0:6bf0743ece18 223 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 224 int ethernet_init()
demayer 0:6bf0743ece18 225 {
demayer 0:6bf0743ece18 226 int regv, tout;
demayer 0:6bf0743ece18 227 char mac[ETHERNET_ADDR_SIZE];
demayer 0:6bf0743ece18 228
demayer 0:6bf0743ece18 229 pin_function(PC_0, (SCU_MODE_INACT | FUNC3)); /* Enable ENET RX CLK */
demayer 0:6bf0743ece18 230 pin_function(P1_19, (SCU_MODE_INACT | FUNC0)); /* Enable ENET TX CLK */
demayer 0:6bf0743ece18 231
demayer 0:6bf0743ece18 232 /* Ethernet pinmuxing */
demayer 0:6bf0743ece18 233 pin_function(P2_0, SCU_PINIO_FAST | FUNC7); /* ENET_MDC */
demayer 0:6bf0743ece18 234 pin_function(P1_17, SCU_PINIO_FAST | FUNC3); /* ENET_MDIO */
demayer 0:6bf0743ece18 235 pin_function(P1_18, SCU_PINIO_FAST | FUNC3); /* ENET_TXD0 */
demayer 0:6bf0743ece18 236 pin_function(P1_20, SCU_PINIO_FAST | FUNC3); /* ENET_TXD1 */
demayer 0:6bf0743ece18 237 pin_function(P1_19, SCU_PINIO_FAST | FUNC0); /* ENET_REF */
demayer 0:6bf0743ece18 238 pin_function(P0_1, SCU_PINIO_FAST | FUNC6); /* ENET_TX_EN */
demayer 0:6bf0743ece18 239 pin_function(P1_15, SCU_PINIO_FAST | FUNC3); /* ENET_RXD0 */
demayer 0:6bf0743ece18 240 pin_function(P0_0, SCU_PINIO_FAST | FUNC2); /* ENET_RXD1 */
demayer 0:6bf0743ece18 241 pin_function(P1_16, SCU_PINIO_FAST | FUNC3); /* ENET_CRS */
demayer 0:6bf0743ece18 242 pin_function(PC_9, SCU_PINIO_FAST | FUNC3); /* ENET_RX_ER */
demayer 0:6bf0743ece18 243 pin_function(P1_16, SCU_PINIO_FAST | FUNC7); /* ENET_RXDV */
demayer 0:6bf0743ece18 244
demayer 0:6bf0743ece18 245 LPC_CREG->CREG6 |= RMII_SELECT;
demayer 0:6bf0743ece18 246
demayer 0:6bf0743ece18 247 /* perform RGU soft reset */
demayer 0:6bf0743ece18 248 LPC_RGU->RESET_CTRL0 = 1 << 22;
demayer 0:6bf0743ece18 249 LPC_RGU->RESET_CTRL0 = 0;
demayer 0:6bf0743ece18 250
demayer 0:6bf0743ece18 251 /* Wait until reset is performed */
demayer 0:6bf0743ece18 252 while(1) {
demayer 0:6bf0743ece18 253 if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1 << 22))
demayer 0:6bf0743ece18 254 break;
demayer 0:6bf0743ece18 255 }
demayer 0:6bf0743ece18 256
demayer 0:6bf0743ece18 257 /* Reset MAC DMA Controller */
demayer 0:6bf0743ece18 258 LPC_ETHERNET->DMA_BUS_MODE |= 0x01;
demayer 0:6bf0743ece18 259 while(LPC_ETHERNET->DMA_BUS_MODE & 0x01);
demayer 0:6bf0743ece18 260
demayer 0:6bf0743ece18 261 phy_write(PHY_REG_BMCR, PHY_BMCR_RESET); /* perform PHY reset */
demayer 0:6bf0743ece18 262
demayer 0:6bf0743ece18 263 for(tout = 0x20000; ; tout--) { /* Wait for hardware reset to end. */
demayer 0:6bf0743ece18 264 regv = phy_read(PHY_REG_BMCR);
demayer 0:6bf0743ece18 265 if(regv < 0 || tout == 0) {
demayer 0:6bf0743ece18 266 return -1; /* Error */
demayer 0:6bf0743ece18 267 }
demayer 0:6bf0743ece18 268 if(!(regv & PHY_BMCR_RESET)) {
demayer 0:6bf0743ece18 269 break; /* Reset complete. */
demayer 0:6bf0743ece18 270 }
demayer 0:6bf0743ece18 271 }
demayer 0:6bf0743ece18 272
demayer 0:6bf0743ece18 273 phy_id = (phy_read(PHY_REG_IDR1) << 16);
demayer 0:6bf0743ece18 274 phy_id |= (phy_read(PHY_REG_IDR2) & 0XFFF0);
demayer 0:6bf0743ece18 275
demayer 0:6bf0743ece18 276 if (phy_id != DP83848C_ID && phy_id != LAN8720_ID) {
demayer 0:6bf0743ece18 277 error("Unknown Ethernet PHY (%x)", (unsigned int)phy_id);
demayer 0:6bf0743ece18 278 }
demayer 0:6bf0743ece18 279
demayer 0:6bf0743ece18 280 ethernet_set_link(-1, 0);
demayer 0:6bf0743ece18 281
demayer 0:6bf0743ece18 282 /* Set the Ethernet MAC Address registers */
demayer 0:6bf0743ece18 283 ethernet_address(mac);
demayer 0:6bf0743ece18 284 LPC_ETHERNET->MAC_ADDR0_HIGH = (mac[5] << 8) | mac[4];
demayer 0:6bf0743ece18 285 LPC_ETHERNET->MAC_ADDR0_LOW = (mac[3] << 24) | (mac[2] << 16) | (mac[1] << 8) | mac[0];
demayer 0:6bf0743ece18 286
demayer 0:6bf0743ece18 287 txdscr_init(); /* initialize DMA TX Descriptor */
demayer 0:6bf0743ece18 288 rxdscr_init(); /* initialize DMA RX Descriptor */
demayer 0:6bf0743ece18 289
demayer 0:6bf0743ece18 290 /* Configure Filter */
demayer 0:6bf0743ece18 291 LPC_ETHERNET->MAC_FRAME_FILTER = MAC_FRAME_FILTER_PR | MAC_FRAME_FILTER_RA;
demayer 0:6bf0743ece18 292
demayer 0:6bf0743ece18 293 /* Enable Receiver and Transmitter */
demayer 0:6bf0743ece18 294 LPC_ETHERNET->MAC_CONFIG |= (MAC_CONFIG_RE | MAC_CONFIG_TE);
demayer 0:6bf0743ece18 295
demayer 0:6bf0743ece18 296 //LPC_ETHERNET->DMA_INT_EN = DMA_INT_EN_NIE | DMA_INT_EN_RIE | DMA_INT_EN_TJE; /* Enable EMAC interrupts. */
demayer 0:6bf0743ece18 297
demayer 0:6bf0743ece18 298 /* Start Transmission & Receive processes */
demayer 0:6bf0743ece18 299 LPC_ETHERNET->DMA_OP_MODE |= (DMA_OP_MODE_SST | DMA_OP_MODE_SSR);
demayer 0:6bf0743ece18 300
demayer 0:6bf0743ece18 301 return 0;
demayer 0:6bf0743ece18 302 }
demayer 0:6bf0743ece18 303
demayer 0:6bf0743ece18 304 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 305 Ethernet Device Uninitialize
demayer 0:6bf0743ece18 306 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 307 void ethernet_free()
demayer 0:6bf0743ece18 308 {
demayer 0:6bf0743ece18 309 }
demayer 0:6bf0743ece18 310
demayer 0:6bf0743ece18 311 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 312 Ethernet write
demayer 0:6bf0743ece18 313 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 314 int ethernet_write(const char *data, int slen)
demayer 0:6bf0743ece18 315 {
demayer 0:6bf0743ece18 316 if (slen > ETH_FRAG_SIZE)
demayer 0:6bf0743ece18 317 return -1;
demayer 0:6bf0743ece18 318
demayer 0:6bf0743ece18 319 txdesc[TxDescIndex].Ctrl = slen;
demayer 0:6bf0743ece18 320 memcpy((void *)txdesc[TxDescIndex].BufAddr1, data, slen);
demayer 0:6bf0743ece18 321 return slen;
demayer 0:6bf0743ece18 322 }
demayer 0:6bf0743ece18 323
demayer 0:6bf0743ece18 324 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 325 Ethernet Send
demayer 0:6bf0743ece18 326 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 327 int ethernet_send()
demayer 0:6bf0743ece18 328 {
demayer 0:6bf0743ece18 329 int s = txdesc[TxDescIndex].Ctrl;
demayer 0:6bf0743ece18 330 txdesc[TxDescIndex].Status |= TRDES_OWN_BIT;
demayer 0:6bf0743ece18 331 LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode
demayer 0:6bf0743ece18 332 TxDescIndex++;
demayer 0:6bf0743ece18 333 if (TxDescIndex == NUM_TX_FRAG)
demayer 0:6bf0743ece18 334 TxDescIndex = 0;
demayer 0:6bf0743ece18 335
demayer 0:6bf0743ece18 336 return s;
demayer 0:6bf0743ece18 337 }
demayer 0:6bf0743ece18 338
demayer 0:6bf0743ece18 339 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 340 Ethernet receive
demayer 0:6bf0743ece18 341 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 342 int ethernet_receive()
demayer 0:6bf0743ece18 343 {
demayer 0:6bf0743ece18 344 int i, slen = 0;
demayer 0:6bf0743ece18 345 for (i = RxDescIndex;; i++) {
demayer 0:6bf0743ece18 346 if (rxdesc[i].Status & TRDES_OWN_BIT)
demayer 0:6bf0743ece18 347 return (slen - RxOffset);
demayer 0:6bf0743ece18 348 else
demayer 0:6bf0743ece18 349 slen += (rxdesc[i].Status >> 16) & 0x03FFF;
demayer 0:6bf0743ece18 350 }
demayer 0:6bf0743ece18 351 return 0;
demayer 0:6bf0743ece18 352 }
demayer 0:6bf0743ece18 353
demayer 0:6bf0743ece18 354
demayer 0:6bf0743ece18 355 /*----------------------------------------------------------------------------
demayer 0:6bf0743ece18 356 Ethernet read
demayer 0:6bf0743ece18 357 *----------------------------------------------------------------------------*/
demayer 0:6bf0743ece18 358 int ethernet_read(char *data, int dlen)
demayer 0:6bf0743ece18 359 {
demayer 0:6bf0743ece18 360 int copylen;
demayer 0:6bf0743ece18 361 uint32_t *pSrc = (uint32_t *)rxdesc[RxDescIndex].BufAddr1;
demayer 0:6bf0743ece18 362 copylen = (rxdesc[RxDescIndex].Status >> 16) & 0x03FFF;
demayer 0:6bf0743ece18 363 if (rxdesc[RxDescIndex].Status & TRDES_OWN_BIT || (dlen + RxOffset) > copylen)
demayer 0:6bf0743ece18 364 return -1;
demayer 0:6bf0743ece18 365
demayer 0:6bf0743ece18 366 if ((dlen + RxOffset) == copylen) {
demayer 0:6bf0743ece18 367 memcpy(&pSrc[RxOffset], data, copylen);
demayer 0:6bf0743ece18 368 rxdesc[RxDescIndex].Status = TRDES_OWN_BIT;
demayer 0:6bf0743ece18 369 RxDescIndex++;
demayer 0:6bf0743ece18 370 RxOffset = 0;
demayer 0:6bf0743ece18 371 if (RxDescIndex == NUM_RX_FRAG)
demayer 0:6bf0743ece18 372 RxDescIndex = 0;
demayer 0:6bf0743ece18 373 } else if ((dlen + RxOffset) < copylen) {
demayer 0:6bf0743ece18 374 copylen = dlen;
demayer 0:6bf0743ece18 375 memcpy(&pSrc[RxOffset], data, copylen);
demayer 0:6bf0743ece18 376 RxOffset += dlen;
demayer 0:6bf0743ece18 377 }
demayer 0:6bf0743ece18 378 return copylen;
demayer 0:6bf0743ece18 379 }
demayer 0:6bf0743ece18 380
demayer 0:6bf0743ece18 381 int ethernet_link(void)
demayer 0:6bf0743ece18 382 {
demayer 0:6bf0743ece18 383
demayer 0:6bf0743ece18 384 if (phy_id == DP83848C_ID) {
demayer 0:6bf0743ece18 385 return (phy_read(PHY_REG_STS) & PHY_STS_LINK);
demayer 0:6bf0743ece18 386 } else { // LAN8720_ID
demayer 0:6bf0743ece18 387 return (phy_read(PHY_REG_BMSR) & PHY_BMSR_LINK);
demayer 0:6bf0743ece18 388 }
demayer 0:6bf0743ece18 389 }
demayer 0:6bf0743ece18 390
demayer 0:6bf0743ece18 391 static int phy_write(unsigned int PhyReg, unsigned short Data)
demayer 0:6bf0743ece18 392 {
demayer 0:6bf0743ece18 393 unsigned int timeOut;
demayer 0:6bf0743ece18 394
demayer 0:6bf0743ece18 395 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
demayer 0:6bf0743ece18 396 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_WRITE;
demayer 0:6bf0743ece18 397 LPC_ETHERNET->MAC_MII_DATA = Data;
demayer 0:6bf0743ece18 398 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY; // Start PHY Write Cycle
demayer 0:6bf0743ece18 399
demayer 0:6bf0743ece18 400 /* Wait utill operation completed */
demayer 0:6bf0743ece18 401 for (timeOut = 0; timeOut < MII_WR_TOUT; timeOut++) {
demayer 0:6bf0743ece18 402 if ((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
demayer 0:6bf0743ece18 403 break;
demayer 0:6bf0743ece18 404 }
demayer 0:6bf0743ece18 405 }
demayer 0:6bf0743ece18 406
demayer 0:6bf0743ece18 407 return -1;
demayer 0:6bf0743ece18 408 }
demayer 0:6bf0743ece18 409
demayer 0:6bf0743ece18 410 static int phy_read(unsigned int PhyReg)
demayer 0:6bf0743ece18 411 {
demayer 0:6bf0743ece18 412 unsigned int timeOut;
demayer 0:6bf0743ece18 413
demayer 0:6bf0743ece18 414 while(LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY);
demayer 0:6bf0743ece18 415 LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | MII_READ;
demayer 0:6bf0743ece18 416 LPC_ETHERNET->MAC_MII_ADDR |= MIND_BUSY;
demayer 0:6bf0743ece18 417
demayer 0:6bf0743ece18 418 for(timeOut = 0; timeOut < MII_RD_TOUT; timeOut++) { /* Wait until operation completed */
demayer 0:6bf0743ece18 419 if((LPC_ETHERNET->MAC_MII_ADDR & MIND_BUSY) == 0) {
demayer 0:6bf0743ece18 420 return LPC_ETHERNET->MAC_MII_DATA; /* Return a 16-bit value. */
demayer 0:6bf0743ece18 421 }
demayer 0:6bf0743ece18 422 }
demayer 0:6bf0743ece18 423
demayer 0:6bf0743ece18 424 return -1;
demayer 0:6bf0743ece18 425 }
demayer 0:6bf0743ece18 426
demayer 0:6bf0743ece18 427 static void txdscr_init()
demayer 0:6bf0743ece18 428 {
demayer 0:6bf0743ece18 429 int i;
demayer 0:6bf0743ece18 430
demayer 0:6bf0743ece18 431 for(i = 0; i < NUM_TX_FRAG; i++) {
demayer 0:6bf0743ece18 432 txdesc[i].Status = TX_LAST_SEGM | TX_FIRST_SEGM;;
demayer 0:6bf0743ece18 433 txdesc[i].Ctrl = 0;
demayer 0:6bf0743ece18 434 txdesc[i].BufAddr1 = (uint32_t)&txbuf[i];
demayer 0:6bf0743ece18 435 if (i == (NUM_TX_FRAG - 1)) {
demayer 0:6bf0743ece18 436 txdesc[i].Status |= TX_END_RING;
demayer 0:6bf0743ece18 437 }
demayer 0:6bf0743ece18 438 }
demayer 0:6bf0743ece18 439
demayer 0:6bf0743ece18 440 LPC_ETHERNET->DMA_TRANS_DES_ADDR = (uint32_t)txdesc; /* Set EMAC Transmit Descriptor Registers. */
demayer 0:6bf0743ece18 441 }
demayer 0:6bf0743ece18 442
demayer 0:6bf0743ece18 443
demayer 0:6bf0743ece18 444 static void rxdscr_init()
demayer 0:6bf0743ece18 445 {
demayer 0:6bf0743ece18 446 int i;
demayer 0:6bf0743ece18 447
demayer 0:6bf0743ece18 448 for(i = 0; i < NUM_RX_FRAG; i++) {
demayer 0:6bf0743ece18 449 rxdesc[i].Status = TRDES_OWN_BIT;
demayer 0:6bf0743ece18 450 rxdesc[i].Ctrl = ETH_FRAG_SIZE;
demayer 0:6bf0743ece18 451 rxdesc[i].BufAddr1 = (uint32_t)&rxbuf[i];
demayer 0:6bf0743ece18 452 if (i == (NUM_RX_FRAG - 1)) {
demayer 0:6bf0743ece18 453 rxdesc[i].Ctrl |= RX_END_RING;
demayer 0:6bf0743ece18 454 }
demayer 0:6bf0743ece18 455 }
demayer 0:6bf0743ece18 456
demayer 0:6bf0743ece18 457 LPC_ETHERNET->DMA_REC_DES_ADDR = (uint32_t)rxdesc; /* Set EMAC Receive Descriptor Registers. */
demayer 0:6bf0743ece18 458 }
demayer 0:6bf0743ece18 459
demayer 0:6bf0743ece18 460 void ethernet_address(char *mac)
demayer 0:6bf0743ece18 461 {
demayer 0:6bf0743ece18 462 mbed_mac_address(mac);
demayer 0:6bf0743ece18 463 }
demayer 0:6bf0743ece18 464
demayer 0:6bf0743ece18 465 void ethernet_set_link(int speed, int duplex)
demayer 0:6bf0743ece18 466 {
demayer 0:6bf0743ece18 467 volatile unsigned short phy_data;
demayer 0:6bf0743ece18 468 int tout;
demayer 0:6bf0743ece18 469
demayer 0:6bf0743ece18 470 if((speed < 0) || (speed > 1)) {
demayer 0:6bf0743ece18 471
demayer 0:6bf0743ece18 472 phy_data = PHY_AUTO_NEG;
demayer 0:6bf0743ece18 473
demayer 0:6bf0743ece18 474 } else {
demayer 0:6bf0743ece18 475
demayer 0:6bf0743ece18 476 phy_data = (((unsigned short) speed << 13) |
demayer 0:6bf0743ece18 477 ((unsigned short) duplex << 8));
demayer 0:6bf0743ece18 478 }
demayer 0:6bf0743ece18 479
demayer 0:6bf0743ece18 480 phy_write(PHY_REG_BMCR, phy_data);
demayer 0:6bf0743ece18 481
demayer 0:6bf0743ece18 482 for(tout = 100; tout; tout--) {
demayer 0:6bf0743ece18 483 __NOP(); /* A short delay */
demayer 0:6bf0743ece18 484 }
demayer 0:6bf0743ece18 485
demayer 0:6bf0743ece18 486 switch(phy_id) {
demayer 0:6bf0743ece18 487 case DP83848C_ID:
demayer 0:6bf0743ece18 488
demayer 0:6bf0743ece18 489 phy_data = phy_read(PHY_REG_STS);
demayer 0:6bf0743ece18 490
demayer 0:6bf0743ece18 491 if(phy_data & PHY_STS_DUPLEX) {
demayer 0:6bf0743ece18 492 /* Full duplex is enabled. */
demayer 0:6bf0743ece18 493 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
demayer 0:6bf0743ece18 494 } else {
demayer 0:6bf0743ece18 495 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
demayer 0:6bf0743ece18 496 }
demayer 0:6bf0743ece18 497
demayer 0:6bf0743ece18 498 if(phy_data & PHY_STS_SPEED) {
demayer 0:6bf0743ece18 499 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
demayer 0:6bf0743ece18 500 } else {
demayer 0:6bf0743ece18 501 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
demayer 0:6bf0743ece18 502 }
demayer 0:6bf0743ece18 503 break;
demayer 0:6bf0743ece18 504
demayer 0:6bf0743ece18 505 case LAN8720_ID:
demayer 0:6bf0743ece18 506
demayer 0:6bf0743ece18 507 for(tout = 100; tout; tout--) {
demayer 0:6bf0743ece18 508 phy_data = phy_read(PHY_REG_BMSR);
demayer 0:6bf0743ece18 509 if (phy_data & PHY_STS_DUPLEX)
demayer 0:6bf0743ece18 510 break;
demayer 0:6bf0743ece18 511 }
demayer 0:6bf0743ece18 512
demayer 0:6bf0743ece18 513 if (phy_data & PHY_STS_DUPLEX) {
demayer 0:6bf0743ece18 514 /* Full duplex is enabled. */
demayer 0:6bf0743ece18 515 LPC_ETHERNET->MAC_CONFIG |= MAC_DUPLEX_MODE;
demayer 0:6bf0743ece18 516 } else {
demayer 0:6bf0743ece18 517 LPC_ETHERNET->MAC_CONFIG &= ~MAC_DUPLEX_MODE;
demayer 0:6bf0743ece18 518 }
demayer 0:6bf0743ece18 519
demayer 0:6bf0743ece18 520 if(phy_data & PHY_STS_SPEED) {
demayer 0:6bf0743ece18 521 LPC_ETHERNET->MAC_CONFIG &= ~SUPP_SPEED;
demayer 0:6bf0743ece18 522 } else {
demayer 0:6bf0743ece18 523 LPC_ETHERNET->MAC_CONFIG |= SUPP_SPEED;
demayer 0:6bf0743ece18 524 }
demayer 0:6bf0743ece18 525 break;
demayer 0:6bf0743ece18 526 }
demayer 0:6bf0743ece18 527 }
demayer 0:6bf0743ece18 528