David Rimer
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RadioHead-148
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radio_config_Si4460.h
00001 /*! @file radio_config.h 00002 * @brief This file contains the automatically generated 00003 * configurations. 00004 * 00005 * @n WDS GUI Version: 3.2.6.0 00006 * @n Device: Si4460 Rev.: B1 00007 * 00008 * @b COPYRIGHT 00009 * @n Silicon Laboratories Confidential 00010 * @n Copyright 2013 Silicon Laboratories, Inc. 00011 * @n http://www.silabs.com 00012 */ 00013 00014 #ifndef RADIO_CONFIG_H_ 00015 #define RADIO_CONFIG_H_ 00016 00017 // USER DEFINED PARAMETERS 00018 // Define your own parameters here 00019 00020 // INPUT DATA 00021 /* 00022 // Crys_freq(Hz): 30000000 Crys_tol(ppm): 20 IF_mode: 2 High_perf_Ch_Fil: 1 OSRtune: 0 Ch_Fil_Bw_AFC: 0 ANT_DIV: 0 PM_pattern: 0 00023 // MOD_type: 3 Rsymb(sps): 50000 Fdev(Hz): 100000 RXBW(Hz): 150000 Manchester: 0 AFC_en: 0 Rsymb_error: 0.0 Chip-Version: 2 00024 // RF Freq.(MHz): 434 API_TC: 31 fhst: 250000 inputBW: 0 BERT: 0 RAW_dout: 0 D_source: 0 Hi_pfm_div: 1 00025 // 00026 // # WB filter 2 (BW = 274.83 kHz); NB-filter 2 (BW = 274.83 kHz) 00027 00028 // 00029 // Modulation index: 4 00030 */ 00031 00032 00033 // CONFIGURATION PARAMETERS 00034 #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ {30000000L} 00035 #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER {0x00} 00036 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH {0x07} 00037 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP {0x03} 00038 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET {0xF000} 00039 #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD {0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5} 00040 00041 00042 // CONFIGURATION COMMANDS 00043 00044 /* 00045 // Command: RF_POWER_UP 00046 // Description: Command to power-up the device and select the operational mode and functionality. 00047 */ 00048 #define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0xC9, 0xC3, 0x80 00049 00050 /* 00051 // Command: RF_GPIO_PIN_CFG 00052 // Description: Configures the GPIO pins. 00053 */ 00054 #define RF_GPIO_PIN_CFG 0x13, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 00055 00056 /* 00057 // Set properties: RF_GLOBAL_XO_TUNE_1 00058 // Number of properties: 1 00059 // Group ID: 0x00 00060 // Start ID: 0x00 00061 // Default values: 0x40, 00062 // Descriptions: 00063 // GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator. 00064 */ 00065 #define RF_GLOBAL_XO_TUNE_1 0x11, 0x00, 0x01, 0x00, 0x52 00066 00067 /* 00068 // Set properties: RF_GLOBAL_CONFIG_1 00069 // Number of properties: 1 00070 // Group ID: 0x00 00071 // Start ID: 0x03 00072 // Default values: 0x20, 00073 // Descriptions: 00074 // GLOBAL_CONFIG - Global configuration settings. 00075 */ 00076 #define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60 00077 00078 /* 00079 // Set properties: RF_INT_CTL_ENABLE_2 00080 // Number of properties: 2 00081 // Group ID: 0x01 00082 // Start ID: 0x00 00083 // Default values: 0x04, 0x00, 00084 // Descriptions: 00085 // INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin. 00086 // INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin. 00087 */ 00088 #define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x38 00089 00090 /* 00091 // Set properties: RF_FRR_CTL_A_MODE_4 00092 // Number of properties: 4 00093 // Group ID: 0x02 00094 // Start ID: 0x00 00095 // Default values: 0x01, 0x02, 0x09, 0x00, 00096 // Descriptions: 00097 // FRR_CTL_A_MODE - Fast Response Register A Configuration. 00098 // FRR_CTL_B_MODE - Fast Response Register B Configuration. 00099 // FRR_CTL_C_MODE - Fast Response Register C Configuration. 00100 // FRR_CTL_D_MODE - Fast Response Register D Configuration. 00101 */ 00102 #define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00 00103 00104 /* 00105 // Set properties: RF_PREAMBLE_TX_LENGTH_9 00106 // Number of properties: 9 00107 // Group ID: 0x10 00108 // Start ID: 0x00 00109 // Default values: 0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 00110 // Descriptions: 00111 // PREAMBLE_TX_LENGTH - Configure length of TX Preamble. 00112 // PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern. 00113 // PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern. 00114 // PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern. 00115 // PREAMBLE_CONFIG - General configuration bits for the Preamble field. 00116 // PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern. 00117 // PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern. 00118 // PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern. 00119 // PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern. 00120 */ 00121 #define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00 00122 00123 /* 00124 // Set properties: RF_SYNC_CONFIG_5 00125 // Number of properties: 5 00126 // Group ID: 0x11 00127 // Start ID: 0x00 00128 // Default values: 0x01, 0x2D, 0xD4, 0x2D, 0xD4, 00129 // Descriptions: 00130 // SYNC_CONFIG - Sync Word configuration bits. 00131 // SYNC_BITS_31_24 - Sync word. 00132 // SYNC_BITS_23_16 - Sync word. 00133 // SYNC_BITS_15_8 - Sync word. 00134 // SYNC_BITS_7_0 - Sync word. 00135 */ 00136 #define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00 00137 00138 /* 00139 // Set properties: RF_PKT_CRC_CONFIG_1 00140 // Number of properties: 1 00141 // Group ID: 0x12 00142 // Start ID: 0x00 00143 // Default values: 0x00, 00144 // Descriptions: 00145 // PKT_CRC_CONFIG - Select a CRC polynomial and seed. 00146 */ 00147 #define RF_PKT_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x00, 0x80 00148 00149 /* 00150 // Set properties: RF_PKT_WHT_SEED_15_8_4 00151 // Number of properties: 4 00152 // Group ID: 0x12 00153 // Start ID: 0x03 00154 // Default values: 0xFF, 0xFF, 0x00, 0x00, 00155 // Descriptions: 00156 // PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening) 00157 // PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening) 00158 // PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling. 00159 // PKT_CONFIG1 - General configuration bits for transmission or reception of a packet. 00160 */ 00161 #define RF_PKT_WHT_SEED_15_8_4 0x11, 0x12, 0x04, 0x03, 0xFF, 0xFF, 0x00, 0x02 00162 00163 /* 00164 // Set properties: RF_PKT_LEN_12 00165 // Number of properties: 12 00166 // Group ID: 0x12 00167 // Start ID: 0x08 00168 // Default values: 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 00169 // Descriptions: 00170 // PKT_LEN - Configuration bits for reception of a variable length packet. 00171 // PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s). 00172 // PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length). 00173 // PKT_TX_THRESHOLD - TX FIFO almost empty threshold. 00174 // PKT_RX_THRESHOLD - RX FIFO Almost Full threshold. 00175 // PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value. 00176 // PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value. 00177 // PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1. 00178 // PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1. 00179 // PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value. 00180 // PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value. 00181 // PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2. 00182 */ 00183 #define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00 00184 00185 /* 00186 // Set properties: RF_PKT_FIELD_2_CRC_CONFIG_12 00187 // Number of properties: 12 00188 // Group ID: 0x12 00189 // Start ID: 0x14 00190 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 00191 // Descriptions: 00192 // PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2. 00193 // PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value. 00194 // PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value. 00195 // PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3. 00196 // PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3. 00197 // PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value. 00198 // PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value. 00199 // PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4. 00200 // PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4. 00201 // PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value. 00202 // PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value. 00203 // PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5. 00204 */ 00205 #define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 00206 00207 /* 00208 // Set properties: RF_PKT_FIELD_5_CRC_CONFIG_1 00209 // Number of properties: 1 00210 // Group ID: 0x12 00211 // Start ID: 0x20 00212 // Default values: 0x00, 00213 // Descriptions: 00214 // PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5. 00215 */ 00216 #define RF_PKT_FIELD_5_CRC_CONFIG_1 0x11, 0x12, 0x01, 0x20, 0x00 00217 00218 /* 00219 // Set properties: RF_MODEM_MOD_TYPE_12 00220 // Number of properties: 12 00221 // Group ID: 0x20 00222 // Start ID: 0x00 00223 // Default values: 0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 00224 // Descriptions: 00225 // MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation. 00226 // MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits. 00227 // MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer. 00228 // MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate 00229 // MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate 00230 // MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate 00231 // MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. 00232 // MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. 00233 // MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. 00234 // MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus. 00235 // MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word. 00236 // MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word. 00237 */ 00238 #define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x0F, 0x42, 0x40, 0x09, 0xC9, 0xC3, 0x80, 0x00, 0x1B 00239 00240 /* 00241 // Set properties: RF_MODEM_FREQ_DEV_0_1 00242 // Number of properties: 1 00243 // Group ID: 0x20 00244 // Start ID: 0x0C 00245 // Default values: 0xD3, 00246 // Descriptions: 00247 // MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word. 00248 */ 00249 #define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x4F 00250 00251 /* 00252 // Set properties: RF_MODEM_TX_RAMP_DELAY_8 00253 // Number of properties: 8 00254 // Group ID: 0x20 00255 // Start ID: 0x18 00256 // Default values: 0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 00257 // Descriptions: 00258 // MODEM_TX_RAMP_DELAY - TX ramp-down delay setting. 00259 // MODEM_MDM_CTRL - MDM control. 00260 // MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation. 00261 // MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number). 00262 // MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number). 00263 // MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number). 00264 // MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter. 00265 // MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter. 00266 */ 00267 #define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x00, 0x10 00268 00269 /* 00270 // Set properties: RF_MODEM_BCR_OSR_1_9 00271 // Number of properties: 9 00272 // Group ID: 0x20 00273 // Start ID: 0x22 00274 // Default values: 0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 00275 // Descriptions: 00276 // MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number). 00277 // MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number). 00278 // MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number). 00279 // MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number). 00280 // MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number). 00281 // MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value. 00282 // MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value. 00283 // MODEM_BCR_GEAR - RX BCR loop gear control. 00284 // MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop. 00285 */ 00286 #define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x00, 0xC8, 0x02, 0x8F, 0x5C, 0x01, 0x48, 0x02, 0xC2 00287 00288 /* 00289 // Set properties: RF_MODEM_AFC_GEAR_7 00290 // Number of properties: 7 00291 // Group ID: 0x20 00292 // Start ID: 0x2C 00293 // Default values: 0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0, 00294 // Descriptions: 00295 // MODEM_AFC_GEAR - RX AFC loop gear control. 00296 // MODEM_AFC_WAIT - RX AFC loop wait time control. 00297 // MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. 00298 // MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality. 00299 // MODEM_AFC_LIMITER_1 - Set the AFC limiter value. 00300 // MODEM_AFC_LIMITER_0 - Set the AFC limiter value. 00301 // MODEM_AFC_MISC - Specifies miscellaneous AFC control bits. 00302 */ 00303 #define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x92, 0x0A, 0x46, 0x80 00304 00305 /* 00306 // Set properties: RF_MODEM_AGC_CONTROL_1 00307 // Number of properties: 1 00308 // Group ID: 0x20 00309 // Start ID: 0x35 00310 // Default values: 0xE0, 00311 // Descriptions: 00312 // MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain. 00313 */ 00314 #define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2 00315 00316 /* 00317 // Set properties: RF_MODEM_AGC_WINDOW_SIZE_9 00318 // Number of properties: 9 00319 // Group ID: 0x20 00320 // Start ID: 0x38 00321 // Default values: 0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 00322 // Descriptions: 00323 // MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm. 00324 // MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors. 00325 // MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors. 00326 // MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression. 00327 // MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression. 00328 // MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold. 00329 // MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold. 00330 // MODEM_FSK4_MAP - 4(G)FSK symbol mapping code. 00331 // MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector. 00332 */ 00333 #define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x2C, 0x2C, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x29 00334 00335 /* 00336 // Set properties: RF_MODEM_OOK_CNT1_11 00337 // Number of properties: 11 00338 // Group ID: 0x20 00339 // Start ID: 0x42 00340 // Default values: 0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 0xFF, 0x0C, 0x01, 00341 // Descriptions: 00342 // MODEM_OOK_CNT1 - OOK control. 00343 // MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator. 00344 // MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors. 00345 // MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode. 00346 // MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold. 00347 // MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold. 00348 // MODEM_ANT_DIV_MODE - Antenna diversity mode settings. 00349 // MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm. 00350 // MODEM_RSSI_THRESH - Configures the RSSI threshold. 00351 // MODEM_RSSI_JUMP_THRESH - Configures the RSSI Jump Detection threshold. 00352 // MODEM_RSSI_CONTROL - Control of the averaging modes and latching time for reporting RSSI value(s). 00353 */ 00354 #define RF_MODEM_OOK_CNT1_11 0x11, 0x20, 0x0B, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x01, 0x7F, 0x01, 0x80, 0xFF, 0x0C, 0x02 00355 00356 /* 00357 // Set properties: RF_MODEM_RSSI_COMP_1 00358 // Number of properties: 1 00359 // Group ID: 0x20 00360 // Start ID: 0x4E 00361 // Default values: 0x40, 00362 // Descriptions: 00363 // MODEM_RSSI_COMP - RSSI compensation value. 00364 */ 00365 #define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40 00366 00367 /* 00368 // Set properties: RF_MODEM_CLKGEN_BAND_1 00369 // Number of properties: 1 00370 // Group ID: 0x20 00371 // Start ID: 0x51 00372 // Default values: 0x08, 00373 // Descriptions: 00374 // MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band. 00375 */ 00376 #define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A 00377 00378 /* 00379 // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 00380 // Number of properties: 12 00381 // Group ID: 0x21 00382 // Start ID: 0x00 00383 // Default values: 0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 00384 // Descriptions: 00385 // MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients. 00386 // MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients. 00387 // MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients. 00388 // MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients. 00389 // MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients. 00390 // MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients. 00391 // MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients. 00392 // MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients. 00393 // MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients. 00394 // MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients. 00395 // MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients. 00396 // MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients. 00397 */ 00398 #define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C 00399 00400 /* 00401 // Set properties: RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 00402 // Number of properties: 12 00403 // Group ID: 0x21 00404 // Start ID: 0x0C 00405 // Default values: 0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 00406 // Descriptions: 00407 // MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients. 00408 // MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients. 00409 // MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients. 00410 // MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients. 00411 // MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients. 00412 // MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients. 00413 // MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients. 00414 // MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients. 00415 // MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients. 00416 // MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients. 00417 // MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients. 00418 // MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients. 00419 */ 00420 #define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5 00421 00422 /* 00423 // Set properties: RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 00424 // Number of properties: 12 00425 // Group ID: 0x21 00426 // Start ID: 0x18 00427 // Default values: 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 00428 // Descriptions: 00429 // MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients. 00430 // MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients. 00431 // MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients. 00432 // MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients. 00433 // MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients. 00434 // MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients. 00435 // MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients. 00436 // MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients. 00437 // MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients. 00438 // MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients. 00439 // MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients. 00440 // MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients. 00441 */ 00442 #define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00 00443 00444 /* 00445 // Set properties: RF_PA_MODE_4 00446 // Number of properties: 4 00447 // Group ID: 0x22 00448 // Start ID: 0x00 00449 // Default values: 0x08, 0x7F, 0x00, 0x5D, 00450 // Descriptions: 00451 // PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size). 00452 // PA_PWR_LVL - Configuration of PA output power level. 00453 // PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source. 00454 // PA_TC - Configuration of PA ramping parameters. 00455 */ 00456 #define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x18, 0x01, 0xC0, 0x3F 00457 00458 /* 00459 // Set properties: RF_SYNTH_PFDCP_CPFF_7 00460 // Number of properties: 7 00461 // Group ID: 0x23 00462 // Start ID: 0x00 00463 // Default values: 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 00464 // Descriptions: 00465 // SYNTH_PFDCP_CPFF - Feed forward charge pump current selection. 00466 // SYNTH_PFDCP_CPINT - Integration charge pump current selection. 00467 // SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path. 00468 // SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter. 00469 // SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter. 00470 // SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter. 00471 // SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter. 00472 */ 00473 #define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03 00474 00475 /* 00476 // Set properties: RF_MATCH_VALUE_1_12 00477 // Number of properties: 12 00478 // Group ID: 0x30 00479 // Start ID: 0x00 00480 // Default values: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 00481 // Descriptions: 00482 // MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte. 00483 // MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte. 00484 // MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1. 00485 // MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte. 00486 // MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte. 00487 // MATCH_CTRL_2 - Configuration of Match Byte 2. 00488 // MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte. 00489 // MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte. 00490 // MATCH_CTRL_3 - Configuration of Match Byte 3. 00491 // MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte. 00492 // MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte. 00493 // MATCH_CTRL_4 - Configuration of Match Byte 4. 00494 */ 00495 #define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 00496 00497 /* 00498 // Set properties: RF_FREQ_CONTROL_INTE_8 00499 // Number of properties: 8 00500 // Group ID: 0x40 00501 // Start ID: 0x00 00502 // Default values: 0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 00503 // Descriptions: 00504 // FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number. 00505 // FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number. 00506 // FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number. 00507 // FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number. 00508 // FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size. 00509 // FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size. 00510 // FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration. 00511 // FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode. 00512 */ 00513 #define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x38, 0x0E, 0xEE, 0xEE, 0x44, 0x44, 0x20, 0xFE 00514 00515 00516 // AUTOMATICALLY GENERATED CODE! 00517 // DO NOT EDIT/MODIFY BELOW THIS LINE! 00518 // -------------------------------------------- 00519 00520 #ifndef FIRMWARE_LOAD_COMPILE 00521 #define RADIO_CONFIGURATION_DATA_ARRAY { \ 00522 0x07, RF_POWER_UP, \ 00523 0x08, RF_GPIO_PIN_CFG, \ 00524 0x05, RF_GLOBAL_XO_TUNE_1, \ 00525 0x05, RF_GLOBAL_CONFIG_1, \ 00526 0x06, RF_INT_CTL_ENABLE_2, \ 00527 0x08, RF_FRR_CTL_A_MODE_4, \ 00528 0x0D, RF_PREAMBLE_TX_LENGTH_9, \ 00529 0x09, RF_SYNC_CONFIG_5, \ 00530 0x05, RF_PKT_CRC_CONFIG_1, \ 00531 0x08, RF_PKT_WHT_SEED_15_8_4, \ 00532 0x10, RF_PKT_LEN_12, \ 00533 0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \ 00534 0x05, RF_PKT_FIELD_5_CRC_CONFIG_1, \ 00535 0x10, RF_MODEM_MOD_TYPE_12, \ 00536 0x05, RF_MODEM_FREQ_DEV_0_1, \ 00537 0x0C, RF_MODEM_TX_RAMP_DELAY_8, \ 00538 0x0D, RF_MODEM_BCR_OSR_1_9, \ 00539 0x0B, RF_MODEM_AFC_GEAR_7, \ 00540 0x05, RF_MODEM_AGC_CONTROL_1, \ 00541 0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \ 00542 0x0F, RF_MODEM_OOK_CNT1_11, \ 00543 0x05, RF_MODEM_RSSI_COMP_1, \ 00544 0x05, RF_MODEM_CLKGEN_BAND_1, \ 00545 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \ 00546 0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \ 00547 0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \ 00548 0x08, RF_PA_MODE_4, \ 00549 0x0B, RF_SYNTH_PFDCP_CPFF_7, \ 00550 0x10, RF_MATCH_VALUE_1_12, \ 00551 0x0C, RF_FREQ_CONTROL_INTE_8, \ 00552 0x00 \ 00553 } 00554 #else 00555 #define RADIO_CONFIGURATION_DATA_ARRAY { 0 } 00556 #endif 00557 00558 // DEFAULT VALUES FOR CONFIGURATION PARAMETERS 00559 #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 30000000L 00560 #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 0x00 00561 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 0x10 00562 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 0x01 00563 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 0x1000 00564 #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT 0x42, 0x55, 0x54, 0x54, 0x4F, 0x4E, 0x31 // BUTTON1 00565 00566 #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED 0x00 00567 #define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE 0x00 00568 #define RADIO_CONFIGURATION_DATA_RADIO_PATCH { } 00569 00570 #ifndef RADIO_CONFIGURATION_DATA_ARRAY 00571 #error "This property must be defined!" 00572 #endif 00573 00574 #ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ 00575 #define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ { RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT } 00576 #endif 00577 00578 #ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER 00579 #define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER { RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT } 00580 #endif 00581 00582 #ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH 00583 #define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH { RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT } 00584 #endif 00585 00586 #ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP 00587 #define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP { RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT } 00588 #endif 00589 00590 #ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET 00591 #define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET { RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT } 00592 #endif 00593 00594 #ifndef RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD 00595 #define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD { RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT } 00596 #endif 00597 00598 #define RADIO_CONFIGURATION_DATA { \ 00599 Radio_Configuration_Data_Array, \ 00600 RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER, \ 00601 RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH, \ 00602 RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP, \ 00603 RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET, \ 00604 RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD \ 00605 } 00606 00607 #endif /* RADIO_CONFIG_H_ */
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