David Prentice
Please run it on your NUCLEO-L152
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pin_shield_8.h
00001 #ifndef PIN_SHIELD_8_H_ 00002 #define PIN_SHIELD_8_H_ 00003 00004 // just provide macros for the 8-bit data bus 00005 // i.e. write_8(), read_8(), setWriteDir(), setReadDir() 00006 00007 00008 #define LPC810 810 00009 #define LPC812 812 00010 #define LPC1343 1343 00011 #define LPC1768 1768 00012 #define LPC2103 2103 00013 #define LPC2148 2148 00014 00015 #define ISTARGET_NUCLEO64 (0 \ 00016 || defined(TARGET_NUCLEO_F072RB) \ 00017 || defined(TARGET_NUCLEO_F103RB) \ 00018 || defined(TARGET_NUCLEO_F401RE) \ 00019 || defined(TARGET_NUCLEO_F411RE) \ 00020 || defined(TARGET_NUCLEO_F446RE) \ 00021 || defined(TARGET_NUCLEO_L152RE) \ 00022 || defined(TARGET_NUCLEO_L433RC_P) \ 00023 || defined(TARGET_NUCLEO_L476RG) \ 00024 ) 00025 00026 #define ISTARGET_NUCLEO144 (0 \ 00027 || defined(TARGET_NUCLEO_F767ZI) \ 00028 ) 00029 00030 //#warning Using pin_SHIELD_8.h 00031 00032 #if 0 00033 00034 #elif defined(MY_BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER 00035 #warning Uno Shield on MY_BLUEPILL_ADAPTER 00036 00037 // configure macros for the data pins 00038 #define AMASK 0x060F 00039 #define BMASK 0x00C0 00040 #define write_8(d) { GPIOA->BSRR = AMASK << 16; GPIOB->BSRR = BMASK << 16; \ 00041 GPIOA->BSRR = (((d) & 3) << 9) | (((d) & 0xF0) >> 4); \ 00042 GPIOB->BSRR = (((d) & 0x0C) << 4); \ 00043 } 00044 #define read_8() (((GPIOA->IDR & (3<<9)) >> 9) | ((GPIOA->IDR & (0x0F)) << 4) | ((GPIOB->IDR & (3<<6)) >> 4)) 00045 00046 #define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); } 00047 #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) 00048 #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) 00049 // PA10,PA9 PA3-PA0 PB7,PB6 00050 #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFF0); GP_OUT(GPIOA, CRL, 0xFFFF); GP_OUT(GPIOB, CRL, 0xFF000000); } 00051 #define setReadDir() {GP_INP(GPIOA, CRH, 0xFF0); GP_INP(GPIOA, CRL, 0xFFFF); GP_INP(GPIOB, CRL, 0xFF000000); } 00052 00053 #elif defined(BLUEPILL) // Uno Shield on BLUEPILL_ADAPTER 00054 #warning Uno Shield on BLUEPILL_ADAPTER 00055 00056 // configure macros for the data pins 00057 #define write_8(d) { GPIOA->BSRR = 0x00FF << 16; GPIOA->BSRR = (d) & 0xFF; } 00058 #define read_8() (GPIOA->IDR & 0xFF) 00059 00060 #define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); } 00061 #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) 00062 #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) 00063 // PA7 ..PA0 00064 #define setWriteDir() {GP_OUT(GPIOA, CRL, 0xFFFFFFFF); } 00065 #define setReadDir() {GP_INP(GPIOA, CRL, 0xFFFFFFFF); } 00066 00067 #elif defined(ITEADMAPLE) // Uno Shield on MAPLE_REV3 board 00068 #warning Uno Shield on MAPLE_REV3 board 00069 00070 #define REGS(x) x 00071 #define GROUP_MODE(port, reg, mask, val) {port->REGS(reg) = (port->REGS(reg) & ~(mask)) | ((mask)&(val)); } 00072 #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) 00073 #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) 00074 00075 // configure macros for the data pins 00076 #define write_8(d) { \ 00077 GPIOA->REGS(BSRR) = 0x0703 << 16; \ 00078 GPIOB->REGS(BSRR) = 0x00E0 << 16; \ 00079 GPIOA->REGS(BSRR) = ( ((d) & (1<<0)) << 10) \ 00080 | (((d) & (1<<2)) >> 2) \ 00081 | (((d) & (1<<3)) >> 2) \ 00082 | (((d) & (1<<6)) << 2) \ 00083 | (((d) & (1<<7)) << 2); \ 00084 GPIOB->REGS(BSRR) = ( ((d) & (1<<1)) << 6) \ 00085 | (((d) & (1<<4)) << 1) \ 00086 | (((d) & (1<<5)) << 1); \ 00087 } 00088 00089 #define read_8() ( ( ( (GPIOA->REGS(IDR) & (1<<10)) >> 10) \ 00090 | ((GPIOB->REGS(IDR) & (1<<7)) >> 6) \ 00091 | ((GPIOA->REGS(IDR) & (1<<0)) << 2) \ 00092 | ((GPIOA->REGS(IDR) & (1<<1)) << 2) \ 00093 | ((GPIOB->REGS(IDR) & (1<<5)) >> 1) \ 00094 | ((GPIOB->REGS(IDR) & (1<<6)) >> 1) \ 00095 | ((GPIOA->REGS(IDR) & (1<<8)) >> 2) \ 00096 | ((GPIOA->REGS(IDR) & (1<<9)) >> 2))) 00097 00098 // PA10,PA9,PA8 PA1,PA0 PB7,PB6,PB5 00099 #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOA, CRL, 0xFF); GP_OUT(GPIOB, CRL, 0xFFF00000); } 00100 #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOA, CRL, 0xFF); GP_INP(GPIOB, CRL, 0xFFF00000); } 00101 00102 #elif defined(NUCLEO144) || ISTARGET_NUCLEO144 00103 #if __MBED__ 00104 #warning MBED knows everything 00105 #elif defined(STM32F767xx) 00106 #include <STM32F7XX.h> 00107 #endif 00108 00109 #define REGS(x) x 00110 // configure macros for the data pins 00111 #define DMASK ((1<<15)) //#1 00112 #define EMASK ((1<<13)|(1<<11)|(1<<9)) //#3, #5, #6 00113 #define FMASK ((1<<12)|(1<<15)|(1<<14)|(1<<13)) //#0, #2, #4, #7 00114 00115 #define write_8(d) { \ 00116 GPIOD->REGS(BSRR) = DMASK << 16; \ 00117 GPIOE->REGS(BSRR) = EMASK << 16; \ 00118 GPIOF->REGS(BSRR) = FMASK << 16; \ 00119 GPIOD->REGS(BSRR) = ( ((d) & (1<<1)) << 14); \ 00120 GPIOE->REGS(BSRR) = ( ((d) & (1<<3)) << 10) \ 00121 | (((d) & (1<<5)) << 6) \ 00122 | (((d) & (1<<6)) << 3); \ 00123 GPIOF->REGS(BSRR) = ( ((d) & (1<<0)) << 12) \ 00124 | (((d) & (1<<2)) << 13) \ 00125 | (((d) & (1<<4)) << 10) \ 00126 | (((d) & (1<<7)) << 6); \ 00127 } 00128 00129 #define read_8() ( ( ( (GPIOF->REGS(IDR) & (1<<12)) >> 12) \ 00130 | ((GPIOD->REGS(IDR) & (1<<15)) >> 14) \ 00131 | ((GPIOF->REGS(IDR) & (1<<15)) >> 13) \ 00132 | ((GPIOE->REGS(IDR) & (1<<13)) >> 10) \ 00133 | ((GPIOF->REGS(IDR) & (1<<14)) >> 10) \ 00134 | ((GPIOE->REGS(IDR) & (1<<11)) >> 6) \ 00135 | ((GPIOE->REGS(IDR) & (1<<9)) >> 3) \ 00136 | ((GPIOF->REGS(IDR) & (1<<13)) >> 6))) 00137 00138 00139 // PD15 PE13,PE11,PE9 PF15,PF14,PF13,PF12 00140 #define setWriteDir() { setReadDir(); \ 00141 GPIOD->MODER |= 0x40000000; GPIOE->MODER |= 0x04440000; GPIOF->MODER |= 0x55000000; } 00142 #define setReadDir() { GPIOD->MODER &= ~0xC0000000; GPIOE->MODER &= ~0x0CCC0000; GPIOF->MODER &= ~0xFF000000; } 00143 00144 00145 #elif defined(NUCLEO) || ISTARGET_NUCLEO64 00146 #if __MBED__ 00147 #warning MBED knows everything 00148 #elif defined(STM32F072xB) 00149 #include <STM32F0XX.h> 00150 #elif defined(STM32F103xB) 00151 #if defined(__CC_ARM) 00152 #include <STM32F10X.h> 00153 #else 00154 #include <STM32F1XX.h> 00155 #endif 00156 #elif defined(STM32L476xx) || defined(STM32L433xx) 00157 #include <STM32L4XX.h> 00158 #elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) 00159 #include <STM32F4XX.h> 00160 #endif 00161 // configure macros for the data pins. -00=10.06, -O1=7.85, -O1t=7.21, -O2=7.87, -O3=7.45, -O3t=7.03 00162 #define write_8(d) { \ 00163 GPIOA->BSRR = 0x0700 << 16; \ 00164 GPIOB->BSRR = 0x0438 << 16; \ 00165 GPIOC->BSRR = 0x0080 << 16; \ 00166 GPIOA->BSRR = (((d) & (1<<0)) << 9) \ 00167 | (((d) & (1<<2)) << 8) \ 00168 | (((d) & (1<<7)) << 1); \ 00169 GPIOB->BSRR = (((d) & (1<<3)) << 0) \ 00170 | (((d) & (1<<4)) << 1) \ 00171 | (((d) & (1<<5)) >> 1) \ 00172 | (((d) & (1<<6)) << 4); \ 00173 GPIOC->BSRR = (((d) & (1<<1)) << 6); \ 00174 } 00175 #define read_8() ( (((GPIOA->IDR & (1<<9)) >> 9) \ 00176 | ((GPIOC->IDR & (1<<7)) >> 6) \ 00177 | ((GPIOA->IDR & (1<<10)) >> 8) \ 00178 | ((GPIOB->IDR & (1<<3)) >> 0) \ 00179 | ((GPIOB->IDR & (1<<5)) >> 1) \ 00180 | ((GPIOB->IDR & (1<<4)) << 1) \ 00181 | ((GPIOB->IDR & (1<<10)) >> 4) \ 00182 | ((GPIOA->IDR & (1<<8)) >> 1))) 00183 // be wise to clear both MODER bits properly. 00184 #if defined(STM32F103xB) 00185 #define GROUP_MODE(port, reg, mask, val) {port->reg = (port->reg & ~(mask)) | ((mask)&(val)); } 00186 #define GP_OUT(port, reg, mask) GROUP_MODE(port, reg, mask, 0x33333333) 00187 #define GP_INP(port, reg, mask) GROUP_MODE(port, reg, mask, 0x44444444) 00188 // PA10,PA9,PA8 PB10 PB5,PB4,PB3 PC7 00189 #define setWriteDir() {GP_OUT(GPIOA, CRH, 0xFFF); GP_OUT(GPIOB, CRH, 0xF00); GP_OUT(GPIOB, CRL, 0xFFF000); GP_OUT(GPIOC, CRL, 0xF0000000); } 00190 #define setReadDir() {GP_INP(GPIOA, CRH, 0xFFF); GP_INP(GPIOB, CRH, 0xF00); GP_INP(GPIOB, CRL, 0xFFF000); GP_INP(GPIOC, CRL, 0xF0000000); } 00191 #else 00192 #define setWriteDir() { setReadDir(); \ 00193 GPIOA->MODER |= 0x150000; GPIOB->MODER |= 0x100540; GPIOC->MODER |= 0x4000; } 00194 #define setReadDir() { GPIOA->MODER &= ~0x3F0000; GPIOB->MODER &= ~0x300FC0; GPIOC->MODER &= ~0xC000; } 00195 #endif 00196 00197 00198 #elif __TARGET_PROCESSOR == LPC1768 00199 #include <LPC17xx.h> 00200 // configure macros for the data pins 00201 #define write_8(d) { \ 00202 LPC_GPIO0->FIOPIN = (LPC_GPIO0->FIOPIN & ~0x01878003) \ 00203 | (((d) & (1<<0)) << 1) \ 00204 | (((d) & (1<<1)) >> 1) \ 00205 | (((d) & (1<<2)) << 22) \ 00206 | (((d) & (1<<3)) << 20) \ 00207 | (((d) & (1<<4)) << 12) \ 00208 | (((d) & (1<<5)) << 10) \ 00209 | (((d) & (1<<6)) << 11) \ 00210 | (((d) & (1<<7)) << 11); \ 00211 } 00212 #define read_8() ( (((LPC_GPIO0->FIOPIN & (1<<1)) >> 1) \ 00213 | ((LPC_GPIO0->FIOPIN & (1<<0)) << 1) \ 00214 | ((LPC_GPIO0->FIOPIN & (1<<24)) >> 22) \ 00215 | ((LPC_GPIO0->FIOPIN & (1<<23)) >> 20) \ 00216 | ((LPC_GPIO0->FIOPIN & (1<<16)) >> 12) \ 00217 | ((LPC_GPIO0->FIOPIN & (1<<15)) >> 10) \ 00218 | ((LPC_GPIO0->FIOPIN & (1<<17)) >> 11) \ 00219 | ((LPC_GPIO0->FIOPIN & (1<<18)) >> 11))) 00220 #define setWriteDir() {LPC_GPIO0->FIODIR |= 0x01878003; } 00221 #define setReadDir() {LPC_GPIO0->FIODIR &= ~0x01878003; } 00222 00223 00224 #elif defined(MKL25Z4) || defined(TARGET_KL25Z) 00225 #include <MKL25Z4.h> 00226 // configure macros for the data pins 00227 #if 1 00228 #define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4)) 00229 #define CMASK ((1<<9)|(1<<8)) 00230 #define DMASK ((1<<5)|(1<<4)) 00231 #define write_8(d) { \ 00232 PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ 00233 PTA->PSOR = (((d) & (1<<0)) << 13) \ 00234 | (((d) & (1<<3)) << 9) \ 00235 | (((d) & (1<<4)) >> 0) \ 00236 | (((d) & (1<<5)) >> 0); \ 00237 PTC->PSOR = (((d) & (1<<6)) << 2) \ 00238 | (((d) & (1<<7)) << 2); \ 00239 PTD->PSOR = (((d) & (1<<1)) << 4) \ 00240 | (((d) & (1<<2)) << 2); \ 00241 } 00242 #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \ 00243 | ((PTA->PDIR & (1<<12)) >> 9) \ 00244 | ((PTA->PDIR & (3<<4)) >> 0) \ 00245 | ((PTC->PDIR & (3<<8)) >> 2) \ 00246 | ((PTD->PDIR & (1<<4)) >> 2) \ 00247 | ((PTD->PDIR & (1<<5)) >> 4))) 00248 #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } 00249 #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } 00250 #else 00251 #define write_8(d) { \ 00252 PTA->PDOR = (PTA->PDOR & ~0x3030) \ 00253 | (((d) & (1<<0)) << 13) \ 00254 | (((d) & (1<<3)) << 9) \ 00255 | (((d) & (3<<4)) << 0); \ 00256 PTC->PDOR = (PTC->PDOR & ~0x0300) \ 00257 | (((d) & (3<<6)) << 2); \ 00258 PTD->PDOR = (PTD->PDOR & ~0x0030) \ 00259 | (((d) & (1<<1)) << 4) \ 00260 | (((d) & (1<<2)) << 2); \ 00261 } 00262 #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \ 00263 | ((PTA->PDIR & (1<<12)) >> 9) \ 00264 | ((PTA->PDIR & (3<<4)) >> 0) \ 00265 | ((PTC->PDIR & (3<<8)) >> 2) \ 00266 | ((PTD->PDIR & (1<<4)) >> 2) \ 00267 | ((PTD->PDIR & (1<<5)) >> 4))) 00268 #define setWriteDir() {PTA->PDDR |= 0x3030;PTC->PDDR |= 0x0300;PTD->PDDR |= 0x0030; } 00269 #define setReadDir() {PTA->PDDR &= ~0x3030;PTC->PDDR &= ~0x0300;PTD->PDDR &= ~0x0030; } 00270 #endif 00271 00272 #elif defined(MKL26Z4) 00273 #include <MKL26Z4.h> 00274 // configure macros for the data pins 00275 #define AMASK ((1<<13)|(1<<12)|(1<<5)|(1<<4)) 00276 #define CMASK ((1<<9)|(1<<8)) 00277 #define DMASK ((1<<3)|(1<<2)) //PTD5, PTD4 on KL25Z 00278 #define write_8(d) { \ 00279 PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ 00280 PTA->PSOR = (((d) & (1<<0)) << 13) \ 00281 | (((d) & (1<<3)) << 9) \ 00282 | (((d) & (1<<4)) >> 0) \ 00283 | (((d) & (1<<5)) >> 0); \ 00284 PTC->PSOR = (((d) & (1<<6)) << 2) \ 00285 | (((d) & (1<<7)) << 2); \ 00286 PTD->PSOR = (((d) & (1<<1)) << 1) \ 00287 | (((d) & (1<<2)) << 1); \ 00288 } 00289 #define read_8() ( (((PTA->PDIR & (1<<13)) >> 13) \ 00290 | ((PTA->PDIR & (1<<12)) >> 9) \ 00291 | ((PTA->PDIR & (3<<4)) >> 0) \ 00292 | ((PTC->PDIR & (3<<8)) >> 2) \ 00293 | ((PTD->PDIR & (1<<3)) >> 1) \ 00294 | ((PTD->PDIR & (1<<2)) >> 1))) 00295 #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } 00296 #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } 00297 00298 #elif defined(MKL05Z4) || defined(TARGET_KL05Z) 00299 #include <MKL05Z4.h> 00300 // configure macros for the data pins 00301 #define write_8(d) { \ 00302 PTA->PDOR = (PTA->PDOR & ~0x1C00) \ 00303 | (((d) & (1<<2)) << 9) \ 00304 | (((d) & (1<<4)) << 6) \ 00305 | (((d) & (1<<5)) << 7); \ 00306 PTB->PDOR = (PTB->PDOR & ~0x0CE0) \ 00307 | (((d) & (3<<0)) << 10) \ 00308 | (((d) & (1<<3)) << 2) \ 00309 | (((d) & (3<<6)) << 0); \ 00310 } 00311 #define read_8() ( (((PTA->PDIR & (1<<11)) >> 9) \ 00312 | ((PTA->PDIR & (1<<10)) >> 6) \ 00313 | ((PTA->PDIR & (1<<12)) >> 7) \ 00314 | ((PTB->PDIR & (3<<10)) >> 10) \ 00315 | ((PTB->PDIR & (1<<5)) >> 2) \ 00316 | ((PTB->PDIR & (3<<6)) >> 0))) 00317 #define setWriteDir() { PTA->PDDR |= 0x1C00; PTB->PDDR |= 0x0CE0; } 00318 #define setReadDir() { PTA->PDDR &= ~0x1C00; PTB->PDDR &= ~0x0CE0; } 00319 00320 00321 #elif (defined(MK20D7) && defined(TEENSY)) || defined(TARGET_TEENSY3_1) 00322 #if __MBED__ 00323 #warning MBED knows everything 00324 #else 00325 #include <MK20D5.h> 00326 #endif 00327 // configure macros for the data pins 00328 #define AMASK ((1<<12)|(1<<13)) 00329 #define CMASK ((1<<3)) 00330 #define DMASK ((1<<0)|(1<<2)|(1<<3)|(1<<4)|(1<<7)) 00331 00332 #define write_8(d) { \ 00333 PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ 00334 PTA->PSOR = (((d) & (1<<3)) << 9) \ 00335 | (((d) & (1<<4)) << 9); \ 00336 PTC->PSOR = (((d) & (1<<1)) << 2); \ 00337 PTD->PSOR = (((d) & (1<<0)) << 3) \ 00338 | (((d) & (1<<2)) >> 2) \ 00339 | (((d) & (1<<5)) << 2) \ 00340 | (((d) & (1<<6)) >> 2) \ 00341 | (((d) & (1<<7)) >> 5); \ 00342 } 00343 #define read_8() ( (((PTD->PDIR & (1<<3)) >> 3) \ 00344 | ((PTC->PDIR & (1<<3)) >> 2) \ 00345 | ((PTD->PDIR & (1<<0)) << 2) \ 00346 | ((PTA->PDIR & (1<<12)) >> 9) \ 00347 | ((PTA->PDIR & (1<<13)) >> 9) \ 00348 | ((PTD->PDIR & (1<<7)) >> 2) \ 00349 | ((PTD->PDIR & (1<<4)) << 2) \ 00350 | ((PTD->PDIR & (1<<2)) << 5))) 00351 #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } 00352 #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } 00353 00354 #elif defined(MK20D5) || defined(TARGET_K20D50M) 00355 #include <MK20D5.h> 00356 // configure macros for the data pins 00357 #define AMASK ((1<<12)|(1<<5)|(1<<2)|(1<<1)) 00358 #define CMASK ((1<<8)|(1<<4)|(1<<3)) 00359 #define DMASK ((1<<4)) 00360 #define write_8(d) { \ 00361 PTA->PCOR = AMASK; PTC->PCOR = CMASK; PTD->PCOR = DMASK; \ 00362 PTA->PSOR = (((d) & (1<<0)) << 12) \ 00363 | (((d) & (1<<1)) << 1) \ 00364 | (((d) & (1<<2)) << 3) \ 00365 | (((d) & (1<<5)) >> 4); \ 00366 PTC->PSOR = (((d) & (1<<4)) << 4) \ 00367 | (((d) & (3<<6)) >> 3); \ 00368 PTD->PSOR = (((d) & (1<<3)) << 1); \ 00369 } 00370 #define read_8() ( (((PTA->PDIR & (1<<5)) >> 3) \ 00371 | ((PTA->PDIR & (1<<1)) << 4) \ 00372 | ((PTA->PDIR & (1<<12)) >> 12) \ 00373 | ((PTA->PDIR & (1<<2)) >> 1) \ 00374 | ((PTC->PDIR & (1<<8)) >> 4) \ 00375 | ((PTC->PDIR & (3<<3)) << 3) \ 00376 | ((PTD->PDIR & (1<<4)) >> 1))) 00377 #define setWriteDir() {PTA->PDDR |= AMASK;PTC->PDDR |= CMASK;PTD->PDDR |= DMASK; } 00378 #define setReadDir() {PTA->PDDR &= ~AMASK;PTC->PDDR &= ~CMASK;PTD->PDDR &= ~DMASK; } 00379 00380 #elif defined(ZERO) 00381 #include <samd21.h> 00382 00383 #ifndef PORTA 00384 #define PORTA PORT->Group[0] 00385 #define PORTB PORT->Group[1] 00386 #endif 00387 // configure macros for the data pins 00388 #if defined(D21_XPRO) 00389 #define AMASK 0x00220000 00390 #define BMASK 0x0000C0E4 00391 #define write_8(d) { \ 00392 PORTA.OUT.reg = (PORTA.OUT.reg & ~AMASK) \ 00393 | (((d) & (1<<5)) << 16) \ 00394 | (((d) & (1<<7)) << 10); \ 00395 PORTB.OUT.reg = (PORTB.OUT.reg & ~BMASK) \ 00396 | (((d) & (3<<0)) << 6) \ 00397 | (((d) & (1<<2)) << 12) \ 00398 | (((d) & (1<<3)) >> 1) \ 00399 | (((d) & (1<<4)) << 1) \ 00400 | (((d) & (1<<6)) << 9); \ 00401 } 00402 #define read_8() ( (((PORTA.IN.reg & (1<<21)) >> 16) \ 00403 | ((PORTA.IN.reg & (1<<17)) >> 10) \ 00404 | ((PORTB.IN.reg & (3<<6)) >> 6) \ 00405 | ((PORTB.IN.reg & (1<<14)) >> 12) \ 00406 | ((PORTB.IN.reg & (1<<2)) << 1) \ 00407 | ((PORTB.IN.reg & (1<<5)) >> 1) \ 00408 | ((PORTB.IN.reg & (1<<15)) >> 9))) 00409 #define setWriteDir() { \ 00410 PORTA.DIRSET.reg = AMASK; \ 00411 PORTB.DIRSET.reg = BMASK; \ 00412 PORTA.WRCONFIG.reg = (AMASK>>16) | (0<<22) | (0<<28) | (1<<30) | (1<<31); \ 00413 PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (0<<22) | (0<<28) | (1<<30); \ 00414 } 00415 #define setReadDir() { \ 00416 PORTA.DIRCLR.reg = AMASK; \ 00417 PORTB.DIRCLR.reg = BMASK; \ 00418 PORTA.WRCONFIG.reg = (AMASK>>16) | (1<<17) | (0<<28) | (1<<30) | (1<<31); \ 00419 PORTB.WRCONFIG.reg = (BMASK & 0xFFFF) | (1<<17) | (0<<28) | (1<<30); \ 00420 } 00421 #else 00422 #define DMASK 0x0030C3C0 00423 #define write_8(x) {PORTA.OUTCLR.reg = (DMASK); \ 00424 PORTA.OUTSET.reg = (((x) & 0x0F) << 6) \ 00425 | (((x) & 0x30) << 10) \ 00426 | (((x) & 0xC0)<<14); } 00427 #define read_8() (((PORTA.IN.reg >> 6) & 0x0F) \ 00428 | ((PORTA.IN.reg >> 10) & 0x30) \ 00429 | ((PORTA.IN.reg >> 14) & 0xC0)) 00430 #define setWriteDir() { PORTA.DIRSET.reg = DMASK; \ 00431 PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (0<<22) | (1<<28) | (1<<30); \ 00432 PORTA.WRCONFIG.reg = (DMASK>>16) | (0<<22) | (1<<28) | (1<<30) | (1<<31); \ 00433 } 00434 #define setReadDir() { PORTA.DIRCLR.reg = DMASK; \ 00435 PORTA.WRCONFIG.reg = (DMASK & 0xFFFF) | (1<<17) | (1<<28) | (1<<30); \ 00436 PORTA.WRCONFIG.reg = (DMASK>>16) | (1<<17) | (1<<28) | (1<<30) | (1<<31); \ 00437 } 00438 #endif 00439 #else 00440 #error MCU unselected 00441 #endif // MCUs 00442 00443 #endif //PIN_SHIELD_8_H
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