mcufriend_serial.h

00001 #if ARDUINO >= 165
00002 #include <SPI.h>
00003 #endif
00004 
00005 #if 0
00006 #elif defined(__AVR_ATmega328P__)
00007 
00008 #define SPI_INIT()   { DDRB |= (1<<5)|(1<<3)|(1<<2); SPCR = (1<<SPE)|(1<<MSTR); SPSR = (1<<SPI2X); SPSR; SPDR; }
00009 static inline uint8_t spi_xfer(uint8_t c)
00010 {
00011     SPDR = c;
00012     while ((SPSR & (1<<SPIF)) == 0) ;
00013     return SPDR;
00014 }
00015 extern uint8_t running;
00016 static inline void write8(uint8_t x)    {
00017                          if (running) {
00018                              while ((SPSR & 0x80) == 0);
00019                              SPDR;
00020                          }
00021                          SPDR = x;
00022                          running = 1;
00023                      }
00024 static inline uint8_t read8(void)    {
00025                          if (running) while ((SPSR & 0x80) == 0);
00026                          running = 0;
00027                          return SPDR;
00028                      }
00029 static inline uint8_t xchg8(uint8_t x) { write8(x); return read8(); }
00030 static inline void flush(void)   {
00031                       if (running) {
00032                           while ((SPSR & 0x80) == 0);
00033                       }
00034                       running = 0;
00035                       SPDR;
00036                   }
00037 
00038 #if defined(SUPPORT_8347D)
00039 #warning using HX8347D hardware
00040 #define CD_PORT PORTD
00041 #define CD_PIN  PD7
00042 #define CS_PORT PORTB
00043 #define CS_PIN  PB2
00044 #define RESET_PORT PORTB
00045 #define RESET_PIN  PB1
00046 #define SD_PIN  PD5
00047 #define XPT_PIN PD4
00048 #define RD_IDLE
00049 #define WR_IDLE
00050 #else
00051 #warning using regular SPI hardware
00052 #define CD_PORT PORTB
00053 #define CD_PIN  1
00054 #define CS_PORT PORTB
00055 #define CS_PIN  2
00056 #define RESET_PORT PORTB
00057 #define RESET_PIN  0
00058 #define RD_IDLE
00059 #define WR_IDLE
00060 #endif
00061 
00062 #define setWriteDir() { }
00063 #define setReadDir()  { }
00064 //#define write8(x)     spi_xfer(x)
00065 #define write16(x)    { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
00066 #define READ_8(dst)   { dst = xchg8(0); }
00067 #define READ_16(dst)  { dst = xchg8(0); dst = (dst << 8) | xchg8(0);  }
00068 
00069 #define PIN_LOW(p, b)        (p) &= ~(1<<(b))
00070 #define PIN_HIGH(p, b)       (p) |= (1<<(b))
00071 #define PIN_OUTPUT(p, b)     *(&p-1) |= (1<<(b))
00072 #elif defined(__SAMD21G18A__)
00073 
00074 #define SPI_INIT()   { SPI.begin(); SPI.setDataMode(SPI_MODE0); SPI.setClockDivider(6); }
00075 
00076 #define CD_PORT PORT->Group[0]
00077 #define CD_PIN  7
00078 #define CS_PORT PORT->Group[0]
00079 #define CS_PIN  18
00080 #define RESET_PORT PORT->Group[0]
00081 #define RESET_PIN  6
00082 #define RD_IDLE
00083 #define WR_IDLE
00084 
00085 
00086 uint8_t running;
00087 static inline void write8(uint8_t c)
00088 {
00089   running = 1;
00090   while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
00091   SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
00092 }
00093 
00094 static inline void flush(void)
00095 {
00096   if (running) while( SERCOM1->SPI.INTFLAG.bit.TXC == 0) ;
00097   running = 0;
00098 }
00099 
00100 static inline uint8_t xchg8(uint8_t c)
00101 {
00102 //  flush();
00103   while( SERCOM1->SPI.INTFLAG.bit.RXC != 0) SERCOM1->SPI.DATA.bit.DATA; //eat up
00104   while( SERCOM1->SPI.INTFLAG.bit.DRE == 0) ;
00105   SERCOM1->SPI.DATA.bit.DATA = c; // Writing data into Data register
00106   while( SERCOM1->SPI.INTFLAG.bit.RXC == 0) ;
00107   return SERCOM1->SPI.DATA.bit.DATA;
00108 }
00109 
00110 
00111 #define setWriteDir() { }
00112 #define setReadDir()  { }
00113 //#define flush()
00114 //#define write8(x) xchg8(x)
00115 //#define xchg8(x)     SPI.transfer(x)
00116 #define write16(x)    { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
00117 #define READ_8(dst)   { dst = xchg8(0); }
00118 #define READ_16(dst)  { dst = xchg8(0); dst = (dst << 8) | xchg8(0);  }
00119 
00120 // Shield Control macros.
00121 #define PIN_LOW(port, pin)    (port).OUTCLR.reg = (1<<(pin))
00122 #define PIN_HIGH(port, pin)   (port).OUTSET.reg = (1<<(pin))
00123 #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin))
00124 
00125 #elif defined(__AVR_ATxmega128A1__)     //3.49s @ 32MHz -O2
00126   #define CD_PORT VPORT2
00127   #define CD_PIN  1
00128   #define CS_PORT VPORT3
00129   #define CS_PIN  4
00130   #define RESET_PORT VPORT2
00131   #define RESET_PIN  0
00132 #define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
00133 #define SETDDR  {VPORT3.DIR |= (1<<4)|(1<<5)|(1<<7); VPORT2.DIR |= 0x03; }
00134 #define SPI_INIT()  { PORTCFG.VPCTRLB=PORTCFG_VP3MAP_PORTF_gc | PORTCFG_VP2MAP_PORTC_gc; CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
00135 
00136 void spi_init(void)
00137 {
00138    SPIF.CTRL=SPI_ENABLE_bm | SPI_MODE_3_gc | (1<<SPI_MASTER_bp) | (1<<SPI_CLK2X_bp);
00139 }
00140 
00141 #define write8(x)    {\
00142                          SPIF.DATA=x;\
00143                          while ((SPIF.STATUS & SPI_IF_bm)==0);\
00144                          SPIF.DATA;\
00145                      }
00146 #define flush()   {\
00147                   }
00148 
00149 #define PIN_LOW(p, b)        (p).OUT &= ~(1<<(b))
00150 #define PIN_HIGH(p, b)       (p).OUT |= (1<<(b))
00151 #define PIN_OUTPUT(p, b)     (p).DIR |= (1<<(b))
00152 
00153 #elif defined(__AVR_ATxmega32A4U__)     //3.49s @ 32MHz -O2.  
00154 // 100ns/150ns for ILI9341 W/R cycle.   100ns/200ns for ILI920.  20ns/150ns HX8347
00155 // Xmega @ 60MHz i.e. 30MHz SCK works with 9341.
00156 #warning Using ATxmega32A4U USART_MSPI
00157   #define CD_PORT VPORT2
00158   #define CD_PIN  1
00159   #define CS_PORT VPORT3
00160   #define CS_PIN  0
00161   #define RESET_PORT VPORT2
00162   #define RESET_PIN  0
00163   #define SD_PORT    PORTC
00164   #define SD_PIN     4
00165 #define SPCRVAL (USART_CLK2X_bm | USART_RXEN_bm | USART_TXEN_bm)
00166 #define SETDDR  {PORTCFG.VPCTRLB=PORTCFG_VP13MAP_PORTD_gc | PORTCFG_VP02MAP_PORTC_gc; VPORT3.DIR |= (1<<0)|(1<<1)|(1<<3); VPORT2.DIR |= 0x03; PIN_HIGH(SD_PORT, SD_PIN); SD_PORT.DIR |= (1<<SD_PIN); }
00167 #define SPI_INIT()  { CS_IDLE; RESET_IDLE; SETDDR; spi_init(); }
00168 
00169 static inline void spi_init(void)
00170 {
00171    USARTD0.CTRLB = SPCRVAL;
00172    USARTD0.CTRLC = USART_CMODE_MSPI_gc | 0x00 | 0x00;   //mode #0 
00173 //   PORTD.PIN1CTRL |= PORT_INVEN_bm;   //CPOL
00174    USARTD0.BAUDCTRLA = 0x00;     //F_CPU/2
00175    USARTD0.BAUDCTRLB = ((0x00 << USART_BSCALE_gp) & USART_BSCALE_gm) | 0x00;
00176    USARTD0.DATA; 
00177 }
00178 
00179 extern uint8_t running;
00180 
00181 #define write8(x)    {\
00182                          while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
00183                          asm("cli");\
00184                          USARTD0.DATA = x;\
00185                          USARTD0.STATUS = USART_TXCIF_bm;\
00186                          asm("sei");\
00187                          running = 1;\
00188                      }
00189 static inline uint8_t read8(void)    {
00190                          if (running) while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
00191                          return USARTD0.DATA;
00192                      }
00193 #define flush()   {\
00194                          if (running) while ((USARTD0.STATUS & USART_TXCIF_bm) == 0) ;\
00195                          while ((USARTD0.STATUS & USART_RXCIF_bm) != 0) USARTD0.DATA;\
00196                          running = 0;\
00197                   }
00198 static inline uint8_t xchg8(uint8_t x)    {
00199                          USARTD0.DATA = x;
00200                          while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;
00201                          return USARTD0.DATA;
00202                      }
00203 /*
00204 #define write8(x)    {\
00205                          while ((USARTD0.STATUS & USART_DREIF_bm) == 0) ;\
00206                          USARTD0.DATA = x;\
00207                          while ((USARTD0.STATUS & USART_RXCIF_bm) == 0) ;\
00208                          USARTD0.DATA;\
00209                      }
00210 #define flush()
00211 */
00212 
00213 #define RD_IDLE
00214 #define WR_IDLE
00215 //#define SPI_INIT()    spi_init()
00216 #define setWriteDir() { }
00217 #define setReadDir()  { }
00218 //#define write8(x)     spi_xfer(x)
00219 #define write16(x)    { uint8_t h = (x)>>8, l = x; write8(h); write8(l); }
00220 #define READ_8(dst)   { dst = xchg8(0); }
00221 #define READ_16(dst)  { dst = xchg8(0); dst = (dst << 8) | xchg8(0);  }
00222 
00223 #define PIN_LOW(p, b)        (p).OUT &= ~(1<<(b))
00224 #define PIN_HIGH(p, b)       (p).OUT |= (1<<(b))
00225 #define PIN_OUTPUT(p, b)     (p).DIR |= (1<<(b))
00226 
00227 #endif
00228 
00229 #define CD_COMMAND {flush(); PIN_LOW(CD_PORT, CD_PIN); }
00230 #define CD_DATA    {flush(); PIN_HIGH(CD_PORT, CD_PIN); }
00231 #define CD_OUTPUT  PIN_OUTPUT(CD_PORT, CD_PIN)
00232 #define CS_ACTIVE  PIN_LOW(CS_PORT, CS_PIN)
00233 #define CS_IDLE    {flush(); PIN_HIGH(CS_PORT, CS_PIN); }
00234 #define CS_OUTPUT  PIN_OUTPUT(CS_PORT, CS_PIN)
00235 #define RESET_ACTIVE  PIN_LOW(RESET_PORT, RESET_PIN)
00236 #define RESET_IDLE    PIN_HIGH(RESET_PORT, RESET_PIN)
00237 #define RESET_OUTPUT  PIN_OUTPUT(RESET_PORT, RESET_PIN)
00238 
00239 // General macros.   IOCLR registers are 1 cycle when optimised.
00240 
00241 #define CTL_INIT()   { CD_OUTPUT; CS_OUTPUT; RESET_OUTPUT; SPI_INIT(); }
00242 #define WriteCmd(x)  { CD_COMMAND; write8(x); }
00243 #define WriteData(x) { CD_DATA; write16(x); }