David Prentice
MCUFRIEND_kbv library for MBED depends on ADA_GFX_kbv library
Dependents: TFT_Touch_botao_v1 TFT_Touch_exemplo5_git_touch TESTE_1 TFT_Touch_exemplo6_git_touch_button_3_ ... more
utility/pin_shield_1.h@1:06c4b34a5a61, 2021-04-28 (annotated)
- Committer:
- davidprentice
- Date:
- Wed Apr 28 11:24:54 2021 +0000
- Revision:
- 1:06c4b34a5a61
- Parent:
- 0:6f633078852b
recognise TARGET_LPC1768 in pin_1.h, pin_8.h
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| davidprentice | 0:6f633078852b | 1 | #ifndef PIN_SHIELD_1_H_ |
| davidprentice | 0:6f633078852b | 2 | #define PIN_SHIELD_1_H_ |
| davidprentice | 0:6f633078852b | 3 | |
| davidprentice | 0:6f633078852b | 4 | // just provide macros for the Arduino pins |
| davidprentice | 0:6f633078852b | 5 | // i.e. PIN_LOW(), PIN_HIGH(), PIN_OUTPUT(), PIN_INPUT(), PIN_READ() |
| davidprentice | 0:6f633078852b | 6 | |
| davidprentice | 0:6f633078852b | 7 | #define LPC810 810 |
| davidprentice | 0:6f633078852b | 8 | #define LPC812 812 |
| davidprentice | 0:6f633078852b | 9 | #define LPC1343 1343 |
| davidprentice | 0:6f633078852b | 10 | #define LPC1768 1768 |
| davidprentice | 0:6f633078852b | 11 | #define LPC2103 2103 |
| davidprentice | 0:6f633078852b | 12 | #define LPC2148 2148 |
| davidprentice | 0:6f633078852b | 13 | |
| davidprentice | 0:6f633078852b | 14 | #define ISTARGET_NUCLEO64 (0 \ |
| davidprentice | 0:6f633078852b | 15 | || defined(TARGET_NUCLEO_F072RB) \ |
| davidprentice | 0:6f633078852b | 16 | || defined(TARGET_NUCLEO_F103RB) \ |
| davidprentice | 0:6f633078852b | 17 | || defined(TARGET_NUCLEO_F401RE) \ |
| davidprentice | 0:6f633078852b | 18 | || defined(TARGET_NUCLEO_F411RE) \ |
| davidprentice | 0:6f633078852b | 19 | || defined(TARGET_NUCLEO_F446RE) \ |
| davidprentice | 0:6f633078852b | 20 | || defined(TARGET_NUCLEO_L433RC_P) \ |
| davidprentice | 0:6f633078852b | 21 | || defined(TARGET_NUCLEO_L476RG) \ |
| davidprentice | 0:6f633078852b | 22 | ) |
| davidprentice | 0:6f633078852b | 23 | |
| davidprentice | 0:6f633078852b | 24 | #define ISTARGET_NUCLEO144 (0 \ |
| davidprentice | 0:6f633078852b | 25 | || defined(TARGET_NUCLEO_F767ZI) \ |
| davidprentice | 0:6f633078852b | 26 | ) |
| davidprentice | 0:6f633078852b | 27 | |
| davidprentice | 0:6f633078852b | 28 | //#warning Using pin_SHIELD_1.h |
| davidprentice | 0:6f633078852b | 29 | |
| davidprentice | 0:6f633078852b | 30 | #if 0 |
| davidprentice | 0:6f633078852b | 31 | #elif defined(MY_BLUEPILL) |
| davidprentice | 0:6f633078852b | 32 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
| davidprentice | 0:6f633078852b | 33 | #if defined(__CC_ARM) |
| davidprentice | 0:6f633078852b | 34 | #include <STM32F10X.h> |
| davidprentice | 0:6f633078852b | 35 | #else |
| davidprentice | 0:6f633078852b | 36 | #include <STM32F1XX.h> |
| davidprentice | 0:6f633078852b | 37 | #endif |
| davidprentice | 0:6f633078852b | 38 | #define D0_PORT GPIOB |
| davidprentice | 0:6f633078852b | 39 | #define D0_PIN 11 |
| davidprentice | 0:6f633078852b | 40 | #define D1_PORT GPIOB |
| davidprentice | 0:6f633078852b | 41 | #define D1_PIN 10 |
| davidprentice | 0:6f633078852b | 42 | #define D2_PORT GPIOB |
| davidprentice | 0:6f633078852b | 43 | #define D2_PIN 6 |
| davidprentice | 0:6f633078852b | 44 | #define D3_PORT GPIOB |
| davidprentice | 0:6f633078852b | 45 | #define D3_PIN 7 |
| davidprentice | 0:6f633078852b | 46 | #define D4_PORT GPIOA |
| davidprentice | 0:6f633078852b | 47 | #define D4_PIN 0 |
| davidprentice | 0:6f633078852b | 48 | #define D5_PORT GPIOA |
| davidprentice | 0:6f633078852b | 49 | #define D5_PIN 1 |
| davidprentice | 0:6f633078852b | 50 | #define D6_PORT GPIOA |
| davidprentice | 0:6f633078852b | 51 | #define D6_PIN 2 |
| davidprentice | 0:6f633078852b | 52 | #define D7_PORT GPIOA |
| davidprentice | 0:6f633078852b | 53 | #define D7_PIN 3 |
| davidprentice | 0:6f633078852b | 54 | #define D8_PORT GPIOA |
| davidprentice | 0:6f633078852b | 55 | #define D8_PIN 9 |
| davidprentice | 0:6f633078852b | 56 | #define D9_PORT GPIOA |
| davidprentice | 0:6f633078852b | 57 | #define D9_PIN 10 |
| davidprentice | 0:6f633078852b | 58 | #define D10_PORT GPIOB |
| davidprentice | 0:6f633078852b | 59 | #define D10_PIN 12 |
| davidprentice | 0:6f633078852b | 60 | #define D11_PORT GPIOB |
| davidprentice | 0:6f633078852b | 61 | #define D11_PIN 15 |
| davidprentice | 0:6f633078852b | 62 | #define D12_PORT GPIOB |
| davidprentice | 0:6f633078852b | 63 | #define D12_PIN 14 |
| davidprentice | 0:6f633078852b | 64 | #define D13_PORT GPIOB |
| davidprentice | 0:6f633078852b | 65 | #define D13_PIN 13 |
| davidprentice | 0:6f633078852b | 66 | #define A0_PORT GPIOB |
| davidprentice | 0:6f633078852b | 67 | #define A0_PIN 1 |
| davidprentice | 0:6f633078852b | 68 | #define A1_PORT GPIOB |
| davidprentice | 0:6f633078852b | 69 | #define A1_PIN 0 |
| davidprentice | 0:6f633078852b | 70 | #define A2_PORT GPIOA |
| davidprentice | 0:6f633078852b | 71 | #define A2_PIN 7 |
| davidprentice | 0:6f633078852b | 72 | #define A3_PORT GPIOA |
| davidprentice | 0:6f633078852b | 73 | #define A3_PIN 6 |
| davidprentice | 0:6f633078852b | 74 | #define A4_PORT GPIOA |
| davidprentice | 0:6f633078852b | 75 | #define A4_PIN 5 |
| davidprentice | 0:6f633078852b | 76 | #define A5_PORT GPIOB |
| davidprentice | 0:6f633078852b | 77 | #define A5_PIN 4 |
| davidprentice | 0:6f633078852b | 78 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 79 | #define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16)) |
| davidprentice | 0:6f633078852b | 80 | #define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 81 | #define PIN_READ(port, pin) (port)->IDR & (1<<(pin)) |
| davidprentice | 0:6f633078852b | 82 | #define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2)) |
| davidprentice | 0:6f633078852b | 83 | #define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7 |
| davidprentice | 0:6f633078852b | 84 | #define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input |
| davidprentice | 0:6f633078852b | 85 | |
| davidprentice | 0:6f633078852b | 86 | |
| davidprentice | 0:6f633078852b | 87 | #elif defined(BLUEPILL) |
| davidprentice | 0:6f633078852b | 88 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
| davidprentice | 0:6f633078852b | 89 | #if defined(__CC_ARM) |
| davidprentice | 0:6f633078852b | 90 | #include <STM32F10X.h> |
| davidprentice | 0:6f633078852b | 91 | #else |
| davidprentice | 0:6f633078852b | 92 | #include <STM32F1XX.h> |
| davidprentice | 0:6f633078852b | 93 | #endif |
| davidprentice | 0:6f633078852b | 94 | #define D0_PORT GPIOA |
| davidprentice | 0:6f633078852b | 95 | #define D0_PIN 10 |
| davidprentice | 0:6f633078852b | 96 | #define D1_PORT GPIOA |
| davidprentice | 0:6f633078852b | 97 | #define D1_PIN 9 |
| davidprentice | 0:6f633078852b | 98 | #define D2_PORT GPIOA |
| davidprentice | 0:6f633078852b | 99 | #define D2_PIN 2 |
| davidprentice | 0:6f633078852b | 100 | #define D3_PORT GPIOA |
| davidprentice | 0:6f633078852b | 101 | #define D3_PIN 3 |
| davidprentice | 0:6f633078852b | 102 | #define D4_PORT GPIOA |
| davidprentice | 0:6f633078852b | 103 | #define D4_PIN 4 |
| davidprentice | 0:6f633078852b | 104 | #define D5_PORT GPIOA |
| davidprentice | 0:6f633078852b | 105 | #define D5_PIN 5 |
| davidprentice | 0:6f633078852b | 106 | #define D6_PORT GPIOA |
| davidprentice | 0:6f633078852b | 107 | #define D6_PIN 6 |
| davidprentice | 0:6f633078852b | 108 | #define D7_PORT GPIOA |
| davidprentice | 0:6f633078852b | 109 | #define D7_PIN 7 |
| davidprentice | 0:6f633078852b | 110 | #define D8_PORT GPIOA |
| davidprentice | 0:6f633078852b | 111 | #define D8_PIN 0 |
| davidprentice | 0:6f633078852b | 112 | #define D9_PORT GPIOA |
| davidprentice | 0:6f633078852b | 113 | #define D9_PIN 1 |
| davidprentice | 0:6f633078852b | 114 | #define D10_PORT GPIOA |
| davidprentice | 0:6f633078852b | 115 | #define D10_PIN 15 |
| davidprentice | 0:6f633078852b | 116 | #define D11_PORT GPIOB |
| davidprentice | 0:6f633078852b | 117 | #define D11_PIN 5 |
| davidprentice | 0:6f633078852b | 118 | #define D12_PORT GPIOB |
| davidprentice | 0:6f633078852b | 119 | #define D12_PIN 4 |
| davidprentice | 0:6f633078852b | 120 | #define D13_PORT GPIOB |
| davidprentice | 0:6f633078852b | 121 | #define D13_PIN 3 |
| davidprentice | 0:6f633078852b | 122 | #define A0_PORT GPIOB |
| davidprentice | 0:6f633078852b | 123 | // #define A0_PIN 5 //original pcb uses SPI pin |
| davidprentice | 0:6f633078852b | 124 | #define A0_PIN 0 //hardware mod to Adapter to PB0. Allows use of PB5 for SD Card |
| davidprentice | 0:6f633078852b | 125 | #define A1_PORT GPIOB |
| davidprentice | 0:6f633078852b | 126 | #define A1_PIN 6 |
| davidprentice | 0:6f633078852b | 127 | #define A2_PORT GPIOB |
| davidprentice | 0:6f633078852b | 128 | #define A2_PIN 7 |
| davidprentice | 0:6f633078852b | 129 | #define A3_PORT GPIOB |
| davidprentice | 0:6f633078852b | 130 | #define A3_PIN 8 |
| davidprentice | 0:6f633078852b | 131 | #define A4_PORT GPIOB |
| davidprentice | 0:6f633078852b | 132 | #define A4_PIN 9 |
| davidprentice | 0:6f633078852b | 133 | #define A5_PORT GPIOB |
| davidprentice | 0:6f633078852b | 134 | #define A5_PIN 10 |
| davidprentice | 0:6f633078852b | 135 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 136 | #define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16)) |
| davidprentice | 0:6f633078852b | 137 | #define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 138 | #define PIN_READ(port, pin) (port)->IDR & (1<<(pin)) |
| davidprentice | 0:6f633078852b | 139 | #define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2)) |
| davidprentice | 0:6f633078852b | 140 | #define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7 |
| davidprentice | 0:6f633078852b | 141 | #define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input |
| davidprentice | 0:6f633078852b | 142 | |
| davidprentice | 0:6f633078852b | 143 | |
| davidprentice | 0:6f633078852b | 144 | #elif defined(ITEADMAPLE) |
| davidprentice | 0:6f633078852b | 145 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
| davidprentice | 0:6f633078852b | 146 | #if defined(__CC_ARM) |
| davidprentice | 0:6f633078852b | 147 | #include <STM32F10X.h> |
| davidprentice | 0:6f633078852b | 148 | #else |
| davidprentice | 0:6f633078852b | 149 | #include <STM32F1XX.h> |
| davidprentice | 0:6f633078852b | 150 | #endif |
| davidprentice | 0:6f633078852b | 151 | #define D0_PORT GPIOA |
| davidprentice | 0:6f633078852b | 152 | #define D0_PIN 3 |
| davidprentice | 0:6f633078852b | 153 | #define D1_PORT GPIOA |
| davidprentice | 0:6f633078852b | 154 | #define D1_PIN 2 |
| davidprentice | 0:6f633078852b | 155 | #define D2_PORT GPIOA |
| davidprentice | 0:6f633078852b | 156 | #define D2_PIN 0 |
| davidprentice | 0:6f633078852b | 157 | #define D3_PORT GPIOA |
| davidprentice | 0:6f633078852b | 158 | #define D3_PIN 1 |
| davidprentice | 0:6f633078852b | 159 | #define D4_PORT GPIOB |
| davidprentice | 0:6f633078852b | 160 | #define D4_PIN 5 |
| davidprentice | 0:6f633078852b | 161 | #define D5_PORT GPIOB |
| davidprentice | 0:6f633078852b | 162 | #define D5_PIN 6 |
| davidprentice | 0:6f633078852b | 163 | #define D6_PORT GPIOA |
| davidprentice | 0:6f633078852b | 164 | #define D6_PIN 8 |
| davidprentice | 0:6f633078852b | 165 | #define D7_PORT GPIOA |
| davidprentice | 0:6f633078852b | 166 | #define D7_PIN 9 |
| davidprentice | 0:6f633078852b | 167 | #define D8_PORT GPIOA |
| davidprentice | 0:6f633078852b | 168 | #define D8_PIN 10 |
| davidprentice | 0:6f633078852b | 169 | #define D9_PORT GPIOB |
| davidprentice | 0:6f633078852b | 170 | #define D9_PIN 7 |
| davidprentice | 0:6f633078852b | 171 | #define D10_PORT GPIOA |
| davidprentice | 0:6f633078852b | 172 | #define D10_PIN 4 |
| davidprentice | 0:6f633078852b | 173 | #define D11_PORT GPIOA |
| davidprentice | 0:6f633078852b | 174 | #define D11_PIN 7 |
| davidprentice | 0:6f633078852b | 175 | #define D12_PORT GPIOA |
| davidprentice | 0:6f633078852b | 176 | #define D12_PIN 6 |
| davidprentice | 0:6f633078852b | 177 | #define D13_PORT GPIOA |
| davidprentice | 0:6f633078852b | 178 | #define D13_PIN 5 |
| davidprentice | 0:6f633078852b | 179 | #define A0_PORT GPIOC |
| davidprentice | 0:6f633078852b | 180 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 181 | #define A1_PORT GPIOC |
| davidprentice | 0:6f633078852b | 182 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 183 | #define A2_PORT GPIOC |
| davidprentice | 0:6f633078852b | 184 | #define A2_PIN 2 |
| davidprentice | 0:6f633078852b | 185 | #define A3_PORT GPIOC |
| davidprentice | 0:6f633078852b | 186 | #define A3_PIN 3 |
| davidprentice | 0:6f633078852b | 187 | #define A4_PORT GPIOC |
| davidprentice | 0:6f633078852b | 188 | #define A4_PIN 4 |
| davidprentice | 0:6f633078852b | 189 | #define A5_PORT GPIOC |
| davidprentice | 0:6f633078852b | 190 | #define A5_PIN 5 |
| davidprentice | 0:6f633078852b | 191 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 192 | #define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16)) |
| davidprentice | 0:6f633078852b | 193 | #define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 194 | #define PIN_READ(port, pin) (port)->IDR & (1<<(pin)) |
| davidprentice | 0:6f633078852b | 195 | #define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2)) |
| davidprentice | 0:6f633078852b | 196 | #define PIN_OUTPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x3); else PIN_MODE4((port)->CRL, pin, 0x3); } //50MHz push-pull only 0-7 |
| davidprentice | 0:6f633078852b | 197 | #define PIN_INPUT(port, pin) {if (pin > 7) PIN_MODE4((port)->CRH, (pin&7), 0x4); else PIN_MODE4((port)->CRL, pin, 0x4); } //input |
| davidprentice | 0:6f633078852b | 198 | |
| davidprentice | 0:6f633078852b | 199 | |
| davidprentice | 0:6f633078852b | 200 | #elif defined(NUCLEO144) || ISTARGET_NUCLEO144 |
| davidprentice | 0:6f633078852b | 201 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
| davidprentice | 0:6f633078852b | 202 | #if __MBED__ |
| davidprentice | 0:6f633078852b | 203 | #warning MBED knows everything |
| davidprentice | 0:6f633078852b | 204 | #elif defined(STM32F767xx) |
| davidprentice | 0:6f633078852b | 205 | #include <STM32F7XX.h> |
| davidprentice | 0:6f633078852b | 206 | #endif |
| davidprentice | 0:6f633078852b | 207 | #define D0_PORT GPIOG |
| davidprentice | 0:6f633078852b | 208 | #define D0_PIN 9 |
| davidprentice | 0:6f633078852b | 209 | #define D1_PORT GPIOG |
| davidprentice | 0:6f633078852b | 210 | #define D1_PIN 14 |
| davidprentice | 0:6f633078852b | 211 | #define D2_PORT GPIOF |
| davidprentice | 0:6f633078852b | 212 | #define D2_PIN 15 |
| davidprentice | 0:6f633078852b | 213 | #define D3_PORT GPIOE |
| davidprentice | 0:6f633078852b | 214 | #define D3_PIN 13 |
| davidprentice | 0:6f633078852b | 215 | #define D4_PORT GPIOF |
| davidprentice | 0:6f633078852b | 216 | #define D4_PIN 14 |
| davidprentice | 0:6f633078852b | 217 | #define D5_PORT GPIOE |
| davidprentice | 0:6f633078852b | 218 | #define D5_PIN 11 |
| davidprentice | 0:6f633078852b | 219 | #define D6_PORT GPIOE |
| davidprentice | 0:6f633078852b | 220 | #define D6_PIN 9 |
| davidprentice | 0:6f633078852b | 221 | #define D7_PORT GPIOF |
| davidprentice | 0:6f633078852b | 222 | #define D7_PIN 13 |
| davidprentice | 0:6f633078852b | 223 | #define D8_PORT GPIOF |
| davidprentice | 0:6f633078852b | 224 | #define D8_PIN 12 |
| davidprentice | 0:6f633078852b | 225 | #define D9_PORT GPIOD |
| davidprentice | 0:6f633078852b | 226 | #define D9_PIN 15 |
| davidprentice | 0:6f633078852b | 227 | #define D10_PORT GPIOD |
| davidprentice | 0:6f633078852b | 228 | #define D10_PIN 14 |
| davidprentice | 0:6f633078852b | 229 | #define D11_PORT GPIOA |
| davidprentice | 0:6f633078852b | 230 | #define D11_PIN 7 |
| davidprentice | 0:6f633078852b | 231 | #define D12_PORT GPIOA |
| davidprentice | 0:6f633078852b | 232 | #define D12_PIN 6 |
| davidprentice | 0:6f633078852b | 233 | #define D13_PORT GPIOA |
| davidprentice | 0:6f633078852b | 234 | #define D13_PIN 5 |
| davidprentice | 0:6f633078852b | 235 | #define A0_PORT GPIOA |
| davidprentice | 0:6f633078852b | 236 | #define A0_PIN 3 |
| davidprentice | 0:6f633078852b | 237 | #define A1_PORT GPIOC |
| davidprentice | 0:6f633078852b | 238 | #define A1_PIN 0 |
| davidprentice | 0:6f633078852b | 239 | #define A2_PORT GPIOC |
| davidprentice | 0:6f633078852b | 240 | #define A2_PIN 3 |
| davidprentice | 0:6f633078852b | 241 | #define A3_PORT GPIOF |
| davidprentice | 0:6f633078852b | 242 | #define A3_PIN 3 |
| davidprentice | 0:6f633078852b | 243 | #define A4_PORT GPIOF |
| davidprentice | 0:6f633078852b | 244 | #define A4_PIN 5 |
| davidprentice | 0:6f633078852b | 245 | #define A5_PORT GPIOF |
| davidprentice | 0:6f633078852b | 246 | #define A5_PIN 10 |
| davidprentice | 0:6f633078852b | 247 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 248 | #define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16)) |
| davidprentice | 0:6f633078852b | 249 | #define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 250 | //#define PIN_LOW(port, pin) (port)->ODR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 251 | //#define PIN_HIGH(port, pin) (port)->ODR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 252 | #define PIN_READ(port, pin) (port)->IDR & (1<<(pin)) |
| davidprentice | 0:6f633078852b | 253 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
| davidprentice | 0:6f633078852b | 254 | #define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0) //.kbv check this |
| davidprentice | 0:6f633078852b | 255 | |
| davidprentice | 0:6f633078852b | 256 | #elif defined(NUCLEO) || ISTARGET_NUCLEO64 |
| davidprentice | 0:6f633078852b | 257 | #define PIN_MODE2(reg, pin, mode) reg=(reg&~(0x3<<((pin)<<1)))|(mode<<((pin)<<1)) |
| davidprentice | 0:6f633078852b | 258 | #if __MBED__ |
| davidprentice | 0:6f633078852b | 259 | #warning MBED knows everything |
| davidprentice | 0:6f633078852b | 260 | #elif defined(STM32F072xB) |
| davidprentice | 0:6f633078852b | 261 | #include <STM32F0XX.h> |
| davidprentice | 0:6f633078852b | 262 | #elif defined(STM32F103xB) |
| davidprentice | 0:6f633078852b | 263 | #if defined(__CC_ARM) |
| davidprentice | 0:6f633078852b | 264 | #include <STM32F10X.h> |
| davidprentice | 0:6f633078852b | 265 | #else |
| davidprentice | 0:6f633078852b | 266 | #include <STM32F1XX.h> |
| davidprentice | 0:6f633078852b | 267 | #endif |
| davidprentice | 0:6f633078852b | 268 | #elif defined(STM32L476xx) || defined(STM32L433xx) |
| davidprentice | 0:6f633078852b | 269 | #include <STM32L4XX.h> |
| davidprentice | 0:6f633078852b | 270 | #elif defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) |
| davidprentice | 0:6f633078852b | 271 | #include <STM32F4XX.h> |
| davidprentice | 0:6f633078852b | 272 | #endif |
| davidprentice | 0:6f633078852b | 273 | #define D0_PORT GPIOA |
| davidprentice | 0:6f633078852b | 274 | #define D0_PIN 3 |
| davidprentice | 0:6f633078852b | 275 | #define D1_PORT GPIOA |
| davidprentice | 0:6f633078852b | 276 | #define D1_PIN 2 |
| davidprentice | 0:6f633078852b | 277 | #define D2_PORT GPIOA |
| davidprentice | 0:6f633078852b | 278 | #define D2_PIN 10 |
| davidprentice | 0:6f633078852b | 279 | #define D3_PORT GPIOB |
| davidprentice | 0:6f633078852b | 280 | #define D3_PIN 3 |
| davidprentice | 0:6f633078852b | 281 | #define D4_PORT GPIOB |
| davidprentice | 0:6f633078852b | 282 | #define D4_PIN 5 |
| davidprentice | 0:6f633078852b | 283 | #define D5_PORT GPIOB |
| davidprentice | 0:6f633078852b | 284 | #define D5_PIN 4 |
| davidprentice | 0:6f633078852b | 285 | #define D6_PORT GPIOB |
| davidprentice | 0:6f633078852b | 286 | #define D6_PIN 10 |
| davidprentice | 0:6f633078852b | 287 | #define D7_PORT GPIOA |
| davidprentice | 0:6f633078852b | 288 | #define D7_PIN 8 |
| davidprentice | 0:6f633078852b | 289 | #define D8_PORT GPIOA |
| davidprentice | 0:6f633078852b | 290 | #define D8_PIN 9 |
| davidprentice | 0:6f633078852b | 291 | #define D9_PORT GPIOC |
| davidprentice | 0:6f633078852b | 292 | #define D9_PIN 7 |
| davidprentice | 0:6f633078852b | 293 | #define D10_PORT GPIOB |
| davidprentice | 0:6f633078852b | 294 | #define D10_PIN 6 |
| davidprentice | 0:6f633078852b | 295 | #define D11_PORT GPIOA |
| davidprentice | 0:6f633078852b | 296 | #define D11_PIN 7 |
| davidprentice | 0:6f633078852b | 297 | #define D12_PORT GPIOA |
| davidprentice | 0:6f633078852b | 298 | #define D12_PIN 6 |
| davidprentice | 0:6f633078852b | 299 | #define D13_PORT GPIOA |
| davidprentice | 0:6f633078852b | 300 | #define D13_PIN 5 |
| davidprentice | 0:6f633078852b | 301 | #define A0_PORT GPIOA |
| davidprentice | 0:6f633078852b | 302 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 303 | #define A1_PORT GPIOA |
| davidprentice | 0:6f633078852b | 304 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 305 | #define A2_PORT GPIOA |
| davidprentice | 0:6f633078852b | 306 | #define A2_PIN 4 |
| davidprentice | 0:6f633078852b | 307 | #define A3_PORT GPIOB |
| davidprentice | 0:6f633078852b | 308 | #define A3_PIN 0 |
| davidprentice | 0:6f633078852b | 309 | #define A4_PORT GPIOC |
| davidprentice | 0:6f633078852b | 310 | #define A4_PIN 1 |
| davidprentice | 0:6f633078852b | 311 | #define A5_PORT GPIOC |
| davidprentice | 0:6f633078852b | 312 | #define A5_PIN 0 |
| davidprentice | 0:6f633078852b | 313 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 314 | #define PIN_LOW(port, pin) (port)->BSRR = (1<<((pin)+16)) |
| davidprentice | 0:6f633078852b | 315 | #define PIN_HIGH(port, pin) (port)->BSRR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 316 | //#define PIN_LOW(port, pin) (port)->ODR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 317 | //#define PIN_HIGH(port, pin) (port)->ODR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 318 | #define PIN_READ(port, pin) (port)->IDR & (1<<(pin)) |
| davidprentice | 0:6f633078852b | 319 | #if defined(STM32F103xB) |
| davidprentice | 0:6f633078852b | 320 | #warning STM32F103xB ****************************** |
| davidprentice | 0:6f633078852b | 321 | #define PIN_MODE4(reg, pin, mode) reg=(reg&~(0xF<<((pin)<<2)))|(mode<<((pin)<<2)) |
| davidprentice | 0:6f633078852b | 322 | #define PIN_OUTPUT(port, pin) PIN_MODE4((port)->CRL, pin, 0x3) //50MHz push-pull only 0-7 |
| davidprentice | 0:6f633078852b | 323 | #define PIN_INPUT(port, pin) PIN_MODE4((port)->CRL, pin, 0x4) //digital input |
| davidprentice | 0:6f633078852b | 324 | #else |
| davidprentice | 0:6f633078852b | 325 | #define PIN_OUTPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x1) |
| davidprentice | 0:6f633078852b | 326 | #define PIN_INPUT(port, pin) PIN_MODE2((port)->MODER, pin, 0x0) //.kbv check this |
| davidprentice | 0:6f633078852b | 327 | #endif |
| davidprentice | 0:6f633078852b | 328 | |
| davidprentice | 1:06c4b34a5a61 | 329 | #elif __TARGET_PROCESSOR == LPC1768 || defined(TARGET_LPC1768) |
| davidprentice | 0:6f633078852b | 330 | #include <LPC17xx.h> |
| davidprentice | 0:6f633078852b | 331 | // configure macros for the control pins |
| davidprentice | 0:6f633078852b | 332 | #define D0_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 333 | #define D0_PIN 3 |
| davidprentice | 0:6f633078852b | 334 | #define D1_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 335 | #define D1_PIN 2 |
| davidprentice | 0:6f633078852b | 336 | #define D2_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 337 | #define D2_PIN 24 //p16 |
| davidprentice | 0:6f633078852b | 338 | #define D3_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 339 | #define D3_PIN 23 //p15 |
| davidprentice | 0:6f633078852b | 340 | #define D4_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 341 | #define D4_PIN 16 //p14 |
| davidprentice | 0:6f633078852b | 342 | #define D5_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 343 | #define D5_PIN 15 //p13 |
| davidprentice | 0:6f633078852b | 344 | #define D6_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 345 | #define D6_PIN 17 //p12 |
| davidprentice | 0:6f633078852b | 346 | #define D7_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 347 | #define D7_PIN 18 //p11 |
| davidprentice | 0:6f633078852b | 348 | #define D8_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 349 | #define D8_PIN 1 //p10 |
| davidprentice | 0:6f633078852b | 350 | #define D9_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 351 | #define D9_PIN 0 //p9 |
| davidprentice | 0:6f633078852b | 352 | #define D10_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 353 | #define D10_PIN 6 //p8 |
| davidprentice | 0:6f633078852b | 354 | #define D11_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 355 | #define D11_PIN 9 //p5 |
| davidprentice | 0:6f633078852b | 356 | #define D12_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 357 | #define D12_PIN 8 //p6 miso |
| davidprentice | 0:6f633078852b | 358 | #define D13_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 359 | #define D13_PIN 7 //p7 |
| davidprentice | 0:6f633078852b | 360 | #define A0_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 361 | #define A0_PIN 25 //p17 |
| davidprentice | 0:6f633078852b | 362 | #define A1_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 363 | #define A1_PIN 26 //p18 |
| davidprentice | 0:6f633078852b | 364 | #define A2_PORT LPC_GPIO1 |
| davidprentice | 0:6f633078852b | 365 | #define A2_PIN 30 //p19 |
| davidprentice | 0:6f633078852b | 366 | #define A3_PORT LPC_GPIO1 |
| davidprentice | 0:6f633078852b | 367 | #define A3_PIN 31 //p20 |
| davidprentice | 0:6f633078852b | 368 | #define A4_PORT LPC_GPIO0 |
| davidprentice | 0:6f633078852b | 369 | #define A4_PIN 10 //p28 |
| davidprentice | 0:6f633078852b | 370 | #define A5_PORT LPC_GP100 |
| davidprentice | 0:6f633078852b | 371 | #define A5_PIN 11 //p27 |
| davidprentice | 0:6f633078852b | 372 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 373 | #define PIN_LOW(port, pin) (port)->FIOCLR = (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 374 | #define PIN_HIGH(port, pin) (port)->FIOSET = (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 375 | #define PIN_OUTPUT(port, pin) (port)->FIODIR |= (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 376 | #define PIN_INPUT(port, pin) (port)->FIODIR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 377 | #define PIN_READ(port, pin) (port)->FIOPIN & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 378 | |
| davidprentice | 0:6f633078852b | 379 | #elif (defined(MK20D7) && defined(TEENSY)) || defined(TARGET_TEENSY3_1) |
| davidprentice | 0:6f633078852b | 380 | #if __MBED__ |
| davidprentice | 0:6f633078852b | 381 | #warning MBED knows everything |
| davidprentice | 0:6f633078852b | 382 | #else |
| davidprentice | 0:6f633078852b | 383 | #include <MK20D5.h> |
| davidprentice | 0:6f633078852b | 384 | #endif |
| davidprentice | 0:6f633078852b | 385 | #define D0_PORT PTB |
| davidprentice | 0:6f633078852b | 386 | #define D0_PIN 16 |
| davidprentice | 0:6f633078852b | 387 | #define D1_PORT PTB |
| davidprentice | 0:6f633078852b | 388 | #define D1_PIN 17 |
| davidprentice | 0:6f633078852b | 389 | #define D2_PORT PTD |
| davidprentice | 0:6f633078852b | 390 | #define D2_PIN 0 |
| davidprentice | 0:6f633078852b | 391 | #define D3_PORT PTA |
| davidprentice | 0:6f633078852b | 392 | #define D3_PIN 12 |
| davidprentice | 0:6f633078852b | 393 | #define D4_PORT PTA |
| davidprentice | 0:6f633078852b | 394 | #define D4_PIN 13 |
| davidprentice | 0:6f633078852b | 395 | #define D5_PORT PTD |
| davidprentice | 0:6f633078852b | 396 | #define D5_PIN 7 |
| davidprentice | 0:6f633078852b | 397 | #define D6_PORT PTD |
| davidprentice | 0:6f633078852b | 398 | #define D6_PIN 4 |
| davidprentice | 0:6f633078852b | 399 | #define D7_PORT PTD |
| davidprentice | 0:6f633078852b | 400 | #define D7_PIN 2 |
| davidprentice | 0:6f633078852b | 401 | #define D8_PORT PTD |
| davidprentice | 0:6f633078852b | 402 | #define D8_PIN 3 |
| davidprentice | 0:6f633078852b | 403 | #define D9_PORT PTC |
| davidprentice | 0:6f633078852b | 404 | #define D9_PIN 3 |
| davidprentice | 0:6f633078852b | 405 | #define D10_PORT PTC |
| davidprentice | 0:6f633078852b | 406 | #define D10_PIN 4 |
| davidprentice | 0:6f633078852b | 407 | #define D11_PORT PTC |
| davidprentice | 0:6f633078852b | 408 | #define D11_PIN 6 |
| davidprentice | 0:6f633078852b | 409 | #define D12_PORT PTC |
| davidprentice | 0:6f633078852b | 410 | #define D12_PIN 7 |
| davidprentice | 0:6f633078852b | 411 | #define D13_PORT PTC |
| davidprentice | 0:6f633078852b | 412 | #define D13_PIN 5 |
| davidprentice | 0:6f633078852b | 413 | #define A0_PORT PTD |
| davidprentice | 0:6f633078852b | 414 | #define A0_PIN 1 |
| davidprentice | 0:6f633078852b | 415 | #define A1_PORT PTC |
| davidprentice | 0:6f633078852b | 416 | #define A1_PIN 0 |
| davidprentice | 0:6f633078852b | 417 | #define A2_PORT PTB |
| davidprentice | 0:6f633078852b | 418 | #define A2_PIN 0 |
| davidprentice | 0:6f633078852b | 419 | #define A3_PORT PTB |
| davidprentice | 0:6f633078852b | 420 | #define A3_PIN 1 |
| davidprentice | 0:6f633078852b | 421 | #define A4_PORT PTB |
| davidprentice | 0:6f633078852b | 422 | #define A4_PIN 3 |
| davidprentice | 0:6f633078852b | 423 | #define A5_PORT PTB |
| davidprentice | 0:6f633078852b | 424 | #define A5_PIN 2 |
| davidprentice | 0:6f633078852b | 425 | // Shield Control macros. Deliberately avoid the IOSET registers |
| davidprentice | 0:6f633078852b | 426 | #define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 427 | #define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 428 | //#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 429 | //#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 430 | #define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 431 | #define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 432 | #define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 433 | |
| davidprentice | 0:6f633078852b | 434 | |
| davidprentice | 0:6f633078852b | 435 | #elif defined(MKL25Z4) || defined(TARGET_KL25Z) |
| davidprentice | 0:6f633078852b | 436 | #include <MKL25Z4.h> |
| davidprentice | 0:6f633078852b | 437 | #define D0_PORT PTA |
| davidprentice | 0:6f633078852b | 438 | #define D0_PIN 1 |
| davidprentice | 0:6f633078852b | 439 | #define D1_PORT PTA |
| davidprentice | 0:6f633078852b | 440 | #define D1_PIN 2 |
| davidprentice | 0:6f633078852b | 441 | #define D2_PORT PTD |
| davidprentice | 0:6f633078852b | 442 | #define D2_PIN 4 |
| davidprentice | 0:6f633078852b | 443 | #define D3_PORT PTA |
| davidprentice | 0:6f633078852b | 444 | #define D3_PIN 12 |
| davidprentice | 0:6f633078852b | 445 | #define D4_PORT PTA |
| davidprentice | 0:6f633078852b | 446 | #define D4_PIN 4 |
| davidprentice | 0:6f633078852b | 447 | #define D5_PORT PTA |
| davidprentice | 0:6f633078852b | 448 | #define D5_PIN 5 |
| davidprentice | 0:6f633078852b | 449 | #define D6_PORT PTC |
| davidprentice | 0:6f633078852b | 450 | #define D6_PIN 8 |
| davidprentice | 0:6f633078852b | 451 | #define D7_PORT PTC |
| davidprentice | 0:6f633078852b | 452 | #define D7_PIN 9 |
| davidprentice | 0:6f633078852b | 453 | #define D8_PORT PTA |
| davidprentice | 0:6f633078852b | 454 | #define D8_PIN 13 |
| davidprentice | 0:6f633078852b | 455 | #define D9_PORT PTD |
| davidprentice | 0:6f633078852b | 456 | #define D9_PIN 5 |
| davidprentice | 0:6f633078852b | 457 | #define D10_PORT PTD |
| davidprentice | 0:6f633078852b | 458 | #define D10_PIN 0 |
| davidprentice | 0:6f633078852b | 459 | #define D11_PORT PTD |
| davidprentice | 0:6f633078852b | 460 | #define D11_PIN 2 |
| davidprentice | 0:6f633078852b | 461 | #define D12_PORT PTD |
| davidprentice | 0:6f633078852b | 462 | #define D12_PIN 3 |
| davidprentice | 0:6f633078852b | 463 | #define D13_PORT PTD |
| davidprentice | 0:6f633078852b | 464 | #define D13_PIN 1 |
| davidprentice | 0:6f633078852b | 465 | #define A0_PORT PTB |
| davidprentice | 0:6f633078852b | 466 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 467 | #define A1_PORT PTB |
| davidprentice | 0:6f633078852b | 468 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 469 | #define A2_PORT PTB |
| davidprentice | 0:6f633078852b | 470 | #define A2_PIN 2 |
| davidprentice | 0:6f633078852b | 471 | #define A3_PORT PTB |
| davidprentice | 0:6f633078852b | 472 | #define A3_PIN 3 |
| davidprentice | 0:6f633078852b | 473 | #define A4_PORT PTC |
| davidprentice | 0:6f633078852b | 474 | #define A4_PIN 2 |
| davidprentice | 0:6f633078852b | 475 | #define A5_PORT PTC |
| davidprentice | 0:6f633078852b | 476 | #define A5_PIN 1 |
| davidprentice | 0:6f633078852b | 477 | // Shield Control macros. Deliberately avoid the IOSET registers |
| davidprentice | 0:6f633078852b | 478 | #define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 479 | #define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 480 | //#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 481 | //#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 482 | #define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 483 | #define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 484 | #define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 485 | |
| davidprentice | 0:6f633078852b | 486 | #elif defined(MKL26Z4) |
| davidprentice | 0:6f633078852b | 487 | #include <MKL26Z4.h> |
| davidprentice | 0:6f633078852b | 488 | #define D0_PORT PTA |
| davidprentice | 0:6f633078852b | 489 | #define D0_PIN 1 |
| davidprentice | 0:6f633078852b | 490 | #define D1_PORT PTA |
| davidprentice | 0:6f633078852b | 491 | #define D1_PIN 2 |
| davidprentice | 0:6f633078852b | 492 | #define D2_PORT PTD |
| davidprentice | 0:6f633078852b | 493 | #define D2_PIN 3 //PTD4 on KL25 |
| davidprentice | 0:6f633078852b | 494 | #define D3_PORT PTA |
| davidprentice | 0:6f633078852b | 495 | #define D3_PIN 12 |
| davidprentice | 0:6f633078852b | 496 | #define D4_PORT PTA |
| davidprentice | 0:6f633078852b | 497 | #define D4_PIN 4 |
| davidprentice | 0:6f633078852b | 498 | #define D5_PORT PTA |
| davidprentice | 0:6f633078852b | 499 | #define D5_PIN 5 |
| davidprentice | 0:6f633078852b | 500 | #define D6_PORT PTC |
| davidprentice | 0:6f633078852b | 501 | #define D6_PIN 8 |
| davidprentice | 0:6f633078852b | 502 | #define D7_PORT PTC |
| davidprentice | 0:6f633078852b | 503 | #define D7_PIN 9 |
| davidprentice | 0:6f633078852b | 504 | #define D8_PORT PTA |
| davidprentice | 0:6f633078852b | 505 | #define D8_PIN 13 |
| davidprentice | 0:6f633078852b | 506 | #define D9_PORT PTD |
| davidprentice | 0:6f633078852b | 507 | #define D9_PIN 2 //PTD5 on KL25 |
| davidprentice | 0:6f633078852b | 508 | #define D10_PORT PTD |
| davidprentice | 0:6f633078852b | 509 | #define D10_PIN 4 //PTD0 |
| davidprentice | 0:6f633078852b | 510 | #define D11_PORT PTD |
| davidprentice | 0:6f633078852b | 511 | #define D11_PIN 6 //PTD2 |
| davidprentice | 0:6f633078852b | 512 | #define D12_PORT PTD |
| davidprentice | 0:6f633078852b | 513 | #define D12_PIN 7 //PTD3 |
| davidprentice | 0:6f633078852b | 514 | #define D13_PORT PTD |
| davidprentice | 0:6f633078852b | 515 | #define D13_PIN 5 //PTD1 |
| davidprentice | 0:6f633078852b | 516 | #define A0_PORT PTB |
| davidprentice | 0:6f633078852b | 517 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 518 | #define A1_PORT PTB |
| davidprentice | 0:6f633078852b | 519 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 520 | #define A2_PORT PTB |
| davidprentice | 0:6f633078852b | 521 | #define A2_PIN 2 |
| davidprentice | 0:6f633078852b | 522 | #define A3_PORT PTB |
| davidprentice | 0:6f633078852b | 523 | #define A3_PIN 3 |
| davidprentice | 0:6f633078852b | 524 | #define A4_PORT PTC |
| davidprentice | 0:6f633078852b | 525 | #define A4_PIN 2 |
| davidprentice | 0:6f633078852b | 526 | #define A5_PORT PTC |
| davidprentice | 0:6f633078852b | 527 | #define A5_PIN 1 |
| davidprentice | 0:6f633078852b | 528 | // Shield Control macros. Deliberately avoid the IOSET registers |
| davidprentice | 0:6f633078852b | 529 | #define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 530 | #define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 531 | //#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 532 | //#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 533 | #define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 534 | #define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 535 | #define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 536 | |
| davidprentice | 0:6f633078852b | 537 | #elif defined(MKL05Z4) || defined(TARGET_KL05Z) |
| davidprentice | 0:6f633078852b | 538 | #include <MKL05Z4.h> |
| davidprentice | 0:6f633078852b | 539 | #define D0_PORT PTB |
| davidprentice | 0:6f633078852b | 540 | #define D0_PIN 2 |
| davidprentice | 0:6f633078852b | 541 | #define D1_PORT PTB |
| davidprentice | 0:6f633078852b | 542 | #define D1_PIN 1 |
| davidprentice | 0:6f633078852b | 543 | #define D2_PORT PTA |
| davidprentice | 0:6f633078852b | 544 | #define D2_PIN 11 |
| davidprentice | 0:6f633078852b | 545 | #define D3_PORT PTB |
| davidprentice | 0:6f633078852b | 546 | #define D3_PIN 5 |
| davidprentice | 0:6f633078852b | 547 | #define D4_PORT PTA |
| davidprentice | 0:6f633078852b | 548 | #define D4_PIN 10 |
| davidprentice | 0:6f633078852b | 549 | #define D5_PORT PTA |
| davidprentice | 0:6f633078852b | 550 | #define D5_PIN 12 |
| davidprentice | 0:6f633078852b | 551 | #define D6_PORT PTB |
| davidprentice | 0:6f633078852b | 552 | #define D6_PIN 6 |
| davidprentice | 0:6f633078852b | 553 | #define D7_PORT PTB |
| davidprentice | 0:6f633078852b | 554 | #define D7_PIN 7 |
| davidprentice | 0:6f633078852b | 555 | #define D8_PORT PTB |
| davidprentice | 0:6f633078852b | 556 | #define D8_PIN 13 |
| davidprentice | 0:6f633078852b | 557 | #define D9_PORT PTB |
| davidprentice | 0:6f633078852b | 558 | #define D9_PIN 5 |
| davidprentice | 0:6f633078852b | 559 | #define D10_PORT PTA |
| davidprentice | 0:6f633078852b | 560 | #define D10_PIN 0 |
| davidprentice | 0:6f633078852b | 561 | #define D11_PORT PTA |
| davidprentice | 0:6f633078852b | 562 | #define D11_PIN 2 |
| davidprentice | 0:6f633078852b | 563 | #define D12_PORT PTA |
| davidprentice | 0:6f633078852b | 564 | #define D12_PIN 3 |
| davidprentice | 0:6f633078852b | 565 | #define D13_PORT PTB |
| davidprentice | 0:6f633078852b | 566 | #define D13_PIN 1 |
| davidprentice | 0:6f633078852b | 567 | #define A0_PORT PTB |
| davidprentice | 0:6f633078852b | 568 | #define A0_PIN 8 |
| davidprentice | 0:6f633078852b | 569 | #define A1_PORT PTB |
| davidprentice | 0:6f633078852b | 570 | #define A1_PIN 9 |
| davidprentice | 0:6f633078852b | 571 | #define A2_PORT PTA |
| davidprentice | 0:6f633078852b | 572 | #define A2_PIN 8 |
| davidprentice | 0:6f633078852b | 573 | #define A3_PORT PTA |
| davidprentice | 0:6f633078852b | 574 | #define A3_PIN 0 |
| davidprentice | 0:6f633078852b | 575 | #define A4_PORT PTA |
| davidprentice | 0:6f633078852b | 576 | #define A4_PIN 9 |
| davidprentice | 0:6f633078852b | 577 | #define A5_PORT PTB |
| davidprentice | 0:6f633078852b | 578 | #define A5_PIN 13 |
| davidprentice | 0:6f633078852b | 579 | // Shield Control macros |
| davidprentice | 0:6f633078852b | 580 | //#define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 581 | //#define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 582 | #define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 583 | #define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 584 | #define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 585 | #define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 586 | #define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 587 | |
| davidprentice | 0:6f633078852b | 588 | #elif defined(MK20D5) || defined(TARGET_K20D50M) |
| davidprentice | 0:6f633078852b | 589 | #include <MK20D5.h> |
| davidprentice | 0:6f633078852b | 590 | #define D0_PORT PTE |
| davidprentice | 0:6f633078852b | 591 | #define D0_PIN 1 |
| davidprentice | 0:6f633078852b | 592 | #define D1_PORT PTE |
| davidprentice | 0:6f633078852b | 593 | #define D1_PIN 0 |
| davidprentice | 0:6f633078852b | 594 | #define D2_PORT PTA |
| davidprentice | 0:6f633078852b | 595 | #define D2_PIN 5 |
| davidprentice | 0:6f633078852b | 596 | #define D3_PORT PTD |
| davidprentice | 0:6f633078852b | 597 | #define D3_PIN 4 |
| davidprentice | 0:6f633078852b | 598 | #define D4_PORT PTC |
| davidprentice | 0:6f633078852b | 599 | #define D4_PIN 8 |
| davidprentice | 0:6f633078852b | 600 | #define D5_PORT PTA |
| davidprentice | 0:6f633078852b | 601 | #define D5_PIN 1 |
| davidprentice | 0:6f633078852b | 602 | #define D6_PORT PTC |
| davidprentice | 0:6f633078852b | 603 | #define D6_PIN 3 |
| davidprentice | 0:6f633078852b | 604 | #define D7_PORT PTC |
| davidprentice | 0:6f633078852b | 605 | #define D7_PIN 4 |
| davidprentice | 0:6f633078852b | 606 | #define D8_PORT PTA |
| davidprentice | 0:6f633078852b | 607 | #define D8_PIN 12 |
| davidprentice | 0:6f633078852b | 608 | #define D9_PORT PTA |
| davidprentice | 0:6f633078852b | 609 | #define D9_PIN 2 |
| davidprentice | 0:6f633078852b | 610 | #define D10_PORT PTC |
| davidprentice | 0:6f633078852b | 611 | #define D10_PIN 2 |
| davidprentice | 0:6f633078852b | 612 | #define D11_PORT PTD |
| davidprentice | 0:6f633078852b | 613 | #define D11_PIN 2 |
| davidprentice | 0:6f633078852b | 614 | #define D12_PORT PTD |
| davidprentice | 0:6f633078852b | 615 | #define D12_PIN 3 |
| davidprentice | 0:6f633078852b | 616 | #define D13_PORT PTD |
| davidprentice | 0:6f633078852b | 617 | #define D13_PIN 1 |
| davidprentice | 0:6f633078852b | 618 | #define A0_PORT PTC |
| davidprentice | 0:6f633078852b | 619 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 620 | #define A1_PORT PTC |
| davidprentice | 0:6f633078852b | 621 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 622 | #define A2_PORT PTD |
| davidprentice | 0:6f633078852b | 623 | #define A2_PIN 6 |
| davidprentice | 0:6f633078852b | 624 | #define A3_PORT PTD |
| davidprentice | 0:6f633078852b | 625 | #define A3_PIN 5 |
| davidprentice | 0:6f633078852b | 626 | #define A4_PORT PTB |
| davidprentice | 0:6f633078852b | 627 | #define A4_PIN 1 |
| davidprentice | 0:6f633078852b | 628 | #define A5_PORT PTB |
| davidprentice | 0:6f633078852b | 629 | #define A5_PIN 0 |
| davidprentice | 0:6f633078852b | 630 | // Shield Control macros. Deliberately avoid the IOSET registers |
| davidprentice | 0:6f633078852b | 631 | #define PIN_LOW(port, pin) (port)->PCOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 632 | #define PIN_HIGH(port, pin) (port)->PSOR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 633 | //#define PIN_LOW(port, pin) (port)->PDOR &= ~(1<<(pin)) |
| davidprentice | 0:6f633078852b | 634 | //#define PIN_HIGH(port, pin) (port)->PDOR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 635 | #define PIN_OUTPUT(port, pin) (port)->PDDR |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 636 | #define PIN_INPUT(port, pin) (port)->PDDR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 637 | #define PIN_READ(port, pin) (port)->PDIR & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 638 | |
| davidprentice | 0:6f633078852b | 639 | |
| davidprentice | 0:6f633078852b | 640 | #elif defined(ZERO) |
| davidprentice | 0:6f633078852b | 641 | #include <samd21.h> |
| davidprentice | 0:6f633078852b | 642 | // configure macros for the data pins |
| davidprentice | 0:6f633078852b | 643 | #if defined(D21_XPRO) |
| davidprentice | 0:6f633078852b | 644 | #define D0_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 645 | #define D0_PIN 9 |
| davidprentice | 0:6f633078852b | 646 | #define D1_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 647 | #define D1_PIN 8 |
| davidprentice | 0:6f633078852b | 648 | #define D2_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 649 | #define D2_PIN 14 |
| davidprentice | 0:6f633078852b | 650 | #define D3_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 651 | #define D3_PIN 2 |
| davidprentice | 0:6f633078852b | 652 | #define D4_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 653 | #define D4_PIN 5 |
| davidprentice | 0:6f633078852b | 654 | #define D5_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 655 | #define D5_PIN 21 |
| davidprentice | 0:6f633078852b | 656 | #define D6_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 657 | #define D6_PIN 15 |
| davidprentice | 0:6f633078852b | 658 | #define D7_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 659 | #define D7_PIN 17 |
| davidprentice | 0:6f633078852b | 660 | #define D8_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 661 | #define D8_PIN 6 |
| davidprentice | 0:6f633078852b | 662 | #define D9_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 663 | #define D9_PIN 7 |
| davidprentice | 0:6f633078852b | 664 | #define D10_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 665 | #define D10_PIN 5 |
| davidprentice | 0:6f633078852b | 666 | #define D11_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 667 | #define D11_PIN 6 |
| davidprentice | 0:6f633078852b | 668 | #define D12_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 669 | #define D12_PIN 4 |
| davidprentice | 0:6f633078852b | 670 | #define D13_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 671 | #define D13_PIN 7 |
| davidprentice | 0:6f633078852b | 672 | #define A0_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 673 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 674 | #define A1_PORT PORT->Group[1] |
| davidprentice | 0:6f633078852b | 675 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 676 | #define A2_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 677 | #define A2_PIN 10 |
| davidprentice | 0:6f633078852b | 678 | #define A3_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 679 | #define A3_PIN 11 |
| davidprentice | 0:6f633078852b | 680 | #define A4_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 681 | #define A4_PIN 8 |
| davidprentice | 0:6f633078852b | 682 | #define A5_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 683 | #define A5_PIN 9 |
| davidprentice | 0:6f633078852b | 684 | #elif defined(M0_PRO) |
| davidprentice | 0:6f633078852b | 685 | #define D0_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 686 | #define D0_PIN 11 |
| davidprentice | 0:6f633078852b | 687 | #define D1_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 688 | #define D1_PIN 10 |
| davidprentice | 0:6f633078852b | 689 | //M0 and Zero physical PA08 and PA14 are swapped |
| davidprentice | 0:6f633078852b | 690 | #define D2_PORT PORT->Group[0] //PA08 (Zero-D4) |
| davidprentice | 0:6f633078852b | 691 | #define D2_PIN 8 |
| davidprentice | 0:6f633078852b | 692 | #define D3_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 693 | #define D3_PIN 9 |
| davidprentice | 0:6f633078852b | 694 | #define D4_PORT PORT->Group[0] //PA14 (Zero-D2) |
| davidprentice | 0:6f633078852b | 695 | #define D4_PIN 14 |
| davidprentice | 0:6f633078852b | 696 | #define D5_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 697 | #define D5_PIN 15 |
| davidprentice | 0:6f633078852b | 698 | #define D6_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 699 | #define D6_PIN 20 |
| davidprentice | 0:6f633078852b | 700 | #define D7_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 701 | #define D7_PIN 21 |
| davidprentice | 0:6f633078852b | 702 | #define D8_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 703 | #define D8_PIN 6 |
| davidprentice | 0:6f633078852b | 704 | #define D9_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 705 | #define D9_PIN 7 |
| davidprentice | 0:6f633078852b | 706 | #define D10_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 707 | #define D10_PIN 18 |
| davidprentice | 0:6f633078852b | 708 | #define D11_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 709 | #define D11_PIN 16 |
| davidprentice | 0:6f633078852b | 710 | #define D12_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 711 | #define D12_PIN 19 |
| davidprentice | 0:6f633078852b | 712 | #define D13_PORT PORT->Group[0] |
| davidprentice | 0:6f633078852b | 713 | #define D13_PIN 17 |
| davidprentice | 0:6f633078852b | 714 | //M0 and Zero Arduino digital pin numbering is DIFFERENT |
| davidprentice | 0:6f633078852b | 715 | #define D16_PORT PORT->Group[0] //PA22 (SDA) (Zero-D20) |
| davidprentice | 0:6f633078852b | 716 | #define D16_PIN 22 |
| davidprentice | 0:6f633078852b | 717 | #define D17_PORT PORT->Group[0] //PA23 (SCL) (Zero-D21) |
| davidprentice | 0:6f633078852b | 718 | #define D17_PIN 23 |
| davidprentice | 0:6f633078852b | 719 | #define D18_PORT PORT->Group[0] //PA12 (MISO) (Zero-D22) |
| davidprentice | 0:6f633078852b | 720 | #define D18_PIN 12 |
| davidprentice | 0:6f633078852b | 721 | #define D20_PORT PORT->Group[1] //PB11 (SCK) (Zero-D24) |
| davidprentice | 0:6f633078852b | 722 | #define D20_PIN 11 |
| davidprentice | 0:6f633078852b | 723 | #define D21_PORT PORT->Group[1] //PB10 (MOSI) (Zero-D23) |
| davidprentice | 0:6f633078852b | 724 | #define D21_PIN 10 |
| davidprentice | 0:6f633078852b | 725 | #define A0_PORT PORT->Group[0] //PA02(M0-D24) (Zero-D14) |
| davidprentice | 0:6f633078852b | 726 | #define A0_PIN 2 |
| davidprentice | 0:6f633078852b | 727 | #define A1_PORT PORT->Group[1] //PB08 |
| davidprentice | 0:6f633078852b | 728 | #define A1_PIN 8 |
| davidprentice | 0:6f633078852b | 729 | #define A2_PORT PORT->Group[1] //PB09 |
| davidprentice | 0:6f633078852b | 730 | #define A2_PIN 9 |
| davidprentice | 0:6f633078852b | 731 | #define A3_PORT PORT->Group[0] //PA04 |
| davidprentice | 0:6f633078852b | 732 | #define A3_PIN 4 |
| davidprentice | 0:6f633078852b | 733 | #define A4_PORT PORT->Group[0] //PA05 |
| davidprentice | 0:6f633078852b | 734 | #define A4_PIN 5 |
| davidprentice | 0:6f633078852b | 735 | #define A5_PORT PORT->Group[1] //PB02 |
| davidprentice | 0:6f633078852b | 736 | #define A5_PIN 2 |
| davidprentice | 0:6f633078852b | 737 | |
| davidprentice | 0:6f633078852b | 738 | #endif |
| davidprentice | 0:6f633078852b | 739 | // Shield Control macros. |
| davidprentice | 0:6f633078852b | 740 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 741 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 742 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 743 | #define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 744 | #define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 745 | |
| davidprentice | 0:6f633078852b | 746 | |
| davidprentice | 0:6f633078852b | 747 | //####################################### DUE ############################ |
| davidprentice | 0:6f633078852b | 748 | #elif defined(__SAM3X8E__) |
| davidprentice | 0:6f633078852b | 749 | #include <sam3xa.h> |
| davidprentice | 0:6f633078852b | 750 | #define D0_PORT PIOA |
| davidprentice | 0:6f633078852b | 751 | #define D0_PIN 8 |
| davidprentice | 0:6f633078852b | 752 | #define D1_PORT PIOA |
| davidprentice | 0:6f633078852b | 753 | #define D1_PIN 9 |
| davidprentice | 0:6f633078852b | 754 | #define D2_PORT PIOB |
| davidprentice | 0:6f633078852b | 755 | #define D2_PIN 25 |
| davidprentice | 0:6f633078852b | 756 | #define D3_PORT PIOC |
| davidprentice | 0:6f633078852b | 757 | #define D3_PIN 28 |
| davidprentice | 0:6f633078852b | 758 | #define D4_PORT PIOC //also PA29 |
| davidprentice | 0:6f633078852b | 759 | #define D4_PIN 26 |
| davidprentice | 0:6f633078852b | 760 | #define D5_PORT PIOC |
| davidprentice | 0:6f633078852b | 761 | #define D5_PIN 25 |
| davidprentice | 0:6f633078852b | 762 | #define D6_PORT PIOC |
| davidprentice | 0:6f633078852b | 763 | #define D6_PIN 24 |
| davidprentice | 0:6f633078852b | 764 | #define D7_PORT PIOC |
| davidprentice | 0:6f633078852b | 765 | #define D7_PIN 23 |
| davidprentice | 0:6f633078852b | 766 | #define D8_PORT PIOC |
| davidprentice | 0:6f633078852b | 767 | #define D8_PIN 22 |
| davidprentice | 0:6f633078852b | 768 | #define D9_PORT PIOC |
| davidprentice | 0:6f633078852b | 769 | #define D9_PIN 21 |
| davidprentice | 0:6f633078852b | 770 | #define D10_PORT PIOC //also PA28 |
| davidprentice | 0:6f633078852b | 771 | #define D10_PIN 29 |
| davidprentice | 0:6f633078852b | 772 | #define D11_PORT PIOD |
| davidprentice | 0:6f633078852b | 773 | #define D11_PIN 7 |
| davidprentice | 0:6f633078852b | 774 | #define D12_PORT PIOD |
| davidprentice | 0:6f633078852b | 775 | #define D12_PIN 8 |
| davidprentice | 0:6f633078852b | 776 | #define D13_PORT PIOB |
| davidprentice | 0:6f633078852b | 777 | #define D13_PIN 27 |
| davidprentice | 0:6f633078852b | 778 | #define A0_PORT PIOA |
| davidprentice | 0:6f633078852b | 779 | #define A0_PIN 16 |
| davidprentice | 0:6f633078852b | 780 | #define A1_PORT PIOA |
| davidprentice | 0:6f633078852b | 781 | #define A1_PIN 24 |
| davidprentice | 0:6f633078852b | 782 | #define A2_PORT PIOA |
| davidprentice | 0:6f633078852b | 783 | #define A2_PIN 23 |
| davidprentice | 0:6f633078852b | 784 | #define A3_PORT PIOA |
| davidprentice | 0:6f633078852b | 785 | #define A3_PIN 22 |
| davidprentice | 0:6f633078852b | 786 | #define A4_PORT PIOA |
| davidprentice | 0:6f633078852b | 787 | #define A4_PIN 6 |
| davidprentice | 0:6f633078852b | 788 | #define A5_PORT PIOA |
| davidprentice | 0:6f633078852b | 789 | #define A5_PIN 4 |
| davidprentice | 0:6f633078852b | 790 | // Shield Control macros. |
| davidprentice | 0:6f633078852b | 791 | #define PIN_LOW(port, pin) (port)->PIO_CODR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 792 | #define PIN_HIGH(port, pin) (port)->PIO_SODR = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 793 | #define PIN_OUTPUT(port, pin) (port)->PIO_OER = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 794 | #define PIN_INPUT(port, pin) (port)->PIO_ODR &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 795 | #define PIN_READ(port, pin) (port)->PIO_PDSR & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 796 | |
| davidprentice | 0:6f633078852b | 797 | |
| davidprentice | 0:6f633078852b | 798 | #elif defined(__AVR_ATxmegaA4U__) |
| davidprentice | 0:6f633078852b | 799 | #include <avr/io.h> |
| davidprentice | 0:6f633078852b | 800 | // PD6, PD7 is used for USB. I could have used PORTA for bus, PORTC for MSPI, SPI and remap |
| davidprentice | 0:6f633078852b | 801 | #define D0_PORT PORTE |
| davidprentice | 0:6f633078852b | 802 | #define D0_PIN 2 |
| davidprentice | 0:6f633078852b | 803 | #define D1_PORT PORTE |
| davidprentice | 0:6f633078852b | 804 | #define D1_PIN 3 |
| davidprentice | 0:6f633078852b | 805 | #define D2_PORT PORTC |
| davidprentice | 0:6f633078852b | 806 | #define D2_PIN 2 |
| davidprentice | 0:6f633078852b | 807 | #define D3_PORT PORTC |
| davidprentice | 0:6f633078852b | 808 | #define D3_PIN 3 |
| davidprentice | 0:6f633078852b | 809 | #define D4_PORT PORTC |
| davidprentice | 0:6f633078852b | 810 | #define D4_PIN 4 |
| davidprentice | 0:6f633078852b | 811 | #define D5_PORT PORTC |
| davidprentice | 0:6f633078852b | 812 | #define D5_PIN 5 |
| davidprentice | 0:6f633078852b | 813 | #define D6_PORT PORTC |
| davidprentice | 0:6f633078852b | 814 | #define D6_PIN 6 |
| davidprentice | 0:6f633078852b | 815 | #define D7_PORT PORTC |
| davidprentice | 0:6f633078852b | 816 | #define D7_PIN 7 |
| davidprentice | 0:6f633078852b | 817 | #define D8_PORT PORTC |
| davidprentice | 0:6f633078852b | 818 | #define D8_PIN 0 |
| davidprentice | 0:6f633078852b | 819 | #define D9_PORT PORTC |
| davidprentice | 0:6f633078852b | 820 | #define D9_PIN 1 |
| davidprentice | 0:6f633078852b | 821 | #define D10_PORT PORTD |
| davidprentice | 0:6f633078852b | 822 | #define D10_PIN 0 |
| davidprentice | 0:6f633078852b | 823 | #define D11_PORT PORTD |
| davidprentice | 0:6f633078852b | 824 | #define D11_PIN 3 |
| davidprentice | 0:6f633078852b | 825 | #define D12_PORT PORTD |
| davidprentice | 0:6f633078852b | 826 | #define D12_PIN 2 |
| davidprentice | 0:6f633078852b | 827 | #define D13_PORT PORTD |
| davidprentice | 0:6f633078852b | 828 | #define D13_PIN 1 |
| davidprentice | 0:6f633078852b | 829 | #define A0_PORT PORTB |
| davidprentice | 0:6f633078852b | 830 | #define A0_PIN 0 |
| davidprentice | 0:6f633078852b | 831 | #define A1_PORT PORTB |
| davidprentice | 0:6f633078852b | 832 | #define A1_PIN 1 |
| davidprentice | 0:6f633078852b | 833 | #define A2_PORT PORTB |
| davidprentice | 0:6f633078852b | 834 | #define A2_PIN 2 |
| davidprentice | 0:6f633078852b | 835 | #define A3_PORT PORTB |
| davidprentice | 0:6f633078852b | 836 | #define A3_PIN 3 |
| davidprentice | 0:6f633078852b | 837 | #define A4_PORT PORTE |
| davidprentice | 0:6f633078852b | 838 | #define A4_PIN 0 |
| davidprentice | 0:6f633078852b | 839 | #define A5_PORT PORTE |
| davidprentice | 0:6f633078852b | 840 | #define A5_PIN 1 |
| davidprentice | 0:6f633078852b | 841 | // Shield Control macros. |
| davidprentice | 0:6f633078852b | 842 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 843 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 844 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 845 | #define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 846 | #define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 847 | |
| davidprentice | 0:6f633078852b | 848 | |
| davidprentice | 0:6f633078852b | 849 | #elif defined(__AVR_ATmega4809__) && defined(ARDUINO_AVR_NANO_EVERY) //NANO-EVERY |
| davidprentice | 0:6f633078852b | 850 | #warning using NANO-EVERY |
| davidprentice | 0:6f633078852b | 851 | #include <avr/io.h> |
| davidprentice | 0:6f633078852b | 852 | #define D0_PORT PORTC |
| davidprentice | 0:6f633078852b | 853 | #define D0_PIN 5 |
| davidprentice | 0:6f633078852b | 854 | #define D1_PORT PORTC |
| davidprentice | 0:6f633078852b | 855 | #define D1_PIN 4 |
| davidprentice | 0:6f633078852b | 856 | #define D2_PORT PORTA |
| davidprentice | 0:6f633078852b | 857 | #define D2_PIN 0 |
| davidprentice | 0:6f633078852b | 858 | #define D3_PORT PORTF |
| davidprentice | 0:6f633078852b | 859 | #define D3_PIN 5 |
| davidprentice | 0:6f633078852b | 860 | #define D4_PORT PORTC |
| davidprentice | 0:6f633078852b | 861 | #define D4_PIN 6 |
| davidprentice | 0:6f633078852b | 862 | #define D5_PORT PORTB |
| davidprentice | 0:6f633078852b | 863 | #define D5_PIN 2 |
| davidprentice | 0:6f633078852b | 864 | #define D6_PORT PORTF |
| davidprentice | 0:6f633078852b | 865 | #define D6_PIN 4 |
| davidprentice | 0:6f633078852b | 866 | #define D7_PORT PORTA |
| davidprentice | 0:6f633078852b | 867 | #define D7_PIN 1 |
| davidprentice | 0:6f633078852b | 868 | #define D8_PORT PORTE |
| davidprentice | 0:6f633078852b | 869 | #define D8_PIN 3 |
| davidprentice | 0:6f633078852b | 870 | #define D9_PORT PORTB |
| davidprentice | 0:6f633078852b | 871 | #define D9_PIN 0 |
| davidprentice | 0:6f633078852b | 872 | #define D10_PORT PORTB //PB1 |
| davidprentice | 0:6f633078852b | 873 | #define D10_PIN 1 |
| davidprentice | 0:6f633078852b | 874 | #define D11_PORT PORTE |
| davidprentice | 0:6f633078852b | 875 | #define D11_PIN 0 |
| davidprentice | 0:6f633078852b | 876 | #define D12_PORT PORTE |
| davidprentice | 0:6f633078852b | 877 | #define D12_PIN 1 |
| davidprentice | 0:6f633078852b | 878 | #define D13_PORT PORTE |
| davidprentice | 0:6f633078852b | 879 | #define D13_PIN 2 |
| davidprentice | 0:6f633078852b | 880 | #define A0_PORT PORTD |
| davidprentice | 0:6f633078852b | 881 | #define A0_PIN 3 |
| davidprentice | 0:6f633078852b | 882 | #define A1_PORT PORTD |
| davidprentice | 0:6f633078852b | 883 | #define A1_PIN 2 |
| davidprentice | 0:6f633078852b | 884 | #define A2_PORT PORTD |
| davidprentice | 0:6f633078852b | 885 | #define A2_PIN 1 |
| davidprentice | 0:6f633078852b | 886 | #define A3_PORT PORTD |
| davidprentice | 0:6f633078852b | 887 | #define A3_PIN 0 |
| davidprentice | 0:6f633078852b | 888 | #define A4_PORT PORTF |
| davidprentice | 0:6f633078852b | 889 | #define A4_PIN 2 |
| davidprentice | 0:6f633078852b | 890 | #define A5_PORT PORTF |
| davidprentice | 0:6f633078852b | 891 | #define A5_PIN 3 |
| davidprentice | 0:6f633078852b | 892 | #define A6_PORT PORTD |
| davidprentice | 0:6f633078852b | 893 | #define A6_PIN 5 |
| davidprentice | 0:6f633078852b | 894 | #define A7_PORT PORTD |
| davidprentice | 0:6f633078852b | 895 | #define A7_PIN 4 |
| davidprentice | 0:6f633078852b | 896 | // Shield Control macros. |
| davidprentice | 0:6f633078852b | 897 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 898 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 899 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 900 | #define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 901 | #define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 902 | |
| davidprentice | 0:6f633078852b | 903 | |
| davidprentice | 0:6f633078852b | 904 | #elif defined(__AVR_ATmega4809__) //XPRO_4809 with XPRO_SHIELD_ADAPTER |
| davidprentice | 0:6f633078852b | 905 | #warning using XPRO_4809 with XPRO_SHIELD_ADAPTER |
| davidprentice | 0:6f633078852b | 906 | #include <avr/io.h> |
| davidprentice | 0:6f633078852b | 907 | #define D0_PORT PORTA |
| davidprentice | 0:6f633078852b | 908 | #define D0_PIN 1 |
| davidprentice | 0:6f633078852b | 909 | #define D1_PORT PORTA |
| davidprentice | 0:6f633078852b | 910 | #define D1_PIN 0 |
| davidprentice | 0:6f633078852b | 911 | #define D2_PORT PORTB |
| davidprentice | 0:6f633078852b | 912 | #define D2_PIN 2 |
| davidprentice | 0:6f633078852b | 913 | #define D3_PORT PORTC |
| davidprentice | 0:6f633078852b | 914 | #define D3_PIN 6 |
| davidprentice | 0:6f633078852b | 915 | #define D4_PORT PORTC |
| davidprentice | 0:6f633078852b | 916 | #define D4_PIN 7 |
| davidprentice | 0:6f633078852b | 917 | #define D5_PORT PORTF |
| davidprentice | 0:6f633078852b | 918 | #define D5_PIN 6 |
| davidprentice | 0:6f633078852b | 919 | #define D6_PORT PORTB |
| davidprentice | 0:6f633078852b | 920 | #define D6_PIN 3 |
| davidprentice | 0:6f633078852b | 921 | #define D7_PORT PORTE |
| davidprentice | 0:6f633078852b | 922 | #define D7_PIN 1 |
| davidprentice | 0:6f633078852b | 923 | #define D8_PORT PORTA |
| davidprentice | 0:6f633078852b | 924 | #define D8_PIN 2 |
| davidprentice | 0:6f633078852b | 925 | #define D9_PORT PORTA |
| davidprentice | 0:6f633078852b | 926 | #define D9_PIN 3 |
| davidprentice | 0:6f633078852b | 927 | #define D10_PORT PORTA |
| davidprentice | 0:6f633078852b | 928 | #define D10_PIN 7 |
| davidprentice | 0:6f633078852b | 929 | #define D11_PORT PORTA //PC5 |
| davidprentice | 0:6f633078852b | 930 | #define D11_PIN 4 |
| davidprentice | 0:6f633078852b | 931 | #define D12_PORT PORTA |
| davidprentice | 0:6f633078852b | 932 | #define D12_PIN 5 |
| davidprentice | 0:6f633078852b | 933 | #define D13_PORT PORTA |
| davidprentice | 0:6f633078852b | 934 | #define D13_PIN 6 |
| davidprentice | 0:6f633078852b | 935 | #define A0_PORT PORTD |
| davidprentice | 0:6f633078852b | 936 | #define A0_PIN 2 |
| davidprentice | 0:6f633078852b | 937 | #define A1_PORT PORTD |
| davidprentice | 0:6f633078852b | 938 | #define A1_PIN 3 |
| davidprentice | 0:6f633078852b | 939 | #define A2_PORT PORTD |
| davidprentice | 0:6f633078852b | 940 | #define A2_PIN 4 |
| davidprentice | 0:6f633078852b | 941 | #define A3_PORT PORTD |
| davidprentice | 0:6f633078852b | 942 | #define A3_PIN 5 |
| davidprentice | 0:6f633078852b | 943 | #define A4_PORT PORTC |
| davidprentice | 0:6f633078852b | 944 | #define A4_PIN 2 |
| davidprentice | 0:6f633078852b | 945 | #define A5_PORT PORTC |
| davidprentice | 0:6f633078852b | 946 | #define A5_PIN 3 |
| davidprentice | 0:6f633078852b | 947 | // Shield Control macros. |
| davidprentice | 0:6f633078852b | 948 | #define PIN_LOW(port, pin) (port).OUTCLR.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 949 | #define PIN_HIGH(port, pin) (port).OUTSET.reg = (1<<(pin)) |
| davidprentice | 0:6f633078852b | 950 | #define PIN_OUTPUT(port, pin) (port).DIR.reg |= (1<<(pin)) |
| davidprentice | 0:6f633078852b | 951 | #define PIN_INPUT(port, pin) (port).DIR.reg &= ~(1u<<(pin)) |
| davidprentice | 0:6f633078852b | 952 | #define PIN_READ(port, pin) (port).IN.reg & (1u<<(pin)) |
| davidprentice | 0:6f633078852b | 953 | |
| davidprentice | 0:6f633078852b | 954 | |
| davidprentice | 0:6f633078852b | 955 | #elif defined(__AVR_ATtiny1634__) |
| davidprentice | 0:6f633078852b | 956 | #include <avr/io.h> |
| davidprentice | 0:6f633078852b | 957 | // |
| davidprentice | 0:6f633078852b | 958 | #define D0_PORT PORTA //PA7 |
| davidprentice | 0:6f633078852b | 959 | #define D0_PIN 7 |
| davidprentice | 0:6f633078852b | 960 | #define D1_PORT PORTB //PB0 |
| davidprentice | 0:6f633078852b | 961 | #define D1_PIN 0 |
| davidprentice | 0:6f633078852b | 962 | #define D2_PORT PORTC //PC2 |
| davidprentice | 0:6f633078852b | 963 | #define D2_PIN 2 |
| davidprentice | 0:6f633078852b | 964 | #define D3_PORT PORTA //PA3 |
| davidprentice | 0:6f633078852b | 965 | #define D3_PIN 3 |
| davidprentice | 0:6f633078852b | 966 | #define D4_PORT PORTA //PA4 |
| davidprentice | 0:6f633078852b | 967 | #define D4_PIN 4 |
| davidprentice | 0:6f633078852b | 968 | #define D5_PORT PORTC //PC4 |
| davidprentice | 0:6f633078852b | 969 | #define D5_PIN 4 |
| davidprentice | 0:6f633078852b | 970 | #define D6_PORT PORTA //PA1 |
| davidprentice | 0:6f633078852b | 971 | #define D6_PIN 1 |
| davidprentice | 0:6f633078852b | 972 | #define D7_PORT PORTA //PA0 |
| davidprentice | 0:6f633078852b | 973 | #define D7_PIN 0 |
| davidprentice | 0:6f633078852b | 974 | #define D8_PORT PORTA //PA2 |
| davidprentice | 0:6f633078852b | 975 | #define D8_PIN 2 |
| davidprentice | 0:6f633078852b | 976 | #define D9_PORT PORTC //PC5 |
| davidprentice | 0:6f633078852b | 977 | #define D9_PIN 5 |
| davidprentice | 0:6f633078852b | 978 | #define D10_PORT PORTA //PA6 |
| davidprentice | 0:6f633078852b | 979 | #define D10_PIN 6 |
| davidprentice | 0:6f633078852b | 980 | #define D11_PORT PORTB //PB2 |
| davidprentice | 0:6f633078852b | 981 | #define D11_PIN 2 |
| davidprentice | 0:6f633078852b | 982 | #define D12_PORT PORTB //PB1 |
| davidprentice | 0:6f633078852b | 983 | #define D12_PIN 1 |
| davidprentice | 0:6f633078852b | 984 | #define D13_PORT PORTC //PC1 |
| davidprentice | 0:6f633078852b | 985 | #define D13_PIN 1 |
| davidprentice | 0:6f633078852b | 986 | #define A0_PORT PORTB //PB3 |
| davidprentice | 0:6f633078852b | 987 | #define A0_PIN 3 |
| davidprentice | 0:6f633078852b | 988 | #define A1_PORT PORTC //PC0 |
| davidprentice | 0:6f633078852b | 989 | #define A1_PIN 0 |
| davidprentice | 0:6f633078852b | 990 | #define A2_PORT PORTA //PA5 |
| davidprentice | 0:6f633078852b | 991 | #define A2_PIN 5 |
| davidprentice | 0:6f633078852b | 992 | #define A3_PORT PORTB //PB2 |
| davidprentice | 0:6f633078852b | 993 | #define A3_PIN 2 |
| davidprentice | 0:6f633078852b | 994 | #define A4_PORT PORTB //PB1 |
| davidprentice | 0:6f633078852b | 995 | #define A4_PIN 1 |
| davidprentice | 0:6f633078852b | 996 | #define A5_PORT PORTC //PC1 |
| davidprentice | 0:6f633078852b | 997 | #define A5_PIN 1 |
| davidprentice | 0:6f633078852b | 998 | #else |
| davidprentice | 0:6f633078852b | 999 | #error MCU unselected |
| davidprentice | 0:6f633078852b | 1000 | #endif // MCUs |
| davidprentice | 0:6f633078852b | 1001 | |
| davidprentice | 0:6f633078852b | 1002 | #endif //PIN_SHIELD_1_H |
| davidprentice | 0:6f633078852b | 1003 | #if 0 |
| davidprentice | 0:6f633078852b | 1004 | #if defined(M0_PRO) |
| davidprentice | 0:6f633078852b | 1005 | #endif |
| davidprentice | 0:6f633078852b | 1006 | #if defined(D21_XPRO) |
| davidprentice | 0:6f633078852b | 1007 | #endif |
| davidprentice | 0:6f633078852b | 1008 | #endif |
| davidprentice | 0:6f633078852b | 1009 |