USBHAL_STM32F4.cpp

00001 /* Copyright (c) 2010-2011 mbed.org, MIT License
00002 *
00003 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
00004 * and associated documentation files (the "Software"), to deal in the Software without
00005 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
00006 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
00007 * Software is furnished to do so, subject to the following conditions:
00008 *
00009 * The above copyright notice and this permission notice shall be included in all copies or
00010 * substantial portions of the Software.
00011 *
00012 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
00013 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
00014 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
00015 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00016 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
00017 */
00018 
00019 #if defined(TARGET_STM32F4)
00020 
00021 #include "USBHAL.h"
00022 #include "USBRegs_STM32.h"
00023 #include "pinmap.h"
00024 
00025 USBHAL * USBHAL::instance;
00026 
00027 static volatile int epComplete = 0;
00028 
00029 static uint32_t bufferEnd = 0;
00030 static const uint32_t rxFifoSize = 512;
00031 static uint32_t rxFifoCount = 0;
00032 
00033 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
00034 
00035 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
00036     return 0;
00037 }
00038 
00039 USBHAL::USBHAL(void) {
00040     NVIC_DisableIRQ(OTG_FS_IRQn);
00041     epCallback[0] = &USBHAL::EP1_OUT_callback;
00042     epCallback[1] = &USBHAL::EP1_IN_callback;
00043     epCallback[2] = &USBHAL::EP2_OUT_callback;
00044     epCallback[3] = &USBHAL::EP2_IN_callback;
00045     epCallback[4] = &USBHAL::EP3_OUT_callback;
00046     epCallback[5] = &USBHAL::EP3_IN_callback;
00047 
00048     // Enable power and clocking
00049     RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
00050 
00051 #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F429ZI)
00052     //pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS)); //SOF
00053     //pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS)); //vbus
00054     //pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)); //Id
00055     pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
00056     pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
00057 #else
00058     pin_function(PA_8, STM_PIN_DATA(2, 10));
00059     pin_function(PA_9, STM_PIN_DATA(0, 0));
00060     pin_function(PA_10, STM_PIN_DATA(2, 10));
00061     pin_function(PA_11, STM_PIN_DATA(2, 10));
00062     pin_function(PA_12, STM_PIN_DATA(2, 10));
00063 
00064     // Set ID pin to open drain with pull-up resistor
00065     pin_mode(PA_10, OpenDrain);
00066     GPIOA->PUPDR &= ~(0x3 << 20);
00067     GPIOA->PUPDR |= 1 << 20;
00068 
00069     // Set VBUS pin to open drain
00070     pin_mode(PA_9, OpenDrain);
00071 #endif
00072     
00073     //enable USB OTG clock
00074     RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
00075 
00076     // Enable interrupts
00077     OTG_FS->GREGS.GAHBCFG |= (1 << 0);
00078 
00079     // Turnaround time to maximum value - too small causes packet loss
00080     OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
00081     OTG_FS->GREGS.GUSBCFG |= (1 << 30); // set FMOD to force device mode
00082 
00083 
00084     // Unmask global interrupts
00085     OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
00086                              (1 << 4) | // RX FIFO not empty
00087                              (1 << 12); // USB reset
00088 
00089     OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
00090                           (1 << 2); // Non-zero-length status OUT handshake
00091 
00092     OTG_FS->GREGS.GCCFG |= (1 << 21) | // Disable VBUS sensing
00093                            (1 << 16); // Power Up                   
00094 
00095     instance = this;
00096     NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
00097     NVIC_SetPriority(OTG_FS_IRQn, 1);
00098 }
00099 
00100 USBHAL::~USBHAL(void) {
00101 }
00102 
00103 void USBHAL::connect(void) {
00104     NVIC_EnableIRQ(OTG_FS_IRQn);
00105 }
00106 
00107 void USBHAL::disconnect(void) {
00108     NVIC_DisableIRQ(OTG_FS_IRQn);
00109 }
00110 
00111 void USBHAL::configureDevice(void) {
00112     // Not needed
00113 }
00114 
00115 void USBHAL::unconfigureDevice(void) {
00116     // Not needed
00117 }
00118 
00119 void USBHAL::setAddress(uint8_t address) {
00120     OTG_FS->DREGS.DCFG |= (address << 4);
00121     EP0write(0, 0);
00122 }
00123 
00124 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
00125                              uint32_t flags) {
00126     uint32_t epIndex = endpoint >> 1;
00127 
00128     uint32_t type;
00129     switch (endpoint) {
00130         case EP0IN:
00131         case EP0OUT:
00132             type = 0;
00133             break;
00134         case EPISO_IN:
00135         case EPISO_OUT:
00136             type = 1;
00137         case EPBULK_IN:
00138         case EPBULK_OUT:
00139             type = 2;
00140             break;
00141         case EPINT_IN:
00142         case EPINT_OUT:
00143             type = 3;
00144             break;
00145     }
00146 
00147     // Generic in or out EP controls
00148     uint32_t control = (maxPacket << 0) | // Packet size
00149                        (1 << 15) | // Active endpoint
00150                        (type << 18); // Endpoint type
00151 
00152     if (endpoint & 0x1) { // In Endpoint
00153         // Set up the Tx FIFO
00154         if (endpoint == EP0IN) {
00155             OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
00156                                                (bufferEnd << 0);
00157         }
00158         else {
00159             OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
00160                                                  (bufferEnd << 0);
00161         }
00162         bufferEnd += maxPacket >> 2;
00163 
00164         // Set the In EP specific control settings
00165         if (endpoint != EP0IN) {
00166             control |= (1 << 28); // SD0PID
00167         }
00168 
00169         control |= (epIndex << 22) | // TxFIFO index
00170                    (1 << 27); // SNAK
00171         OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
00172 
00173         // Unmask the interrupt
00174         OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
00175     }
00176     else { // Out endpoint
00177         // Set the out EP specific control settings
00178         control |= (1 << 26); // CNAK
00179         OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
00180 
00181         // Unmask the interrupt
00182         OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
00183     }
00184     return true;
00185 }
00186 
00187 // read setup packet
00188 void USBHAL::EP0setup(uint8_t *buffer) {
00189     memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
00190 }
00191 
00192 void USBHAL::EP0readStage(void) {
00193 }
00194 
00195 void USBHAL::EP0read(void) {
00196 }
00197 
00198 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
00199     uint32_t* buffer32 = (uint32_t *) buffer;
00200     uint32_t length = rxFifoCount;
00201     for (uint32_t i = 0; i < length; i += 4) {
00202         buffer32[i >> 2] = OTG_FS->FIFO[0][0];
00203     }
00204 
00205     rxFifoCount = 0;
00206     return length;
00207 }
00208 
00209 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
00210     endpointWrite(0, buffer, size);
00211 }
00212 
00213 void USBHAL::EP0getWriteResult(void) {
00214 }
00215 
00216 void USBHAL::EP0stall(void) {
00217     // If we stall the out endpoint here then we have problems transferring
00218     // and setup requests after the (stalled) get device qualifier requests.
00219     // TODO: Find out if this is correct behavior, or whether we are doing
00220     // something else wrong
00221     stallEndpoint(EP0IN);
00222 //    stallEndpoint(EP0OUT);
00223 }
00224 
00225 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
00226     uint32_t epIndex = endpoint >> 1;
00227     uint32_t size = (1 << 19) | // 1 packet
00228                     (maximumSize << 0); // Packet size
00229 //    if (endpoint == EP0OUT) {
00230         size |= (1 << 29); // 1 setup packet
00231 //    }
00232     OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
00233     OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
00234                                            (1 << 26); // Clear NAK
00235 
00236     epComplete &= ~(1 << endpoint);
00237     return EP_PENDING;
00238 }
00239 
00240 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
00241     if (!(epComplete & (1 << endpoint))) {
00242         return EP_PENDING;
00243     }
00244 
00245     uint32_t* buffer32 = (uint32_t *) buffer;
00246     uint32_t length = rxFifoCount;
00247     for (uint32_t i = 0; i < length; i += 4) {
00248         buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
00249     }
00250     rxFifoCount = 0;
00251     *bytesRead = length;
00252     return EP_COMPLETED;
00253 }
00254 
00255 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
00256     uint32_t epIndex = endpoint >> 1;
00257     OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
00258                                           (size << 0); // Size of packet
00259     OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
00260                                           (1 << 26); // CNAK
00261     OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
00262 
00263     while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
00264 
00265     for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
00266         OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
00267     }
00268 
00269     epComplete &= ~(1 << endpoint);
00270 
00271     return EP_PENDING;
00272 }
00273 
00274 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
00275     if (epComplete & (1 << endpoint)) {
00276         epComplete &= ~(1 << endpoint);
00277         return EP_COMPLETED;
00278     }
00279 
00280     return EP_PENDING;
00281 }
00282 
00283 void USBHAL::stallEndpoint(uint8_t endpoint) {
00284     if (endpoint & 0x1) { // In EP
00285         OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
00286                                                     (1 << 21); // Stall
00287     }
00288     else {  // Out EP
00289         OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
00290         OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
00291                                                      (1 << 21); // Stall
00292     }
00293 }
00294 
00295 void USBHAL::unstallEndpoint(uint8_t endpoint) {
00296 
00297 }
00298 
00299 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
00300     return false;
00301 }
00302 
00303 void USBHAL::remoteWakeup(void) {
00304 }
00305 
00306 
00307 void USBHAL::_usbisr(void) {
00308     instance->usbisr();
00309 }
00310 
00311 
00312 void USBHAL::usbisr(void) {
00313     if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
00314         suspendStateChanged(1);
00315     };
00316 
00317     if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
00318         suspendStateChanged(0);
00319 
00320         // Set SNAK bits
00321         OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
00322         OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
00323         OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
00324         OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
00325 
00326         OTG_FS->DREGS.DIEPMSK = (1 << 0);
00327 
00328         bufferEnd = 0;
00329 
00330         // Set the receive FIFO size
00331         OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
00332         bufferEnd += rxFifoSize >> 2;
00333 
00334         // Create the endpoints, and wait for setup packets on out EP0
00335         realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
00336         realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
00337         endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
00338 
00339         OTG_FS->GREGS.GINTSTS = (1 << 12);
00340     }
00341 
00342     if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
00343         uint32_t status = OTG_FS->GREGS.GRXSTSP;
00344 
00345         uint32_t endpoint = (status & 0xF) << 1;
00346         uint32_t length = (status >> 4) & 0x7FF;
00347         uint32_t type = (status >> 17) & 0xF;
00348 
00349         rxFifoCount = length;
00350 
00351         if (type == 0x6) {
00352             // Setup packet
00353             for (uint32_t i=0; i<length; i+=4) {
00354                 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
00355             }
00356             rxFifoCount = 0;
00357         }
00358 
00359         if (type == 0x4) {
00360             // Setup complete
00361             EP0setupCallback();
00362             endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
00363         }
00364 
00365         if (type == 0x2) {
00366             // Out packet
00367             if (endpoint == EP0OUT) {
00368                 EP0out();
00369             }
00370             else {
00371                 epComplete |= (1 << endpoint);
00372                 if ((instance->*(epCallback[endpoint - 2]))()) {
00373                     epComplete &= (1 << endpoint);
00374                 }
00375             }
00376         }
00377 
00378         for (uint32_t i=0; i<rxFifoCount; i+=4) {
00379             (void) OTG_FS->FIFO[0][0];
00380         }
00381         OTG_FS->GREGS.GINTSTS = (1 << 4);
00382     }
00383 
00384     if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
00385         // Loop through the in endpoints
00386         for (uint32_t i=0; i<4; i++) {
00387             if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
00388 
00389                 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
00390                     // If the Tx FIFO is empty on EP0 we need to send a further
00391                     // packet, so call EP0in()
00392                     if (i == 0) {
00393                         EP0in();
00394                     }
00395                     // Clear the interrupt
00396                     OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
00397                     // Stop firing Tx empty interrupts
00398                     // Will get turned on again if another write is called
00399                     OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
00400                 }
00401 
00402                 // If the transfer is complete
00403                 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
00404                     epComplete |= (1 << (1 + (i << 1)));
00405                     OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
00406                 }
00407             }
00408         }
00409         OTG_FS->GREGS.GINTSTS = (1 << 18);
00410     }
00411 
00412     if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
00413         SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
00414         OTG_FS->GREGS.GINTSTS = (1 << 3);
00415     }
00416 }
00417 
00418 
00419 #endif