Daniele Lacamera / USB_Ethernet

CDC/ECM driver for mbed, based on USBDevice by mbed-official. Uses PicoTCP to access Ethernet USB device. License: GPLv2

Dependents:   USBEthernet_TEST

Fork of USB_Ethernet by Daniele Lacamera

USBDevice/USBHAL_KL25Z.cpp@2:540f6e142d59, 2013-08-03 (annotated)

Committer:
daniele
Date:
Sat Aug 03 13:16:14 2013 +0000
Revision:
2:540f6e142d59
Moved to single package

Who changed what in which revision?

UserRevisionLine numberNew contents of line
daniele 2:540f6e142d59 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
daniele 2:540f6e142d59 2 *
daniele 2:540f6e142d59 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
daniele 2:540f6e142d59 4 * and associated documentation files (the "Software"), to deal in the Software without
daniele 2:540f6e142d59 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
daniele 2:540f6e142d59 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
daniele 2:540f6e142d59 7 * Software is furnished to do so, subject to the following conditions:
daniele 2:540f6e142d59 8 *
daniele 2:540f6e142d59 9 * The above copyright notice and this permission notice shall be included in all copies or
daniele 2:540f6e142d59 10 * substantial portions of the Software.
daniele 2:540f6e142d59 11 *
daniele 2:540f6e142d59 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
daniele 2:540f6e142d59 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
daniele 2:540f6e142d59 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
daniele 2:540f6e142d59 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
daniele 2:540f6e142d59 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
daniele 2:540f6e142d59 17 */
daniele 2:540f6e142d59 18
daniele 2:540f6e142d59 19 #if defined(TARGET_KL25Z)
daniele 2:540f6e142d59 20
daniele 2:540f6e142d59 21 #include "USBHAL.h"
daniele 2:540f6e142d59 22
daniele 2:540f6e142d59 23 USBHAL * USBHAL::instance;
daniele 2:540f6e142d59 24
daniele 2:540f6e142d59 25 static volatile int epComplete = 0;
daniele 2:540f6e142d59 26
daniele 2:540f6e142d59 27 // Convert physical endpoint number to register bit
daniele 2:540f6e142d59 28 #define EP(endpoint) (1<<(endpoint))
daniele 2:540f6e142d59 29
daniele 2:540f6e142d59 30 // Convert physical to logical
daniele 2:540f6e142d59 31 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
daniele 2:540f6e142d59 32
daniele 2:540f6e142d59 33 // Get endpoint direction
daniele 2:540f6e142d59 34 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
daniele 2:540f6e142d59 35 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
daniele 2:540f6e142d59 36
daniele 2:540f6e142d59 37 #define BD_OWN_MASK (1<<7)
daniele 2:540f6e142d59 38 #define BD_DATA01_MASK (1<<6)
daniele 2:540f6e142d59 39 #define BD_KEEP_MASK (1<<5)
daniele 2:540f6e142d59 40 #define BD_NINC_MASK (1<<4)
daniele 2:540f6e142d59 41 #define BD_DTS_MASK (1<<3)
daniele 2:540f6e142d59 42 #define BD_STALL_MASK (1<<2)
daniele 2:540f6e142d59 43
daniele 2:540f6e142d59 44 #define TX 1
daniele 2:540f6e142d59 45 #define RX 0
daniele 2:540f6e142d59 46 #define ODD 0
daniele 2:540f6e142d59 47 #define EVEN 1
daniele 2:540f6e142d59 48 // this macro waits a physical endpoint number
daniele 2:540f6e142d59 49 #define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
daniele 2:540f6e142d59 50
daniele 2:540f6e142d59 51 #define SETUP_TOKEN 0x0D
daniele 2:540f6e142d59 52 #define IN_TOKEN 0x09
daniele 2:540f6e142d59 53 #define OUT_TOKEN 0x01
daniele 2:540f6e142d59 54 #define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
daniele 2:540f6e142d59 55
daniele 2:540f6e142d59 56 // for each endpt: 8 bytes
daniele 2:540f6e142d59 57 typedef struct BDT {
daniele 2:540f6e142d59 58 uint8_t info; // BD[0:7]
daniele 2:540f6e142d59 59 uint8_t dummy; // RSVD: BD[8:15]
daniele 2:540f6e142d59 60 uint16_t byte_count; // BD[16:32]
daniele 2:540f6e142d59 61 uint32_t address; // Addr
daniele 2:540f6e142d59 62 } BDT;
daniele 2:540f6e142d59 63
daniele 2:540f6e142d59 64
daniele 2:540f6e142d59 65 // there are:
daniele 2:540f6e142d59 66 // * 16 bidirectionnal endpt -> 32 physical endpt
daniele 2:540f6e142d59 67 // * as there are ODD and EVEN buffer -> 32*2 bdt
daniele 2:540f6e142d59 68 __attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
daniele 2:540f6e142d59 69 uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
daniele 2:540f6e142d59 70 uint8_t * endpoint_buffer_iso[2*2];
daniele 2:540f6e142d59 71
daniele 2:540f6e142d59 72 static uint8_t set_addr = 0;
daniele 2:540f6e142d59 73 static uint8_t addr = 0;
daniele 2:540f6e142d59 74
daniele 2:540f6e142d59 75 static uint32_t Data1 = 0x55555555;
daniele 2:540f6e142d59 76
daniele 2:540f6e142d59 77 static uint32_t frameNumber() {
daniele 2:540f6e142d59 78 return((USB0->FRMNUML | (USB0->FRMNUMH << 8) & 0x07FF));
daniele 2:540f6e142d59 79 }
daniele 2:540f6e142d59 80
daniele 2:540f6e142d59 81 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
daniele 2:540f6e142d59 82 return 0;
daniele 2:540f6e142d59 83 }
daniele 2:540f6e142d59 84
daniele 2:540f6e142d59 85 USBHAL::USBHAL(void) {
daniele 2:540f6e142d59 86 // Disable IRQ
daniele 2:540f6e142d59 87 NVIC_DisableIRQ(USB0_IRQn);
daniele 2:540f6e142d59 88
daniele 2:540f6e142d59 89 // fill in callback array
daniele 2:540f6e142d59 90 epCallback[0] = &USBHAL::EP1_OUT_callback;
daniele 2:540f6e142d59 91 epCallback[1] = &USBHAL::EP1_IN_callback;
daniele 2:540f6e142d59 92 epCallback[2] = &USBHAL::EP2_OUT_callback;
daniele 2:540f6e142d59 93 epCallback[3] = &USBHAL::EP2_IN_callback;
daniele 2:540f6e142d59 94 epCallback[4] = &USBHAL::EP3_OUT_callback;
daniele 2:540f6e142d59 95 epCallback[5] = &USBHAL::EP3_IN_callback;
daniele 2:540f6e142d59 96 epCallback[6] = &USBHAL::EP4_OUT_callback;
daniele 2:540f6e142d59 97 epCallback[7] = &USBHAL::EP4_IN_callback;
daniele 2:540f6e142d59 98 epCallback[8] = &USBHAL::EP5_OUT_callback;
daniele 2:540f6e142d59 99 epCallback[9] = &USBHAL::EP5_IN_callback;
daniele 2:540f6e142d59 100 epCallback[10] = &USBHAL::EP6_OUT_callback;
daniele 2:540f6e142d59 101 epCallback[11] = &USBHAL::EP6_IN_callback;
daniele 2:540f6e142d59 102 epCallback[12] = &USBHAL::EP7_OUT_callback;
daniele 2:540f6e142d59 103 epCallback[13] = &USBHAL::EP7_IN_callback;
daniele 2:540f6e142d59 104 epCallback[14] = &USBHAL::EP8_OUT_callback;
daniele 2:540f6e142d59 105 epCallback[15] = &USBHAL::EP8_IN_callback;
daniele 2:540f6e142d59 106 epCallback[16] = &USBHAL::EP9_OUT_callback;
daniele 2:540f6e142d59 107 epCallback[17] = &USBHAL::EP9_IN_callback;
daniele 2:540f6e142d59 108 epCallback[18] = &USBHAL::EP10_OUT_callback;
daniele 2:540f6e142d59 109 epCallback[19] = &USBHAL::EP10_IN_callback;
daniele 2:540f6e142d59 110 epCallback[20] = &USBHAL::EP11_OUT_callback;
daniele 2:540f6e142d59 111 epCallback[21] = &USBHAL::EP11_IN_callback;
daniele 2:540f6e142d59 112 epCallback[22] = &USBHAL::EP12_OUT_callback;
daniele 2:540f6e142d59 113 epCallback[23] = &USBHAL::EP12_IN_callback;
daniele 2:540f6e142d59 114 epCallback[24] = &USBHAL::EP13_OUT_callback;
daniele 2:540f6e142d59 115 epCallback[25] = &USBHAL::EP13_IN_callback;
daniele 2:540f6e142d59 116 epCallback[26] = &USBHAL::EP14_OUT_callback;
daniele 2:540f6e142d59 117 epCallback[27] = &USBHAL::EP14_IN_callback;
daniele 2:540f6e142d59 118 epCallback[28] = &USBHAL::EP15_OUT_callback;
daniele 2:540f6e142d59 119 epCallback[29] = &USBHAL::EP15_IN_callback;
daniele 2:540f6e142d59 120
daniele 2:540f6e142d59 121
daniele 2:540f6e142d59 122 // choose usb src as PLL
daniele 2:540f6e142d59 123 SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
daniele 2:540f6e142d59 124
daniele 2:540f6e142d59 125 // enable OTG clock
daniele 2:540f6e142d59 126 SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
daniele 2:540f6e142d59 127
daniele 2:540f6e142d59 128 // Attach IRQ
daniele 2:540f6e142d59 129 instance = this;
daniele 2:540f6e142d59 130 NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
daniele 2:540f6e142d59 131 NVIC_EnableIRQ(USB0_IRQn);
daniele 2:540f6e142d59 132
daniele 2:540f6e142d59 133 // USB Module Configuration
daniele 2:540f6e142d59 134 // Reset USB Module
daniele 2:540f6e142d59 135 USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
daniele 2:540f6e142d59 136 while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
daniele 2:540f6e142d59 137
daniele 2:540f6e142d59 138 // Set BDT Base Register
daniele 2:540f6e142d59 139 USB0->BDTPAGE1=(uint8_t)((uint32_t)bdt>>8);
daniele 2:540f6e142d59 140 USB0->BDTPAGE2=(uint8_t)((uint32_t)bdt>>16);
daniele 2:540f6e142d59 141 USB0->BDTPAGE3=(uint8_t)((uint32_t)bdt>>24);
daniele 2:540f6e142d59 142
daniele 2:540f6e142d59 143 // Clear interrupt flag
daniele 2:540f6e142d59 144 USB0->ISTAT = 0xff;
daniele 2:540f6e142d59 145
daniele 2:540f6e142d59 146 // USB Interrupt Enablers
daniele 2:540f6e142d59 147 USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
daniele 2:540f6e142d59 148 USB_INTEN_SOFTOKEN_MASK |
daniele 2:540f6e142d59 149 USB_INTEN_ERROREN_MASK |
daniele 2:540f6e142d59 150 USB_INTEN_USBRSTEN_MASK;
daniele 2:540f6e142d59 151
daniele 2:540f6e142d59 152 // Disable weak pull downs
daniele 2:540f6e142d59 153 USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
daniele 2:540f6e142d59 154
daniele 2:540f6e142d59 155 USB0->USBTRC0 |= 0x40;
daniele 2:540f6e142d59 156 }
daniele 2:540f6e142d59 157
daniele 2:540f6e142d59 158 USBHAL::~USBHAL(void) { }
daniele 2:540f6e142d59 159
daniele 2:540f6e142d59 160 void USBHAL::connect(void) {
daniele 2:540f6e142d59 161 // enable USB
daniele 2:540f6e142d59 162 USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
daniele 2:540f6e142d59 163 // Pull up enable
daniele 2:540f6e142d59 164 USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
daniele 2:540f6e142d59 165 }
daniele 2:540f6e142d59 166
daniele 2:540f6e142d59 167 void USBHAL::disconnect(void) {
daniele 2:540f6e142d59 168 // disable USB
daniele 2:540f6e142d59 169 USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
daniele 2:540f6e142d59 170 // Pull up disable
daniele 2:540f6e142d59 171 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
daniele 2:540f6e142d59 172 }
daniele 2:540f6e142d59 173
daniele 2:540f6e142d59 174 void USBHAL::configureDevice(void) {
daniele 2:540f6e142d59 175 // not needed
daniele 2:540f6e142d59 176 }
daniele 2:540f6e142d59 177
daniele 2:540f6e142d59 178 void USBHAL::unconfigureDevice(void) {
daniele 2:540f6e142d59 179 // not needed
daniele 2:540f6e142d59 180 }
daniele 2:540f6e142d59 181
daniele 2:540f6e142d59 182 void USBHAL::setAddress(uint8_t address) {
daniele 2:540f6e142d59 183 // we don't set the address now otherwise the usb controller does not ack
daniele 2:540f6e142d59 184 // we set a flag instead
daniele 2:540f6e142d59 185 // see usbisr when an IN token is received
daniele 2:540f6e142d59 186 set_addr = 1;
daniele 2:540f6e142d59 187 addr = address;
daniele 2:540f6e142d59 188 }
daniele 2:540f6e142d59 189
daniele 2:540f6e142d59 190 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
daniele 2:540f6e142d59 191 uint32_t handshake_flag = 0;
daniele 2:540f6e142d59 192 uint8_t * buf;
daniele 2:540f6e142d59 193
daniele 2:540f6e142d59 194 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
daniele 2:540f6e142d59 195 return false;
daniele 2:540f6e142d59 196 }
daniele 2:540f6e142d59 197
daniele 2:540f6e142d59 198 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
daniele 2:540f6e142d59 199
daniele 2:540f6e142d59 200 if ((flags & ISOCHRONOUS) == 0) {
daniele 2:540f6e142d59 201 handshake_flag = USB_ENDPT_EPHSHK_MASK;
daniele 2:540f6e142d59 202 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 203 endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD )] = (uint8_t *) malloc (64*2);
daniele 2:540f6e142d59 204 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD )][0];
daniele 2:540f6e142d59 205 } else {
daniele 2:540f6e142d59 206 endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD )] = (uint8_t *) malloc (64*2);
daniele 2:540f6e142d59 207 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD )][0];
daniele 2:540f6e142d59 208 }
daniele 2:540f6e142d59 209 } else {
daniele 2:540f6e142d59 210 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 211 endpoint_buffer_iso[2] = (uint8_t *) malloc (1023*2);
daniele 2:540f6e142d59 212 buf = &endpoint_buffer_iso[2][0];
daniele 2:540f6e142d59 213 } else {
daniele 2:540f6e142d59 214 endpoint_buffer_iso[0] = (uint8_t *) malloc (1023*2);
daniele 2:540f6e142d59 215 buf = &endpoint_buffer_iso[0][0];
daniele 2:540f6e142d59 216 }
daniele 2:540f6e142d59 217 }
daniele 2:540f6e142d59 218
daniele 2:540f6e142d59 219 // IN endpt -> device to host (TX)
daniele 2:540f6e142d59 220 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 221 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
daniele 2:540f6e142d59 222 USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
daniele 2:540f6e142d59 223 bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
daniele 2:540f6e142d59 224 bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
daniele 2:540f6e142d59 225 }
daniele 2:540f6e142d59 226 // OUT endpt -> host to device (RX)
daniele 2:540f6e142d59 227 else {
daniele 2:540f6e142d59 228 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
daniele 2:540f6e142d59 229 USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
daniele 2:540f6e142d59 230 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
daniele 2:540f6e142d59 231 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
daniele 2:540f6e142d59 232 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
daniele 2:540f6e142d59 233 bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
daniele 2:540f6e142d59 234 }
daniele 2:540f6e142d59 235
daniele 2:540f6e142d59 236 Data1 |= (1 << endpoint);
daniele 2:540f6e142d59 237
daniele 2:540f6e142d59 238 return true;
daniele 2:540f6e142d59 239 }
daniele 2:540f6e142d59 240
daniele 2:540f6e142d59 241 // read setup packet
daniele 2:540f6e142d59 242 void USBHAL::EP0setup(uint8_t *buffer) {
daniele 2:540f6e142d59 243 uint32_t sz;
daniele 2:540f6e142d59 244 endpointReadResult(EP0OUT, buffer, &sz);
daniele 2:540f6e142d59 245 }
daniele 2:540f6e142d59 246
daniele 2:540f6e142d59 247 void USBHAL::EP0readStage(void) {
daniele 2:540f6e142d59 248 Data1 &= ~1UL; // set DATA0
daniele 2:540f6e142d59 249 bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
daniele 2:540f6e142d59 250 }
daniele 2:540f6e142d59 251
daniele 2:540f6e142d59 252 void USBHAL::EP0read(void) {
daniele 2:540f6e142d59 253 uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
daniele 2:540f6e142d59 254 bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
daniele 2:540f6e142d59 255 }
daniele 2:540f6e142d59 256
daniele 2:540f6e142d59 257 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
daniele 2:540f6e142d59 258 uint32_t sz;
daniele 2:540f6e142d59 259 endpointReadResult(EP0OUT, buffer, &sz);
daniele 2:540f6e142d59 260 return sz;
daniele 2:540f6e142d59 261 }
daniele 2:540f6e142d59 262
daniele 2:540f6e142d59 263 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
daniele 2:540f6e142d59 264 endpointWrite(EP0IN, buffer, size);
daniele 2:540f6e142d59 265 }
daniele 2:540f6e142d59 266
daniele 2:540f6e142d59 267 void USBHAL::EP0getWriteResult(void) {
daniele 2:540f6e142d59 268 }
daniele 2:540f6e142d59 269
daniele 2:540f6e142d59 270 void USBHAL::EP0stall(void) {
daniele 2:540f6e142d59 271 stallEndpoint(EP0OUT);
daniele 2:540f6e142d59 272 }
daniele 2:540f6e142d59 273
daniele 2:540f6e142d59 274 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
daniele 2:540f6e142d59 275 endpoint = PHY_TO_LOG(endpoint);
daniele 2:540f6e142d59 276 uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
daniele 2:540f6e142d59 277 bdt[idx].byte_count = maximumSize;
daniele 2:540f6e142d59 278 return EP_PENDING;
daniele 2:540f6e142d59 279 }
daniele 2:540f6e142d59 280
daniele 2:540f6e142d59 281 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
daniele 2:540f6e142d59 282 uint32_t n, sz, idx, setup = 0;
daniele 2:540f6e142d59 283 uint8_t not_iso;
daniele 2:540f6e142d59 284 uint8_t * ep_buf;
daniele 2:540f6e142d59 285
daniele 2:540f6e142d59 286 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
daniele 2:540f6e142d59 287
daniele 2:540f6e142d59 288 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
daniele 2:540f6e142d59 289 return EP_INVALID;
daniele 2:540f6e142d59 290 }
daniele 2:540f6e142d59 291
daniele 2:540f6e142d59 292 // if read on a IN endpoint -> error
daniele 2:540f6e142d59 293 if (IN_EP(endpoint)) {
daniele 2:540f6e142d59 294 return EP_INVALID;
daniele 2:540f6e142d59 295 }
daniele 2:540f6e142d59 296
daniele 2:540f6e142d59 297 idx = EP_BDT_IDX(log_endpoint, RX, 0);
daniele 2:540f6e142d59 298 sz = bdt[idx].byte_count;
daniele 2:540f6e142d59 299 not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
daniele 2:540f6e142d59 300
daniele 2:540f6e142d59 301 //for isochronous endpoint, we don't wait an interrupt
daniele 2:540f6e142d59 302 if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
daniele 2:540f6e142d59 303 return EP_PENDING;
daniele 2:540f6e142d59 304 }
daniele 2:540f6e142d59 305
daniele 2:540f6e142d59 306 if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
daniele 2:540f6e142d59 307 setup = 1;
daniele 2:540f6e142d59 308 }
daniele 2:540f6e142d59 309
daniele 2:540f6e142d59 310 // non iso endpoint
daniele 2:540f6e142d59 311 if (not_iso) {
daniele 2:540f6e142d59 312 ep_buf = endpoint_buffer[idx];
daniele 2:540f6e142d59 313 } else {
daniele 2:540f6e142d59 314 ep_buf = endpoint_buffer_iso[0];
daniele 2:540f6e142d59 315 }
daniele 2:540f6e142d59 316
daniele 2:540f6e142d59 317 for (n = 0; n < sz; n++) {
daniele 2:540f6e142d59 318 buffer[n] = ep_buf[n];
daniele 2:540f6e142d59 319 }
daniele 2:540f6e142d59 320
daniele 2:540f6e142d59 321 if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
daniele 2:540f6e142d59 322 if (setup && (buffer[6] == 0)) // if no setup data stage,
daniele 2:540f6e142d59 323 Data1 &= ~1UL; // set DATA0
daniele 2:540f6e142d59 324 else
daniele 2:540f6e142d59 325 Data1 ^= (1 << endpoint);
daniele 2:540f6e142d59 326 }
daniele 2:540f6e142d59 327
daniele 2:540f6e142d59 328 if (((Data1 >> endpoint) & 1)) {
daniele 2:540f6e142d59 329 bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
daniele 2:540f6e142d59 330 }
daniele 2:540f6e142d59 331 else {
daniele 2:540f6e142d59 332 bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
daniele 2:540f6e142d59 333 }
daniele 2:540f6e142d59 334
daniele 2:540f6e142d59 335 USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
daniele 2:540f6e142d59 336 *bytesRead = sz;
daniele 2:540f6e142d59 337
daniele 2:540f6e142d59 338 epComplete &= ~EP(endpoint);
daniele 2:540f6e142d59 339 return EP_COMPLETED;
daniele 2:540f6e142d59 340 }
daniele 2:540f6e142d59 341
daniele 2:540f6e142d59 342 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
daniele 2:540f6e142d59 343 uint32_t idx, n;
daniele 2:540f6e142d59 344 uint8_t * ep_buf;
daniele 2:540f6e142d59 345
daniele 2:540f6e142d59 346 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
daniele 2:540f6e142d59 347 return EP_INVALID;
daniele 2:540f6e142d59 348 }
daniele 2:540f6e142d59 349
daniele 2:540f6e142d59 350 // if write on a OUT endpoint -> error
daniele 2:540f6e142d59 351 if (OUT_EP(endpoint)) {
daniele 2:540f6e142d59 352 return EP_INVALID;
daniele 2:540f6e142d59 353 }
daniele 2:540f6e142d59 354
daniele 2:540f6e142d59 355 idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
daniele 2:540f6e142d59 356 bdt[idx].byte_count = size;
daniele 2:540f6e142d59 357
daniele 2:540f6e142d59 358
daniele 2:540f6e142d59 359 // non iso endpoint
daniele 2:540f6e142d59 360 if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
daniele 2:540f6e142d59 361 ep_buf = endpoint_buffer[idx];
daniele 2:540f6e142d59 362 } else {
daniele 2:540f6e142d59 363 ep_buf = endpoint_buffer_iso[2];
daniele 2:540f6e142d59 364 }
daniele 2:540f6e142d59 365
daniele 2:540f6e142d59 366 for (n = 0; n < size; n++) {
daniele 2:540f6e142d59 367 ep_buf[n] = data[n];
daniele 2:540f6e142d59 368 }
daniele 2:540f6e142d59 369
daniele 2:540f6e142d59 370 if ((Data1 >> endpoint) & 1) {
daniele 2:540f6e142d59 371 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
daniele 2:540f6e142d59 372 } else {
daniele 2:540f6e142d59 373 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
daniele 2:540f6e142d59 374 }
daniele 2:540f6e142d59 375
daniele 2:540f6e142d59 376 Data1 ^= (1 << endpoint);
daniele 2:540f6e142d59 377
daniele 2:540f6e142d59 378 return EP_PENDING;
daniele 2:540f6e142d59 379 }
daniele 2:540f6e142d59 380
daniele 2:540f6e142d59 381 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
daniele 2:540f6e142d59 382 if (epComplete & EP(endpoint)) {
daniele 2:540f6e142d59 383 epComplete &= ~EP(endpoint);
daniele 2:540f6e142d59 384 return EP_COMPLETED;
daniele 2:540f6e142d59 385 }
daniele 2:540f6e142d59 386
daniele 2:540f6e142d59 387 return EP_PENDING;
daniele 2:540f6e142d59 388 }
daniele 2:540f6e142d59 389
daniele 2:540f6e142d59 390 void USBHAL::stallEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 391 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
daniele 2:540f6e142d59 392 }
daniele 2:540f6e142d59 393
daniele 2:540f6e142d59 394 void USBHAL::unstallEndpoint(uint8_t endpoint) {
daniele 2:540f6e142d59 395 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
daniele 2:540f6e142d59 396 }
daniele 2:540f6e142d59 397
daniele 2:540f6e142d59 398 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
daniele 2:540f6e142d59 399 uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
daniele 2:540f6e142d59 400 return (stall) ? true : false;
daniele 2:540f6e142d59 401 }
daniele 2:540f6e142d59 402
daniele 2:540f6e142d59 403 void USBHAL::remoteWakeup(void) {
daniele 2:540f6e142d59 404 // [TODO]
daniele 2:540f6e142d59 405 }
daniele 2:540f6e142d59 406
daniele 2:540f6e142d59 407
daniele 2:540f6e142d59 408 void USBHAL::_usbisr(void) {
daniele 2:540f6e142d59 409 instance->usbisr();
daniele 2:540f6e142d59 410 }
daniele 2:540f6e142d59 411
daniele 2:540f6e142d59 412
daniele 2:540f6e142d59 413 void USBHAL::usbisr(void) {
daniele 2:540f6e142d59 414 uint8_t i;
daniele 2:540f6e142d59 415 uint8_t istat = USB0->ISTAT;
daniele 2:540f6e142d59 416
daniele 2:540f6e142d59 417 // reset interrupt
daniele 2:540f6e142d59 418 if (istat & USB_ISTAT_USBRST_MASK) {
daniele 2:540f6e142d59 419 // disable all endpt
daniele 2:540f6e142d59 420 for(i = 0; i < 16; i++) {
daniele 2:540f6e142d59 421 USB0->ENDPOINT[i].ENDPT = 0x00;
daniele 2:540f6e142d59 422 }
daniele 2:540f6e142d59 423
daniele 2:540f6e142d59 424 // enable control endpoint
daniele 2:540f6e142d59 425 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
daniele 2:540f6e142d59 426 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
daniele 2:540f6e142d59 427
daniele 2:540f6e142d59 428 Data1 = 0x55555555;
daniele 2:540f6e142d59 429 USB0->CTL |= USB_CTL_ODDRST_MASK;
daniele 2:540f6e142d59 430
daniele 2:540f6e142d59 431 USB0->ISTAT = 0xFF; // clear all interrupt status flags
daniele 2:540f6e142d59 432 USB0->ERRSTAT = 0xFF; // clear all error flags
daniele 2:540f6e142d59 433 USB0->ERREN = 0xFF; // enable error interrupt sources
daniele 2:540f6e142d59 434 USB0->ADDR = 0x00; // set default address
daniele 2:540f6e142d59 435
daniele 2:540f6e142d59 436 return;
daniele 2:540f6e142d59 437 }
daniele 2:540f6e142d59 438
daniele 2:540f6e142d59 439 // resume interrupt
daniele 2:540f6e142d59 440 if (istat & USB_ISTAT_RESUME_MASK) {
daniele 2:540f6e142d59 441 USB0->ISTAT = USB_ISTAT_RESUME_MASK;
daniele 2:540f6e142d59 442 }
daniele 2:540f6e142d59 443
daniele 2:540f6e142d59 444 // SOF interrupt
daniele 2:540f6e142d59 445 if (istat & USB_ISTAT_SOFTOK_MASK) {
daniele 2:540f6e142d59 446 USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
daniele 2:540f6e142d59 447 // SOF event, read frame number
daniele 2:540f6e142d59 448 SOF(frameNumber());
daniele 2:540f6e142d59 449 }
daniele 2:540f6e142d59 450
daniele 2:540f6e142d59 451 // stall interrupt
daniele 2:540f6e142d59 452 if (istat & 1<<7) {
daniele 2:540f6e142d59 453 if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
daniele 2:540f6e142d59 454 USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
daniele 2:540f6e142d59 455 USB0->ISTAT |= USB_ISTAT_STALL_MASK;
daniele 2:540f6e142d59 456 }
daniele 2:540f6e142d59 457
daniele 2:540f6e142d59 458 // token interrupt
daniele 2:540f6e142d59 459 if (istat & 1<<3) {
daniele 2:540f6e142d59 460 uint32_t num = (USB0->STAT >> 4) & 0x0F;
daniele 2:540f6e142d59 461 uint32_t dir = (USB0->STAT >> 3) & 0x01;
daniele 2:540f6e142d59 462 uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
daniele 2:540f6e142d59 463
daniele 2:540f6e142d59 464 // setup packet
daniele 2:540f6e142d59 465 if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
daniele 2:540f6e142d59 466 Data1 &= ~0x02;
daniele 2:540f6e142d59 467 bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
daniele 2:540f6e142d59 468 bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
daniele 2:540f6e142d59 469
daniele 2:540f6e142d59 470 // EP0 SETUP event (SETUP data received)
daniele 2:540f6e142d59 471 EP0setupCallback();
daniele 2:540f6e142d59 472
daniele 2:540f6e142d59 473 } else {
daniele 2:540f6e142d59 474 // OUT packet
daniele 2:540f6e142d59 475 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
daniele 2:540f6e142d59 476 if (num == 0)
daniele 2:540f6e142d59 477 EP0out();
daniele 2:540f6e142d59 478 else {
daniele 2:540f6e142d59 479 epComplete |= (1 << EP(num));
daniele 2:540f6e142d59 480 if ((instance->*(epCallback[EP(num) - 2]))()) {
daniele 2:540f6e142d59 481 epComplete &= ~(1 << EP(num));
daniele 2:540f6e142d59 482 }
daniele 2:540f6e142d59 483 }
daniele 2:540f6e142d59 484 }
daniele 2:540f6e142d59 485
daniele 2:540f6e142d59 486 // IN packet
daniele 2:540f6e142d59 487 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
daniele 2:540f6e142d59 488 if (num == 0) {
daniele 2:540f6e142d59 489 EP0in();
daniele 2:540f6e142d59 490 if (set_addr == 1) {
daniele 2:540f6e142d59 491 USB0->ADDR = addr & 0x7F;
daniele 2:540f6e142d59 492 set_addr = 0;
daniele 2:540f6e142d59 493 }
daniele 2:540f6e142d59 494 }
daniele 2:540f6e142d59 495 else {
daniele 2:540f6e142d59 496 epComplete |= (1 << (EP(num) + 1));
daniele 2:540f6e142d59 497 if ((instance->*(epCallback[EP(num) + 1 - 2]))()) {
daniele 2:540f6e142d59 498 epComplete &= ~(1 << (EP(num) + 1));
daniele 2:540f6e142d59 499 }
daniele 2:540f6e142d59 500 }
daniele 2:540f6e142d59 501 }
daniele 2:540f6e142d59 502 }
daniele 2:540f6e142d59 503
daniele 2:540f6e142d59 504 USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
daniele 2:540f6e142d59 505 }
daniele 2:540f6e142d59 506
daniele 2:540f6e142d59 507 // sleep interrupt
daniele 2:540f6e142d59 508 if (istat & 1<<4) {
daniele 2:540f6e142d59 509 USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
daniele 2:540f6e142d59 510 }
daniele 2:540f6e142d59 511
daniele 2:540f6e142d59 512 // error interrupt
daniele 2:540f6e142d59 513 if (istat & USB_ISTAT_ERROR_MASK) {
daniele 2:540f6e142d59 514 USB0->ERRSTAT = 0xFF;
daniele 2:540f6e142d59 515 USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
daniele 2:540f6e142d59 516 }
daniele 2:540f6e142d59 517 }
daniele 2:540f6e142d59 518
daniele 2:540f6e142d59 519
daniele 2:540f6e142d59 520 #endif