Christophe MARIN / Mbed 2 deprecated TestClock

Small snippet for mbed-cli test

Dependencies:   mbed

main.cpp@0:6c856a0de933, 2019-01-31 (annotated)

Committer:
cthalatoo
Date:
Thu Jan 31 09:20:00 2019 +0000
Revision:
0:6c856a0de933
TestClock mbed cli test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cthalatoo 0:6c856a0de933 1 #include "mbed.h"
cthalatoo 0:6c856a0de933 2 DigitalOut pt(PC_4);
cthalatoo 0:6c856a0de933 3
cthalatoo 0:6c856a0de933 4 Serial pc(USBTX, USBRX);
cthalatoo 0:6c856a0de933 5
cthalatoo 0:6c856a0de933 6 void SystemClock_Config(void);
cthalatoo 0:6c856a0de933 7
cthalatoo 0:6c856a0de933 8
cthalatoo 0:6c856a0de933 9 int main()
cthalatoo 0:6c856a0de933 10 {
cthalatoo 0:6c856a0de933 11 int dbgCount;
cthalatoo 0:6c856a0de933 12
cthalatoo 0:6c856a0de933 13 dbgCount=0;
cthalatoo 0:6c856a0de933 14 //SystemClock_Config();
cthalatoo 0:6c856a0de933 15 pc.baud(115200);
cthalatoo 0:6c856a0de933 16 printf("CPU SystemCoreClock is %d Hz\r\n", SystemCoreClock);
cthalatoo 0:6c856a0de933 17 while(1)
cthalatoo 0:6c856a0de933 18 {
cthalatoo 0:6c856a0de933 19 printf("\r\n%d",dbgCount++);
cthalatoo 0:6c856a0de933 20 wait(1);
cthalatoo 0:6c856a0de933 21 }
cthalatoo 0:6c856a0de933 22 }
cthalatoo 0:6c856a0de933 23
cthalatoo 0:6c856a0de933 24 void SystemClock_Config(void)
cthalatoo 0:6c856a0de933 25 {
cthalatoo 0:6c856a0de933 26 GPIO_InitTypeDef InitStruct;
cthalatoo 0:6c856a0de933 27
cthalatoo 0:6c856a0de933 28
cthalatoo 0:6c856a0de933 29 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
cthalatoo 0:6c856a0de933 30 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
cthalatoo 0:6c856a0de933 31
cthalatoo 0:6c856a0de933 32 /* MSI 2 MHz as source clock for Low Power Run mode */
cthalatoo 0:6c856a0de933 33 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
cthalatoo 0:6c856a0de933 34 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
cthalatoo 0:6c856a0de933 35 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; // 2 MHz
cthalatoo 0:6c856a0de933 36 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
cthalatoo 0:6c856a0de933 37 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF;
cthalatoo 0:6c856a0de933 38 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
cthalatoo 0:6c856a0de933 39 // Error
cthalatoo 0:6c856a0de933 40 }
cthalatoo 0:6c856a0de933 41
cthalatoo 0:6c856a0de933 42 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
cthalatoo 0:6c856a0de933 43 clocks dividers */
cthalatoo 0:6c856a0de933 44 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
cthalatoo 0:6c856a0de933 45 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
cthalatoo 0:6c856a0de933 46 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
cthalatoo 0:6c856a0de933 47 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
cthalatoo 0:6c856a0de933 48 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
cthalatoo 0:6c856a0de933 49 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
cthalatoo 0:6c856a0de933 50 printf("\r\n!!! MainClock configuration failure, case #1\r\n");
cthalatoo 0:6c856a0de933 51 }
cthalatoo 0:6c856a0de933 52
cthalatoo 0:6c856a0de933 53 /* The voltage scaling allows optimizing the power consumption when the device is
cthalatoo 0:6c856a0de933 54 clocked below the maximum system frequency, to update the voltage scaling value
cthalatoo 0:6c856a0de933 55 regarding system frequency refer to product datasheet. */
cthalatoo 0:6c856a0de933 56
cthalatoo 0:6c856a0de933 57 /* Enable Power Control clock */
cthalatoo 0:6c856a0de933 58 __HAL_RCC_PWR_CLK_ENABLE();
cthalatoo 0:6c856a0de933 59
cthalatoo 0:6c856a0de933 60 if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE2) != HAL_OK) {
cthalatoo 0:6c856a0de933 61 printf("\r\n!!! MainClock configuration failure, case #2\r\n");
cthalatoo 0:6c856a0de933 62 }
cthalatoo 0:6c856a0de933 63
cthalatoo 0:6c856a0de933 64 /* Enter Low Power Run mode */
cthalatoo 0:6c856a0de933 65 HAL_PWREx_EnableLowPowerRunMode();
cthalatoo 0:6c856a0de933 66
cthalatoo 0:6c856a0de933 67 /* Disable Power Control clock */
cthalatoo 0:6c856a0de933 68 __HAL_RCC_PWR_CLK_DISABLE();
cthalatoo 0:6c856a0de933 69
cthalatoo 0:6c856a0de933 70 SystemCoreClockUpdate();
cthalatoo 0:6c856a0de933 71
cthalatoo 0:6c856a0de933 72 ///////////////////////////////////Ouputing sysclock / 16 for control
cthalatoo 0:6c856a0de933 73 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_16); // select PLLCLK as source
cthalatoo 0:6c856a0de933 74
cthalatoo 0:6c856a0de933 75
cthalatoo 0:6c856a0de933 76 /*Configure GPIO pin to output clock signal at PA8 */
cthalatoo 0:6c856a0de933 77 InitStruct.Pin = GPIO_PIN_8;
cthalatoo 0:6c856a0de933 78 InitStruct.Mode = GPIO_MODE_AF_PP;
cthalatoo 0:6c856a0de933 79 InitStruct.Pull = GPIO_NOPULL;
cthalatoo 0:6c856a0de933 80 InitStruct.Speed = GPIO_SPEED_HIGH;
cthalatoo 0:6c856a0de933 81 InitStruct.Alternate = GPIO_AF0_MCO;
cthalatoo 0:6c856a0de933 82 HAL_GPIO_Init(GPIOA, &InitStruct);
cthalatoo 0:6c856a0de933 83 }