Cortney Padua / mbed-dev

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targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015 Nordic Semiconductor ASA
<> 144:ef7eb2e8f9f7 3 * All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 6 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * 1. Redistributions of source code must retain the above copyright notice, this list
<> 144:ef7eb2e8f9f7 9 * of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
<> 144:ef7eb2e8f9f7 12 * integrated circuit in a product or a software update for such product, must reproduce
<> 144:ef7eb2e8f9f7 13 * the above copyright notice, this list of conditions and the following disclaimer in
<> 144:ef7eb2e8f9f7 14 * the documentation and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
<> 144:ef7eb2e8f9f7 17 * used to endorse or promote products derived from this software without specific prior
<> 144:ef7eb2e8f9f7 18 * written permission.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * 4. This software, with or without modification, must only be used with a
<> 144:ef7eb2e8f9f7 21 * Nordic Semiconductor ASA integrated circuit.
<> 144:ef7eb2e8f9f7 22 *
<> 144:ef7eb2e8f9f7 23 * 5. Any software provided in binary or object form under this license must not be reverse
<> 144:ef7eb2e8f9f7 24 * engineered, decompiled, modified and/or disassembled.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 144:ef7eb2e8f9f7 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 144:ef7eb2e8f9f7 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 144:ef7eb2e8f9f7 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 144:ef7eb2e8f9f7 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 144:ef7eb2e8f9f7 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 144:ef7eb2e8f9f7 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 144:ef7eb2e8f9f7 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 144:ef7eb2e8f9f7 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 36 *
<> 144:ef7eb2e8f9f7 37 */
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #ifndef __NRF52_BITS_H
<> 144:ef7eb2e8f9f7 40 #define __NRF52_BITS_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 /*lint ++flb "Enter library region" */
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* Peripheral: AAR */
<> 144:ef7eb2e8f9f7 45 /* Description: Accelerated Address Resolver */
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /* Register: AAR_INTENSET */
<> 144:ef7eb2e8f9f7 48 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
<> 144:ef7eb2e8f9f7 51 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
<> 144:ef7eb2e8f9f7 52 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
<> 144:ef7eb2e8f9f7 53 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 54 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 55 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
<> 144:ef7eb2e8f9f7 58 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
<> 144:ef7eb2e8f9f7 59 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
<> 144:ef7eb2e8f9f7 60 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 61 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 62 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /* Bit 0 : Write '1' to Enable interrupt for END event */
<> 144:ef7eb2e8f9f7 65 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 66 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 67 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 68 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 69 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Register: AAR_INTENCLR */
<> 144:ef7eb2e8f9f7 72 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
<> 144:ef7eb2e8f9f7 75 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
<> 144:ef7eb2e8f9f7 76 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
<> 144:ef7eb2e8f9f7 77 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 78 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 79 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
<> 144:ef7eb2e8f9f7 82 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
<> 144:ef7eb2e8f9f7 83 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
<> 144:ef7eb2e8f9f7 84 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 85 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 86 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Bit 0 : Write '1' to Disable interrupt for END event */
<> 144:ef7eb2e8f9f7 89 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 90 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 91 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 92 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 93 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /* Register: AAR_STATUS */
<> 144:ef7eb2e8f9f7 96 /* Description: Resolution status */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* Bits 3..0 : The IRK that was used last time an address was resolved */
<> 144:ef7eb2e8f9f7 99 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
<> 144:ef7eb2e8f9f7 100 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Register: AAR_ENABLE */
<> 144:ef7eb2e8f9f7 103 /* Description: Enable AAR */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /* Bits 1..0 : Enable or disable AAR */
<> 144:ef7eb2e8f9f7 106 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 107 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 108 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 109 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /* Register: AAR_NIRK */
<> 144:ef7eb2e8f9f7 112 /* Description: Number of IRKs */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
<> 144:ef7eb2e8f9f7 115 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
<> 144:ef7eb2e8f9f7 116 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 /* Register: AAR_IRKPTR */
<> 144:ef7eb2e8f9f7 119 /* Description: Pointer to IRK data structure */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /* Bits 31..0 : Pointer to the IRK data structure */
<> 144:ef7eb2e8f9f7 122 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
<> 144:ef7eb2e8f9f7 123 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /* Register: AAR_ADDRPTR */
<> 144:ef7eb2e8f9f7 126 /* Description: Pointer to the resolvable address */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
<> 144:ef7eb2e8f9f7 129 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
<> 144:ef7eb2e8f9f7 130 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Register: AAR_SCRATCHPTR */
<> 144:ef7eb2e8f9f7 133 /* Description: Pointer to data area used for temporary storage */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
<> 144:ef7eb2e8f9f7 136 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
<> 144:ef7eb2e8f9f7 137 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Peripheral: AMLI */
<> 144:ef7eb2e8f9f7 141 /* Description: AHB Multi-Layer Interface */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /* Register: AMLI_RAMPRI_CPU0 */
<> 144:ef7eb2e8f9f7 144 /* Description: AHB bus master priority register for CPU0 */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 147 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 148 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 149 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 150 #define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 151 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 152 #define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 153 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 154 #define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 155 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 156 #define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 157 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 158 #define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 159 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 160 #define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 161 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 162 #define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 163 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 164 #define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 167 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 168 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 169 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 170 #define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 171 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 172 #define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 173 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 174 #define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 175 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 176 #define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 177 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 178 #define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 179 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 180 #define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 181 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 182 #define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 183 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 184 #define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 187 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 188 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 189 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 190 #define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 191 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 192 #define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 193 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 194 #define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 195 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 196 #define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 197 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 198 #define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 199 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 200 #define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 201 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 202 #define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 203 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 204 #define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 207 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 208 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 209 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 210 #define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 211 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 212 #define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 213 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 214 #define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 215 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 216 #define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 217 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 218 #define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 219 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 220 #define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 221 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 222 #define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 223 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 224 #define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 227 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 228 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 229 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 230 #define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 231 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 232 #define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 233 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 234 #define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 235 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 236 #define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 237 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 238 #define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 239 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 240 #define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 241 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 242 #define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 243 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 244 #define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 247 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 248 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 249 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 250 #define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 251 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 252 #define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 253 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 254 #define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 255 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 256 #define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 257 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 258 #define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 259 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 260 #define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 261 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 262 #define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 263 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 264 #define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 267 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 268 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 269 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 270 #define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 271 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 272 #define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 273 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 274 #define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 275 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 276 #define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 277 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 278 #define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 279 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 280 #define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 281 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 282 #define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 283 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 284 #define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 287 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 288 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 289 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 290 #define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 291 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 292 #define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 293 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 294 #define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 295 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 296 #define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 297 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 298 #define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 299 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 300 #define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 301 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 302 #define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 303 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 304 #define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Register: AMLI_RAMPRI_SPIS1 */
<> 144:ef7eb2e8f9f7 307 /* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 310 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 311 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 312 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 313 #define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 314 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 315 #define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 316 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 317 #define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 318 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 319 #define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 320 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 321 #define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 322 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 323 #define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 324 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 325 #define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 326 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 327 #define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 330 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 331 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 332 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 333 #define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 334 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 335 #define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 336 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 337 #define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 338 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 339 #define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 340 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 341 #define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 342 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 343 #define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 344 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 345 #define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 350 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 351 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 352 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 353 #define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 354 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 355 #define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 357 #define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 371 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 380 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 381 #define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 382 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 383 #define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 384 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 385 #define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 386 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 387 #define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 391 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 397 #define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 398 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 399 #define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 400 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 401 #define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 402 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 403 #define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 404 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 405 #define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 406 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 407 #define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 410 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 411 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 412 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 413 #define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 414 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 415 #define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 416 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 417 #define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 418 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 419 #define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 420 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 421 #define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 422 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 423 #define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 424 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 425 #define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 426 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 427 #define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 430 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 431 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 432 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 433 #define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 434 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 435 #define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 436 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 437 #define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 438 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 439 #define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 440 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 441 #define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 442 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 443 #define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 444 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 445 #define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 446 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 447 #define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 450 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 451 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 452 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 453 #define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 454 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 455 #define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 456 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 457 #define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 458 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 459 #define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 460 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 461 #define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 462 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 463 #define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 464 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 465 #define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 466 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 467 #define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /* Register: AMLI_RAMPRI_RADIO */
<> 144:ef7eb2e8f9f7 470 /* Description: AHB bus master priority register for RADIO */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 473 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 474 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 475 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 476 #define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 477 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 478 #define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 479 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 480 #define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 481 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 482 #define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 483 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 484 #define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 485 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 486 #define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 487 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 488 #define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 489 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 490 #define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 493 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 494 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 495 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 496 #define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 497 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 498 #define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 499 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 500 #define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 501 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 502 #define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 503 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 504 #define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 505 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 506 #define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 507 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 508 #define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 509 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 510 #define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 513 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 514 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 515 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 516 #define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 517 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 518 #define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 519 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 520 #define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 521 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 522 #define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 523 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 524 #define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 525 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 526 #define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 527 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 528 #define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 529 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 530 #define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 533 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 534 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 535 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 536 #define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 537 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 538 #define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 539 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 540 #define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 541 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 542 #define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 543 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 544 #define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 545 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 546 #define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 547 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 548 #define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 549 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 550 #define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 553 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 554 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 555 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 556 #define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 557 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 558 #define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 559 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 560 #define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 561 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 562 #define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 563 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 564 #define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 565 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 566 #define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 567 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 568 #define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 569 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 570 #define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 573 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 574 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 575 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 576 #define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 577 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 578 #define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 579 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 580 #define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 581 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 582 #define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 583 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 584 #define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 585 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 586 #define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 587 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 588 #define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 589 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 590 #define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 591
<> 144:ef7eb2e8f9f7 592 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 593 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 594 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 595 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 596 #define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 597 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 598 #define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 599 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 600 #define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 601 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 602 #define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 603 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 604 #define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 605 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 606 #define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 607 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 608 #define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 609 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 610 #define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 613 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 614 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 615 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 616 #define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 617 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 618 #define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 619 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 620 #define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 621 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 622 #define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 623 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 624 #define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 625 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 626 #define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 627 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 628 #define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 629 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 630 #define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Register: AMLI_RAMPRI_ECB */
<> 144:ef7eb2e8f9f7 633 /* Description: AHB bus master priority register for ECB */
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 636 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 637 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 638 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 639 #define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 640 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 641 #define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 642 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 643 #define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 644 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 645 #define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 646 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 647 #define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 648 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 649 #define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 650 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 651 #define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 652 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 653 #define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 656 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 657 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 658 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 659 #define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 660 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 661 #define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 662 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 663 #define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 664 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 665 #define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 666 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 667 #define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 668 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 669 #define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 670 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 671 #define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 672 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 673 #define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 676 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 677 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 678 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 679 #define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 680 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 681 #define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 682 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 683 #define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 684 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 685 #define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 686 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 687 #define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 688 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 689 #define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 690 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 691 #define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 692 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 693 #define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 696 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 697 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 698 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 699 #define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 700 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 701 #define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 702 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 703 #define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 704 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 705 #define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 706 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 707 #define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 708 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 709 #define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 710 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 711 #define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 712 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 713 #define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 716 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 717 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 718 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 719 #define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 720 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 721 #define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 722 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 723 #define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 724 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 725 #define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 726 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 727 #define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 728 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 729 #define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 730 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 731 #define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 732 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 733 #define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 736 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 737 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 738 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 739 #define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 740 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 741 #define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 742 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 743 #define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 744 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 745 #define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 746 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 747 #define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 748 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 749 #define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 750 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 751 #define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 752 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 753 #define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 756 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 757 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 758 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 759 #define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 760 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 761 #define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 762 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 763 #define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 764 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 765 #define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 766 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 767 #define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 768 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 769 #define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 770 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 771 #define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 772 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 773 #define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 776 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 777 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 778 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 779 #define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 780 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 781 #define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 782 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 783 #define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 784 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 785 #define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 786 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 787 #define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 788 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 789 #define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 790 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 791 #define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 792 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 793 #define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /* Register: AMLI_RAMPRI_CCM */
<> 144:ef7eb2e8f9f7 796 /* Description: AHB bus master priority register for CCM */
<> 144:ef7eb2e8f9f7 797
<> 144:ef7eb2e8f9f7 798 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 799 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 800 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 801 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 802 #define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 803 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 804 #define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 805 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 806 #define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 807 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 808 #define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 809 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 810 #define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 811 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 812 #define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 813 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 814 #define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 815 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 816 #define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 819 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 820 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 821 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 822 #define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 823 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 824 #define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 825 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 826 #define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 827 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 828 #define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 829 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 830 #define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 831 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 832 #define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 833 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 834 #define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 835 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 836 #define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 839 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 840 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 841 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 842 #define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 843 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 844 #define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 845 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 846 #define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 847 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 848 #define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 849 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 850 #define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 851 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 852 #define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 853 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 854 #define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 855 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 856 #define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 859 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 860 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 861 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 862 #define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 863 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 864 #define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 865 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 866 #define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 867 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 868 #define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 869 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 870 #define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 871 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 872 #define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 873 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 874 #define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 875 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 876 #define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 879 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 880 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 881 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 882 #define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 883 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 884 #define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 885 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 886 #define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 887 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 888 #define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 889 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 890 #define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 891 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 892 #define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 893 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 894 #define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 895 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 896 #define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 899 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 900 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 901 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 902 #define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 903 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 904 #define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 905 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 906 #define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 907 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 908 #define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 909 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 910 #define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 911 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 912 #define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 913 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 914 #define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 915 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 916 #define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 917
<> 144:ef7eb2e8f9f7 918 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 919 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 920 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 921 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 922 #define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 923 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 924 #define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 925 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 926 #define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 927 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 928 #define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 929 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 930 #define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 931 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 932 #define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 933 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 934 #define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 935 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 936 #define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 939 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 940 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 941 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 942 #define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 943 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 944 #define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 945 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 946 #define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 947 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 948 #define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 949 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 950 #define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 951 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 952 #define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 953 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 954 #define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 955 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 956 #define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958 /* Register: AMLI_RAMPRI_AAR */
<> 144:ef7eb2e8f9f7 959 /* Description: AHB bus master priority register for AAR */
<> 144:ef7eb2e8f9f7 960
<> 144:ef7eb2e8f9f7 961 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 962 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 963 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 964 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 965 #define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 966 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 967 #define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 968 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 969 #define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 970 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 971 #define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 972 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 973 #define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 974 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 975 #define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 976 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 977 #define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 978 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 979 #define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 982 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 983 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 984 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 985 #define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 986 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 987 #define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 988 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 989 #define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 990 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 991 #define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 992 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 993 #define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 994 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 995 #define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 996 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 997 #define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 998 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 999 #define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1002 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1003 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1004 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1005 #define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1006 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1007 #define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1008 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1009 #define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1010 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1011 #define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1012 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1013 #define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1014 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1015 #define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1016 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1017 #define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1018 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1019 #define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 1022 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 1023 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 1024 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1025 #define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1026 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1027 #define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1028 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1029 #define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1030 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1031 #define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1032 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1033 #define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1034 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1035 #define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1036 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1037 #define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1038 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1039 #define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 1042 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 1043 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 1044 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1045 #define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1046 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1047 #define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1048 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1049 #define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1050 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1051 #define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1052 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1053 #define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1054 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1055 #define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1056 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1057 #define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1058 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1059 #define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 1062 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 1063 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 1064 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1065 #define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1066 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1067 #define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1068 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1069 #define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1070 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1071 #define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1072 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1073 #define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1074 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1075 #define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1076 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1077 #define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1078 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1079 #define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 1082 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 1083 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 1084 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1085 #define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1086 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1087 #define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1088 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1089 #define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1090 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1091 #define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1092 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1093 #define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1094 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1095 #define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1096 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1097 #define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1098 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1099 #define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1100
<> 144:ef7eb2e8f9f7 1101 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 1102 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 1103 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 1104 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1105 #define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1106 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1107 #define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1108 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1109 #define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1110 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1111 #define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1112 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1113 #define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1114 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1115 #define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1116 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1117 #define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1118 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1119 #define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /* Register: AMLI_RAMPRI_SAADC */
<> 144:ef7eb2e8f9f7 1122 /* Description: AHB bus master priority register for SAADC */
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 1125 #define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 1126 #define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 1127 #define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1128 #define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1129 #define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1130 #define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1131 #define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1132 #define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1133 #define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1134 #define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1135 #define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1136 #define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1137 #define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1138 #define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1139 #define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1140 #define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1141 #define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1142 #define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 1145 #define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 1146 #define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 1147 #define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1148 #define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1149 #define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1150 #define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1151 #define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1152 #define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1153 #define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1154 #define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1155 #define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1156 #define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1157 #define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1158 #define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1159 #define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1160 #define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1161 #define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1162 #define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1165 #define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1166 #define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1167 #define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1168 #define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1169 #define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1170 #define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1171 #define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1172 #define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1173 #define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1174 #define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1175 #define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1176 #define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1177 #define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1178 #define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1179 #define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1180 #define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1181 #define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1182 #define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 1185 #define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 1186 #define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 1187 #define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1188 #define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1189 #define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1190 #define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1191 #define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1192 #define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1193 #define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1194 #define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1195 #define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1196 #define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1197 #define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1198 #define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1199 #define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1200 #define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1201 #define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1202 #define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 1205 #define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 1206 #define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 1207 #define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1208 #define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1209 #define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1210 #define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1211 #define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1212 #define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1213 #define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1214 #define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1215 #define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1216 #define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1217 #define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1218 #define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1219 #define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1220 #define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1221 #define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1222 #define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1223
<> 144:ef7eb2e8f9f7 1224 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 1225 #define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 1226 #define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 1227 #define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1228 #define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1229 #define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1230 #define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1231 #define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1232 #define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1233 #define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1234 #define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1235 #define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1236 #define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1237 #define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1238 #define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1239 #define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1240 #define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1241 #define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1242 #define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1243
<> 144:ef7eb2e8f9f7 1244 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 1245 #define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 1246 #define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 1247 #define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1248 #define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1249 #define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1250 #define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1251 #define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1252 #define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1253 #define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1254 #define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1255 #define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1256 #define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1257 #define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1258 #define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1259 #define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1260 #define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1261 #define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1262 #define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 1265 #define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 1266 #define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 1267 #define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1268 #define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1269 #define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1270 #define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1271 #define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1272 #define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1273 #define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1274 #define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1275 #define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1276 #define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1277 #define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1278 #define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1279 #define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1280 #define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1281 #define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1282 #define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 /* Register: AMLI_RAMPRI_UARTE */
<> 144:ef7eb2e8f9f7 1285 /* Description: AHB bus master priority register for UARTE */
<> 144:ef7eb2e8f9f7 1286
<> 144:ef7eb2e8f9f7 1287 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 1288 #define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 1289 #define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 1290 #define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1291 #define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1292 #define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1293 #define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1294 #define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1295 #define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1296 #define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1297 #define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1298 #define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1299 #define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1300 #define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1301 #define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1302 #define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1303 #define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1304 #define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1305 #define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 1308 #define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 1309 #define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 1310 #define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1311 #define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1312 #define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1313 #define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1314 #define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1315 #define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1316 #define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1317 #define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1318 #define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1319 #define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1320 #define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1321 #define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1322 #define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1323 #define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1324 #define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1325 #define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1326
<> 144:ef7eb2e8f9f7 1327 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1328 #define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1329 #define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1330 #define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1331 #define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1332 #define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1333 #define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1334 #define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1335 #define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1336 #define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1337 #define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1338 #define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1339 #define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1340 #define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1341 #define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1342 #define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1343 #define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1344 #define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1345 #define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 1348 #define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 1349 #define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 1350 #define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1351 #define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1352 #define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1353 #define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1354 #define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1355 #define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1356 #define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1357 #define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1358 #define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1359 #define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1360 #define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1361 #define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1362 #define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1363 #define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1364 #define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1365 #define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1366
<> 144:ef7eb2e8f9f7 1367 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 1368 #define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 1369 #define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 1370 #define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1371 #define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1372 #define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1373 #define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1374 #define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1375 #define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1376 #define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1377 #define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1378 #define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1379 #define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1380 #define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1381 #define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1382 #define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1383 #define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1384 #define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1385 #define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1386
<> 144:ef7eb2e8f9f7 1387 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 1388 #define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 1389 #define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 1390 #define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1391 #define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1392 #define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1393 #define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1394 #define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1395 #define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1396 #define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1397 #define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1398 #define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1399 #define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1400 #define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1401 #define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1402 #define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1403 #define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1404 #define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1405 #define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 1408 #define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 1409 #define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 1410 #define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1411 #define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1412 #define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1413 #define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1414 #define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1415 #define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1416 #define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1417 #define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1418 #define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1419 #define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1420 #define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1421 #define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1422 #define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1423 #define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1424 #define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1425 #define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 1428 #define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 1429 #define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 1430 #define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1431 #define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1432 #define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1433 #define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1434 #define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1435 #define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1436 #define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1437 #define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1438 #define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1439 #define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1440 #define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1441 #define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1442 #define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1443 #define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1444 #define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1445 #define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1446
<> 144:ef7eb2e8f9f7 1447 /* Register: AMLI_RAMPRI_SERIAL0 */
<> 144:ef7eb2e8f9f7 1448 /* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */
<> 144:ef7eb2e8f9f7 1449
<> 144:ef7eb2e8f9f7 1450 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 1451 #define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 1452 #define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 1453 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1454 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1455 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1456 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1457 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1458 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1459 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1460 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1461 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1462 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1463 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1464 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1465 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1466 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1467 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1468 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 1471 #define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 1472 #define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 1473 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1474 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1475 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1476 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1477 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1478 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1479 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1480 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1481 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1482 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1483 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1484 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1485 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1486 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1487 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1488 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1491 #define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1492 #define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1493 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1494 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1495 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1496 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1497 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1498 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1499 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1500 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1501 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1502 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1503 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1504 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1505 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1506 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1507 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1508 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 1511 #define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 1512 #define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 1513 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1514 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1515 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1516 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1517 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1518 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1519 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1520 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1521 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1522 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1523 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1524 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1525 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1526 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1527 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1528 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 1531 #define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 1532 #define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 1533 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1534 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1535 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1536 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1537 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1538 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1539 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1540 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1541 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1542 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1543 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1544 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1545 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1546 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1547 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1548 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 1551 #define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 1552 #define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 1553 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1554 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1555 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1556 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1557 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1558 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1559 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1560 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1561 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1562 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1563 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1564 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1565 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1566 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1567 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1568 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 1571 #define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 1572 #define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 1573 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1574 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1575 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1576 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1577 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1578 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1579 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1580 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1581 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1582 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1583 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1584 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1585 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1586 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1587 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1588 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1589
<> 144:ef7eb2e8f9f7 1590 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 1591 #define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 1592 #define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 1593 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1594 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1595 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1596 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1597 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1598 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1599 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1600 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1601 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1602 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1603 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1604 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1605 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1606 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1607 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1608 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1609
<> 144:ef7eb2e8f9f7 1610 /* Register: AMLI_RAMPRI_SERIAL2 */
<> 144:ef7eb2e8f9f7 1611 /* Description: AHB bus master priority register for SPIM2 and SPIS2 */
<> 144:ef7eb2e8f9f7 1612
<> 144:ef7eb2e8f9f7 1613 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 1614 #define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 1615 #define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 1616 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1617 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1618 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1619 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1620 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1621 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1622 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1623 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1624 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1625 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1626 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1627 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1628 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1629 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1630 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1631 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 1634 #define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 1635 #define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 1636 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1637 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1638 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1639 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1640 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1641 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1642 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1643 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1644 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1645 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1646 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1647 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1648 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1649 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1650 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1651 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1652
<> 144:ef7eb2e8f9f7 1653 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1654 #define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1655 #define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1656 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1657 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1658 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1659 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1660 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1661 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1662 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1663 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1664 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1665 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1666 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1667 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1668 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1669 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1670 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1671 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 1674 #define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 1675 #define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 1676 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1677 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1678 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1679 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1680 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1681 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1682 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1683 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1684 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1685 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1686 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1687 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1688 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1689 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1690 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1691 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 1694 #define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 1695 #define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 1696 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1697 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1698 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1699 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1700 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1701 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1702 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1703 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1704 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1705 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1706 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1707 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1708 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1709 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1710 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1711 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 1714 #define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 1715 #define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 1716 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1717 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1718 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1719 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1720 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1721 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1722 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1723 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1724 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1725 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1726 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1727 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1728 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1729 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1730 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1731 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1732
<> 144:ef7eb2e8f9f7 1733 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 1734 #define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 1735 #define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 1736 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1737 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1738 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1739 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1740 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1741 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1742 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1743 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1744 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1745 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1746 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1747 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1748 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1749 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1750 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1751 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 1754 #define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 1755 #define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 1756 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1757 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1758 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1759 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1760 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1761 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1762 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1763 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1764 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1765 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1766 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1767 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1768 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1769 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1770 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1771 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 /* Register: AMLI_RAMPRI_NFCT */
<> 144:ef7eb2e8f9f7 1774 /* Description: AHB bus master priority register for NFCT */
<> 144:ef7eb2e8f9f7 1775
<> 144:ef7eb2e8f9f7 1776 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 1777 #define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 1778 #define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 1779 #define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1780 #define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1781 #define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1782 #define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1783 #define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1784 #define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1785 #define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1786 #define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1787 #define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1788 #define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1789 #define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1790 #define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1791 #define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1792 #define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1793 #define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1794 #define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1795
<> 144:ef7eb2e8f9f7 1796 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 1797 #define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 1798 #define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 1799 #define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1800 #define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1801 #define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1802 #define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1803 #define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1804 #define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1805 #define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1806 #define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1807 #define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1808 #define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1809 #define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1810 #define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1811 #define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1812 #define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1813 #define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1814 #define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1817 #define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1818 #define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1819 #define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1820 #define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1821 #define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1822 #define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1823 #define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1824 #define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1825 #define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1826 #define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1827 #define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1828 #define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1829 #define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1830 #define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1831 #define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1832 #define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1833 #define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1834 #define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 1837 #define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 1838 #define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 1839 #define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1840 #define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1841 #define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1842 #define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1843 #define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1844 #define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1845 #define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1846 #define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1847 #define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1848 #define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1849 #define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1850 #define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1851 #define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1852 #define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1853 #define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1854 #define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1855
<> 144:ef7eb2e8f9f7 1856 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 1857 #define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 1858 #define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 1859 #define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1860 #define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1861 #define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1862 #define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1863 #define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1864 #define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1865 #define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1866 #define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1867 #define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1868 #define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1869 #define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1870 #define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1871 #define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1872 #define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1873 #define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1874 #define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1875
<> 144:ef7eb2e8f9f7 1876 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 1877 #define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 1878 #define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 1879 #define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1880 #define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1881 #define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1882 #define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1883 #define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1884 #define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1885 #define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1886 #define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1887 #define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1888 #define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1889 #define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1890 #define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1891 #define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1892 #define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1893 #define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1894 #define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 1897 #define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 1898 #define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 1899 #define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1900 #define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1901 #define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1902 #define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1903 #define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1904 #define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1905 #define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1906 #define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1907 #define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1908 #define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1909 #define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1910 #define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1911 #define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1912 #define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1913 #define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1914 #define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 1917 #define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 1918 #define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 1919 #define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1920 #define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1921 #define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1922 #define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1923 #define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1924 #define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1925 #define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1926 #define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1927 #define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1928 #define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1929 #define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1930 #define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1931 #define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1932 #define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1933 #define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1934 #define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1935
<> 144:ef7eb2e8f9f7 1936 /* Register: AMLI_RAMPRI_I2S */
<> 144:ef7eb2e8f9f7 1937 /* Description: AHB bus master priority register for I2S */
<> 144:ef7eb2e8f9f7 1938
<> 144:ef7eb2e8f9f7 1939 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 1940 #define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 1941 #define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 1942 #define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1943 #define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1944 #define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1945 #define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1946 #define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1947 #define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1948 #define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1949 #define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1950 #define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1951 #define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1952 #define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1953 #define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1954 #define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1955 #define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1956 #define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1957 #define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1958
<> 144:ef7eb2e8f9f7 1959 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 1960 #define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 1961 #define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 1962 #define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1963 #define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1964 #define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1965 #define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1966 #define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1967 #define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1968 #define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1969 #define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1970 #define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1971 #define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1972 #define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1973 #define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1974 #define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1975 #define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1976 #define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1977 #define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1978
<> 144:ef7eb2e8f9f7 1979 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 1980 #define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 1981 #define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 1982 #define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 1983 #define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 1984 #define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 1985 #define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 1986 #define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 1987 #define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 1988 #define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 1989 #define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 1990 #define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 1991 #define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 1992 #define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 1993 #define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 1994 #define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 1995 #define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 1996 #define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 1997 #define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 1998
<> 144:ef7eb2e8f9f7 1999 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 2000 #define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 2001 #define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 2002 #define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2003 #define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2004 #define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2005 #define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2006 #define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2007 #define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2008 #define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2009 #define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2010 #define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2011 #define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2012 #define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2013 #define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2014 #define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2015 #define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2016 #define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2017 #define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2018
<> 144:ef7eb2e8f9f7 2019 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 2020 #define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 2021 #define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 2022 #define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2023 #define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2024 #define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2025 #define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2026 #define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2027 #define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2028 #define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2029 #define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2030 #define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2031 #define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2032 #define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2033 #define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2034 #define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2035 #define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2036 #define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2037 #define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2038
<> 144:ef7eb2e8f9f7 2039 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 2040 #define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 2041 #define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 2042 #define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2043 #define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2044 #define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2045 #define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2046 #define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2047 #define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2048 #define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2049 #define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2050 #define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2051 #define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2052 #define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2053 #define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2054 #define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2055 #define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2056 #define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2057 #define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2058
<> 144:ef7eb2e8f9f7 2059 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 2060 #define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 2061 #define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 2062 #define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2063 #define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2064 #define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2065 #define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2066 #define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2067 #define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2068 #define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2069 #define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2070 #define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2071 #define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2072 #define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2073 #define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2074 #define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2075 #define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2076 #define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2077 #define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2078
<> 144:ef7eb2e8f9f7 2079 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 2080 #define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 2081 #define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 2082 #define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2083 #define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2084 #define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2085 #define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2086 #define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2087 #define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2088 #define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2089 #define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2090 #define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2091 #define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2092 #define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2093 #define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2094 #define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2095 #define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2096 #define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2097 #define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099 /* Register: AMLI_RAMPRI_PDM */
<> 144:ef7eb2e8f9f7 2100 /* Description: AHB bus master priority register for PDM */
<> 144:ef7eb2e8f9f7 2101
<> 144:ef7eb2e8f9f7 2102 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 2103 #define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 2104 #define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 2105 #define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2106 #define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2107 #define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2108 #define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2109 #define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2110 #define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2111 #define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2112 #define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2113 #define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2114 #define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2115 #define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2116 #define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2117 #define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2118 #define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2119 #define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2120 #define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2121
<> 144:ef7eb2e8f9f7 2122 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 2123 #define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 2124 #define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 2125 #define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2126 #define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2127 #define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2128 #define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2129 #define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2130 #define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2131 #define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2132 #define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2133 #define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2134 #define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2135 #define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2136 #define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2137 #define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2138 #define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2139 #define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2140 #define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2141
<> 144:ef7eb2e8f9f7 2142 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 2143 #define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 2144 #define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 2145 #define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2146 #define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2147 #define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2148 #define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2149 #define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2150 #define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2151 #define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2152 #define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2153 #define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2154 #define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2155 #define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2156 #define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2157 #define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2158 #define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2159 #define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2160 #define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2161
<> 144:ef7eb2e8f9f7 2162 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 2163 #define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 2164 #define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 2165 #define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2166 #define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2167 #define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2168 #define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2169 #define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2170 #define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2171 #define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2172 #define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2173 #define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2174 #define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2175 #define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2176 #define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2177 #define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2178 #define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2179 #define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2180 #define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2181
<> 144:ef7eb2e8f9f7 2182 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 2183 #define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 2184 #define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 2185 #define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2186 #define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2187 #define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2188 #define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2189 #define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2190 #define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2191 #define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2192 #define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2193 #define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2194 #define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2195 #define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2196 #define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2197 #define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2198 #define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2199 #define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2200 #define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2201
<> 144:ef7eb2e8f9f7 2202 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 2203 #define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 2204 #define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 2205 #define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2206 #define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2207 #define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2208 #define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2209 #define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2210 #define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2211 #define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2212 #define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2213 #define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2214 #define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2215 #define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2216 #define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2217 #define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2218 #define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2219 #define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2220 #define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2221
<> 144:ef7eb2e8f9f7 2222 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 2223 #define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 2224 #define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 2225 #define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2226 #define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2227 #define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2228 #define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2229 #define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2230 #define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2231 #define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2232 #define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2233 #define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2234 #define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2235 #define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2236 #define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2237 #define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2238 #define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2239 #define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2240 #define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2241
<> 144:ef7eb2e8f9f7 2242 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 2243 #define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 2244 #define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 2245 #define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2246 #define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2247 #define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2248 #define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2249 #define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2250 #define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2251 #define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2252 #define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2253 #define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2254 #define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2255 #define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2256 #define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2257 #define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2258 #define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2259 #define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2260 #define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2261
<> 144:ef7eb2e8f9f7 2262 /* Register: AMLI_RAMPRI_PWM */
<> 144:ef7eb2e8f9f7 2263 /* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */
<> 144:ef7eb2e8f9f7 2264
<> 144:ef7eb2e8f9f7 2265 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
<> 144:ef7eb2e8f9f7 2266 #define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
<> 144:ef7eb2e8f9f7 2267 #define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
<> 144:ef7eb2e8f9f7 2268 #define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2269 #define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2270 #define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2271 #define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2272 #define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2273 #define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2274 #define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2275 #define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2276 #define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2277 #define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2278 #define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2279 #define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2280 #define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2281 #define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2282 #define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2283 #define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2284
<> 144:ef7eb2e8f9f7 2285 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
<> 144:ef7eb2e8f9f7 2286 #define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
<> 144:ef7eb2e8f9f7 2287 #define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
<> 144:ef7eb2e8f9f7 2288 #define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2289 #define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2290 #define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2291 #define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2292 #define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2293 #define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2294 #define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2295 #define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2296 #define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2297 #define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2298 #define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2299 #define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2300 #define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2301 #define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2302 #define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2303 #define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2304
<> 144:ef7eb2e8f9f7 2305 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
<> 144:ef7eb2e8f9f7 2306 #define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
<> 144:ef7eb2e8f9f7 2307 #define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
<> 144:ef7eb2e8f9f7 2308 #define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2309 #define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2310 #define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2311 #define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2312 #define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2313 #define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2314 #define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2315 #define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2316 #define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2317 #define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2318 #define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2319 #define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2320 #define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2321 #define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2322 #define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2323 #define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2324
<> 144:ef7eb2e8f9f7 2325 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
<> 144:ef7eb2e8f9f7 2326 #define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
<> 144:ef7eb2e8f9f7 2327 #define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
<> 144:ef7eb2e8f9f7 2328 #define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2329 #define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2330 #define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2331 #define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2332 #define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2333 #define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2334 #define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2335 #define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2336 #define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2337 #define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2338 #define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2339 #define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2340 #define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2341 #define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2342 #define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2343 #define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2344
<> 144:ef7eb2e8f9f7 2345 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
<> 144:ef7eb2e8f9f7 2346 #define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
<> 144:ef7eb2e8f9f7 2347 #define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
<> 144:ef7eb2e8f9f7 2348 #define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2349 #define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2350 #define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2351 #define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2352 #define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2353 #define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2354 #define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2355 #define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2356 #define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2357 #define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2358 #define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2359 #define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2360 #define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2361 #define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2362 #define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2363 #define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2364
<> 144:ef7eb2e8f9f7 2365 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
<> 144:ef7eb2e8f9f7 2366 #define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
<> 144:ef7eb2e8f9f7 2367 #define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
<> 144:ef7eb2e8f9f7 2368 #define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2369 #define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2370 #define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2371 #define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2372 #define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2373 #define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2374 #define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2375 #define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2376 #define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2377 #define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2378 #define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2379 #define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2380 #define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2381 #define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2382 #define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2383 #define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2384
<> 144:ef7eb2e8f9f7 2385 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
<> 144:ef7eb2e8f9f7 2386 #define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
<> 144:ef7eb2e8f9f7 2387 #define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
<> 144:ef7eb2e8f9f7 2388 #define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2389 #define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2390 #define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2391 #define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2392 #define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2393 #define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2394 #define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2395 #define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2396 #define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2397 #define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2398 #define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2399 #define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2400 #define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2401 #define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2402 #define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2403 #define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2404
<> 144:ef7eb2e8f9f7 2405 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
<> 144:ef7eb2e8f9f7 2406 #define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
<> 144:ef7eb2e8f9f7 2407 #define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
<> 144:ef7eb2e8f9f7 2408 #define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */
<> 144:ef7eb2e8f9f7 2409 #define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */
<> 144:ef7eb2e8f9f7 2410 #define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */
<> 144:ef7eb2e8f9f7 2411 #define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */
<> 144:ef7eb2e8f9f7 2412 #define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */
<> 144:ef7eb2e8f9f7 2413 #define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */
<> 144:ef7eb2e8f9f7 2414 #define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */
<> 144:ef7eb2e8f9f7 2415 #define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */
<> 144:ef7eb2e8f9f7 2416 #define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */
<> 144:ef7eb2e8f9f7 2417 #define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */
<> 144:ef7eb2e8f9f7 2418 #define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */
<> 144:ef7eb2e8f9f7 2419 #define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */
<> 144:ef7eb2e8f9f7 2420 #define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */
<> 144:ef7eb2e8f9f7 2421 #define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */
<> 144:ef7eb2e8f9f7 2422 #define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */
<> 144:ef7eb2e8f9f7 2423 #define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425
<> 144:ef7eb2e8f9f7 2426 /* Peripheral: BPROT */
<> 144:ef7eb2e8f9f7 2427 /* Description: Block Protect */
<> 144:ef7eb2e8f9f7 2428
<> 144:ef7eb2e8f9f7 2429 /* Register: BPROT_CONFIG0 */
<> 144:ef7eb2e8f9f7 2430 /* Description: Block protect configuration register 0 */
<> 144:ef7eb2e8f9f7 2431
<> 144:ef7eb2e8f9f7 2432 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2433 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
<> 144:ef7eb2e8f9f7 2434 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
<> 144:ef7eb2e8f9f7 2435 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2436 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2437
<> 144:ef7eb2e8f9f7 2438 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2439 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
<> 144:ef7eb2e8f9f7 2440 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
<> 144:ef7eb2e8f9f7 2441 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2442 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2443
<> 144:ef7eb2e8f9f7 2444 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2445 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
<> 144:ef7eb2e8f9f7 2446 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
<> 144:ef7eb2e8f9f7 2447 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2448 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2449
<> 144:ef7eb2e8f9f7 2450 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2451 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
<> 144:ef7eb2e8f9f7 2452 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
<> 144:ef7eb2e8f9f7 2453 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2454 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2455
<> 144:ef7eb2e8f9f7 2456 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2457 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
<> 144:ef7eb2e8f9f7 2458 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
<> 144:ef7eb2e8f9f7 2459 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2460 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2461
<> 144:ef7eb2e8f9f7 2462 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2463 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
<> 144:ef7eb2e8f9f7 2464 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
<> 144:ef7eb2e8f9f7 2465 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2466 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2467
<> 144:ef7eb2e8f9f7 2468 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2469 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
<> 144:ef7eb2e8f9f7 2470 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
<> 144:ef7eb2e8f9f7 2471 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2472 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2473
<> 144:ef7eb2e8f9f7 2474 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2475 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
<> 144:ef7eb2e8f9f7 2476 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
<> 144:ef7eb2e8f9f7 2477 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2478 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2479
<> 144:ef7eb2e8f9f7 2480 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2481 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
<> 144:ef7eb2e8f9f7 2482 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
<> 144:ef7eb2e8f9f7 2483 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2484 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2485
<> 144:ef7eb2e8f9f7 2486 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2487 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
<> 144:ef7eb2e8f9f7 2488 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
<> 144:ef7eb2e8f9f7 2489 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2490 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2491
<> 144:ef7eb2e8f9f7 2492 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2493 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
<> 144:ef7eb2e8f9f7 2494 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
<> 144:ef7eb2e8f9f7 2495 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2496 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2497
<> 144:ef7eb2e8f9f7 2498 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2499 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
<> 144:ef7eb2e8f9f7 2500 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
<> 144:ef7eb2e8f9f7 2501 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2502 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2503
<> 144:ef7eb2e8f9f7 2504 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2505 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
<> 144:ef7eb2e8f9f7 2506 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
<> 144:ef7eb2e8f9f7 2507 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2508 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2509
<> 144:ef7eb2e8f9f7 2510 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2511 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
<> 144:ef7eb2e8f9f7 2512 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
<> 144:ef7eb2e8f9f7 2513 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2514 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2515
<> 144:ef7eb2e8f9f7 2516 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2517 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
<> 144:ef7eb2e8f9f7 2518 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
<> 144:ef7eb2e8f9f7 2519 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2520 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2521
<> 144:ef7eb2e8f9f7 2522 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2523 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
<> 144:ef7eb2e8f9f7 2524 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
<> 144:ef7eb2e8f9f7 2525 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2526 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2527
<> 144:ef7eb2e8f9f7 2528 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2529 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
<> 144:ef7eb2e8f9f7 2530 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
<> 144:ef7eb2e8f9f7 2531 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2532 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2533
<> 144:ef7eb2e8f9f7 2534 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2535 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
<> 144:ef7eb2e8f9f7 2536 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
<> 144:ef7eb2e8f9f7 2537 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2538 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2539
<> 144:ef7eb2e8f9f7 2540 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2541 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
<> 144:ef7eb2e8f9f7 2542 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
<> 144:ef7eb2e8f9f7 2543 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2544 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2545
<> 144:ef7eb2e8f9f7 2546 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2547 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
<> 144:ef7eb2e8f9f7 2548 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
<> 144:ef7eb2e8f9f7 2549 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2550 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2551
<> 144:ef7eb2e8f9f7 2552 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2553 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
<> 144:ef7eb2e8f9f7 2554 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
<> 144:ef7eb2e8f9f7 2555 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2556 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2557
<> 144:ef7eb2e8f9f7 2558 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2559 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
<> 144:ef7eb2e8f9f7 2560 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
<> 144:ef7eb2e8f9f7 2561 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2562 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2563
<> 144:ef7eb2e8f9f7 2564 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2565 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
<> 144:ef7eb2e8f9f7 2566 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
<> 144:ef7eb2e8f9f7 2567 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2568 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2569
<> 144:ef7eb2e8f9f7 2570 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2571 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
<> 144:ef7eb2e8f9f7 2572 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
<> 144:ef7eb2e8f9f7 2573 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2574 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2575
<> 144:ef7eb2e8f9f7 2576 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2577 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
<> 144:ef7eb2e8f9f7 2578 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
<> 144:ef7eb2e8f9f7 2579 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2580 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2581
<> 144:ef7eb2e8f9f7 2582 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2583 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
<> 144:ef7eb2e8f9f7 2584 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
<> 144:ef7eb2e8f9f7 2585 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2586 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2587
<> 144:ef7eb2e8f9f7 2588 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2589 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
<> 144:ef7eb2e8f9f7 2590 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
<> 144:ef7eb2e8f9f7 2591 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2592 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2593
<> 144:ef7eb2e8f9f7 2594 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2595 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
<> 144:ef7eb2e8f9f7 2596 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
<> 144:ef7eb2e8f9f7 2597 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2598 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2599
<> 144:ef7eb2e8f9f7 2600 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2601 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
<> 144:ef7eb2e8f9f7 2602 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
<> 144:ef7eb2e8f9f7 2603 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2604 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2605
<> 144:ef7eb2e8f9f7 2606 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2607 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
<> 144:ef7eb2e8f9f7 2608 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
<> 144:ef7eb2e8f9f7 2609 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2610 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2611
<> 144:ef7eb2e8f9f7 2612 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2613 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
<> 144:ef7eb2e8f9f7 2614 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
<> 144:ef7eb2e8f9f7 2615 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2616 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2617
<> 144:ef7eb2e8f9f7 2618 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2619 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
<> 144:ef7eb2e8f9f7 2620 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
<> 144:ef7eb2e8f9f7 2621 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2622 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
<> 144:ef7eb2e8f9f7 2623
<> 144:ef7eb2e8f9f7 2624 /* Register: BPROT_CONFIG1 */
<> 144:ef7eb2e8f9f7 2625 /* Description: Block protect configuration register 1 */
<> 144:ef7eb2e8f9f7 2626
<> 144:ef7eb2e8f9f7 2627 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2628 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
<> 144:ef7eb2e8f9f7 2629 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
<> 144:ef7eb2e8f9f7 2630 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2631 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2632
<> 144:ef7eb2e8f9f7 2633 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2634 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
<> 144:ef7eb2e8f9f7 2635 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
<> 144:ef7eb2e8f9f7 2636 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2637 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2638
<> 144:ef7eb2e8f9f7 2639 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2640 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
<> 144:ef7eb2e8f9f7 2641 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
<> 144:ef7eb2e8f9f7 2642 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2643 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2644
<> 144:ef7eb2e8f9f7 2645 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2646 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
<> 144:ef7eb2e8f9f7 2647 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
<> 144:ef7eb2e8f9f7 2648 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2649 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2650
<> 144:ef7eb2e8f9f7 2651 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2652 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
<> 144:ef7eb2e8f9f7 2653 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
<> 144:ef7eb2e8f9f7 2654 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2655 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2656
<> 144:ef7eb2e8f9f7 2657 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2658 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
<> 144:ef7eb2e8f9f7 2659 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
<> 144:ef7eb2e8f9f7 2660 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2661 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2662
<> 144:ef7eb2e8f9f7 2663 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2664 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
<> 144:ef7eb2e8f9f7 2665 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
<> 144:ef7eb2e8f9f7 2666 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2667 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2668
<> 144:ef7eb2e8f9f7 2669 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2670 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
<> 144:ef7eb2e8f9f7 2671 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
<> 144:ef7eb2e8f9f7 2672 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2673 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2674
<> 144:ef7eb2e8f9f7 2675 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2676 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
<> 144:ef7eb2e8f9f7 2677 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
<> 144:ef7eb2e8f9f7 2678 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2679 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2680
<> 144:ef7eb2e8f9f7 2681 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2682 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
<> 144:ef7eb2e8f9f7 2683 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
<> 144:ef7eb2e8f9f7 2684 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2685 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2686
<> 144:ef7eb2e8f9f7 2687 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2688 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
<> 144:ef7eb2e8f9f7 2689 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
<> 144:ef7eb2e8f9f7 2690 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2691 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2692
<> 144:ef7eb2e8f9f7 2693 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2694 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
<> 144:ef7eb2e8f9f7 2695 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
<> 144:ef7eb2e8f9f7 2696 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2697 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2698
<> 144:ef7eb2e8f9f7 2699 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2700 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
<> 144:ef7eb2e8f9f7 2701 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
<> 144:ef7eb2e8f9f7 2702 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2703 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2704
<> 144:ef7eb2e8f9f7 2705 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2706 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
<> 144:ef7eb2e8f9f7 2707 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
<> 144:ef7eb2e8f9f7 2708 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2709 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2710
<> 144:ef7eb2e8f9f7 2711 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2712 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
<> 144:ef7eb2e8f9f7 2713 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
<> 144:ef7eb2e8f9f7 2714 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2715 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2716
<> 144:ef7eb2e8f9f7 2717 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2718 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
<> 144:ef7eb2e8f9f7 2719 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
<> 144:ef7eb2e8f9f7 2720 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2721 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2722
<> 144:ef7eb2e8f9f7 2723 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2724 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
<> 144:ef7eb2e8f9f7 2725 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
<> 144:ef7eb2e8f9f7 2726 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2727 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2728
<> 144:ef7eb2e8f9f7 2729 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2730 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
<> 144:ef7eb2e8f9f7 2731 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
<> 144:ef7eb2e8f9f7 2732 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2733 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2734
<> 144:ef7eb2e8f9f7 2735 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2736 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
<> 144:ef7eb2e8f9f7 2737 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
<> 144:ef7eb2e8f9f7 2738 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2739 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2740
<> 144:ef7eb2e8f9f7 2741 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2742 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
<> 144:ef7eb2e8f9f7 2743 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
<> 144:ef7eb2e8f9f7 2744 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2745 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2746
<> 144:ef7eb2e8f9f7 2747 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2748 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
<> 144:ef7eb2e8f9f7 2749 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
<> 144:ef7eb2e8f9f7 2750 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2751 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2752
<> 144:ef7eb2e8f9f7 2753 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2754 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
<> 144:ef7eb2e8f9f7 2755 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
<> 144:ef7eb2e8f9f7 2756 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2757 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2758
<> 144:ef7eb2e8f9f7 2759 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2760 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
<> 144:ef7eb2e8f9f7 2761 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
<> 144:ef7eb2e8f9f7 2762 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2763 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2764
<> 144:ef7eb2e8f9f7 2765 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2766 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
<> 144:ef7eb2e8f9f7 2767 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
<> 144:ef7eb2e8f9f7 2768 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2769 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2770
<> 144:ef7eb2e8f9f7 2771 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2772 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
<> 144:ef7eb2e8f9f7 2773 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
<> 144:ef7eb2e8f9f7 2774 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2775 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2776
<> 144:ef7eb2e8f9f7 2777 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2778 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
<> 144:ef7eb2e8f9f7 2779 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
<> 144:ef7eb2e8f9f7 2780 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2781 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2782
<> 144:ef7eb2e8f9f7 2783 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2784 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
<> 144:ef7eb2e8f9f7 2785 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
<> 144:ef7eb2e8f9f7 2786 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2787 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2788
<> 144:ef7eb2e8f9f7 2789 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2790 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
<> 144:ef7eb2e8f9f7 2791 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
<> 144:ef7eb2e8f9f7 2792 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2793 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2794
<> 144:ef7eb2e8f9f7 2795 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2796 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
<> 144:ef7eb2e8f9f7 2797 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
<> 144:ef7eb2e8f9f7 2798 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2799 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2800
<> 144:ef7eb2e8f9f7 2801 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2802 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
<> 144:ef7eb2e8f9f7 2803 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
<> 144:ef7eb2e8f9f7 2804 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2805 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2806
<> 144:ef7eb2e8f9f7 2807 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2808 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
<> 144:ef7eb2e8f9f7 2809 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
<> 144:ef7eb2e8f9f7 2810 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2811 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2812
<> 144:ef7eb2e8f9f7 2813 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2814 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
<> 144:ef7eb2e8f9f7 2815 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
<> 144:ef7eb2e8f9f7 2816 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2817 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2818
<> 144:ef7eb2e8f9f7 2819 /* Register: BPROT_DISABLEINDEBUG */
<> 144:ef7eb2e8f9f7 2820 /* Description: Disable protection mechanism in debug interface mode */
<> 144:ef7eb2e8f9f7 2821
<> 144:ef7eb2e8f9f7 2822 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
<> 144:ef7eb2e8f9f7 2823 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
<> 144:ef7eb2e8f9f7 2824 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
<> 144:ef7eb2e8f9f7 2825 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
<> 144:ef7eb2e8f9f7 2826 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
<> 144:ef7eb2e8f9f7 2827
<> 144:ef7eb2e8f9f7 2828 /* Register: BPROT_CONFIG2 */
<> 144:ef7eb2e8f9f7 2829 /* Description: Block protect configuration register 2 */
<> 144:ef7eb2e8f9f7 2830
<> 144:ef7eb2e8f9f7 2831 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2832 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
<> 144:ef7eb2e8f9f7 2833 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
<> 144:ef7eb2e8f9f7 2834 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2835 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2836
<> 144:ef7eb2e8f9f7 2837 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2838 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
<> 144:ef7eb2e8f9f7 2839 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
<> 144:ef7eb2e8f9f7 2840 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2841 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2842
<> 144:ef7eb2e8f9f7 2843 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2844 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
<> 144:ef7eb2e8f9f7 2845 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
<> 144:ef7eb2e8f9f7 2846 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2847 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2848
<> 144:ef7eb2e8f9f7 2849 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2850 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
<> 144:ef7eb2e8f9f7 2851 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
<> 144:ef7eb2e8f9f7 2852 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2853 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2854
<> 144:ef7eb2e8f9f7 2855 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2856 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
<> 144:ef7eb2e8f9f7 2857 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
<> 144:ef7eb2e8f9f7 2858 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2859 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2860
<> 144:ef7eb2e8f9f7 2861 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2862 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
<> 144:ef7eb2e8f9f7 2863 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
<> 144:ef7eb2e8f9f7 2864 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2865 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2866
<> 144:ef7eb2e8f9f7 2867 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2868 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
<> 144:ef7eb2e8f9f7 2869 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
<> 144:ef7eb2e8f9f7 2870 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2871 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2872
<> 144:ef7eb2e8f9f7 2873 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2874 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
<> 144:ef7eb2e8f9f7 2875 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
<> 144:ef7eb2e8f9f7 2876 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2877 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2878
<> 144:ef7eb2e8f9f7 2879 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2880 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
<> 144:ef7eb2e8f9f7 2881 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
<> 144:ef7eb2e8f9f7 2882 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2883 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2884
<> 144:ef7eb2e8f9f7 2885 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2886 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
<> 144:ef7eb2e8f9f7 2887 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
<> 144:ef7eb2e8f9f7 2888 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2889 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2890
<> 144:ef7eb2e8f9f7 2891 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2892 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
<> 144:ef7eb2e8f9f7 2893 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
<> 144:ef7eb2e8f9f7 2894 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2895 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2896
<> 144:ef7eb2e8f9f7 2897 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2898 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
<> 144:ef7eb2e8f9f7 2899 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
<> 144:ef7eb2e8f9f7 2900 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2901 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2902
<> 144:ef7eb2e8f9f7 2903 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2904 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
<> 144:ef7eb2e8f9f7 2905 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
<> 144:ef7eb2e8f9f7 2906 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2907 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2908
<> 144:ef7eb2e8f9f7 2909 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2910 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
<> 144:ef7eb2e8f9f7 2911 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
<> 144:ef7eb2e8f9f7 2912 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2913 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2914
<> 144:ef7eb2e8f9f7 2915 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2916 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
<> 144:ef7eb2e8f9f7 2917 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
<> 144:ef7eb2e8f9f7 2918 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2919 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2920
<> 144:ef7eb2e8f9f7 2921 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2922 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
<> 144:ef7eb2e8f9f7 2923 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
<> 144:ef7eb2e8f9f7 2924 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2925 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2926
<> 144:ef7eb2e8f9f7 2927 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2928 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
<> 144:ef7eb2e8f9f7 2929 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
<> 144:ef7eb2e8f9f7 2930 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2931 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2932
<> 144:ef7eb2e8f9f7 2933 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2934 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
<> 144:ef7eb2e8f9f7 2935 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
<> 144:ef7eb2e8f9f7 2936 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2937 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2938
<> 144:ef7eb2e8f9f7 2939 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2940 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
<> 144:ef7eb2e8f9f7 2941 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
<> 144:ef7eb2e8f9f7 2942 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2943 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2944
<> 144:ef7eb2e8f9f7 2945 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2946 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
<> 144:ef7eb2e8f9f7 2947 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
<> 144:ef7eb2e8f9f7 2948 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2949 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2950
<> 144:ef7eb2e8f9f7 2951 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2952 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
<> 144:ef7eb2e8f9f7 2953 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
<> 144:ef7eb2e8f9f7 2954 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2955 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2956
<> 144:ef7eb2e8f9f7 2957 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2958 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
<> 144:ef7eb2e8f9f7 2959 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
<> 144:ef7eb2e8f9f7 2960 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2961 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2962
<> 144:ef7eb2e8f9f7 2963 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2964 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
<> 144:ef7eb2e8f9f7 2965 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
<> 144:ef7eb2e8f9f7 2966 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2967 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2968
<> 144:ef7eb2e8f9f7 2969 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2970 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
<> 144:ef7eb2e8f9f7 2971 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
<> 144:ef7eb2e8f9f7 2972 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2973 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2974
<> 144:ef7eb2e8f9f7 2975 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2976 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
<> 144:ef7eb2e8f9f7 2977 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
<> 144:ef7eb2e8f9f7 2978 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2979 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2980
<> 144:ef7eb2e8f9f7 2981 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2982 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
<> 144:ef7eb2e8f9f7 2983 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
<> 144:ef7eb2e8f9f7 2984 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2985 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2986
<> 144:ef7eb2e8f9f7 2987 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2988 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
<> 144:ef7eb2e8f9f7 2989 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
<> 144:ef7eb2e8f9f7 2990 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2991 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2992
<> 144:ef7eb2e8f9f7 2993 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 2994 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
<> 144:ef7eb2e8f9f7 2995 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
<> 144:ef7eb2e8f9f7 2996 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 2997 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 2998
<> 144:ef7eb2e8f9f7 2999 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3000 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
<> 144:ef7eb2e8f9f7 3001 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
<> 144:ef7eb2e8f9f7 3002 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3003 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3004
<> 144:ef7eb2e8f9f7 3005 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3006 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
<> 144:ef7eb2e8f9f7 3007 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
<> 144:ef7eb2e8f9f7 3008 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3009 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3010
<> 144:ef7eb2e8f9f7 3011 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3012 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
<> 144:ef7eb2e8f9f7 3013 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
<> 144:ef7eb2e8f9f7 3014 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3015 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3016
<> 144:ef7eb2e8f9f7 3017 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3018 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
<> 144:ef7eb2e8f9f7 3019 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
<> 144:ef7eb2e8f9f7 3020 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3021 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3022
<> 144:ef7eb2e8f9f7 3023 /* Register: BPROT_CONFIG3 */
<> 144:ef7eb2e8f9f7 3024 /* Description: Block protect configuration register 3 */
<> 144:ef7eb2e8f9f7 3025
<> 144:ef7eb2e8f9f7 3026 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3027 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
<> 144:ef7eb2e8f9f7 3028 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
<> 144:ef7eb2e8f9f7 3029 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3030 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3031
<> 144:ef7eb2e8f9f7 3032 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3033 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
<> 144:ef7eb2e8f9f7 3034 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
<> 144:ef7eb2e8f9f7 3035 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3036 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3037
<> 144:ef7eb2e8f9f7 3038 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3039 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
<> 144:ef7eb2e8f9f7 3040 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
<> 144:ef7eb2e8f9f7 3041 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3042 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3043
<> 144:ef7eb2e8f9f7 3044 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3045 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
<> 144:ef7eb2e8f9f7 3046 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
<> 144:ef7eb2e8f9f7 3047 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3048 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3049
<> 144:ef7eb2e8f9f7 3050 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3051 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
<> 144:ef7eb2e8f9f7 3052 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
<> 144:ef7eb2e8f9f7 3053 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3054 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3055
<> 144:ef7eb2e8f9f7 3056 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3057 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
<> 144:ef7eb2e8f9f7 3058 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
<> 144:ef7eb2e8f9f7 3059 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3060 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3061
<> 144:ef7eb2e8f9f7 3062 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3063 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
<> 144:ef7eb2e8f9f7 3064 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
<> 144:ef7eb2e8f9f7 3065 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3066 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3067
<> 144:ef7eb2e8f9f7 3068 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3069 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
<> 144:ef7eb2e8f9f7 3070 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
<> 144:ef7eb2e8f9f7 3071 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3072 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3073
<> 144:ef7eb2e8f9f7 3074 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3075 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
<> 144:ef7eb2e8f9f7 3076 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
<> 144:ef7eb2e8f9f7 3077 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3078 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3079
<> 144:ef7eb2e8f9f7 3080 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3081 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
<> 144:ef7eb2e8f9f7 3082 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
<> 144:ef7eb2e8f9f7 3083 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3084 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3085
<> 144:ef7eb2e8f9f7 3086 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3087 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
<> 144:ef7eb2e8f9f7 3088 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
<> 144:ef7eb2e8f9f7 3089 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3090 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3091
<> 144:ef7eb2e8f9f7 3092 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3093 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
<> 144:ef7eb2e8f9f7 3094 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
<> 144:ef7eb2e8f9f7 3095 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3096 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3097
<> 144:ef7eb2e8f9f7 3098 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3099 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
<> 144:ef7eb2e8f9f7 3100 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
<> 144:ef7eb2e8f9f7 3101 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3102 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3103
<> 144:ef7eb2e8f9f7 3104 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3105 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
<> 144:ef7eb2e8f9f7 3106 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
<> 144:ef7eb2e8f9f7 3107 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3108 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3109
<> 144:ef7eb2e8f9f7 3110 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3111 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
<> 144:ef7eb2e8f9f7 3112 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
<> 144:ef7eb2e8f9f7 3113 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3114 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3115
<> 144:ef7eb2e8f9f7 3116 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3117 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
<> 144:ef7eb2e8f9f7 3118 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
<> 144:ef7eb2e8f9f7 3119 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3120 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3121
<> 144:ef7eb2e8f9f7 3122 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3123 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
<> 144:ef7eb2e8f9f7 3124 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
<> 144:ef7eb2e8f9f7 3125 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3126 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3127
<> 144:ef7eb2e8f9f7 3128 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3129 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
<> 144:ef7eb2e8f9f7 3130 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
<> 144:ef7eb2e8f9f7 3131 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3132 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3133
<> 144:ef7eb2e8f9f7 3134 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3135 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
<> 144:ef7eb2e8f9f7 3136 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
<> 144:ef7eb2e8f9f7 3137 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3138 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3139
<> 144:ef7eb2e8f9f7 3140 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3141 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
<> 144:ef7eb2e8f9f7 3142 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
<> 144:ef7eb2e8f9f7 3143 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3144 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3145
<> 144:ef7eb2e8f9f7 3146 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3147 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
<> 144:ef7eb2e8f9f7 3148 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
<> 144:ef7eb2e8f9f7 3149 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3150 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3151
<> 144:ef7eb2e8f9f7 3152 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3153 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
<> 144:ef7eb2e8f9f7 3154 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
<> 144:ef7eb2e8f9f7 3155 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3156 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3157
<> 144:ef7eb2e8f9f7 3158 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3159 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
<> 144:ef7eb2e8f9f7 3160 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
<> 144:ef7eb2e8f9f7 3161 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3162 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3163
<> 144:ef7eb2e8f9f7 3164 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3165 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
<> 144:ef7eb2e8f9f7 3166 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
<> 144:ef7eb2e8f9f7 3167 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3168 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3169
<> 144:ef7eb2e8f9f7 3170 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3171 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
<> 144:ef7eb2e8f9f7 3172 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
<> 144:ef7eb2e8f9f7 3173 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3174 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3175
<> 144:ef7eb2e8f9f7 3176 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3177 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
<> 144:ef7eb2e8f9f7 3178 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
<> 144:ef7eb2e8f9f7 3179 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3180 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3181
<> 144:ef7eb2e8f9f7 3182 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3183 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
<> 144:ef7eb2e8f9f7 3184 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
<> 144:ef7eb2e8f9f7 3185 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3186 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3187
<> 144:ef7eb2e8f9f7 3188 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3189 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
<> 144:ef7eb2e8f9f7 3190 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
<> 144:ef7eb2e8f9f7 3191 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3192 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3193
<> 144:ef7eb2e8f9f7 3194 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3195 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
<> 144:ef7eb2e8f9f7 3196 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
<> 144:ef7eb2e8f9f7 3197 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3198 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3199
<> 144:ef7eb2e8f9f7 3200 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3201 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
<> 144:ef7eb2e8f9f7 3202 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
<> 144:ef7eb2e8f9f7 3203 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3204 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3205
<> 144:ef7eb2e8f9f7 3206 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3207 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
<> 144:ef7eb2e8f9f7 3208 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
<> 144:ef7eb2e8f9f7 3209 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3210 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3211
<> 144:ef7eb2e8f9f7 3212 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
<> 144:ef7eb2e8f9f7 3213 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
<> 144:ef7eb2e8f9f7 3214 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
<> 144:ef7eb2e8f9f7 3215 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
<> 144:ef7eb2e8f9f7 3216 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
<> 144:ef7eb2e8f9f7 3217
<> 144:ef7eb2e8f9f7 3218
<> 144:ef7eb2e8f9f7 3219 /* Peripheral: CCM */
<> 144:ef7eb2e8f9f7 3220 /* Description: AES CCM Mode Encryption */
<> 144:ef7eb2e8f9f7 3221
<> 144:ef7eb2e8f9f7 3222 /* Register: CCM_SHORTS */
<> 144:ef7eb2e8f9f7 3223 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 3224
<> 144:ef7eb2e8f9f7 3225 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
<> 144:ef7eb2e8f9f7 3226 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
<> 144:ef7eb2e8f9f7 3227 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
<> 144:ef7eb2e8f9f7 3228 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 3229 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 3230
<> 144:ef7eb2e8f9f7 3231 /* Register: CCM_INTENSET */
<> 144:ef7eb2e8f9f7 3232 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 3233
<> 144:ef7eb2e8f9f7 3234 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 3235 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 3236 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 3237 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3238 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3239 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3240
<> 144:ef7eb2e8f9f7 3241 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
<> 144:ef7eb2e8f9f7 3242 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
<> 144:ef7eb2e8f9f7 3243 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
<> 144:ef7eb2e8f9f7 3244 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3245 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3246 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3247
<> 144:ef7eb2e8f9f7 3248 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
<> 144:ef7eb2e8f9f7 3249 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
<> 144:ef7eb2e8f9f7 3250 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
<> 144:ef7eb2e8f9f7 3251 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3252 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3253 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3254
<> 144:ef7eb2e8f9f7 3255 /* Register: CCM_INTENCLR */
<> 144:ef7eb2e8f9f7 3256 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 3257
<> 144:ef7eb2e8f9f7 3258 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 3259 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 3260 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 3261 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3262 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3263 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3264
<> 144:ef7eb2e8f9f7 3265 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
<> 144:ef7eb2e8f9f7 3266 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
<> 144:ef7eb2e8f9f7 3267 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
<> 144:ef7eb2e8f9f7 3268 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3269 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3270 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3271
<> 144:ef7eb2e8f9f7 3272 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
<> 144:ef7eb2e8f9f7 3273 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
<> 144:ef7eb2e8f9f7 3274 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
<> 144:ef7eb2e8f9f7 3275 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3276 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3277 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3278
<> 144:ef7eb2e8f9f7 3279 /* Register: CCM_MICSTATUS */
<> 144:ef7eb2e8f9f7 3280 /* Description: MIC check result */
<> 144:ef7eb2e8f9f7 3281
<> 144:ef7eb2e8f9f7 3282 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
<> 144:ef7eb2e8f9f7 3283 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
<> 144:ef7eb2e8f9f7 3284 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
<> 144:ef7eb2e8f9f7 3285 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
<> 144:ef7eb2e8f9f7 3286 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
<> 144:ef7eb2e8f9f7 3287
<> 144:ef7eb2e8f9f7 3288 /* Register: CCM_ENABLE */
<> 144:ef7eb2e8f9f7 3289 /* Description: Enable */
<> 144:ef7eb2e8f9f7 3290
<> 144:ef7eb2e8f9f7 3291 /* Bits 1..0 : Enable or disable CCM */
<> 144:ef7eb2e8f9f7 3292 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 3293 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 3294 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3295 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3296
<> 144:ef7eb2e8f9f7 3297 /* Register: CCM_MODE */
<> 144:ef7eb2e8f9f7 3298 /* Description: Operation mode */
<> 144:ef7eb2e8f9f7 3299
<> 144:ef7eb2e8f9f7 3300 /* Bit 24 : Packet length configuration */
<> 144:ef7eb2e8f9f7 3301 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
<> 144:ef7eb2e8f9f7 3302 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
<> 144:ef7eb2e8f9f7 3303 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
<> 144:ef7eb2e8f9f7 3304 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
<> 144:ef7eb2e8f9f7 3305
<> 144:ef7eb2e8f9f7 3306 /* Bit 16 : Data rate that the CCM shall run in synch with */
<> 144:ef7eb2e8f9f7 3307 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
<> 144:ef7eb2e8f9f7 3308 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
<> 144:ef7eb2e8f9f7 3309 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
<> 144:ef7eb2e8f9f7 3310 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
<> 144:ef7eb2e8f9f7 3311
<> 144:ef7eb2e8f9f7 3312 /* Bit 0 : The mode of operation to be used */
<> 144:ef7eb2e8f9f7 3313 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 3314 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 3315 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
<> 144:ef7eb2e8f9f7 3316 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
<> 144:ef7eb2e8f9f7 3317
<> 144:ef7eb2e8f9f7 3318 /* Register: CCM_CNFPTR */
<> 144:ef7eb2e8f9f7 3319 /* Description: Pointer to data structure holding AES key and NONCE vector */
<> 144:ef7eb2e8f9f7 3320
<> 144:ef7eb2e8f9f7 3321 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
<> 144:ef7eb2e8f9f7 3322 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
<> 144:ef7eb2e8f9f7 3323 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
<> 144:ef7eb2e8f9f7 3324
<> 144:ef7eb2e8f9f7 3325 /* Register: CCM_INPTR */
<> 144:ef7eb2e8f9f7 3326 /* Description: Input pointer */
<> 144:ef7eb2e8f9f7 3327
<> 144:ef7eb2e8f9f7 3328 /* Bits 31..0 : Input pointer */
<> 144:ef7eb2e8f9f7 3329 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
<> 144:ef7eb2e8f9f7 3330 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
<> 144:ef7eb2e8f9f7 3331
<> 144:ef7eb2e8f9f7 3332 /* Register: CCM_OUTPTR */
<> 144:ef7eb2e8f9f7 3333 /* Description: Output pointer */
<> 144:ef7eb2e8f9f7 3334
<> 144:ef7eb2e8f9f7 3335 /* Bits 31..0 : Output pointer */
<> 144:ef7eb2e8f9f7 3336 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
<> 144:ef7eb2e8f9f7 3337 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
<> 144:ef7eb2e8f9f7 3338
<> 144:ef7eb2e8f9f7 3339 /* Register: CCM_SCRATCHPTR */
<> 144:ef7eb2e8f9f7 3340 /* Description: Pointer to data area used for temporary storage */
<> 144:ef7eb2e8f9f7 3341
<> 144:ef7eb2e8f9f7 3342 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
<> 144:ef7eb2e8f9f7 3343 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
<> 144:ef7eb2e8f9f7 3344 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
<> 144:ef7eb2e8f9f7 3345
<> 144:ef7eb2e8f9f7 3346
<> 144:ef7eb2e8f9f7 3347 /* Peripheral: CLOCK */
<> 144:ef7eb2e8f9f7 3348 /* Description: Clock control */
<> 144:ef7eb2e8f9f7 3349
<> 144:ef7eb2e8f9f7 3350 /* Register: CLOCK_INTENSET */
<> 144:ef7eb2e8f9f7 3351 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 3352
<> 144:ef7eb2e8f9f7 3353 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
<> 144:ef7eb2e8f9f7 3354 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
<> 144:ef7eb2e8f9f7 3355 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
<> 144:ef7eb2e8f9f7 3356 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3357 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3358 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3359
<> 144:ef7eb2e8f9f7 3360 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
<> 144:ef7eb2e8f9f7 3361 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
<> 144:ef7eb2e8f9f7 3362 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
<> 144:ef7eb2e8f9f7 3363 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3364 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3365 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3366
<> 144:ef7eb2e8f9f7 3367 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
<> 144:ef7eb2e8f9f7 3368 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3369 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3370 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3371 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3372 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3373
<> 144:ef7eb2e8f9f7 3374 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
<> 144:ef7eb2e8f9f7 3375 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3376 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3377 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3378 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3379 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3380
<> 144:ef7eb2e8f9f7 3381 /* Register: CLOCK_INTENCLR */
<> 144:ef7eb2e8f9f7 3382 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 3383
<> 144:ef7eb2e8f9f7 3384 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
<> 144:ef7eb2e8f9f7 3385 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
<> 144:ef7eb2e8f9f7 3386 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
<> 144:ef7eb2e8f9f7 3387 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3388 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3389 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3390
<> 144:ef7eb2e8f9f7 3391 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
<> 144:ef7eb2e8f9f7 3392 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
<> 144:ef7eb2e8f9f7 3393 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
<> 144:ef7eb2e8f9f7 3394 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3395 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3396 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3397
<> 144:ef7eb2e8f9f7 3398 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
<> 144:ef7eb2e8f9f7 3399 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3400 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3401 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3402 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3403 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3404
<> 144:ef7eb2e8f9f7 3405 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
<> 144:ef7eb2e8f9f7 3406 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3407 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
<> 144:ef7eb2e8f9f7 3408 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3409 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3410 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3411
<> 144:ef7eb2e8f9f7 3412 /* Register: CLOCK_HFCLKRUN */
<> 144:ef7eb2e8f9f7 3413 /* Description: Status indicating that HFCLKSTART task has been triggered */
<> 144:ef7eb2e8f9f7 3414
<> 144:ef7eb2e8f9f7 3415 /* Bit 0 : HFCLKSTART task triggered or not */
<> 144:ef7eb2e8f9f7 3416 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
<> 144:ef7eb2e8f9f7 3417 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
<> 144:ef7eb2e8f9f7 3418 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
<> 144:ef7eb2e8f9f7 3419 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
<> 144:ef7eb2e8f9f7 3420
<> 144:ef7eb2e8f9f7 3421 /* Register: CLOCK_HFCLKSTAT */
<> 144:ef7eb2e8f9f7 3422 /* Description: HFCLK status */
<> 144:ef7eb2e8f9f7 3423
<> 144:ef7eb2e8f9f7 3424 /* Bit 16 : HFCLK state */
<> 144:ef7eb2e8f9f7 3425 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
<> 144:ef7eb2e8f9f7 3426 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
<> 144:ef7eb2e8f9f7 3427 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
<> 144:ef7eb2e8f9f7 3428 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
<> 144:ef7eb2e8f9f7 3429
<> 144:ef7eb2e8f9f7 3430 /* Bit 0 : Source of HFCLK */
<> 144:ef7eb2e8f9f7 3431 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
<> 144:ef7eb2e8f9f7 3432 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
<> 144:ef7eb2e8f9f7 3433 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
<> 144:ef7eb2e8f9f7 3434 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
<> 144:ef7eb2e8f9f7 3435
<> 144:ef7eb2e8f9f7 3436 /* Register: CLOCK_LFCLKRUN */
<> 144:ef7eb2e8f9f7 3437 /* Description: Status indicating that LFCLKSTART task has been triggered */
<> 144:ef7eb2e8f9f7 3438
<> 144:ef7eb2e8f9f7 3439 /* Bit 0 : LFCLKSTART task triggered or not */
<> 144:ef7eb2e8f9f7 3440 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
<> 144:ef7eb2e8f9f7 3441 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
<> 144:ef7eb2e8f9f7 3442 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
<> 144:ef7eb2e8f9f7 3443 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
<> 144:ef7eb2e8f9f7 3444
<> 144:ef7eb2e8f9f7 3445 /* Register: CLOCK_LFCLKSTAT */
<> 144:ef7eb2e8f9f7 3446 /* Description: LFCLK status */
<> 144:ef7eb2e8f9f7 3447
<> 144:ef7eb2e8f9f7 3448 /* Bit 16 : LFCLK state */
<> 144:ef7eb2e8f9f7 3449 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
<> 144:ef7eb2e8f9f7 3450 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
<> 144:ef7eb2e8f9f7 3451 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
<> 144:ef7eb2e8f9f7 3452 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
<> 144:ef7eb2e8f9f7 3453
<> 144:ef7eb2e8f9f7 3454 /* Bits 1..0 : Source of LFCLK */
<> 144:ef7eb2e8f9f7 3455 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
<> 144:ef7eb2e8f9f7 3456 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
<> 144:ef7eb2e8f9f7 3457 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
<> 144:ef7eb2e8f9f7 3458 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
<> 144:ef7eb2e8f9f7 3459 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
<> 144:ef7eb2e8f9f7 3460
<> 144:ef7eb2e8f9f7 3461 /* Register: CLOCK_LFCLKSRCCOPY */
<> 144:ef7eb2e8f9f7 3462 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
<> 144:ef7eb2e8f9f7 3463
<> 144:ef7eb2e8f9f7 3464 /* Bits 1..0 : Clock source */
<> 144:ef7eb2e8f9f7 3465 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
<> 144:ef7eb2e8f9f7 3466 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
<> 144:ef7eb2e8f9f7 3467 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
<> 144:ef7eb2e8f9f7 3468 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
<> 144:ef7eb2e8f9f7 3469 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
<> 144:ef7eb2e8f9f7 3470
<> 144:ef7eb2e8f9f7 3471 /* Register: CLOCK_LFCLKSRC */
<> 144:ef7eb2e8f9f7 3472 /* Description: Clock source for the LFCLK */
<> 144:ef7eb2e8f9f7 3473
<> 144:ef7eb2e8f9f7 3474 /* Bits 1..0 : Clock source */
<> 144:ef7eb2e8f9f7 3475 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
<> 144:ef7eb2e8f9f7 3476 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
<> 144:ef7eb2e8f9f7 3477 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
<> 144:ef7eb2e8f9f7 3478 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
<> 144:ef7eb2e8f9f7 3479 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
<> 144:ef7eb2e8f9f7 3480
<> 144:ef7eb2e8f9f7 3481 /* Register: CLOCK_CTIV */
<> 144:ef7eb2e8f9f7 3482 /* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
<> 144:ef7eb2e8f9f7 3483
<> 144:ef7eb2e8f9f7 3484 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
<> 144:ef7eb2e8f9f7 3485 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
<> 144:ef7eb2e8f9f7 3486 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
<> 144:ef7eb2e8f9f7 3487
<> 144:ef7eb2e8f9f7 3488 /* Register: CLOCK_TRACECONFIG */
<> 144:ef7eb2e8f9f7 3489 /* Description: Clocking options for the Trace Port debug interface */
<> 144:ef7eb2e8f9f7 3490
<> 144:ef7eb2e8f9f7 3491 /* Bits 17..16 : Pin multiplexing of trace signals. */
<> 144:ef7eb2e8f9f7 3492 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
<> 144:ef7eb2e8f9f7 3493 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
<> 144:ef7eb2e8f9f7 3494 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
<> 144:ef7eb2e8f9f7 3495 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
<> 144:ef7eb2e8f9f7 3496 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
<> 144:ef7eb2e8f9f7 3497
<> 144:ef7eb2e8f9f7 3498 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
<> 144:ef7eb2e8f9f7 3499 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
<> 144:ef7eb2e8f9f7 3500 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
<> 144:ef7eb2e8f9f7 3501 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
<> 144:ef7eb2e8f9f7 3502 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
<> 144:ef7eb2e8f9f7 3503 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
<> 144:ef7eb2e8f9f7 3504 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
<> 144:ef7eb2e8f9f7 3505
<> 144:ef7eb2e8f9f7 3506
<> 144:ef7eb2e8f9f7 3507 /* Peripheral: COMP */
<> 144:ef7eb2e8f9f7 3508 /* Description: Comparator */
<> 144:ef7eb2e8f9f7 3509
<> 144:ef7eb2e8f9f7 3510 /* Register: COMP_SHORTS */
<> 144:ef7eb2e8f9f7 3511 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 3512
<> 144:ef7eb2e8f9f7 3513 /* Bit 4 : Shortcut between CROSS event and STOP task */
<> 144:ef7eb2e8f9f7 3514 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
<> 144:ef7eb2e8f9f7 3515 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
<> 144:ef7eb2e8f9f7 3516 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 3517 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 3518
<> 144:ef7eb2e8f9f7 3519 /* Bit 3 : Shortcut between UP event and STOP task */
<> 144:ef7eb2e8f9f7 3520 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
<> 144:ef7eb2e8f9f7 3521 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
<> 144:ef7eb2e8f9f7 3522 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 3523 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 3524
<> 144:ef7eb2e8f9f7 3525 /* Bit 2 : Shortcut between DOWN event and STOP task */
<> 144:ef7eb2e8f9f7 3526 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
<> 144:ef7eb2e8f9f7 3527 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
<> 144:ef7eb2e8f9f7 3528 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 3529 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 3530
<> 144:ef7eb2e8f9f7 3531 /* Bit 1 : Shortcut between READY event and STOP task */
<> 144:ef7eb2e8f9f7 3532 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
<> 144:ef7eb2e8f9f7 3533 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
<> 144:ef7eb2e8f9f7 3534 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 3535 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 3536
<> 144:ef7eb2e8f9f7 3537 /* Bit 0 : Shortcut between READY event and SAMPLE task */
<> 144:ef7eb2e8f9f7 3538 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
<> 144:ef7eb2e8f9f7 3539 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
<> 144:ef7eb2e8f9f7 3540 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 3541 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 3542
<> 144:ef7eb2e8f9f7 3543 /* Register: COMP_INTEN */
<> 144:ef7eb2e8f9f7 3544 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 3545
<> 144:ef7eb2e8f9f7 3546 /* Bit 3 : Enable or disable interrupt for CROSS event */
<> 144:ef7eb2e8f9f7 3547 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
<> 144:ef7eb2e8f9f7 3548 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
<> 144:ef7eb2e8f9f7 3549 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3550 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3551
<> 144:ef7eb2e8f9f7 3552 /* Bit 2 : Enable or disable interrupt for UP event */
<> 144:ef7eb2e8f9f7 3553 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
<> 144:ef7eb2e8f9f7 3554 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
<> 144:ef7eb2e8f9f7 3555 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3556 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3557
<> 144:ef7eb2e8f9f7 3558 /* Bit 1 : Enable or disable interrupt for DOWN event */
<> 144:ef7eb2e8f9f7 3559 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
<> 144:ef7eb2e8f9f7 3560 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
<> 144:ef7eb2e8f9f7 3561 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3562 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3563
<> 144:ef7eb2e8f9f7 3564 /* Bit 0 : Enable or disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 3565 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 3566 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 3567 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3568 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3569
<> 144:ef7eb2e8f9f7 3570 /* Register: COMP_INTENSET */
<> 144:ef7eb2e8f9f7 3571 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 3572
<> 144:ef7eb2e8f9f7 3573 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
<> 144:ef7eb2e8f9f7 3574 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
<> 144:ef7eb2e8f9f7 3575 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
<> 144:ef7eb2e8f9f7 3576 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3577 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3578 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3579
<> 144:ef7eb2e8f9f7 3580 /* Bit 2 : Write '1' to Enable interrupt for UP event */
<> 144:ef7eb2e8f9f7 3581 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
<> 144:ef7eb2e8f9f7 3582 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
<> 144:ef7eb2e8f9f7 3583 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3584 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3585 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3586
<> 144:ef7eb2e8f9f7 3587 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
<> 144:ef7eb2e8f9f7 3588 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
<> 144:ef7eb2e8f9f7 3589 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
<> 144:ef7eb2e8f9f7 3590 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3591 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3592 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3593
<> 144:ef7eb2e8f9f7 3594 /* Bit 0 : Write '1' to Enable interrupt for READY event */
<> 144:ef7eb2e8f9f7 3595 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 3596 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 3597 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3598 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3599 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3600
<> 144:ef7eb2e8f9f7 3601 /* Register: COMP_INTENCLR */
<> 144:ef7eb2e8f9f7 3602 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 3603
<> 144:ef7eb2e8f9f7 3604 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
<> 144:ef7eb2e8f9f7 3605 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
<> 144:ef7eb2e8f9f7 3606 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
<> 144:ef7eb2e8f9f7 3607 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3608 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3609 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3610
<> 144:ef7eb2e8f9f7 3611 /* Bit 2 : Write '1' to Disable interrupt for UP event */
<> 144:ef7eb2e8f9f7 3612 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
<> 144:ef7eb2e8f9f7 3613 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
<> 144:ef7eb2e8f9f7 3614 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3615 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3616 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3617
<> 144:ef7eb2e8f9f7 3618 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
<> 144:ef7eb2e8f9f7 3619 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
<> 144:ef7eb2e8f9f7 3620 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
<> 144:ef7eb2e8f9f7 3621 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3622 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3623 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3624
<> 144:ef7eb2e8f9f7 3625 /* Bit 0 : Write '1' to Disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 3626 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 3627 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 3628 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3629 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3630 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3631
<> 144:ef7eb2e8f9f7 3632 /* Register: COMP_RESULT */
<> 144:ef7eb2e8f9f7 3633 /* Description: Compare result */
<> 144:ef7eb2e8f9f7 3634
<> 144:ef7eb2e8f9f7 3635 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
<> 144:ef7eb2e8f9f7 3636 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
<> 144:ef7eb2e8f9f7 3637 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
<> 144:ef7eb2e8f9f7 3638 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
<> 144:ef7eb2e8f9f7 3639 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
<> 144:ef7eb2e8f9f7 3640
<> 144:ef7eb2e8f9f7 3641 /* Register: COMP_ENABLE */
<> 144:ef7eb2e8f9f7 3642 /* Description: COMP enable */
<> 144:ef7eb2e8f9f7 3643
<> 144:ef7eb2e8f9f7 3644 /* Bits 1..0 : Enable or disable COMP */
<> 144:ef7eb2e8f9f7 3645 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 3646 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 3647 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3648 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3649
<> 144:ef7eb2e8f9f7 3650 /* Register: COMP_PSEL */
<> 144:ef7eb2e8f9f7 3651 /* Description: Pin select */
<> 144:ef7eb2e8f9f7 3652
<> 144:ef7eb2e8f9f7 3653 /* Bits 2..0 : Analog pin select */
<> 144:ef7eb2e8f9f7 3654 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
<> 144:ef7eb2e8f9f7 3655 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
<> 144:ef7eb2e8f9f7 3656 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
<> 144:ef7eb2e8f9f7 3657 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
<> 144:ef7eb2e8f9f7 3658 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
<> 144:ef7eb2e8f9f7 3659 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
<> 144:ef7eb2e8f9f7 3660 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
<> 144:ef7eb2e8f9f7 3661 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
<> 144:ef7eb2e8f9f7 3662 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
<> 144:ef7eb2e8f9f7 3663 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
<> 144:ef7eb2e8f9f7 3664
<> 144:ef7eb2e8f9f7 3665 /* Register: COMP_REFSEL */
<> 144:ef7eb2e8f9f7 3666 /* Description: Reference source select */
<> 144:ef7eb2e8f9f7 3667
<> 144:ef7eb2e8f9f7 3668 /* Bits 2..0 : Reference select */
<> 144:ef7eb2e8f9f7 3669 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
<> 144:ef7eb2e8f9f7 3670 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
<> 144:ef7eb2e8f9f7 3671 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
<> 144:ef7eb2e8f9f7 3672 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
<> 144:ef7eb2e8f9f7 3673 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
<> 144:ef7eb2e8f9f7 3674 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
<> 144:ef7eb2e8f9f7 3675 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
<> 144:ef7eb2e8f9f7 3676
<> 144:ef7eb2e8f9f7 3677 /* Register: COMP_EXTREFSEL */
<> 144:ef7eb2e8f9f7 3678 /* Description: External reference select */
<> 144:ef7eb2e8f9f7 3679
<> 144:ef7eb2e8f9f7 3680 /* Bit 0 : External analog reference select */
<> 144:ef7eb2e8f9f7 3681 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
<> 144:ef7eb2e8f9f7 3682 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
<> 144:ef7eb2e8f9f7 3683 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
<> 144:ef7eb2e8f9f7 3684 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
<> 144:ef7eb2e8f9f7 3685
<> 144:ef7eb2e8f9f7 3686 /* Register: COMP_TH */
<> 144:ef7eb2e8f9f7 3687 /* Description: Threshold configuration for hysteresis unit */
<> 144:ef7eb2e8f9f7 3688
<> 144:ef7eb2e8f9f7 3689 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
<> 144:ef7eb2e8f9f7 3690 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
<> 144:ef7eb2e8f9f7 3691 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
<> 144:ef7eb2e8f9f7 3692
<> 144:ef7eb2e8f9f7 3693 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
<> 144:ef7eb2e8f9f7 3694 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
<> 144:ef7eb2e8f9f7 3695 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
<> 144:ef7eb2e8f9f7 3696
<> 144:ef7eb2e8f9f7 3697 /* Register: COMP_MODE */
<> 144:ef7eb2e8f9f7 3698 /* Description: Mode configuration */
<> 144:ef7eb2e8f9f7 3699
<> 144:ef7eb2e8f9f7 3700 /* Bit 8 : Main operation mode */
<> 144:ef7eb2e8f9f7 3701 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
<> 144:ef7eb2e8f9f7 3702 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
<> 144:ef7eb2e8f9f7 3703 #define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
<> 144:ef7eb2e8f9f7 3704 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
<> 144:ef7eb2e8f9f7 3705
<> 144:ef7eb2e8f9f7 3706 /* Bits 1..0 : Speed and power mode */
<> 144:ef7eb2e8f9f7 3707 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
<> 144:ef7eb2e8f9f7 3708 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
<> 144:ef7eb2e8f9f7 3709 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
<> 144:ef7eb2e8f9f7 3710 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
<> 144:ef7eb2e8f9f7 3711 #define COMP_MODE_SP_High (2UL) /*!< High speed mode */
<> 144:ef7eb2e8f9f7 3712
<> 144:ef7eb2e8f9f7 3713 /* Register: COMP_HYST */
<> 144:ef7eb2e8f9f7 3714 /* Description: Comparator hysteresis enable */
<> 144:ef7eb2e8f9f7 3715
<> 144:ef7eb2e8f9f7 3716 /* Bit 0 : Comparator hysteresis */
<> 144:ef7eb2e8f9f7 3717 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
<> 144:ef7eb2e8f9f7 3718 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
<> 144:ef7eb2e8f9f7 3719 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
<> 144:ef7eb2e8f9f7 3720 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
<> 144:ef7eb2e8f9f7 3721
<> 144:ef7eb2e8f9f7 3722 /* Register: COMP_ISOURCE */
<> 144:ef7eb2e8f9f7 3723 /* Description: Current source select on analog input */
<> 144:ef7eb2e8f9f7 3724
<> 144:ef7eb2e8f9f7 3725 /* Bits 1..0 : Comparator hysteresis */
<> 144:ef7eb2e8f9f7 3726 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
<> 144:ef7eb2e8f9f7 3727 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
<> 144:ef7eb2e8f9f7 3728 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
<> 144:ef7eb2e8f9f7 3729 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
<> 144:ef7eb2e8f9f7 3730 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
<> 144:ef7eb2e8f9f7 3731 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
<> 144:ef7eb2e8f9f7 3732
<> 144:ef7eb2e8f9f7 3733
<> 144:ef7eb2e8f9f7 3734 /* Peripheral: ECB */
<> 144:ef7eb2e8f9f7 3735 /* Description: AES ECB Mode Encryption */
<> 144:ef7eb2e8f9f7 3736
<> 144:ef7eb2e8f9f7 3737 /* Register: ECB_INTENSET */
<> 144:ef7eb2e8f9f7 3738 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 3739
<> 144:ef7eb2e8f9f7 3740 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
<> 144:ef7eb2e8f9f7 3741 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
<> 144:ef7eb2e8f9f7 3742 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
<> 144:ef7eb2e8f9f7 3743 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3744 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3745 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3746
<> 144:ef7eb2e8f9f7 3747 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
<> 144:ef7eb2e8f9f7 3748 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
<> 144:ef7eb2e8f9f7 3749 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
<> 144:ef7eb2e8f9f7 3750 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3751 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3752 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3753
<> 144:ef7eb2e8f9f7 3754 /* Register: ECB_INTENCLR */
<> 144:ef7eb2e8f9f7 3755 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 3756
<> 144:ef7eb2e8f9f7 3757 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
<> 144:ef7eb2e8f9f7 3758 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
<> 144:ef7eb2e8f9f7 3759 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
<> 144:ef7eb2e8f9f7 3760 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3761 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3762 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3763
<> 144:ef7eb2e8f9f7 3764 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
<> 144:ef7eb2e8f9f7 3765 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
<> 144:ef7eb2e8f9f7 3766 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
<> 144:ef7eb2e8f9f7 3767 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3768 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3769 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3770
<> 144:ef7eb2e8f9f7 3771 /* Register: ECB_ECBDATAPTR */
<> 144:ef7eb2e8f9f7 3772 /* Description: ECB block encrypt memory pointers */
<> 144:ef7eb2e8f9f7 3773
<> 144:ef7eb2e8f9f7 3774 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
<> 144:ef7eb2e8f9f7 3775 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
<> 144:ef7eb2e8f9f7 3776 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
<> 144:ef7eb2e8f9f7 3777
<> 144:ef7eb2e8f9f7 3778
<> 144:ef7eb2e8f9f7 3779 /* Peripheral: EGU */
<> 144:ef7eb2e8f9f7 3780 /* Description: Event Generator Unit 0 */
<> 144:ef7eb2e8f9f7 3781
<> 144:ef7eb2e8f9f7 3782 /* Register: EGU_INTEN */
<> 144:ef7eb2e8f9f7 3783 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 3784
<> 144:ef7eb2e8f9f7 3785 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
<> 144:ef7eb2e8f9f7 3786 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
<> 144:ef7eb2e8f9f7 3787 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
<> 144:ef7eb2e8f9f7 3788 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3789 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3790
<> 144:ef7eb2e8f9f7 3791 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
<> 144:ef7eb2e8f9f7 3792 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
<> 144:ef7eb2e8f9f7 3793 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
<> 144:ef7eb2e8f9f7 3794 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3795 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3796
<> 144:ef7eb2e8f9f7 3797 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
<> 144:ef7eb2e8f9f7 3798 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
<> 144:ef7eb2e8f9f7 3799 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
<> 144:ef7eb2e8f9f7 3800 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3801 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3802
<> 144:ef7eb2e8f9f7 3803 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
<> 144:ef7eb2e8f9f7 3804 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
<> 144:ef7eb2e8f9f7 3805 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
<> 144:ef7eb2e8f9f7 3806 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3807 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3808
<> 144:ef7eb2e8f9f7 3809 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
<> 144:ef7eb2e8f9f7 3810 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
<> 144:ef7eb2e8f9f7 3811 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
<> 144:ef7eb2e8f9f7 3812 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3813 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3814
<> 144:ef7eb2e8f9f7 3815 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
<> 144:ef7eb2e8f9f7 3816 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
<> 144:ef7eb2e8f9f7 3817 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
<> 144:ef7eb2e8f9f7 3818 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3819 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3820
<> 144:ef7eb2e8f9f7 3821 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
<> 144:ef7eb2e8f9f7 3822 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
<> 144:ef7eb2e8f9f7 3823 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
<> 144:ef7eb2e8f9f7 3824 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3825 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3826
<> 144:ef7eb2e8f9f7 3827 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
<> 144:ef7eb2e8f9f7 3828 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
<> 144:ef7eb2e8f9f7 3829 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
<> 144:ef7eb2e8f9f7 3830 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3831 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3832
<> 144:ef7eb2e8f9f7 3833 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
<> 144:ef7eb2e8f9f7 3834 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
<> 144:ef7eb2e8f9f7 3835 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
<> 144:ef7eb2e8f9f7 3836 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3837 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3838
<> 144:ef7eb2e8f9f7 3839 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
<> 144:ef7eb2e8f9f7 3840 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
<> 144:ef7eb2e8f9f7 3841 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
<> 144:ef7eb2e8f9f7 3842 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3843 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3844
<> 144:ef7eb2e8f9f7 3845 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
<> 144:ef7eb2e8f9f7 3846 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
<> 144:ef7eb2e8f9f7 3847 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
<> 144:ef7eb2e8f9f7 3848 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3849 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3850
<> 144:ef7eb2e8f9f7 3851 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
<> 144:ef7eb2e8f9f7 3852 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
<> 144:ef7eb2e8f9f7 3853 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
<> 144:ef7eb2e8f9f7 3854 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3855 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3856
<> 144:ef7eb2e8f9f7 3857 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
<> 144:ef7eb2e8f9f7 3858 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
<> 144:ef7eb2e8f9f7 3859 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
<> 144:ef7eb2e8f9f7 3860 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3861 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3862
<> 144:ef7eb2e8f9f7 3863 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
<> 144:ef7eb2e8f9f7 3864 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
<> 144:ef7eb2e8f9f7 3865 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
<> 144:ef7eb2e8f9f7 3866 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3867 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3868
<> 144:ef7eb2e8f9f7 3869 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
<> 144:ef7eb2e8f9f7 3870 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
<> 144:ef7eb2e8f9f7 3871 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
<> 144:ef7eb2e8f9f7 3872 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3873 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3874
<> 144:ef7eb2e8f9f7 3875 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
<> 144:ef7eb2e8f9f7 3876 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
<> 144:ef7eb2e8f9f7 3877 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
<> 144:ef7eb2e8f9f7 3878 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 3879 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3880
<> 144:ef7eb2e8f9f7 3881 /* Register: EGU_INTENSET */
<> 144:ef7eb2e8f9f7 3882 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 3883
<> 144:ef7eb2e8f9f7 3884 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
<> 144:ef7eb2e8f9f7 3885 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
<> 144:ef7eb2e8f9f7 3886 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
<> 144:ef7eb2e8f9f7 3887 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3888 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3889 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3890
<> 144:ef7eb2e8f9f7 3891 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
<> 144:ef7eb2e8f9f7 3892 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
<> 144:ef7eb2e8f9f7 3893 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
<> 144:ef7eb2e8f9f7 3894 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3895 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3896 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3897
<> 144:ef7eb2e8f9f7 3898 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
<> 144:ef7eb2e8f9f7 3899 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
<> 144:ef7eb2e8f9f7 3900 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
<> 144:ef7eb2e8f9f7 3901 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3902 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3903 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3904
<> 144:ef7eb2e8f9f7 3905 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
<> 144:ef7eb2e8f9f7 3906 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
<> 144:ef7eb2e8f9f7 3907 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
<> 144:ef7eb2e8f9f7 3908 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3909 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3910 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3911
<> 144:ef7eb2e8f9f7 3912 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
<> 144:ef7eb2e8f9f7 3913 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
<> 144:ef7eb2e8f9f7 3914 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
<> 144:ef7eb2e8f9f7 3915 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3916 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3917 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3918
<> 144:ef7eb2e8f9f7 3919 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
<> 144:ef7eb2e8f9f7 3920 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
<> 144:ef7eb2e8f9f7 3921 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
<> 144:ef7eb2e8f9f7 3922 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3923 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3924 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3925
<> 144:ef7eb2e8f9f7 3926 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
<> 144:ef7eb2e8f9f7 3927 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
<> 144:ef7eb2e8f9f7 3928 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
<> 144:ef7eb2e8f9f7 3929 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3930 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3931 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3932
<> 144:ef7eb2e8f9f7 3933 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
<> 144:ef7eb2e8f9f7 3934 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
<> 144:ef7eb2e8f9f7 3935 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
<> 144:ef7eb2e8f9f7 3936 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3937 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3938 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3939
<> 144:ef7eb2e8f9f7 3940 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
<> 144:ef7eb2e8f9f7 3941 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
<> 144:ef7eb2e8f9f7 3942 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
<> 144:ef7eb2e8f9f7 3943 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3944 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3945 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3946
<> 144:ef7eb2e8f9f7 3947 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
<> 144:ef7eb2e8f9f7 3948 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
<> 144:ef7eb2e8f9f7 3949 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
<> 144:ef7eb2e8f9f7 3950 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3951 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3952 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3953
<> 144:ef7eb2e8f9f7 3954 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
<> 144:ef7eb2e8f9f7 3955 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
<> 144:ef7eb2e8f9f7 3956 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
<> 144:ef7eb2e8f9f7 3957 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3958 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3959 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3960
<> 144:ef7eb2e8f9f7 3961 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
<> 144:ef7eb2e8f9f7 3962 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
<> 144:ef7eb2e8f9f7 3963 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
<> 144:ef7eb2e8f9f7 3964 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3965 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3966 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3967
<> 144:ef7eb2e8f9f7 3968 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
<> 144:ef7eb2e8f9f7 3969 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
<> 144:ef7eb2e8f9f7 3970 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
<> 144:ef7eb2e8f9f7 3971 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3972 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3973 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3974
<> 144:ef7eb2e8f9f7 3975 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
<> 144:ef7eb2e8f9f7 3976 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
<> 144:ef7eb2e8f9f7 3977 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
<> 144:ef7eb2e8f9f7 3978 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3979 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3980 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3981
<> 144:ef7eb2e8f9f7 3982 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
<> 144:ef7eb2e8f9f7 3983 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
<> 144:ef7eb2e8f9f7 3984 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
<> 144:ef7eb2e8f9f7 3985 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3986 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3987 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3988
<> 144:ef7eb2e8f9f7 3989 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
<> 144:ef7eb2e8f9f7 3990 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
<> 144:ef7eb2e8f9f7 3991 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
<> 144:ef7eb2e8f9f7 3992 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 3993 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 3994 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 3995
<> 144:ef7eb2e8f9f7 3996 /* Register: EGU_INTENCLR */
<> 144:ef7eb2e8f9f7 3997 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 3998
<> 144:ef7eb2e8f9f7 3999 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
<> 144:ef7eb2e8f9f7 4000 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
<> 144:ef7eb2e8f9f7 4001 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
<> 144:ef7eb2e8f9f7 4002 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4003 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4004 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4005
<> 144:ef7eb2e8f9f7 4006 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
<> 144:ef7eb2e8f9f7 4007 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
<> 144:ef7eb2e8f9f7 4008 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
<> 144:ef7eb2e8f9f7 4009 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4010 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4011 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4012
<> 144:ef7eb2e8f9f7 4013 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
<> 144:ef7eb2e8f9f7 4014 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
<> 144:ef7eb2e8f9f7 4015 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
<> 144:ef7eb2e8f9f7 4016 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4017 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4018 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4019
<> 144:ef7eb2e8f9f7 4020 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
<> 144:ef7eb2e8f9f7 4021 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
<> 144:ef7eb2e8f9f7 4022 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
<> 144:ef7eb2e8f9f7 4023 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4024 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4025 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4026
<> 144:ef7eb2e8f9f7 4027 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
<> 144:ef7eb2e8f9f7 4028 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
<> 144:ef7eb2e8f9f7 4029 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
<> 144:ef7eb2e8f9f7 4030 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4031 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4032 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4033
<> 144:ef7eb2e8f9f7 4034 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
<> 144:ef7eb2e8f9f7 4035 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
<> 144:ef7eb2e8f9f7 4036 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
<> 144:ef7eb2e8f9f7 4037 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4038 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4039 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4040
<> 144:ef7eb2e8f9f7 4041 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
<> 144:ef7eb2e8f9f7 4042 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
<> 144:ef7eb2e8f9f7 4043 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
<> 144:ef7eb2e8f9f7 4044 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4045 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4046 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4047
<> 144:ef7eb2e8f9f7 4048 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
<> 144:ef7eb2e8f9f7 4049 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
<> 144:ef7eb2e8f9f7 4050 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
<> 144:ef7eb2e8f9f7 4051 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4052 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4053 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4054
<> 144:ef7eb2e8f9f7 4055 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
<> 144:ef7eb2e8f9f7 4056 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
<> 144:ef7eb2e8f9f7 4057 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
<> 144:ef7eb2e8f9f7 4058 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4059 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4060 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4061
<> 144:ef7eb2e8f9f7 4062 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
<> 144:ef7eb2e8f9f7 4063 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
<> 144:ef7eb2e8f9f7 4064 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
<> 144:ef7eb2e8f9f7 4065 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4066 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4067 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4068
<> 144:ef7eb2e8f9f7 4069 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
<> 144:ef7eb2e8f9f7 4070 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
<> 144:ef7eb2e8f9f7 4071 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
<> 144:ef7eb2e8f9f7 4072 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4073 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4074 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4075
<> 144:ef7eb2e8f9f7 4076 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
<> 144:ef7eb2e8f9f7 4077 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
<> 144:ef7eb2e8f9f7 4078 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
<> 144:ef7eb2e8f9f7 4079 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4080 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4081 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4082
<> 144:ef7eb2e8f9f7 4083 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
<> 144:ef7eb2e8f9f7 4084 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
<> 144:ef7eb2e8f9f7 4085 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
<> 144:ef7eb2e8f9f7 4086 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4087 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4088 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4089
<> 144:ef7eb2e8f9f7 4090 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
<> 144:ef7eb2e8f9f7 4091 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
<> 144:ef7eb2e8f9f7 4092 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
<> 144:ef7eb2e8f9f7 4093 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4094 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4095 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4096
<> 144:ef7eb2e8f9f7 4097 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
<> 144:ef7eb2e8f9f7 4098 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
<> 144:ef7eb2e8f9f7 4099 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
<> 144:ef7eb2e8f9f7 4100 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4101 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4102 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4103
<> 144:ef7eb2e8f9f7 4104 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
<> 144:ef7eb2e8f9f7 4105 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
<> 144:ef7eb2e8f9f7 4106 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
<> 144:ef7eb2e8f9f7 4107 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4108 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4109 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4110
<> 144:ef7eb2e8f9f7 4111
<> 144:ef7eb2e8f9f7 4112 /* Peripheral: FICR */
<> 144:ef7eb2e8f9f7 4113 /* Description: Factory Information Configuration Registers */
<> 144:ef7eb2e8f9f7 4114
<> 144:ef7eb2e8f9f7 4115 /* Register: FICR_CODEPAGESIZE */
<> 144:ef7eb2e8f9f7 4116 /* Description: Code memory page size */
<> 144:ef7eb2e8f9f7 4117
<> 144:ef7eb2e8f9f7 4118 /* Bits 31..0 : Code memory page size */
<> 144:ef7eb2e8f9f7 4119 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
<> 144:ef7eb2e8f9f7 4120 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
<> 144:ef7eb2e8f9f7 4121
<> 144:ef7eb2e8f9f7 4122 /* Register: FICR_CODESIZE */
<> 144:ef7eb2e8f9f7 4123 /* Description: Code memory size */
<> 144:ef7eb2e8f9f7 4124
<> 144:ef7eb2e8f9f7 4125 /* Bits 31..0 : Code memory size in number of pages */
<> 144:ef7eb2e8f9f7 4126 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
<> 144:ef7eb2e8f9f7 4127 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
<> 144:ef7eb2e8f9f7 4128
<> 144:ef7eb2e8f9f7 4129 /* Register: FICR_DEVICEID */
<> 144:ef7eb2e8f9f7 4130 /* Description: Description collection[0]: Device identifier */
<> 144:ef7eb2e8f9f7 4131
<> 144:ef7eb2e8f9f7 4132 /* Bits 31..0 : 64 bit unique device identifier */
<> 144:ef7eb2e8f9f7 4133 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
<> 144:ef7eb2e8f9f7 4134 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
<> 144:ef7eb2e8f9f7 4135
<> 144:ef7eb2e8f9f7 4136 /* Register: FICR_ER */
<> 144:ef7eb2e8f9f7 4137 /* Description: Description collection[0]: Encryption Root, word 0 */
<> 144:ef7eb2e8f9f7 4138
<> 144:ef7eb2e8f9f7 4139 /* Bits 31..0 : Encryption Root, word n */
<> 144:ef7eb2e8f9f7 4140 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
<> 144:ef7eb2e8f9f7 4141 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
<> 144:ef7eb2e8f9f7 4142
<> 144:ef7eb2e8f9f7 4143 /* Register: FICR_IR */
<> 144:ef7eb2e8f9f7 4144 /* Description: Description collection[0]: Identity Root, word 0 */
<> 144:ef7eb2e8f9f7 4145
<> 144:ef7eb2e8f9f7 4146 /* Bits 31..0 : Identity Root, word n */
<> 144:ef7eb2e8f9f7 4147 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
<> 144:ef7eb2e8f9f7 4148 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
<> 144:ef7eb2e8f9f7 4149
<> 144:ef7eb2e8f9f7 4150 /* Register: FICR_DEVICEADDRTYPE */
<> 144:ef7eb2e8f9f7 4151 /* Description: Device address type */
<> 144:ef7eb2e8f9f7 4152
<> 144:ef7eb2e8f9f7 4153 /* Bit 0 : Device address type */
<> 144:ef7eb2e8f9f7 4154 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
<> 144:ef7eb2e8f9f7 4155 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
<> 144:ef7eb2e8f9f7 4156 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
<> 144:ef7eb2e8f9f7 4157 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
<> 144:ef7eb2e8f9f7 4158
<> 144:ef7eb2e8f9f7 4159 /* Register: FICR_DEVICEADDR */
<> 144:ef7eb2e8f9f7 4160 /* Description: Description collection[0]: Device address 0 */
<> 144:ef7eb2e8f9f7 4161
<> 144:ef7eb2e8f9f7 4162 /* Bits 31..0 : 48 bit device address */
<> 144:ef7eb2e8f9f7 4163 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
<> 144:ef7eb2e8f9f7 4164 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
<> 144:ef7eb2e8f9f7 4165
<> 144:ef7eb2e8f9f7 4166 /* Register: FICR_INFO_PART */
<> 144:ef7eb2e8f9f7 4167 /* Description: Part code */
<> 144:ef7eb2e8f9f7 4168
<> 144:ef7eb2e8f9f7 4169 /* Bits 31..0 : Part code */
<> 144:ef7eb2e8f9f7 4170 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
<> 144:ef7eb2e8f9f7 4171 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
<> 144:ef7eb2e8f9f7 4172 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
<> 144:ef7eb2e8f9f7 4173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
<> 144:ef7eb2e8f9f7 4174
<> 144:ef7eb2e8f9f7 4175 /* Register: FICR_INFO_VARIANT */
<> 144:ef7eb2e8f9f7 4176 /* Description: Part Variant, Hardware version and Production configuration */
<> 144:ef7eb2e8f9f7 4177
<> 144:ef7eb2e8f9f7 4178 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
<> 144:ef7eb2e8f9f7 4179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
<> 144:ef7eb2e8f9f7 4180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
<> 144:ef7eb2e8f9f7 4181 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
<> 144:ef7eb2e8f9f7 4182 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
<> 144:ef7eb2e8f9f7 4183 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
<> 144:ef7eb2e8f9f7 4184 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
<> 144:ef7eb2e8f9f7 4185 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
<> 144:ef7eb2e8f9f7 4186
<> 144:ef7eb2e8f9f7 4187 /* Register: FICR_INFO_PACKAGE */
<> 144:ef7eb2e8f9f7 4188 /* Description: Package option */
<> 144:ef7eb2e8f9f7 4189
<> 144:ef7eb2e8f9f7 4190 /* Bits 31..0 : Package option */
<> 144:ef7eb2e8f9f7 4191 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
<> 144:ef7eb2e8f9f7 4192 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
<> 144:ef7eb2e8f9f7 4193 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
<> 144:ef7eb2e8f9f7 4194 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
<> 144:ef7eb2e8f9f7 4195 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
<> 144:ef7eb2e8f9f7 4196
<> 144:ef7eb2e8f9f7 4197 /* Register: FICR_INFO_RAM */
<> 144:ef7eb2e8f9f7 4198 /* Description: RAM variant */
<> 144:ef7eb2e8f9f7 4199
<> 144:ef7eb2e8f9f7 4200 /* Bits 31..0 : RAM variant */
<> 144:ef7eb2e8f9f7 4201 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
<> 144:ef7eb2e8f9f7 4202 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
<> 144:ef7eb2e8f9f7 4203 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
<> 144:ef7eb2e8f9f7 4204 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
<> 144:ef7eb2e8f9f7 4205 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
<> 144:ef7eb2e8f9f7 4206 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
<> 144:ef7eb2e8f9f7 4207
<> 144:ef7eb2e8f9f7 4208 /* Register: FICR_INFO_FLASH */
<> 144:ef7eb2e8f9f7 4209 /* Description: Flash variant */
<> 144:ef7eb2e8f9f7 4210
<> 144:ef7eb2e8f9f7 4211 /* Bits 31..0 : Flash variant */
<> 144:ef7eb2e8f9f7 4212 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
<> 144:ef7eb2e8f9f7 4213 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
<> 144:ef7eb2e8f9f7 4214 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
<> 144:ef7eb2e8f9f7 4215 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
<> 144:ef7eb2e8f9f7 4216 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
<> 144:ef7eb2e8f9f7 4217 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
<> 144:ef7eb2e8f9f7 4218
<> 144:ef7eb2e8f9f7 4219 /* Register: FICR_TEMP_A0 */
<> 144:ef7eb2e8f9f7 4220 /* Description: Slope definition A0. */
<> 144:ef7eb2e8f9f7 4221
<> 144:ef7eb2e8f9f7 4222 /* Bits 11..0 : A (slope definition) register. */
<> 144:ef7eb2e8f9f7 4223 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
<> 144:ef7eb2e8f9f7 4224 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
<> 144:ef7eb2e8f9f7 4225
<> 144:ef7eb2e8f9f7 4226 /* Register: FICR_TEMP_A1 */
<> 144:ef7eb2e8f9f7 4227 /* Description: Slope definition A1. */
<> 144:ef7eb2e8f9f7 4228
<> 144:ef7eb2e8f9f7 4229 /* Bits 11..0 : A (slope definition) register. */
<> 144:ef7eb2e8f9f7 4230 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
<> 144:ef7eb2e8f9f7 4231 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
<> 144:ef7eb2e8f9f7 4232
<> 144:ef7eb2e8f9f7 4233 /* Register: FICR_TEMP_A2 */
<> 144:ef7eb2e8f9f7 4234 /* Description: Slope definition A2. */
<> 144:ef7eb2e8f9f7 4235
<> 144:ef7eb2e8f9f7 4236 /* Bits 11..0 : A (slope definition) register. */
<> 144:ef7eb2e8f9f7 4237 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
<> 144:ef7eb2e8f9f7 4238 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
<> 144:ef7eb2e8f9f7 4239
<> 144:ef7eb2e8f9f7 4240 /* Register: FICR_TEMP_A3 */
<> 144:ef7eb2e8f9f7 4241 /* Description: Slope definition A3. */
<> 144:ef7eb2e8f9f7 4242
<> 144:ef7eb2e8f9f7 4243 /* Bits 11..0 : A (slope definition) register. */
<> 144:ef7eb2e8f9f7 4244 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
<> 144:ef7eb2e8f9f7 4245 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
<> 144:ef7eb2e8f9f7 4246
<> 144:ef7eb2e8f9f7 4247 /* Register: FICR_TEMP_A4 */
<> 144:ef7eb2e8f9f7 4248 /* Description: Slope definition A4. */
<> 144:ef7eb2e8f9f7 4249
<> 144:ef7eb2e8f9f7 4250 /* Bits 11..0 : A (slope definition) register. */
<> 144:ef7eb2e8f9f7 4251 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
<> 144:ef7eb2e8f9f7 4252 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
<> 144:ef7eb2e8f9f7 4253
<> 144:ef7eb2e8f9f7 4254 /* Register: FICR_TEMP_A5 */
<> 144:ef7eb2e8f9f7 4255 /* Description: Slope definition A5. */
<> 144:ef7eb2e8f9f7 4256
<> 144:ef7eb2e8f9f7 4257 /* Bits 11..0 : A (slope definition) register. */
<> 144:ef7eb2e8f9f7 4258 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
<> 144:ef7eb2e8f9f7 4259 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
<> 144:ef7eb2e8f9f7 4260
<> 144:ef7eb2e8f9f7 4261 /* Register: FICR_TEMP_B0 */
<> 144:ef7eb2e8f9f7 4262 /* Description: y-intercept B0. */
<> 144:ef7eb2e8f9f7 4263
<> 144:ef7eb2e8f9f7 4264 /* Bits 13..0 : B (y-intercept) */
<> 144:ef7eb2e8f9f7 4265 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
<> 144:ef7eb2e8f9f7 4266 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
<> 144:ef7eb2e8f9f7 4267
<> 144:ef7eb2e8f9f7 4268 /* Register: FICR_TEMP_B1 */
<> 144:ef7eb2e8f9f7 4269 /* Description: y-intercept B1. */
<> 144:ef7eb2e8f9f7 4270
<> 144:ef7eb2e8f9f7 4271 /* Bits 13..0 : B (y-intercept) */
<> 144:ef7eb2e8f9f7 4272 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
<> 144:ef7eb2e8f9f7 4273 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
<> 144:ef7eb2e8f9f7 4274
<> 144:ef7eb2e8f9f7 4275 /* Register: FICR_TEMP_B2 */
<> 144:ef7eb2e8f9f7 4276 /* Description: y-intercept B2. */
<> 144:ef7eb2e8f9f7 4277
<> 144:ef7eb2e8f9f7 4278 /* Bits 13..0 : B (y-intercept) */
<> 144:ef7eb2e8f9f7 4279 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
<> 144:ef7eb2e8f9f7 4280 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
<> 144:ef7eb2e8f9f7 4281
<> 144:ef7eb2e8f9f7 4282 /* Register: FICR_TEMP_B3 */
<> 144:ef7eb2e8f9f7 4283 /* Description: y-intercept B3. */
<> 144:ef7eb2e8f9f7 4284
<> 144:ef7eb2e8f9f7 4285 /* Bits 13..0 : B (y-intercept) */
<> 144:ef7eb2e8f9f7 4286 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
<> 144:ef7eb2e8f9f7 4287 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
<> 144:ef7eb2e8f9f7 4288
<> 144:ef7eb2e8f9f7 4289 /* Register: FICR_TEMP_B4 */
<> 144:ef7eb2e8f9f7 4290 /* Description: y-intercept B4. */
<> 144:ef7eb2e8f9f7 4291
<> 144:ef7eb2e8f9f7 4292 /* Bits 13..0 : B (y-intercept) */
<> 144:ef7eb2e8f9f7 4293 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
<> 144:ef7eb2e8f9f7 4294 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
<> 144:ef7eb2e8f9f7 4295
<> 144:ef7eb2e8f9f7 4296 /* Register: FICR_TEMP_B5 */
<> 144:ef7eb2e8f9f7 4297 /* Description: y-intercept B5. */
<> 144:ef7eb2e8f9f7 4298
<> 144:ef7eb2e8f9f7 4299 /* Bits 13..0 : B (y-intercept) */
<> 144:ef7eb2e8f9f7 4300 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
<> 144:ef7eb2e8f9f7 4301 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
<> 144:ef7eb2e8f9f7 4302
<> 144:ef7eb2e8f9f7 4303 /* Register: FICR_TEMP_T0 */
<> 144:ef7eb2e8f9f7 4304 /* Description: Segment end T0. */
<> 144:ef7eb2e8f9f7 4305
<> 144:ef7eb2e8f9f7 4306 /* Bits 7..0 : T (segment end)register. */
<> 144:ef7eb2e8f9f7 4307 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
<> 144:ef7eb2e8f9f7 4308 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
<> 144:ef7eb2e8f9f7 4309
<> 144:ef7eb2e8f9f7 4310 /* Register: FICR_TEMP_T1 */
<> 144:ef7eb2e8f9f7 4311 /* Description: Segment end T1. */
<> 144:ef7eb2e8f9f7 4312
<> 144:ef7eb2e8f9f7 4313 /* Bits 7..0 : T (segment end)register. */
<> 144:ef7eb2e8f9f7 4314 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
<> 144:ef7eb2e8f9f7 4315 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
<> 144:ef7eb2e8f9f7 4316
<> 144:ef7eb2e8f9f7 4317 /* Register: FICR_TEMP_T2 */
<> 144:ef7eb2e8f9f7 4318 /* Description: Segment end T2. */
<> 144:ef7eb2e8f9f7 4319
<> 144:ef7eb2e8f9f7 4320 /* Bits 7..0 : T (segment end)register. */
<> 144:ef7eb2e8f9f7 4321 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
<> 144:ef7eb2e8f9f7 4322 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
<> 144:ef7eb2e8f9f7 4323
<> 144:ef7eb2e8f9f7 4324 /* Register: FICR_TEMP_T3 */
<> 144:ef7eb2e8f9f7 4325 /* Description: Segment end T3. */
<> 144:ef7eb2e8f9f7 4326
<> 144:ef7eb2e8f9f7 4327 /* Bits 7..0 : T (segment end)register. */
<> 144:ef7eb2e8f9f7 4328 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
<> 144:ef7eb2e8f9f7 4329 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
<> 144:ef7eb2e8f9f7 4330
<> 144:ef7eb2e8f9f7 4331 /* Register: FICR_TEMP_T4 */
<> 144:ef7eb2e8f9f7 4332 /* Description: Segment end T4. */
<> 144:ef7eb2e8f9f7 4333
<> 144:ef7eb2e8f9f7 4334 /* Bits 7..0 : T (segment end)register. */
<> 144:ef7eb2e8f9f7 4335 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
<> 144:ef7eb2e8f9f7 4336 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
<> 144:ef7eb2e8f9f7 4337
<> 144:ef7eb2e8f9f7 4338 /* Register: FICR_NFC_TAGHEADER0 */
<> 144:ef7eb2e8f9f7 4339 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
<> 144:ef7eb2e8f9f7 4340
<> 144:ef7eb2e8f9f7 4341 /* Bits 31..24 : Unique identifier byte 3 */
<> 144:ef7eb2e8f9f7 4342 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
<> 144:ef7eb2e8f9f7 4343 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
<> 144:ef7eb2e8f9f7 4344
<> 144:ef7eb2e8f9f7 4345 /* Bits 23..16 : Unique identifier byte 2 */
<> 144:ef7eb2e8f9f7 4346 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
<> 144:ef7eb2e8f9f7 4347 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
<> 144:ef7eb2e8f9f7 4348
<> 144:ef7eb2e8f9f7 4349 /* Bits 15..8 : Unique identifier byte 1 */
<> 144:ef7eb2e8f9f7 4350 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
<> 144:ef7eb2e8f9f7 4351 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
<> 144:ef7eb2e8f9f7 4352
<> 144:ef7eb2e8f9f7 4353 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
<> 144:ef7eb2e8f9f7 4354 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
<> 144:ef7eb2e8f9f7 4355 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
<> 144:ef7eb2e8f9f7 4356
<> 144:ef7eb2e8f9f7 4357 /* Register: FICR_NFC_TAGHEADER1 */
<> 144:ef7eb2e8f9f7 4358 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
<> 144:ef7eb2e8f9f7 4359
<> 144:ef7eb2e8f9f7 4360 /* Bits 31..24 : Unique identifier byte 7 */
<> 144:ef7eb2e8f9f7 4361 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
<> 144:ef7eb2e8f9f7 4362 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
<> 144:ef7eb2e8f9f7 4363
<> 144:ef7eb2e8f9f7 4364 /* Bits 23..16 : Unique identifier byte 6 */
<> 144:ef7eb2e8f9f7 4365 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
<> 144:ef7eb2e8f9f7 4366 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
<> 144:ef7eb2e8f9f7 4367
<> 144:ef7eb2e8f9f7 4368 /* Bits 15..8 : Unique identifier byte 5 */
<> 144:ef7eb2e8f9f7 4369 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
<> 144:ef7eb2e8f9f7 4370 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
<> 144:ef7eb2e8f9f7 4371
<> 144:ef7eb2e8f9f7 4372 /* Bits 7..0 : Unique identifier byte 4 */
<> 144:ef7eb2e8f9f7 4373 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
<> 144:ef7eb2e8f9f7 4374 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
<> 144:ef7eb2e8f9f7 4375
<> 144:ef7eb2e8f9f7 4376 /* Register: FICR_NFC_TAGHEADER2 */
<> 144:ef7eb2e8f9f7 4377 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
<> 144:ef7eb2e8f9f7 4378
<> 144:ef7eb2e8f9f7 4379 /* Bits 31..24 : Unique identifier byte 11 */
<> 144:ef7eb2e8f9f7 4380 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
<> 144:ef7eb2e8f9f7 4381 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
<> 144:ef7eb2e8f9f7 4382
<> 144:ef7eb2e8f9f7 4383 /* Bits 23..16 : Unique identifier byte 10 */
<> 144:ef7eb2e8f9f7 4384 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
<> 144:ef7eb2e8f9f7 4385 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
<> 144:ef7eb2e8f9f7 4386
<> 144:ef7eb2e8f9f7 4387 /* Bits 15..8 : Unique identifier byte 9 */
<> 144:ef7eb2e8f9f7 4388 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
<> 144:ef7eb2e8f9f7 4389 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
<> 144:ef7eb2e8f9f7 4390
<> 144:ef7eb2e8f9f7 4391 /* Bits 7..0 : Unique identifier byte 8 */
<> 144:ef7eb2e8f9f7 4392 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
<> 144:ef7eb2e8f9f7 4393 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
<> 144:ef7eb2e8f9f7 4394
<> 144:ef7eb2e8f9f7 4395 /* Register: FICR_NFC_TAGHEADER3 */
<> 144:ef7eb2e8f9f7 4396 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
<> 144:ef7eb2e8f9f7 4397
<> 144:ef7eb2e8f9f7 4398 /* Bits 31..24 : Unique identifier byte 15 */
<> 144:ef7eb2e8f9f7 4399 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
<> 144:ef7eb2e8f9f7 4400 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
<> 144:ef7eb2e8f9f7 4401
<> 144:ef7eb2e8f9f7 4402 /* Bits 23..16 : Unique identifier byte 14 */
<> 144:ef7eb2e8f9f7 4403 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
<> 144:ef7eb2e8f9f7 4404 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
<> 144:ef7eb2e8f9f7 4405
<> 144:ef7eb2e8f9f7 4406 /* Bits 15..8 : Unique identifier byte 13 */
<> 144:ef7eb2e8f9f7 4407 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
<> 144:ef7eb2e8f9f7 4408 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
<> 144:ef7eb2e8f9f7 4409
<> 144:ef7eb2e8f9f7 4410 /* Bits 7..0 : Unique identifier byte 12 */
<> 144:ef7eb2e8f9f7 4411 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
<> 144:ef7eb2e8f9f7 4412 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
<> 144:ef7eb2e8f9f7 4413
<> 144:ef7eb2e8f9f7 4414
<> 144:ef7eb2e8f9f7 4415 /* Peripheral: GPIOTE */
<> 144:ef7eb2e8f9f7 4416 /* Description: GPIO Tasks and Events */
<> 144:ef7eb2e8f9f7 4417
<> 144:ef7eb2e8f9f7 4418 /* Register: GPIOTE_INTENSET */
<> 144:ef7eb2e8f9f7 4419 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 4420
<> 144:ef7eb2e8f9f7 4421 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
<> 144:ef7eb2e8f9f7 4422 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
<> 144:ef7eb2e8f9f7 4423 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
<> 144:ef7eb2e8f9f7 4424 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4425 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4426 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4427
<> 144:ef7eb2e8f9f7 4428 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
<> 144:ef7eb2e8f9f7 4429 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
<> 144:ef7eb2e8f9f7 4430 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
<> 144:ef7eb2e8f9f7 4431 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4432 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4433 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4434
<> 144:ef7eb2e8f9f7 4435 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
<> 144:ef7eb2e8f9f7 4436 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
<> 144:ef7eb2e8f9f7 4437 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
<> 144:ef7eb2e8f9f7 4438 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4439 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4440 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4441
<> 144:ef7eb2e8f9f7 4442 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
<> 144:ef7eb2e8f9f7 4443 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
<> 144:ef7eb2e8f9f7 4444 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
<> 144:ef7eb2e8f9f7 4445 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4446 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4447 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4448
<> 144:ef7eb2e8f9f7 4449 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
<> 144:ef7eb2e8f9f7 4450 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
<> 144:ef7eb2e8f9f7 4451 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
<> 144:ef7eb2e8f9f7 4452 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4453 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4454 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4455
<> 144:ef7eb2e8f9f7 4456 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
<> 144:ef7eb2e8f9f7 4457 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
<> 144:ef7eb2e8f9f7 4458 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
<> 144:ef7eb2e8f9f7 4459 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4460 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4461 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4462
<> 144:ef7eb2e8f9f7 4463 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
<> 144:ef7eb2e8f9f7 4464 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
<> 144:ef7eb2e8f9f7 4465 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
<> 144:ef7eb2e8f9f7 4466 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4467 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4468 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4469
<> 144:ef7eb2e8f9f7 4470 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
<> 144:ef7eb2e8f9f7 4471 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
<> 144:ef7eb2e8f9f7 4472 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
<> 144:ef7eb2e8f9f7 4473 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4474 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4475 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4476
<> 144:ef7eb2e8f9f7 4477 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
<> 144:ef7eb2e8f9f7 4478 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
<> 144:ef7eb2e8f9f7 4479 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
<> 144:ef7eb2e8f9f7 4480 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4481 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4482 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4483
<> 144:ef7eb2e8f9f7 4484 /* Register: GPIOTE_INTENCLR */
<> 144:ef7eb2e8f9f7 4485 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 4486
<> 144:ef7eb2e8f9f7 4487 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
<> 144:ef7eb2e8f9f7 4488 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
<> 144:ef7eb2e8f9f7 4489 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
<> 144:ef7eb2e8f9f7 4490 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4491 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4492 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4493
<> 144:ef7eb2e8f9f7 4494 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
<> 144:ef7eb2e8f9f7 4495 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
<> 144:ef7eb2e8f9f7 4496 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
<> 144:ef7eb2e8f9f7 4497 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4498 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4499 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4500
<> 144:ef7eb2e8f9f7 4501 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
<> 144:ef7eb2e8f9f7 4502 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
<> 144:ef7eb2e8f9f7 4503 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
<> 144:ef7eb2e8f9f7 4504 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4505 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4506 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4507
<> 144:ef7eb2e8f9f7 4508 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
<> 144:ef7eb2e8f9f7 4509 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
<> 144:ef7eb2e8f9f7 4510 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
<> 144:ef7eb2e8f9f7 4511 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4512 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4513 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4514
<> 144:ef7eb2e8f9f7 4515 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
<> 144:ef7eb2e8f9f7 4516 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
<> 144:ef7eb2e8f9f7 4517 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
<> 144:ef7eb2e8f9f7 4518 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4519 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4520 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4521
<> 144:ef7eb2e8f9f7 4522 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
<> 144:ef7eb2e8f9f7 4523 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
<> 144:ef7eb2e8f9f7 4524 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
<> 144:ef7eb2e8f9f7 4525 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4526 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4527 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4528
<> 144:ef7eb2e8f9f7 4529 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
<> 144:ef7eb2e8f9f7 4530 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
<> 144:ef7eb2e8f9f7 4531 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
<> 144:ef7eb2e8f9f7 4532 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4533 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4534 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4535
<> 144:ef7eb2e8f9f7 4536 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
<> 144:ef7eb2e8f9f7 4537 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
<> 144:ef7eb2e8f9f7 4538 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
<> 144:ef7eb2e8f9f7 4539 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4540 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4541 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4542
<> 144:ef7eb2e8f9f7 4543 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
<> 144:ef7eb2e8f9f7 4544 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
<> 144:ef7eb2e8f9f7 4545 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
<> 144:ef7eb2e8f9f7 4546 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4547 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4548 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4549
<> 144:ef7eb2e8f9f7 4550 /* Register: GPIOTE_CONFIG */
<> 144:ef7eb2e8f9f7 4551 /* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
<> 144:ef7eb2e8f9f7 4552
<> 144:ef7eb2e8f9f7 4553 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
<> 144:ef7eb2e8f9f7 4554 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
<> 144:ef7eb2e8f9f7 4555 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
<> 144:ef7eb2e8f9f7 4556 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
<> 144:ef7eb2e8f9f7 4557 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
<> 144:ef7eb2e8f9f7 4558
<> 144:ef7eb2e8f9f7 4559 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
<> 144:ef7eb2e8f9f7 4560 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
<> 144:ef7eb2e8f9f7 4561 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
<> 144:ef7eb2e8f9f7 4562 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
<> 144:ef7eb2e8f9f7 4563 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
<> 144:ef7eb2e8f9f7 4564 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
<> 144:ef7eb2e8f9f7 4565 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
<> 144:ef7eb2e8f9f7 4566
<> 144:ef7eb2e8f9f7 4567 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
<> 144:ef7eb2e8f9f7 4568 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
<> 144:ef7eb2e8f9f7 4569 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
<> 144:ef7eb2e8f9f7 4570
<> 144:ef7eb2e8f9f7 4571 /* Bits 1..0 : Mode */
<> 144:ef7eb2e8f9f7 4572 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 4573 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 4574 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
<> 144:ef7eb2e8f9f7 4575 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
<> 144:ef7eb2e8f9f7 4576 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
<> 144:ef7eb2e8f9f7 4577
<> 144:ef7eb2e8f9f7 4578
<> 144:ef7eb2e8f9f7 4579 /* Peripheral: I2S */
<> 144:ef7eb2e8f9f7 4580 /* Description: Inter-IC Sound */
<> 144:ef7eb2e8f9f7 4581
<> 144:ef7eb2e8f9f7 4582 /* Register: I2S_INTEN */
<> 144:ef7eb2e8f9f7 4583 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 4584
<> 144:ef7eb2e8f9f7 4585 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
<> 144:ef7eb2e8f9f7 4586 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4587 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4588 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4589 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4590
<> 144:ef7eb2e8f9f7 4591 /* Bit 2 : Enable or disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 4592 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 4593 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 4594 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4595 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4596
<> 144:ef7eb2e8f9f7 4597 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
<> 144:ef7eb2e8f9f7 4598 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4599 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4600 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4601 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4602
<> 144:ef7eb2e8f9f7 4603 /* Register: I2S_INTENSET */
<> 144:ef7eb2e8f9f7 4604 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 4605
<> 144:ef7eb2e8f9f7 4606 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
<> 144:ef7eb2e8f9f7 4607 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4608 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4609 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4610 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4611 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4612
<> 144:ef7eb2e8f9f7 4613 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 4614 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 4615 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 4616 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4617 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4618 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4619
<> 144:ef7eb2e8f9f7 4620 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
<> 144:ef7eb2e8f9f7 4621 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4622 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4623 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4624 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4625 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4626
<> 144:ef7eb2e8f9f7 4627 /* Register: I2S_INTENCLR */
<> 144:ef7eb2e8f9f7 4628 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 4629
<> 144:ef7eb2e8f9f7 4630 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
<> 144:ef7eb2e8f9f7 4631 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4632 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4633 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4634 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4635 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4636
<> 144:ef7eb2e8f9f7 4637 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 4638 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 4639 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 4640 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4641 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4642 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4643
<> 144:ef7eb2e8f9f7 4644 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
<> 144:ef7eb2e8f9f7 4645 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4646 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
<> 144:ef7eb2e8f9f7 4647 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4648 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4649 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4650
<> 144:ef7eb2e8f9f7 4651 /* Register: I2S_ENABLE */
<> 144:ef7eb2e8f9f7 4652 /* Description: Enable I2S module. */
<> 144:ef7eb2e8f9f7 4653
<> 144:ef7eb2e8f9f7 4654 /* Bit 0 : Enable I2S module. */
<> 144:ef7eb2e8f9f7 4655 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 4656 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 4657 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4658 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4659
<> 144:ef7eb2e8f9f7 4660 /* Register: I2S_CONFIG_MODE */
<> 144:ef7eb2e8f9f7 4661 /* Description: I2S mode. */
<> 144:ef7eb2e8f9f7 4662
<> 144:ef7eb2e8f9f7 4663 /* Bit 0 : I2S mode. */
<> 144:ef7eb2e8f9f7 4664 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 4665 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 4666 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
<> 144:ef7eb2e8f9f7 4667 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
<> 144:ef7eb2e8f9f7 4668
<> 144:ef7eb2e8f9f7 4669 /* Register: I2S_CONFIG_RXEN */
<> 144:ef7eb2e8f9f7 4670 /* Description: Reception (RX) enable. */
<> 144:ef7eb2e8f9f7 4671
<> 144:ef7eb2e8f9f7 4672 /* Bit 0 : Reception (RX) enable. */
<> 144:ef7eb2e8f9f7 4673 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
<> 144:ef7eb2e8f9f7 4674 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
<> 144:ef7eb2e8f9f7 4675 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
<> 144:ef7eb2e8f9f7 4676 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
<> 144:ef7eb2e8f9f7 4677
<> 144:ef7eb2e8f9f7 4678 /* Register: I2S_CONFIG_TXEN */
<> 144:ef7eb2e8f9f7 4679 /* Description: Transmission (TX) enable. */
<> 144:ef7eb2e8f9f7 4680
<> 144:ef7eb2e8f9f7 4681 /* Bit 0 : Transmission (TX) enable. */
<> 144:ef7eb2e8f9f7 4682 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
<> 144:ef7eb2e8f9f7 4683 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
<> 144:ef7eb2e8f9f7 4684 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
<> 144:ef7eb2e8f9f7 4685 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
<> 144:ef7eb2e8f9f7 4686
<> 144:ef7eb2e8f9f7 4687 /* Register: I2S_CONFIG_MCKEN */
<> 144:ef7eb2e8f9f7 4688 /* Description: Master clock generator enable. */
<> 144:ef7eb2e8f9f7 4689
<> 144:ef7eb2e8f9f7 4690 /* Bit 0 : Master clock generator enable. */
<> 144:ef7eb2e8f9f7 4691 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
<> 144:ef7eb2e8f9f7 4692 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
<> 144:ef7eb2e8f9f7 4693 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
<> 144:ef7eb2e8f9f7 4694 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
<> 144:ef7eb2e8f9f7 4695
<> 144:ef7eb2e8f9f7 4696 /* Register: I2S_CONFIG_MCKFREQ */
<> 144:ef7eb2e8f9f7 4697 /* Description: Master clock generator frequency. */
<> 144:ef7eb2e8f9f7 4698
<> 144:ef7eb2e8f9f7 4699 /* Bits 31..0 : Master clock generator frequency. */
<> 144:ef7eb2e8f9f7 4700 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
<> 144:ef7eb2e8f9f7 4701 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
<> 144:ef7eb2e8f9f7 4702 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
<> 144:ef7eb2e8f9f7 4703 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
<> 144:ef7eb2e8f9f7 4704 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
<> 144:ef7eb2e8f9f7 4705 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
<> 144:ef7eb2e8f9f7 4706 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
<> 144:ef7eb2e8f9f7 4707 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
<> 144:ef7eb2e8f9f7 4708 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
<> 144:ef7eb2e8f9f7 4709 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
<> 144:ef7eb2e8f9f7 4710 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
<> 144:ef7eb2e8f9f7 4711 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
<> 144:ef7eb2e8f9f7 4712 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
<> 144:ef7eb2e8f9f7 4713 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
<> 144:ef7eb2e8f9f7 4714 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
<> 144:ef7eb2e8f9f7 4715 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
<> 144:ef7eb2e8f9f7 4716 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
<> 144:ef7eb2e8f9f7 4717 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
<> 144:ef7eb2e8f9f7 4718 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
<> 144:ef7eb2e8f9f7 4719 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
<> 144:ef7eb2e8f9f7 4720
<> 144:ef7eb2e8f9f7 4721 /* Register: I2S_CONFIG_RATIO */
<> 144:ef7eb2e8f9f7 4722 /* Description: MCK / LRCK ratio. */
<> 144:ef7eb2e8f9f7 4723
<> 144:ef7eb2e8f9f7 4724 /* Bits 3..0 : MCK / LRCK ratio. */
<> 144:ef7eb2e8f9f7 4725 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
<> 144:ef7eb2e8f9f7 4726 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
<> 144:ef7eb2e8f9f7 4727 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
<> 144:ef7eb2e8f9f7 4728 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
<> 144:ef7eb2e8f9f7 4729 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
<> 144:ef7eb2e8f9f7 4730 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
<> 144:ef7eb2e8f9f7 4731 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
<> 144:ef7eb2e8f9f7 4732 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
<> 144:ef7eb2e8f9f7 4733 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
<> 144:ef7eb2e8f9f7 4734 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
<> 144:ef7eb2e8f9f7 4735 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
<> 144:ef7eb2e8f9f7 4736
<> 144:ef7eb2e8f9f7 4737 /* Register: I2S_CONFIG_SWIDTH */
<> 144:ef7eb2e8f9f7 4738 /* Description: Sample width. */
<> 144:ef7eb2e8f9f7 4739
<> 144:ef7eb2e8f9f7 4740 /* Bits 1..0 : Sample width. */
<> 144:ef7eb2e8f9f7 4741 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
<> 144:ef7eb2e8f9f7 4742 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
<> 144:ef7eb2e8f9f7 4743 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
<> 144:ef7eb2e8f9f7 4744 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
<> 144:ef7eb2e8f9f7 4745 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
<> 144:ef7eb2e8f9f7 4746
<> 144:ef7eb2e8f9f7 4747 /* Register: I2S_CONFIG_ALIGN */
<> 144:ef7eb2e8f9f7 4748 /* Description: Alignment of sample within a frame. */
<> 144:ef7eb2e8f9f7 4749
<> 144:ef7eb2e8f9f7 4750 /* Bit 0 : Alignment of sample within a frame. */
<> 144:ef7eb2e8f9f7 4751 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
<> 144:ef7eb2e8f9f7 4752 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
<> 144:ef7eb2e8f9f7 4753 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
<> 144:ef7eb2e8f9f7 4754 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
<> 144:ef7eb2e8f9f7 4755
<> 144:ef7eb2e8f9f7 4756 /* Register: I2S_CONFIG_FORMAT */
<> 144:ef7eb2e8f9f7 4757 /* Description: Frame format. */
<> 144:ef7eb2e8f9f7 4758
<> 144:ef7eb2e8f9f7 4759 /* Bit 0 : Frame format. */
<> 144:ef7eb2e8f9f7 4760 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
<> 144:ef7eb2e8f9f7 4761 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
<> 144:ef7eb2e8f9f7 4762 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
<> 144:ef7eb2e8f9f7 4763 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
<> 144:ef7eb2e8f9f7 4764
<> 144:ef7eb2e8f9f7 4765 /* Register: I2S_CONFIG_CHANNELS */
<> 144:ef7eb2e8f9f7 4766 /* Description: Enable channels. */
<> 144:ef7eb2e8f9f7 4767
<> 144:ef7eb2e8f9f7 4768 /* Bits 1..0 : Enable channels. */
<> 144:ef7eb2e8f9f7 4769 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
<> 144:ef7eb2e8f9f7 4770 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
<> 144:ef7eb2e8f9f7 4771 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
<> 144:ef7eb2e8f9f7 4772 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
<> 144:ef7eb2e8f9f7 4773 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
<> 144:ef7eb2e8f9f7 4774
<> 144:ef7eb2e8f9f7 4775 /* Register: I2S_RXD_PTR */
<> 144:ef7eb2e8f9f7 4776 /* Description: Receive buffer RAM start address. */
<> 144:ef7eb2e8f9f7 4777
<> 144:ef7eb2e8f9f7 4778 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
<> 144:ef7eb2e8f9f7 4779 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 4780 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 4781
<> 144:ef7eb2e8f9f7 4782 /* Register: I2S_TXD_PTR */
<> 144:ef7eb2e8f9f7 4783 /* Description: Transmit buffer RAM start address. */
<> 144:ef7eb2e8f9f7 4784
<> 144:ef7eb2e8f9f7 4785 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
<> 144:ef7eb2e8f9f7 4786 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 4787 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 4788
<> 144:ef7eb2e8f9f7 4789 /* Register: I2S_RXTXD_MAXCNT */
<> 144:ef7eb2e8f9f7 4790 /* Description: Size of RXD and TXD buffers. */
<> 144:ef7eb2e8f9f7 4791
<> 144:ef7eb2e8f9f7 4792 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
<> 144:ef7eb2e8f9f7 4793 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 4794 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 4795
<> 144:ef7eb2e8f9f7 4796 /* Register: I2S_PSEL_MCK */
<> 144:ef7eb2e8f9f7 4797 /* Description: Pin select for MCK signal. */
<> 144:ef7eb2e8f9f7 4798
<> 144:ef7eb2e8f9f7 4799 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 4800 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 4801 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 4802 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 4803 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 4804
<> 144:ef7eb2e8f9f7 4805 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 4806 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 4807 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 4808
<> 144:ef7eb2e8f9f7 4809 /* Register: I2S_PSEL_SCK */
<> 144:ef7eb2e8f9f7 4810 /* Description: Pin select for SCK signal. */
<> 144:ef7eb2e8f9f7 4811
<> 144:ef7eb2e8f9f7 4812 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 4813 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 4814 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 4815 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 4816 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 4817
<> 144:ef7eb2e8f9f7 4818 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 4819 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 4820 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 4821
<> 144:ef7eb2e8f9f7 4822 /* Register: I2S_PSEL_LRCK */
<> 144:ef7eb2e8f9f7 4823 /* Description: Pin select for LRCK signal. */
<> 144:ef7eb2e8f9f7 4824
<> 144:ef7eb2e8f9f7 4825 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 4826 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 4827 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 4828 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 4829 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 4830
<> 144:ef7eb2e8f9f7 4831 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 4832 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 4833 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 4834
<> 144:ef7eb2e8f9f7 4835 /* Register: I2S_PSEL_SDIN */
<> 144:ef7eb2e8f9f7 4836 /* Description: Pin select for SDIN signal. */
<> 144:ef7eb2e8f9f7 4837
<> 144:ef7eb2e8f9f7 4838 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 4839 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 4840 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 4841 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 4842 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 4843
<> 144:ef7eb2e8f9f7 4844 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 4845 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 4846 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 4847
<> 144:ef7eb2e8f9f7 4848 /* Register: I2S_PSEL_SDOUT */
<> 144:ef7eb2e8f9f7 4849 /* Description: Pin select for SDOUT signal. */
<> 144:ef7eb2e8f9f7 4850
<> 144:ef7eb2e8f9f7 4851 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 4852 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 4853 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 4854 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 4855 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 4856
<> 144:ef7eb2e8f9f7 4857 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 4858 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 4859 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 4860
<> 144:ef7eb2e8f9f7 4861
<> 144:ef7eb2e8f9f7 4862 /* Peripheral: LPCOMP */
<> 144:ef7eb2e8f9f7 4863 /* Description: Low Power Comparator */
<> 144:ef7eb2e8f9f7 4864
<> 144:ef7eb2e8f9f7 4865 /* Register: LPCOMP_SHORTS */
<> 144:ef7eb2e8f9f7 4866 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 4867
<> 144:ef7eb2e8f9f7 4868 /* Bit 4 : Shortcut between CROSS event and STOP task */
<> 144:ef7eb2e8f9f7 4869 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
<> 144:ef7eb2e8f9f7 4870 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
<> 144:ef7eb2e8f9f7 4871 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 4872 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 4873
<> 144:ef7eb2e8f9f7 4874 /* Bit 3 : Shortcut between UP event and STOP task */
<> 144:ef7eb2e8f9f7 4875 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
<> 144:ef7eb2e8f9f7 4876 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
<> 144:ef7eb2e8f9f7 4877 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 4878 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 4879
<> 144:ef7eb2e8f9f7 4880 /* Bit 2 : Shortcut between DOWN event and STOP task */
<> 144:ef7eb2e8f9f7 4881 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
<> 144:ef7eb2e8f9f7 4882 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
<> 144:ef7eb2e8f9f7 4883 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 4884 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 4885
<> 144:ef7eb2e8f9f7 4886 /* Bit 1 : Shortcut between READY event and STOP task */
<> 144:ef7eb2e8f9f7 4887 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
<> 144:ef7eb2e8f9f7 4888 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
<> 144:ef7eb2e8f9f7 4889 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 4890 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 4891
<> 144:ef7eb2e8f9f7 4892 /* Bit 0 : Shortcut between READY event and SAMPLE task */
<> 144:ef7eb2e8f9f7 4893 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
<> 144:ef7eb2e8f9f7 4894 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
<> 144:ef7eb2e8f9f7 4895 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 4896 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 4897
<> 144:ef7eb2e8f9f7 4898 /* Register: LPCOMP_INTENSET */
<> 144:ef7eb2e8f9f7 4899 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 4900
<> 144:ef7eb2e8f9f7 4901 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
<> 144:ef7eb2e8f9f7 4902 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
<> 144:ef7eb2e8f9f7 4903 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
<> 144:ef7eb2e8f9f7 4904 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4905 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4906 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4907
<> 144:ef7eb2e8f9f7 4908 /* Bit 2 : Write '1' to Enable interrupt for UP event */
<> 144:ef7eb2e8f9f7 4909 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
<> 144:ef7eb2e8f9f7 4910 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
<> 144:ef7eb2e8f9f7 4911 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4912 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4913 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4914
<> 144:ef7eb2e8f9f7 4915 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
<> 144:ef7eb2e8f9f7 4916 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
<> 144:ef7eb2e8f9f7 4917 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
<> 144:ef7eb2e8f9f7 4918 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4919 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4920 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4921
<> 144:ef7eb2e8f9f7 4922 /* Bit 0 : Write '1' to Enable interrupt for READY event */
<> 144:ef7eb2e8f9f7 4923 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 4924 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 4925 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4926 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4927 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4928
<> 144:ef7eb2e8f9f7 4929 /* Register: LPCOMP_INTENCLR */
<> 144:ef7eb2e8f9f7 4930 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 4931
<> 144:ef7eb2e8f9f7 4932 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
<> 144:ef7eb2e8f9f7 4933 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
<> 144:ef7eb2e8f9f7 4934 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
<> 144:ef7eb2e8f9f7 4935 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4936 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4937 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4938
<> 144:ef7eb2e8f9f7 4939 /* Bit 2 : Write '1' to Disable interrupt for UP event */
<> 144:ef7eb2e8f9f7 4940 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
<> 144:ef7eb2e8f9f7 4941 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
<> 144:ef7eb2e8f9f7 4942 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4943 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4944 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4945
<> 144:ef7eb2e8f9f7 4946 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
<> 144:ef7eb2e8f9f7 4947 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
<> 144:ef7eb2e8f9f7 4948 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
<> 144:ef7eb2e8f9f7 4949 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4950 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4951 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4952
<> 144:ef7eb2e8f9f7 4953 /* Bit 0 : Write '1' to Disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 4954 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 4955 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 4956 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 4957 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 4958 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4959
<> 144:ef7eb2e8f9f7 4960 /* Register: LPCOMP_RESULT */
<> 144:ef7eb2e8f9f7 4961 /* Description: Compare result */
<> 144:ef7eb2e8f9f7 4962
<> 144:ef7eb2e8f9f7 4963 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
<> 144:ef7eb2e8f9f7 4964 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
<> 144:ef7eb2e8f9f7 4965 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
<> 144:ef7eb2e8f9f7 4966 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
<> 144:ef7eb2e8f9f7 4967 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
<> 144:ef7eb2e8f9f7 4968
<> 144:ef7eb2e8f9f7 4969 /* Register: LPCOMP_ENABLE */
<> 144:ef7eb2e8f9f7 4970 /* Description: Enable LPCOMP */
<> 144:ef7eb2e8f9f7 4971
<> 144:ef7eb2e8f9f7 4972 /* Bits 1..0 : Enable or disable LPCOMP */
<> 144:ef7eb2e8f9f7 4973 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 4974 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 4975 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 4976 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 4977
<> 144:ef7eb2e8f9f7 4978 /* Register: LPCOMP_PSEL */
<> 144:ef7eb2e8f9f7 4979 /* Description: Input pin select */
<> 144:ef7eb2e8f9f7 4980
<> 144:ef7eb2e8f9f7 4981 /* Bits 2..0 : Analog pin select */
<> 144:ef7eb2e8f9f7 4982 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
<> 144:ef7eb2e8f9f7 4983 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
<> 144:ef7eb2e8f9f7 4984 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
<> 144:ef7eb2e8f9f7 4985 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
<> 144:ef7eb2e8f9f7 4986 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
<> 144:ef7eb2e8f9f7 4987 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
<> 144:ef7eb2e8f9f7 4988 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
<> 144:ef7eb2e8f9f7 4989 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
<> 144:ef7eb2e8f9f7 4990 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
<> 144:ef7eb2e8f9f7 4991 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
<> 144:ef7eb2e8f9f7 4992
<> 144:ef7eb2e8f9f7 4993 /* Register: LPCOMP_REFSEL */
<> 144:ef7eb2e8f9f7 4994 /* Description: Reference select */
<> 144:ef7eb2e8f9f7 4995
<> 144:ef7eb2e8f9f7 4996 /* Bits 3..0 : Reference select */
<> 144:ef7eb2e8f9f7 4997 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
<> 144:ef7eb2e8f9f7 4998 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
<> 144:ef7eb2e8f9f7 4999 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
<> 144:ef7eb2e8f9f7 5000 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
<> 144:ef7eb2e8f9f7 5001 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
<> 144:ef7eb2e8f9f7 5002 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
<> 144:ef7eb2e8f9f7 5003 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
<> 144:ef7eb2e8f9f7 5004 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
<> 144:ef7eb2e8f9f7 5005 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
<> 144:ef7eb2e8f9f7 5006 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
<> 144:ef7eb2e8f9f7 5007 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
<> 144:ef7eb2e8f9f7 5008 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
<> 144:ef7eb2e8f9f7 5009 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
<> 144:ef7eb2e8f9f7 5010 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
<> 144:ef7eb2e8f9f7 5011 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
<> 144:ef7eb2e8f9f7 5012 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
<> 144:ef7eb2e8f9f7 5013 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
<> 144:ef7eb2e8f9f7 5014 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
<> 144:ef7eb2e8f9f7 5015
<> 144:ef7eb2e8f9f7 5016 /* Register: LPCOMP_EXTREFSEL */
<> 144:ef7eb2e8f9f7 5017 /* Description: External reference select */
<> 144:ef7eb2e8f9f7 5018
<> 144:ef7eb2e8f9f7 5019 /* Bit 0 : External analog reference select */
<> 144:ef7eb2e8f9f7 5020 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
<> 144:ef7eb2e8f9f7 5021 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
<> 144:ef7eb2e8f9f7 5022 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
<> 144:ef7eb2e8f9f7 5023 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
<> 144:ef7eb2e8f9f7 5024
<> 144:ef7eb2e8f9f7 5025 /* Register: LPCOMP_ANADETECT */
<> 144:ef7eb2e8f9f7 5026 /* Description: Analog detect configuration */
<> 144:ef7eb2e8f9f7 5027
<> 144:ef7eb2e8f9f7 5028 /* Bits 1..0 : Analog detect configuration */
<> 144:ef7eb2e8f9f7 5029 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
<> 144:ef7eb2e8f9f7 5030 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
<> 144:ef7eb2e8f9f7 5031 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
<> 144:ef7eb2e8f9f7 5032 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
<> 144:ef7eb2e8f9f7 5033 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
<> 144:ef7eb2e8f9f7 5034
<> 144:ef7eb2e8f9f7 5035 /* Register: LPCOMP_HYST */
<> 144:ef7eb2e8f9f7 5036 /* Description: Comparator hysteresis enable */
<> 144:ef7eb2e8f9f7 5037
<> 144:ef7eb2e8f9f7 5038 /* Bit 0 : Comparator hysteresis enable */
<> 144:ef7eb2e8f9f7 5039 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
<> 144:ef7eb2e8f9f7 5040 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
<> 144:ef7eb2e8f9f7 5041 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
<> 144:ef7eb2e8f9f7 5042 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
<> 144:ef7eb2e8f9f7 5043
<> 144:ef7eb2e8f9f7 5044
<> 144:ef7eb2e8f9f7 5045 /* Peripheral: MWU */
<> 144:ef7eb2e8f9f7 5046 /* Description: Memory Watch Unit */
<> 144:ef7eb2e8f9f7 5047
<> 144:ef7eb2e8f9f7 5048 /* Register: MWU_INTEN */
<> 144:ef7eb2e8f9f7 5049 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 5050
<> 144:ef7eb2e8f9f7 5051 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
<> 144:ef7eb2e8f9f7 5052 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5053 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5054 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5055 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5056
<> 144:ef7eb2e8f9f7 5057 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
<> 144:ef7eb2e8f9f7 5058 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5059 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5060 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5061 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5062
<> 144:ef7eb2e8f9f7 5063 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
<> 144:ef7eb2e8f9f7 5064 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5065 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5066 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5067 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5068
<> 144:ef7eb2e8f9f7 5069 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
<> 144:ef7eb2e8f9f7 5070 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5071 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5072 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5073 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5074
<> 144:ef7eb2e8f9f7 5075 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
<> 144:ef7eb2e8f9f7 5076 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5077 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5078 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5079 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5080
<> 144:ef7eb2e8f9f7 5081 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
<> 144:ef7eb2e8f9f7 5082 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5083 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5084 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5085 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5086
<> 144:ef7eb2e8f9f7 5087 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
<> 144:ef7eb2e8f9f7 5088 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5089 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5090 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5091 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5092
<> 144:ef7eb2e8f9f7 5093 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
<> 144:ef7eb2e8f9f7 5094 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5095 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5096 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5097 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5098
<> 144:ef7eb2e8f9f7 5099 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
<> 144:ef7eb2e8f9f7 5100 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5101 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5102 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5103 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5104
<> 144:ef7eb2e8f9f7 5105 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
<> 144:ef7eb2e8f9f7 5106 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5107 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5108 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5109 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5110
<> 144:ef7eb2e8f9f7 5111 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
<> 144:ef7eb2e8f9f7 5112 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5113 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5114 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5115 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5116
<> 144:ef7eb2e8f9f7 5117 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
<> 144:ef7eb2e8f9f7 5118 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5119 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5120 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5121 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5122
<> 144:ef7eb2e8f9f7 5123 /* Register: MWU_INTENSET */
<> 144:ef7eb2e8f9f7 5124 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 5125
<> 144:ef7eb2e8f9f7 5126 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
<> 144:ef7eb2e8f9f7 5127 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5128 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5129 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5130 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5131 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5132
<> 144:ef7eb2e8f9f7 5133 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
<> 144:ef7eb2e8f9f7 5134 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5135 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5136 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5137 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5138 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5139
<> 144:ef7eb2e8f9f7 5140 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
<> 144:ef7eb2e8f9f7 5141 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5142 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5143 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5144 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5145 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5146
<> 144:ef7eb2e8f9f7 5147 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
<> 144:ef7eb2e8f9f7 5148 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5149 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5150 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5151 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5152 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5153
<> 144:ef7eb2e8f9f7 5154 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
<> 144:ef7eb2e8f9f7 5155 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5156 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5157 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5158 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5159 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5160
<> 144:ef7eb2e8f9f7 5161 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
<> 144:ef7eb2e8f9f7 5162 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5163 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5164 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5165 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5166 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5167
<> 144:ef7eb2e8f9f7 5168 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
<> 144:ef7eb2e8f9f7 5169 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5170 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5171 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5172 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5173 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5174
<> 144:ef7eb2e8f9f7 5175 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
<> 144:ef7eb2e8f9f7 5176 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5177 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5178 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5179 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5180 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5181
<> 144:ef7eb2e8f9f7 5182 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
<> 144:ef7eb2e8f9f7 5183 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5184 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5185 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5186 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5187 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5188
<> 144:ef7eb2e8f9f7 5189 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
<> 144:ef7eb2e8f9f7 5190 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5191 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5192 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5193 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5194 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5195
<> 144:ef7eb2e8f9f7 5196 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
<> 144:ef7eb2e8f9f7 5197 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5198 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5199 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5200 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5201 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5202
<> 144:ef7eb2e8f9f7 5203 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
<> 144:ef7eb2e8f9f7 5204 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5205 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5206 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5207 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5208 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5209
<> 144:ef7eb2e8f9f7 5210 /* Register: MWU_INTENCLR */
<> 144:ef7eb2e8f9f7 5211 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 5212
<> 144:ef7eb2e8f9f7 5213 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
<> 144:ef7eb2e8f9f7 5214 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5215 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5216 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5217 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5218 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5219
<> 144:ef7eb2e8f9f7 5220 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
<> 144:ef7eb2e8f9f7 5221 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5222 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5223 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5224 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5225 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5226
<> 144:ef7eb2e8f9f7 5227 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
<> 144:ef7eb2e8f9f7 5228 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5229 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5230 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5231 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5232 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5233
<> 144:ef7eb2e8f9f7 5234 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
<> 144:ef7eb2e8f9f7 5235 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5236 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5237 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5238 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5239 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5240
<> 144:ef7eb2e8f9f7 5241 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
<> 144:ef7eb2e8f9f7 5242 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5243 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5244 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5245 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5246 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5247
<> 144:ef7eb2e8f9f7 5248 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
<> 144:ef7eb2e8f9f7 5249 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5250 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5251 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5252 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5253 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5254
<> 144:ef7eb2e8f9f7 5255 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
<> 144:ef7eb2e8f9f7 5256 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5257 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5258 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5259 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5260 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5261
<> 144:ef7eb2e8f9f7 5262 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
<> 144:ef7eb2e8f9f7 5263 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5264 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5265 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5266 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5267 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5268
<> 144:ef7eb2e8f9f7 5269 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
<> 144:ef7eb2e8f9f7 5270 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5271 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5272 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5273 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5274 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5275
<> 144:ef7eb2e8f9f7 5276 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
<> 144:ef7eb2e8f9f7 5277 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5278 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5279 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5280 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5281 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5282
<> 144:ef7eb2e8f9f7 5283 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
<> 144:ef7eb2e8f9f7 5284 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5285 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5286 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5287 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5288 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5289
<> 144:ef7eb2e8f9f7 5290 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
<> 144:ef7eb2e8f9f7 5291 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5292 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5293 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5294 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5295 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5296
<> 144:ef7eb2e8f9f7 5297 /* Register: MWU_NMIEN */
<> 144:ef7eb2e8f9f7 5298 /* Description: Enable or disable non-maskable interrupt */
<> 144:ef7eb2e8f9f7 5299
<> 144:ef7eb2e8f9f7 5300 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
<> 144:ef7eb2e8f9f7 5301 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5302 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5303 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5304 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5305
<> 144:ef7eb2e8f9f7 5306 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
<> 144:ef7eb2e8f9f7 5307 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5308 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5309 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5310 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5311
<> 144:ef7eb2e8f9f7 5312 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
<> 144:ef7eb2e8f9f7 5313 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5314 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5315 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5316 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5317
<> 144:ef7eb2e8f9f7 5318 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
<> 144:ef7eb2e8f9f7 5319 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5320 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5321 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5322 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5323
<> 144:ef7eb2e8f9f7 5324 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
<> 144:ef7eb2e8f9f7 5325 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5326 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5327 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5328 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5329
<> 144:ef7eb2e8f9f7 5330 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
<> 144:ef7eb2e8f9f7 5331 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5332 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5333 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5334 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5335
<> 144:ef7eb2e8f9f7 5336 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
<> 144:ef7eb2e8f9f7 5337 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5338 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5339 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5340 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5341
<> 144:ef7eb2e8f9f7 5342 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
<> 144:ef7eb2e8f9f7 5343 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5344 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5345 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5346 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5347
<> 144:ef7eb2e8f9f7 5348 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
<> 144:ef7eb2e8f9f7 5349 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5350 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5351 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5352 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5353
<> 144:ef7eb2e8f9f7 5354 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
<> 144:ef7eb2e8f9f7 5355 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5356 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5357 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5358 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5359
<> 144:ef7eb2e8f9f7 5360 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
<> 144:ef7eb2e8f9f7 5361 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5362 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5363 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5364 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5365
<> 144:ef7eb2e8f9f7 5366 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
<> 144:ef7eb2e8f9f7 5367 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5368 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5369 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5370 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5371
<> 144:ef7eb2e8f9f7 5372 /* Register: MWU_NMIENSET */
<> 144:ef7eb2e8f9f7 5373 /* Description: Enable non-maskable interrupt */
<> 144:ef7eb2e8f9f7 5374
<> 144:ef7eb2e8f9f7 5375 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
<> 144:ef7eb2e8f9f7 5376 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5377 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5378 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5379 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5380 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5381
<> 144:ef7eb2e8f9f7 5382 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
<> 144:ef7eb2e8f9f7 5383 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5384 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5385 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5386 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5387 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5388
<> 144:ef7eb2e8f9f7 5389 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
<> 144:ef7eb2e8f9f7 5390 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5391 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5392 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5393 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5394 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5395
<> 144:ef7eb2e8f9f7 5396 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
<> 144:ef7eb2e8f9f7 5397 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5398 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5399 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5400 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5401 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5402
<> 144:ef7eb2e8f9f7 5403 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
<> 144:ef7eb2e8f9f7 5404 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5405 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5406 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5407 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5408 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5409
<> 144:ef7eb2e8f9f7 5410 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
<> 144:ef7eb2e8f9f7 5411 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5412 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5413 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5414 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5415 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5416
<> 144:ef7eb2e8f9f7 5417 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
<> 144:ef7eb2e8f9f7 5418 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5419 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5420 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5421 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5422 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5423
<> 144:ef7eb2e8f9f7 5424 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
<> 144:ef7eb2e8f9f7 5425 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5426 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5427 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5428 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5429 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5430
<> 144:ef7eb2e8f9f7 5431 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
<> 144:ef7eb2e8f9f7 5432 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5433 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5434 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5435 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5436 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5437
<> 144:ef7eb2e8f9f7 5438 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
<> 144:ef7eb2e8f9f7 5439 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5440 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5441 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5442 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5443 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5444
<> 144:ef7eb2e8f9f7 5445 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
<> 144:ef7eb2e8f9f7 5446 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5447 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5448 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5449 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5450 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5451
<> 144:ef7eb2e8f9f7 5452 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
<> 144:ef7eb2e8f9f7 5453 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5454 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5455 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5456 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5457 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 5458
<> 144:ef7eb2e8f9f7 5459 /* Register: MWU_NMIENCLR */
<> 144:ef7eb2e8f9f7 5460 /* Description: Disable non-maskable interrupt */
<> 144:ef7eb2e8f9f7 5461
<> 144:ef7eb2e8f9f7 5462 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
<> 144:ef7eb2e8f9f7 5463 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5464 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
<> 144:ef7eb2e8f9f7 5465 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5466 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5467 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5468
<> 144:ef7eb2e8f9f7 5469 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
<> 144:ef7eb2e8f9f7 5470 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5471 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
<> 144:ef7eb2e8f9f7 5472 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5473 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5474 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5475
<> 144:ef7eb2e8f9f7 5476 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
<> 144:ef7eb2e8f9f7 5477 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5478 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
<> 144:ef7eb2e8f9f7 5479 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5480 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5481 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5482
<> 144:ef7eb2e8f9f7 5483 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
<> 144:ef7eb2e8f9f7 5484 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5485 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
<> 144:ef7eb2e8f9f7 5486 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5487 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5488 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5489
<> 144:ef7eb2e8f9f7 5490 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
<> 144:ef7eb2e8f9f7 5491 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5492 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
<> 144:ef7eb2e8f9f7 5493 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5494 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5495 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5496
<> 144:ef7eb2e8f9f7 5497 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
<> 144:ef7eb2e8f9f7 5498 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5499 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
<> 144:ef7eb2e8f9f7 5500 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5501 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5502 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5503
<> 144:ef7eb2e8f9f7 5504 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
<> 144:ef7eb2e8f9f7 5505 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5506 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
<> 144:ef7eb2e8f9f7 5507 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5508 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5509 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5510
<> 144:ef7eb2e8f9f7 5511 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
<> 144:ef7eb2e8f9f7 5512 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5513 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
<> 144:ef7eb2e8f9f7 5514 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5515 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5516 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5517
<> 144:ef7eb2e8f9f7 5518 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
<> 144:ef7eb2e8f9f7 5519 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5520 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
<> 144:ef7eb2e8f9f7 5521 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5522 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5523 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5524
<> 144:ef7eb2e8f9f7 5525 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
<> 144:ef7eb2e8f9f7 5526 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5527 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
<> 144:ef7eb2e8f9f7 5528 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5529 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5530 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5531
<> 144:ef7eb2e8f9f7 5532 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
<> 144:ef7eb2e8f9f7 5533 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5534 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
<> 144:ef7eb2e8f9f7 5535 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5536 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5537 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5538
<> 144:ef7eb2e8f9f7 5539 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
<> 144:ef7eb2e8f9f7 5540 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5541 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
<> 144:ef7eb2e8f9f7 5542 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 5543 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 5544 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 5545
<> 144:ef7eb2e8f9f7 5546 /* Register: MWU_PERREGION_SUBSTATWA */
<> 144:ef7eb2e8f9f7 5547 /* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
<> 144:ef7eb2e8f9f7 5548
<> 144:ef7eb2e8f9f7 5549 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5550 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
<> 144:ef7eb2e8f9f7 5551 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
<> 144:ef7eb2e8f9f7 5552 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5553 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5554
<> 144:ef7eb2e8f9f7 5555 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5556 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
<> 144:ef7eb2e8f9f7 5557 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
<> 144:ef7eb2e8f9f7 5558 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5559 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5560
<> 144:ef7eb2e8f9f7 5561 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5562 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
<> 144:ef7eb2e8f9f7 5563 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
<> 144:ef7eb2e8f9f7 5564 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5565 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5566
<> 144:ef7eb2e8f9f7 5567 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5568 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
<> 144:ef7eb2e8f9f7 5569 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
<> 144:ef7eb2e8f9f7 5570 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5571 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5572
<> 144:ef7eb2e8f9f7 5573 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5574 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
<> 144:ef7eb2e8f9f7 5575 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
<> 144:ef7eb2e8f9f7 5576 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5577 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5578
<> 144:ef7eb2e8f9f7 5579 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5580 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
<> 144:ef7eb2e8f9f7 5581 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
<> 144:ef7eb2e8f9f7 5582 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5583 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5584
<> 144:ef7eb2e8f9f7 5585 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5586 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
<> 144:ef7eb2e8f9f7 5587 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
<> 144:ef7eb2e8f9f7 5588 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5589 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5590
<> 144:ef7eb2e8f9f7 5591 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5592 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
<> 144:ef7eb2e8f9f7 5593 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
<> 144:ef7eb2e8f9f7 5594 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5595 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5596
<> 144:ef7eb2e8f9f7 5597 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5598 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
<> 144:ef7eb2e8f9f7 5599 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
<> 144:ef7eb2e8f9f7 5600 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5601 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5602
<> 144:ef7eb2e8f9f7 5603 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5604 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
<> 144:ef7eb2e8f9f7 5605 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
<> 144:ef7eb2e8f9f7 5606 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5607 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5608
<> 144:ef7eb2e8f9f7 5609 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5610 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
<> 144:ef7eb2e8f9f7 5611 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
<> 144:ef7eb2e8f9f7 5612 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5613 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5614
<> 144:ef7eb2e8f9f7 5615 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5616 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
<> 144:ef7eb2e8f9f7 5617 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
<> 144:ef7eb2e8f9f7 5618 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5619 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5620
<> 144:ef7eb2e8f9f7 5621 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5622 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
<> 144:ef7eb2e8f9f7 5623 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
<> 144:ef7eb2e8f9f7 5624 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5625 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5626
<> 144:ef7eb2e8f9f7 5627 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5628 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
<> 144:ef7eb2e8f9f7 5629 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
<> 144:ef7eb2e8f9f7 5630 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5631 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5632
<> 144:ef7eb2e8f9f7 5633 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5634 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
<> 144:ef7eb2e8f9f7 5635 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
<> 144:ef7eb2e8f9f7 5636 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5637 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5638
<> 144:ef7eb2e8f9f7 5639 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5640 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
<> 144:ef7eb2e8f9f7 5641 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
<> 144:ef7eb2e8f9f7 5642 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5643 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5644
<> 144:ef7eb2e8f9f7 5645 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5646 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
<> 144:ef7eb2e8f9f7 5647 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
<> 144:ef7eb2e8f9f7 5648 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5649 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5650
<> 144:ef7eb2e8f9f7 5651 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5652 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
<> 144:ef7eb2e8f9f7 5653 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
<> 144:ef7eb2e8f9f7 5654 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5655 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5656
<> 144:ef7eb2e8f9f7 5657 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5658 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
<> 144:ef7eb2e8f9f7 5659 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
<> 144:ef7eb2e8f9f7 5660 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5661 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5662
<> 144:ef7eb2e8f9f7 5663 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5664 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
<> 144:ef7eb2e8f9f7 5665 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
<> 144:ef7eb2e8f9f7 5666 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5667 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5668
<> 144:ef7eb2e8f9f7 5669 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5670 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
<> 144:ef7eb2e8f9f7 5671 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
<> 144:ef7eb2e8f9f7 5672 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5673 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5674
<> 144:ef7eb2e8f9f7 5675 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5676 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
<> 144:ef7eb2e8f9f7 5677 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
<> 144:ef7eb2e8f9f7 5678 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5679 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5680
<> 144:ef7eb2e8f9f7 5681 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5682 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
<> 144:ef7eb2e8f9f7 5683 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
<> 144:ef7eb2e8f9f7 5684 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5685 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5686
<> 144:ef7eb2e8f9f7 5687 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5688 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
<> 144:ef7eb2e8f9f7 5689 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
<> 144:ef7eb2e8f9f7 5690 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5691 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5692
<> 144:ef7eb2e8f9f7 5693 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5694 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
<> 144:ef7eb2e8f9f7 5695 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
<> 144:ef7eb2e8f9f7 5696 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5697 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5698
<> 144:ef7eb2e8f9f7 5699 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5700 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
<> 144:ef7eb2e8f9f7 5701 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
<> 144:ef7eb2e8f9f7 5702 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5703 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5704
<> 144:ef7eb2e8f9f7 5705 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5706 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
<> 144:ef7eb2e8f9f7 5707 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
<> 144:ef7eb2e8f9f7 5708 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5709 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5710
<> 144:ef7eb2e8f9f7 5711 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5712 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
<> 144:ef7eb2e8f9f7 5713 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
<> 144:ef7eb2e8f9f7 5714 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5715 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5716
<> 144:ef7eb2e8f9f7 5717 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5718 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
<> 144:ef7eb2e8f9f7 5719 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
<> 144:ef7eb2e8f9f7 5720 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5721 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5722
<> 144:ef7eb2e8f9f7 5723 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5724 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
<> 144:ef7eb2e8f9f7 5725 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
<> 144:ef7eb2e8f9f7 5726 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5727 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5728
<> 144:ef7eb2e8f9f7 5729 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5730 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
<> 144:ef7eb2e8f9f7 5731 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
<> 144:ef7eb2e8f9f7 5732 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5733 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5734
<> 144:ef7eb2e8f9f7 5735 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5736 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
<> 144:ef7eb2e8f9f7 5737 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
<> 144:ef7eb2e8f9f7 5738 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5739 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5740
<> 144:ef7eb2e8f9f7 5741 /* Register: MWU_PERREGION_SUBSTATRA */
<> 144:ef7eb2e8f9f7 5742 /* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
<> 144:ef7eb2e8f9f7 5743
<> 144:ef7eb2e8f9f7 5744 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5745 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
<> 144:ef7eb2e8f9f7 5746 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
<> 144:ef7eb2e8f9f7 5747 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5748 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5749
<> 144:ef7eb2e8f9f7 5750 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5751 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
<> 144:ef7eb2e8f9f7 5752 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
<> 144:ef7eb2e8f9f7 5753 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5754 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5755
<> 144:ef7eb2e8f9f7 5756 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5757 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
<> 144:ef7eb2e8f9f7 5758 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
<> 144:ef7eb2e8f9f7 5759 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5760 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5761
<> 144:ef7eb2e8f9f7 5762 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5763 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
<> 144:ef7eb2e8f9f7 5764 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
<> 144:ef7eb2e8f9f7 5765 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5766 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5767
<> 144:ef7eb2e8f9f7 5768 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5769 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
<> 144:ef7eb2e8f9f7 5770 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
<> 144:ef7eb2e8f9f7 5771 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5772 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5773
<> 144:ef7eb2e8f9f7 5774 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5775 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
<> 144:ef7eb2e8f9f7 5776 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
<> 144:ef7eb2e8f9f7 5777 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5778 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5779
<> 144:ef7eb2e8f9f7 5780 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5781 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
<> 144:ef7eb2e8f9f7 5782 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
<> 144:ef7eb2e8f9f7 5783 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5784 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5785
<> 144:ef7eb2e8f9f7 5786 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5787 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
<> 144:ef7eb2e8f9f7 5788 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
<> 144:ef7eb2e8f9f7 5789 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5790 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5791
<> 144:ef7eb2e8f9f7 5792 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5793 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
<> 144:ef7eb2e8f9f7 5794 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
<> 144:ef7eb2e8f9f7 5795 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5796 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5797
<> 144:ef7eb2e8f9f7 5798 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5799 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
<> 144:ef7eb2e8f9f7 5800 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
<> 144:ef7eb2e8f9f7 5801 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5802 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5803
<> 144:ef7eb2e8f9f7 5804 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5805 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
<> 144:ef7eb2e8f9f7 5806 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
<> 144:ef7eb2e8f9f7 5807 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5808 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5809
<> 144:ef7eb2e8f9f7 5810 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5811 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
<> 144:ef7eb2e8f9f7 5812 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
<> 144:ef7eb2e8f9f7 5813 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5814 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5815
<> 144:ef7eb2e8f9f7 5816 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5817 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
<> 144:ef7eb2e8f9f7 5818 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
<> 144:ef7eb2e8f9f7 5819 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5820 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5821
<> 144:ef7eb2e8f9f7 5822 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5823 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
<> 144:ef7eb2e8f9f7 5824 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
<> 144:ef7eb2e8f9f7 5825 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5826 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5827
<> 144:ef7eb2e8f9f7 5828 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5829 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
<> 144:ef7eb2e8f9f7 5830 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
<> 144:ef7eb2e8f9f7 5831 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5832 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5833
<> 144:ef7eb2e8f9f7 5834 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5835 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
<> 144:ef7eb2e8f9f7 5836 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
<> 144:ef7eb2e8f9f7 5837 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5838 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5839
<> 144:ef7eb2e8f9f7 5840 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5841 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
<> 144:ef7eb2e8f9f7 5842 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
<> 144:ef7eb2e8f9f7 5843 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5844 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5845
<> 144:ef7eb2e8f9f7 5846 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5847 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
<> 144:ef7eb2e8f9f7 5848 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
<> 144:ef7eb2e8f9f7 5849 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5850 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5851
<> 144:ef7eb2e8f9f7 5852 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5853 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
<> 144:ef7eb2e8f9f7 5854 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
<> 144:ef7eb2e8f9f7 5855 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5856 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5857
<> 144:ef7eb2e8f9f7 5858 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5859 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
<> 144:ef7eb2e8f9f7 5860 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
<> 144:ef7eb2e8f9f7 5861 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5862 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5863
<> 144:ef7eb2e8f9f7 5864 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5865 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
<> 144:ef7eb2e8f9f7 5866 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
<> 144:ef7eb2e8f9f7 5867 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5868 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5869
<> 144:ef7eb2e8f9f7 5870 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5871 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
<> 144:ef7eb2e8f9f7 5872 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
<> 144:ef7eb2e8f9f7 5873 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5874 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5875
<> 144:ef7eb2e8f9f7 5876 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5877 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
<> 144:ef7eb2e8f9f7 5878 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
<> 144:ef7eb2e8f9f7 5879 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5880 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5881
<> 144:ef7eb2e8f9f7 5882 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5883 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
<> 144:ef7eb2e8f9f7 5884 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
<> 144:ef7eb2e8f9f7 5885 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5886 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5887
<> 144:ef7eb2e8f9f7 5888 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5889 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
<> 144:ef7eb2e8f9f7 5890 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
<> 144:ef7eb2e8f9f7 5891 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5892 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5893
<> 144:ef7eb2e8f9f7 5894 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5895 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
<> 144:ef7eb2e8f9f7 5896 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
<> 144:ef7eb2e8f9f7 5897 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5898 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5899
<> 144:ef7eb2e8f9f7 5900 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5901 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
<> 144:ef7eb2e8f9f7 5902 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
<> 144:ef7eb2e8f9f7 5903 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5904 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5905
<> 144:ef7eb2e8f9f7 5906 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5907 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
<> 144:ef7eb2e8f9f7 5908 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
<> 144:ef7eb2e8f9f7 5909 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5910 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5911
<> 144:ef7eb2e8f9f7 5912 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5913 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
<> 144:ef7eb2e8f9f7 5914 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
<> 144:ef7eb2e8f9f7 5915 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5916 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5917
<> 144:ef7eb2e8f9f7 5918 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5919 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
<> 144:ef7eb2e8f9f7 5920 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
<> 144:ef7eb2e8f9f7 5921 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5922 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5923
<> 144:ef7eb2e8f9f7 5924 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5925 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
<> 144:ef7eb2e8f9f7 5926 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
<> 144:ef7eb2e8f9f7 5927 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5928 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5929
<> 144:ef7eb2e8f9f7 5930 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
<> 144:ef7eb2e8f9f7 5931 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
<> 144:ef7eb2e8f9f7 5932 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
<> 144:ef7eb2e8f9f7 5933 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
<> 144:ef7eb2e8f9f7 5934 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
<> 144:ef7eb2e8f9f7 5935
<> 144:ef7eb2e8f9f7 5936 /* Register: MWU_REGIONEN */
<> 144:ef7eb2e8f9f7 5937 /* Description: Enable/disable regions watch */
<> 144:ef7eb2e8f9f7 5938
<> 144:ef7eb2e8f9f7 5939 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
<> 144:ef7eb2e8f9f7 5940 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
<> 144:ef7eb2e8f9f7 5941 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
<> 144:ef7eb2e8f9f7 5942 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5943 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5944
<> 144:ef7eb2e8f9f7 5945 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
<> 144:ef7eb2e8f9f7 5946 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
<> 144:ef7eb2e8f9f7 5947 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
<> 144:ef7eb2e8f9f7 5948 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5949 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5950
<> 144:ef7eb2e8f9f7 5951 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
<> 144:ef7eb2e8f9f7 5952 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
<> 144:ef7eb2e8f9f7 5953 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
<> 144:ef7eb2e8f9f7 5954 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5955 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5956
<> 144:ef7eb2e8f9f7 5957 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
<> 144:ef7eb2e8f9f7 5958 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
<> 144:ef7eb2e8f9f7 5959 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
<> 144:ef7eb2e8f9f7 5960 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5961 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 5962
<> 144:ef7eb2e8f9f7 5963 /* Bit 7 : Enable/disable read access watch in region[3] */
<> 144:ef7eb2e8f9f7 5964 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
<> 144:ef7eb2e8f9f7 5965 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
<> 144:ef7eb2e8f9f7 5966 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 5967 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 5968
<> 144:ef7eb2e8f9f7 5969 /* Bit 6 : Enable/disable write access watch in region[3] */
<> 144:ef7eb2e8f9f7 5970 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
<> 144:ef7eb2e8f9f7 5971 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
<> 144:ef7eb2e8f9f7 5972 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 5973 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 5974
<> 144:ef7eb2e8f9f7 5975 /* Bit 5 : Enable/disable read access watch in region[2] */
<> 144:ef7eb2e8f9f7 5976 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
<> 144:ef7eb2e8f9f7 5977 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
<> 144:ef7eb2e8f9f7 5978 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 5979 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 5980
<> 144:ef7eb2e8f9f7 5981 /* Bit 4 : Enable/disable write access watch in region[2] */
<> 144:ef7eb2e8f9f7 5982 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
<> 144:ef7eb2e8f9f7 5983 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
<> 144:ef7eb2e8f9f7 5984 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 5985 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 5986
<> 144:ef7eb2e8f9f7 5987 /* Bit 3 : Enable/disable read access watch in region[1] */
<> 144:ef7eb2e8f9f7 5988 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
<> 144:ef7eb2e8f9f7 5989 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
<> 144:ef7eb2e8f9f7 5990 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 5991 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 5992
<> 144:ef7eb2e8f9f7 5993 /* Bit 2 : Enable/disable write access watch in region[1] */
<> 144:ef7eb2e8f9f7 5994 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
<> 144:ef7eb2e8f9f7 5995 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
<> 144:ef7eb2e8f9f7 5996 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 5997 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 5998
<> 144:ef7eb2e8f9f7 5999 /* Bit 1 : Enable/disable read access watch in region[0] */
<> 144:ef7eb2e8f9f7 6000 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
<> 144:ef7eb2e8f9f7 6001 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
<> 144:ef7eb2e8f9f7 6002 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 6003 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 6004
<> 144:ef7eb2e8f9f7 6005 /* Bit 0 : Enable/disable write access watch in region[0] */
<> 144:ef7eb2e8f9f7 6006 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
<> 144:ef7eb2e8f9f7 6007 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
<> 144:ef7eb2e8f9f7 6008 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 6009 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 6010
<> 144:ef7eb2e8f9f7 6011 /* Register: MWU_REGIONENSET */
<> 144:ef7eb2e8f9f7 6012 /* Description: Enable regions watch */
<> 144:ef7eb2e8f9f7 6013
<> 144:ef7eb2e8f9f7 6014 /* Bit 27 : Enable read access watch in PREGION[1] */
<> 144:ef7eb2e8f9f7 6015 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
<> 144:ef7eb2e8f9f7 6016 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
<> 144:ef7eb2e8f9f7 6017 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6018 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6019 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6020
<> 144:ef7eb2e8f9f7 6021 /* Bit 26 : Enable write access watch in PREGION[1] */
<> 144:ef7eb2e8f9f7 6022 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
<> 144:ef7eb2e8f9f7 6023 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
<> 144:ef7eb2e8f9f7 6024 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6025 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6026 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6027
<> 144:ef7eb2e8f9f7 6028 /* Bit 25 : Enable read access watch in PREGION[0] */
<> 144:ef7eb2e8f9f7 6029 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
<> 144:ef7eb2e8f9f7 6030 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
<> 144:ef7eb2e8f9f7 6031 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6032 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6033 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6034
<> 144:ef7eb2e8f9f7 6035 /* Bit 24 : Enable write access watch in PREGION[0] */
<> 144:ef7eb2e8f9f7 6036 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
<> 144:ef7eb2e8f9f7 6037 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
<> 144:ef7eb2e8f9f7 6038 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6039 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6040 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6041
<> 144:ef7eb2e8f9f7 6042 /* Bit 7 : Enable read access watch in region[3] */
<> 144:ef7eb2e8f9f7 6043 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
<> 144:ef7eb2e8f9f7 6044 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
<> 144:ef7eb2e8f9f7 6045 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6046 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6047 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 6048
<> 144:ef7eb2e8f9f7 6049 /* Bit 6 : Enable write access watch in region[3] */
<> 144:ef7eb2e8f9f7 6050 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
<> 144:ef7eb2e8f9f7 6051 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
<> 144:ef7eb2e8f9f7 6052 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6053 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6054 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 6055
<> 144:ef7eb2e8f9f7 6056 /* Bit 5 : Enable read access watch in region[2] */
<> 144:ef7eb2e8f9f7 6057 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
<> 144:ef7eb2e8f9f7 6058 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
<> 144:ef7eb2e8f9f7 6059 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6060 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6061 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 6062
<> 144:ef7eb2e8f9f7 6063 /* Bit 4 : Enable write access watch in region[2] */
<> 144:ef7eb2e8f9f7 6064 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
<> 144:ef7eb2e8f9f7 6065 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
<> 144:ef7eb2e8f9f7 6066 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6067 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6068 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 6069
<> 144:ef7eb2e8f9f7 6070 /* Bit 3 : Enable read access watch in region[1] */
<> 144:ef7eb2e8f9f7 6071 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
<> 144:ef7eb2e8f9f7 6072 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
<> 144:ef7eb2e8f9f7 6073 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6074 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6075 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 6076
<> 144:ef7eb2e8f9f7 6077 /* Bit 2 : Enable write access watch in region[1] */
<> 144:ef7eb2e8f9f7 6078 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
<> 144:ef7eb2e8f9f7 6079 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
<> 144:ef7eb2e8f9f7 6080 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6081 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6082 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 6083
<> 144:ef7eb2e8f9f7 6084 /* Bit 1 : Enable read access watch in region[0] */
<> 144:ef7eb2e8f9f7 6085 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
<> 144:ef7eb2e8f9f7 6086 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
<> 144:ef7eb2e8f9f7 6087 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6088 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6089 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
<> 144:ef7eb2e8f9f7 6090
<> 144:ef7eb2e8f9f7 6091 /* Bit 0 : Enable write access watch in region[0] */
<> 144:ef7eb2e8f9f7 6092 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
<> 144:ef7eb2e8f9f7 6093 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
<> 144:ef7eb2e8f9f7 6094 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6095 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6096 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
<> 144:ef7eb2e8f9f7 6097
<> 144:ef7eb2e8f9f7 6098 /* Register: MWU_REGIONENCLR */
<> 144:ef7eb2e8f9f7 6099 /* Description: Disable regions watch */
<> 144:ef7eb2e8f9f7 6100
<> 144:ef7eb2e8f9f7 6101 /* Bit 27 : Disable read access watch in PREGION[1] */
<> 144:ef7eb2e8f9f7 6102 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
<> 144:ef7eb2e8f9f7 6103 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
<> 144:ef7eb2e8f9f7 6104 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6105 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6106 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6107
<> 144:ef7eb2e8f9f7 6108 /* Bit 26 : Disable write access watch in PREGION[1] */
<> 144:ef7eb2e8f9f7 6109 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
<> 144:ef7eb2e8f9f7 6110 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
<> 144:ef7eb2e8f9f7 6111 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6112 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6113 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6114
<> 144:ef7eb2e8f9f7 6115 /* Bit 25 : Disable read access watch in PREGION[0] */
<> 144:ef7eb2e8f9f7 6116 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
<> 144:ef7eb2e8f9f7 6117 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
<> 144:ef7eb2e8f9f7 6118 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6119 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6120 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6121
<> 144:ef7eb2e8f9f7 6122 /* Bit 24 : Disable write access watch in PREGION[0] */
<> 144:ef7eb2e8f9f7 6123 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
<> 144:ef7eb2e8f9f7 6124 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
<> 144:ef7eb2e8f9f7 6125 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
<> 144:ef7eb2e8f9f7 6126 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
<> 144:ef7eb2e8f9f7 6127 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
<> 144:ef7eb2e8f9f7 6128
<> 144:ef7eb2e8f9f7 6129 /* Bit 7 : Disable read access watch in region[3] */
<> 144:ef7eb2e8f9f7 6130 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
<> 144:ef7eb2e8f9f7 6131 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
<> 144:ef7eb2e8f9f7 6132 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6133 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6134 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 6135
<> 144:ef7eb2e8f9f7 6136 /* Bit 6 : Disable write access watch in region[3] */
<> 144:ef7eb2e8f9f7 6137 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
<> 144:ef7eb2e8f9f7 6138 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
<> 144:ef7eb2e8f9f7 6139 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6140 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6141 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 6142
<> 144:ef7eb2e8f9f7 6143 /* Bit 5 : Disable read access watch in region[2] */
<> 144:ef7eb2e8f9f7 6144 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
<> 144:ef7eb2e8f9f7 6145 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
<> 144:ef7eb2e8f9f7 6146 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6147 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6148 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 6149
<> 144:ef7eb2e8f9f7 6150 /* Bit 4 : Disable write access watch in region[2] */
<> 144:ef7eb2e8f9f7 6151 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
<> 144:ef7eb2e8f9f7 6152 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
<> 144:ef7eb2e8f9f7 6153 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6154 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6155 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 6156
<> 144:ef7eb2e8f9f7 6157 /* Bit 3 : Disable read access watch in region[1] */
<> 144:ef7eb2e8f9f7 6158 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
<> 144:ef7eb2e8f9f7 6159 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
<> 144:ef7eb2e8f9f7 6160 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6161 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6162 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 6163
<> 144:ef7eb2e8f9f7 6164 /* Bit 2 : Disable write access watch in region[1] */
<> 144:ef7eb2e8f9f7 6165 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
<> 144:ef7eb2e8f9f7 6166 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
<> 144:ef7eb2e8f9f7 6167 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6168 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6169 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 6170
<> 144:ef7eb2e8f9f7 6171 /* Bit 1 : Disable read access watch in region[0] */
<> 144:ef7eb2e8f9f7 6172 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
<> 144:ef7eb2e8f9f7 6173 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
<> 144:ef7eb2e8f9f7 6174 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6175 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6176 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
<> 144:ef7eb2e8f9f7 6177
<> 144:ef7eb2e8f9f7 6178 /* Bit 0 : Disable write access watch in region[0] */
<> 144:ef7eb2e8f9f7 6179 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
<> 144:ef7eb2e8f9f7 6180 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
<> 144:ef7eb2e8f9f7 6181 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
<> 144:ef7eb2e8f9f7 6182 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
<> 144:ef7eb2e8f9f7 6183 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
<> 144:ef7eb2e8f9f7 6184
<> 144:ef7eb2e8f9f7 6185 /* Register: MWU_REGION_START */
<> 144:ef7eb2e8f9f7 6186 /* Description: Description cluster[0]: Start address for region 0 */
<> 144:ef7eb2e8f9f7 6187
<> 144:ef7eb2e8f9f7 6188 /* Bits 31..0 : Start address for region */
<> 144:ef7eb2e8f9f7 6189 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
<> 144:ef7eb2e8f9f7 6190 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
<> 144:ef7eb2e8f9f7 6191
<> 144:ef7eb2e8f9f7 6192 /* Register: MWU_REGION_END */
<> 144:ef7eb2e8f9f7 6193 /* Description: Description cluster[0]: End address of region 0 */
<> 144:ef7eb2e8f9f7 6194
<> 144:ef7eb2e8f9f7 6195 /* Bits 31..0 : End address of region. */
<> 144:ef7eb2e8f9f7 6196 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 6197 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 6198
<> 144:ef7eb2e8f9f7 6199 /* Register: MWU_PREGION_START */
<> 144:ef7eb2e8f9f7 6200 /* Description: Description cluster[0]: Reserved for future use */
<> 144:ef7eb2e8f9f7 6201
<> 144:ef7eb2e8f9f7 6202 /* Bits 31..0 : Reserved for future use */
<> 144:ef7eb2e8f9f7 6203 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
<> 144:ef7eb2e8f9f7 6204 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
<> 144:ef7eb2e8f9f7 6205
<> 144:ef7eb2e8f9f7 6206 /* Register: MWU_PREGION_END */
<> 144:ef7eb2e8f9f7 6207 /* Description: Description cluster[0]: Reserved for future use */
<> 144:ef7eb2e8f9f7 6208
<> 144:ef7eb2e8f9f7 6209 /* Bits 31..0 : Reserved for future use */
<> 144:ef7eb2e8f9f7 6210 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 6211 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 6212
<> 144:ef7eb2e8f9f7 6213 /* Register: MWU_PREGION_SUBS */
<> 144:ef7eb2e8f9f7 6214 /* Description: Description cluster[0]: Subregions of region 0 */
<> 144:ef7eb2e8f9f7 6215
<> 144:ef7eb2e8f9f7 6216 /* Bit 31 : Include or exclude subregion 31 in region */
<> 144:ef7eb2e8f9f7 6217 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
<> 144:ef7eb2e8f9f7 6218 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
<> 144:ef7eb2e8f9f7 6219 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6220 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6221
<> 144:ef7eb2e8f9f7 6222 /* Bit 30 : Include or exclude subregion 30 in region */
<> 144:ef7eb2e8f9f7 6223 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
<> 144:ef7eb2e8f9f7 6224 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
<> 144:ef7eb2e8f9f7 6225 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6226 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6227
<> 144:ef7eb2e8f9f7 6228 /* Bit 29 : Include or exclude subregion 29 in region */
<> 144:ef7eb2e8f9f7 6229 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
<> 144:ef7eb2e8f9f7 6230 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
<> 144:ef7eb2e8f9f7 6231 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6232 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6233
<> 144:ef7eb2e8f9f7 6234 /* Bit 28 : Include or exclude subregion 28 in region */
<> 144:ef7eb2e8f9f7 6235 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
<> 144:ef7eb2e8f9f7 6236 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
<> 144:ef7eb2e8f9f7 6237 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6238 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6239
<> 144:ef7eb2e8f9f7 6240 /* Bit 27 : Include or exclude subregion 27 in region */
<> 144:ef7eb2e8f9f7 6241 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
<> 144:ef7eb2e8f9f7 6242 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
<> 144:ef7eb2e8f9f7 6243 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6244 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6245
<> 144:ef7eb2e8f9f7 6246 /* Bit 26 : Include or exclude subregion 26 in region */
<> 144:ef7eb2e8f9f7 6247 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
<> 144:ef7eb2e8f9f7 6248 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
<> 144:ef7eb2e8f9f7 6249 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6250 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6251
<> 144:ef7eb2e8f9f7 6252 /* Bit 25 : Include or exclude subregion 25 in region */
<> 144:ef7eb2e8f9f7 6253 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
<> 144:ef7eb2e8f9f7 6254 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
<> 144:ef7eb2e8f9f7 6255 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6256 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6257
<> 144:ef7eb2e8f9f7 6258 /* Bit 24 : Include or exclude subregion 24 in region */
<> 144:ef7eb2e8f9f7 6259 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
<> 144:ef7eb2e8f9f7 6260 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
<> 144:ef7eb2e8f9f7 6261 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6262 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6263
<> 144:ef7eb2e8f9f7 6264 /* Bit 23 : Include or exclude subregion 23 in region */
<> 144:ef7eb2e8f9f7 6265 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
<> 144:ef7eb2e8f9f7 6266 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
<> 144:ef7eb2e8f9f7 6267 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6268 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6269
<> 144:ef7eb2e8f9f7 6270 /* Bit 22 : Include or exclude subregion 22 in region */
<> 144:ef7eb2e8f9f7 6271 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
<> 144:ef7eb2e8f9f7 6272 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
<> 144:ef7eb2e8f9f7 6273 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6274 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6275
<> 144:ef7eb2e8f9f7 6276 /* Bit 21 : Include or exclude subregion 21 in region */
<> 144:ef7eb2e8f9f7 6277 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
<> 144:ef7eb2e8f9f7 6278 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
<> 144:ef7eb2e8f9f7 6279 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6280 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6281
<> 144:ef7eb2e8f9f7 6282 /* Bit 20 : Include or exclude subregion 20 in region */
<> 144:ef7eb2e8f9f7 6283 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
<> 144:ef7eb2e8f9f7 6284 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
<> 144:ef7eb2e8f9f7 6285 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6286 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6287
<> 144:ef7eb2e8f9f7 6288 /* Bit 19 : Include or exclude subregion 19 in region */
<> 144:ef7eb2e8f9f7 6289 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
<> 144:ef7eb2e8f9f7 6290 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
<> 144:ef7eb2e8f9f7 6291 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6292 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6293
<> 144:ef7eb2e8f9f7 6294 /* Bit 18 : Include or exclude subregion 18 in region */
<> 144:ef7eb2e8f9f7 6295 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
<> 144:ef7eb2e8f9f7 6296 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
<> 144:ef7eb2e8f9f7 6297 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6298 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6299
<> 144:ef7eb2e8f9f7 6300 /* Bit 17 : Include or exclude subregion 17 in region */
<> 144:ef7eb2e8f9f7 6301 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
<> 144:ef7eb2e8f9f7 6302 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
<> 144:ef7eb2e8f9f7 6303 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6304 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6305
<> 144:ef7eb2e8f9f7 6306 /* Bit 16 : Include or exclude subregion 16 in region */
<> 144:ef7eb2e8f9f7 6307 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
<> 144:ef7eb2e8f9f7 6308 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
<> 144:ef7eb2e8f9f7 6309 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6310 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6311
<> 144:ef7eb2e8f9f7 6312 /* Bit 15 : Include or exclude subregion 15 in region */
<> 144:ef7eb2e8f9f7 6313 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
<> 144:ef7eb2e8f9f7 6314 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
<> 144:ef7eb2e8f9f7 6315 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6316 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6317
<> 144:ef7eb2e8f9f7 6318 /* Bit 14 : Include or exclude subregion 14 in region */
<> 144:ef7eb2e8f9f7 6319 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
<> 144:ef7eb2e8f9f7 6320 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
<> 144:ef7eb2e8f9f7 6321 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6322 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6323
<> 144:ef7eb2e8f9f7 6324 /* Bit 13 : Include or exclude subregion 13 in region */
<> 144:ef7eb2e8f9f7 6325 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
<> 144:ef7eb2e8f9f7 6326 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
<> 144:ef7eb2e8f9f7 6327 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6328 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6329
<> 144:ef7eb2e8f9f7 6330 /* Bit 12 : Include or exclude subregion 12 in region */
<> 144:ef7eb2e8f9f7 6331 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
<> 144:ef7eb2e8f9f7 6332 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
<> 144:ef7eb2e8f9f7 6333 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6334 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6335
<> 144:ef7eb2e8f9f7 6336 /* Bit 11 : Include or exclude subregion 11 in region */
<> 144:ef7eb2e8f9f7 6337 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
<> 144:ef7eb2e8f9f7 6338 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
<> 144:ef7eb2e8f9f7 6339 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6340 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6341
<> 144:ef7eb2e8f9f7 6342 /* Bit 10 : Include or exclude subregion 10 in region */
<> 144:ef7eb2e8f9f7 6343 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
<> 144:ef7eb2e8f9f7 6344 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
<> 144:ef7eb2e8f9f7 6345 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6346 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6347
<> 144:ef7eb2e8f9f7 6348 /* Bit 9 : Include or exclude subregion 9 in region */
<> 144:ef7eb2e8f9f7 6349 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
<> 144:ef7eb2e8f9f7 6350 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
<> 144:ef7eb2e8f9f7 6351 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6352 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6353
<> 144:ef7eb2e8f9f7 6354 /* Bit 8 : Include or exclude subregion 8 in region */
<> 144:ef7eb2e8f9f7 6355 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
<> 144:ef7eb2e8f9f7 6356 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
<> 144:ef7eb2e8f9f7 6357 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6358 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6359
<> 144:ef7eb2e8f9f7 6360 /* Bit 7 : Include or exclude subregion 7 in region */
<> 144:ef7eb2e8f9f7 6361 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
<> 144:ef7eb2e8f9f7 6362 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
<> 144:ef7eb2e8f9f7 6363 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6364 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6365
<> 144:ef7eb2e8f9f7 6366 /* Bit 6 : Include or exclude subregion 6 in region */
<> 144:ef7eb2e8f9f7 6367 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
<> 144:ef7eb2e8f9f7 6368 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
<> 144:ef7eb2e8f9f7 6369 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6370 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6371
<> 144:ef7eb2e8f9f7 6372 /* Bit 5 : Include or exclude subregion 5 in region */
<> 144:ef7eb2e8f9f7 6373 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
<> 144:ef7eb2e8f9f7 6374 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
<> 144:ef7eb2e8f9f7 6375 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6376 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6377
<> 144:ef7eb2e8f9f7 6378 /* Bit 4 : Include or exclude subregion 4 in region */
<> 144:ef7eb2e8f9f7 6379 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
<> 144:ef7eb2e8f9f7 6380 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
<> 144:ef7eb2e8f9f7 6381 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6382 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6383
<> 144:ef7eb2e8f9f7 6384 /* Bit 3 : Include or exclude subregion 3 in region */
<> 144:ef7eb2e8f9f7 6385 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
<> 144:ef7eb2e8f9f7 6386 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
<> 144:ef7eb2e8f9f7 6387 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6388 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6389
<> 144:ef7eb2e8f9f7 6390 /* Bit 2 : Include or exclude subregion 2 in region */
<> 144:ef7eb2e8f9f7 6391 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
<> 144:ef7eb2e8f9f7 6392 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
<> 144:ef7eb2e8f9f7 6393 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6394 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6395
<> 144:ef7eb2e8f9f7 6396 /* Bit 1 : Include or exclude subregion 1 in region */
<> 144:ef7eb2e8f9f7 6397 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
<> 144:ef7eb2e8f9f7 6398 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
<> 144:ef7eb2e8f9f7 6399 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6400 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6401
<> 144:ef7eb2e8f9f7 6402 /* Bit 0 : Include or exclude subregion 0 in region */
<> 144:ef7eb2e8f9f7 6403 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
<> 144:ef7eb2e8f9f7 6404 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
<> 144:ef7eb2e8f9f7 6405 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 6406 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 6407
<> 144:ef7eb2e8f9f7 6408
<> 144:ef7eb2e8f9f7 6409 /* Peripheral: NFCT */
<> 144:ef7eb2e8f9f7 6410 /* Description: NFC-A compatible radio */
<> 144:ef7eb2e8f9f7 6411
<> 144:ef7eb2e8f9f7 6412 /* Register: NFCT_SHORTS */
<> 144:ef7eb2e8f9f7 6413 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 6414
<> 144:ef7eb2e8f9f7 6415 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
<> 144:ef7eb2e8f9f7 6416 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
<> 144:ef7eb2e8f9f7 6417 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
<> 144:ef7eb2e8f9f7 6418 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 6419 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 6420
<> 144:ef7eb2e8f9f7 6421 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
<> 144:ef7eb2e8f9f7 6422 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
<> 144:ef7eb2e8f9f7 6423 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
<> 144:ef7eb2e8f9f7 6424 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 6425 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 6426
<> 144:ef7eb2e8f9f7 6427 /* Register: NFCT_INTEN */
<> 144:ef7eb2e8f9f7 6428 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 6429
<> 144:ef7eb2e8f9f7 6430 /* Bit 20 : Enable or disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 6431 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 6432 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 6433 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6434 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6435
<> 144:ef7eb2e8f9f7 6436 /* Bit 19 : Enable or disable interrupt for SELECTED event */
<> 144:ef7eb2e8f9f7 6437 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
<> 144:ef7eb2e8f9f7 6438 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
<> 144:ef7eb2e8f9f7 6439 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6440 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6441
<> 144:ef7eb2e8f9f7 6442 /* Bit 18 : Enable or disable interrupt for COLLISION event */
<> 144:ef7eb2e8f9f7 6443 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
<> 144:ef7eb2e8f9f7 6444 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
<> 144:ef7eb2e8f9f7 6445 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6446 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6447
<> 144:ef7eb2e8f9f7 6448 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
<> 144:ef7eb2e8f9f7 6449 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
<> 144:ef7eb2e8f9f7 6450 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
<> 144:ef7eb2e8f9f7 6451 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6452 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6453
<> 144:ef7eb2e8f9f7 6454 /* Bit 12 : Enable or disable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 6455 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 6456 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 6457 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6458 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6459
<> 144:ef7eb2e8f9f7 6460 /* Bit 11 : Enable or disable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 6461 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 6462 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 6463 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6464 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6465
<> 144:ef7eb2e8f9f7 6466 /* Bit 10 : Enable or disable interrupt for RXERROR event */
<> 144:ef7eb2e8f9f7 6467 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
<> 144:ef7eb2e8f9f7 6468 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
<> 144:ef7eb2e8f9f7 6469 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6470 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6471
<> 144:ef7eb2e8f9f7 6472 /* Bit 7 : Enable or disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 6473 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 6474 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 6475 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6476 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6477
<> 144:ef7eb2e8f9f7 6478 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
<> 144:ef7eb2e8f9f7 6479 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6480 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6481 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6482 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6483
<> 144:ef7eb2e8f9f7 6484 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
<> 144:ef7eb2e8f9f7 6485 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6486 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6487 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6488 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6489
<> 144:ef7eb2e8f9f7 6490 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
<> 144:ef7eb2e8f9f7 6491 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6492 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6493 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6494 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6495
<> 144:ef7eb2e8f9f7 6496 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
<> 144:ef7eb2e8f9f7 6497 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6498 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6499 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6500 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6501
<> 144:ef7eb2e8f9f7 6502 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
<> 144:ef7eb2e8f9f7 6503 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
<> 144:ef7eb2e8f9f7 6504 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
<> 144:ef7eb2e8f9f7 6505 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6506 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6507
<> 144:ef7eb2e8f9f7 6508 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
<> 144:ef7eb2e8f9f7 6509 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
<> 144:ef7eb2e8f9f7 6510 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
<> 144:ef7eb2e8f9f7 6511 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6512 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6513
<> 144:ef7eb2e8f9f7 6514 /* Bit 0 : Enable or disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 6515 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 6516 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 6517 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6518 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6519
<> 144:ef7eb2e8f9f7 6520 /* Register: NFCT_INTENSET */
<> 144:ef7eb2e8f9f7 6521 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 6522
<> 144:ef7eb2e8f9f7 6523 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 6524 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 6525 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 6526 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6527 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6528 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6529
<> 144:ef7eb2e8f9f7 6530 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
<> 144:ef7eb2e8f9f7 6531 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
<> 144:ef7eb2e8f9f7 6532 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
<> 144:ef7eb2e8f9f7 6533 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6534 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6535 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6536
<> 144:ef7eb2e8f9f7 6537 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
<> 144:ef7eb2e8f9f7 6538 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
<> 144:ef7eb2e8f9f7 6539 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
<> 144:ef7eb2e8f9f7 6540 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6541 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6542 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6543
<> 144:ef7eb2e8f9f7 6544 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
<> 144:ef7eb2e8f9f7 6545 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
<> 144:ef7eb2e8f9f7 6546 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
<> 144:ef7eb2e8f9f7 6547 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6548 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6549 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6550
<> 144:ef7eb2e8f9f7 6551 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 6552 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 6553 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 6554 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6555 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6556 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6557
<> 144:ef7eb2e8f9f7 6558 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 6559 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 6560 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 6561 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6562 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6563 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6564
<> 144:ef7eb2e8f9f7 6565 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
<> 144:ef7eb2e8f9f7 6566 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
<> 144:ef7eb2e8f9f7 6567 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
<> 144:ef7eb2e8f9f7 6568 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6569 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6570 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6571
<> 144:ef7eb2e8f9f7 6572 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 6573 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 6574 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 6575 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6576 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6577 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6578
<> 144:ef7eb2e8f9f7 6579 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
<> 144:ef7eb2e8f9f7 6580 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6581 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6582 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6583 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6584 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6585
<> 144:ef7eb2e8f9f7 6586 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
<> 144:ef7eb2e8f9f7 6587 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6588 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6589 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6590 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6591 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6592
<> 144:ef7eb2e8f9f7 6593 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
<> 144:ef7eb2e8f9f7 6594 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6595 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6596 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6597 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6598 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6599
<> 144:ef7eb2e8f9f7 6600 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
<> 144:ef7eb2e8f9f7 6601 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6602 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6603 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6604 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6605 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6606
<> 144:ef7eb2e8f9f7 6607 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
<> 144:ef7eb2e8f9f7 6608 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
<> 144:ef7eb2e8f9f7 6609 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
<> 144:ef7eb2e8f9f7 6610 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6611 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6612 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6613
<> 144:ef7eb2e8f9f7 6614 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
<> 144:ef7eb2e8f9f7 6615 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
<> 144:ef7eb2e8f9f7 6616 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
<> 144:ef7eb2e8f9f7 6617 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6618 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6619 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6620
<> 144:ef7eb2e8f9f7 6621 /* Bit 0 : Write '1' to Enable interrupt for READY event */
<> 144:ef7eb2e8f9f7 6622 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 6623 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 6624 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6625 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6626 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 6627
<> 144:ef7eb2e8f9f7 6628 /* Register: NFCT_INTENCLR */
<> 144:ef7eb2e8f9f7 6629 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 6630
<> 144:ef7eb2e8f9f7 6631 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 6632 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 6633 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 6634 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6635 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6636 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6637
<> 144:ef7eb2e8f9f7 6638 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
<> 144:ef7eb2e8f9f7 6639 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
<> 144:ef7eb2e8f9f7 6640 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
<> 144:ef7eb2e8f9f7 6641 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6642 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6643 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6644
<> 144:ef7eb2e8f9f7 6645 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
<> 144:ef7eb2e8f9f7 6646 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
<> 144:ef7eb2e8f9f7 6647 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
<> 144:ef7eb2e8f9f7 6648 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6649 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6650 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6651
<> 144:ef7eb2e8f9f7 6652 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
<> 144:ef7eb2e8f9f7 6653 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
<> 144:ef7eb2e8f9f7 6654 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
<> 144:ef7eb2e8f9f7 6655 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6656 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6657 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6658
<> 144:ef7eb2e8f9f7 6659 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 6660 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 6661 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 6662 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6663 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6664 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6665
<> 144:ef7eb2e8f9f7 6666 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 6667 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 6668 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 6669 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6670 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6671 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6672
<> 144:ef7eb2e8f9f7 6673 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
<> 144:ef7eb2e8f9f7 6674 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
<> 144:ef7eb2e8f9f7 6675 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
<> 144:ef7eb2e8f9f7 6676 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6677 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6678 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6679
<> 144:ef7eb2e8f9f7 6680 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 6681 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 6682 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 6683 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6684 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6685 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6686
<> 144:ef7eb2e8f9f7 6687 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
<> 144:ef7eb2e8f9f7 6688 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6689 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6690 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6691 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6692 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6693
<> 144:ef7eb2e8f9f7 6694 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
<> 144:ef7eb2e8f9f7 6695 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6696 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6697 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6698 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6699 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6700
<> 144:ef7eb2e8f9f7 6701 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
<> 144:ef7eb2e8f9f7 6702 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6703 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
<> 144:ef7eb2e8f9f7 6704 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6705 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6706 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6707
<> 144:ef7eb2e8f9f7 6708 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
<> 144:ef7eb2e8f9f7 6709 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6710 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
<> 144:ef7eb2e8f9f7 6711 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6712 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6713 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6714
<> 144:ef7eb2e8f9f7 6715 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
<> 144:ef7eb2e8f9f7 6716 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
<> 144:ef7eb2e8f9f7 6717 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
<> 144:ef7eb2e8f9f7 6718 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6719 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6720 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6721
<> 144:ef7eb2e8f9f7 6722 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
<> 144:ef7eb2e8f9f7 6723 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
<> 144:ef7eb2e8f9f7 6724 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
<> 144:ef7eb2e8f9f7 6725 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6726 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6727 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6728
<> 144:ef7eb2e8f9f7 6729 /* Bit 0 : Write '1' to Disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 6730 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 6731 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 6732 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 6733 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 6734 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 6735
<> 144:ef7eb2e8f9f7 6736 /* Register: NFCT_ERRORSTATUS */
<> 144:ef7eb2e8f9f7 6737 /* Description: NFC Error Status register */
<> 144:ef7eb2e8f9f7 6738
<> 144:ef7eb2e8f9f7 6739 /* Bit 3 : Field level is too low at min load resistance */
<> 144:ef7eb2e8f9f7 6740 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
<> 144:ef7eb2e8f9f7 6741 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
<> 144:ef7eb2e8f9f7 6742
<> 144:ef7eb2e8f9f7 6743 /* Bit 2 : Field level is too high at max load resistance */
<> 144:ef7eb2e8f9f7 6744 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
<> 144:ef7eb2e8f9f7 6745 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
<> 144:ef7eb2e8f9f7 6746
<> 144:ef7eb2e8f9f7 6747 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
<> 144:ef7eb2e8f9f7 6748 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
<> 144:ef7eb2e8f9f7 6749 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
<> 144:ef7eb2e8f9f7 6750
<> 144:ef7eb2e8f9f7 6751 /* Register: NFCT_FRAMESTATUS_RX */
<> 144:ef7eb2e8f9f7 6752 /* Description: Result of last incoming frames */
<> 144:ef7eb2e8f9f7 6753
<> 144:ef7eb2e8f9f7 6754 /* Bit 3 : Overrun detected */
<> 144:ef7eb2e8f9f7 6755 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
<> 144:ef7eb2e8f9f7 6756 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
<> 144:ef7eb2e8f9f7 6757 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
<> 144:ef7eb2e8f9f7 6758 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
<> 144:ef7eb2e8f9f7 6759
<> 144:ef7eb2e8f9f7 6760 /* Bit 2 : Parity status of received frame */
<> 144:ef7eb2e8f9f7 6761 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
<> 144:ef7eb2e8f9f7 6762 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
<> 144:ef7eb2e8f9f7 6763 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
<> 144:ef7eb2e8f9f7 6764 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
<> 144:ef7eb2e8f9f7 6765
<> 144:ef7eb2e8f9f7 6766 /* Bit 0 : No valid End of Frame detected */
<> 144:ef7eb2e8f9f7 6767 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
<> 144:ef7eb2e8f9f7 6768 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
<> 144:ef7eb2e8f9f7 6769 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
<> 144:ef7eb2e8f9f7 6770 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
<> 144:ef7eb2e8f9f7 6771
<> 144:ef7eb2e8f9f7 6772 /* Register: NFCT_CURRENTLOADCTRL */
<> 144:ef7eb2e8f9f7 6773 /* Description: Current value driven to the NFC Load Control */
<> 144:ef7eb2e8f9f7 6774
<> 144:ef7eb2e8f9f7 6775 /* Bits 5..0 : Current value driven to the NFC Load Control */
<> 144:ef7eb2e8f9f7 6776 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
<> 144:ef7eb2e8f9f7 6777 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
<> 144:ef7eb2e8f9f7 6778
<> 144:ef7eb2e8f9f7 6779 /* Register: NFCT_FIELDPRESENT */
<> 144:ef7eb2e8f9f7 6780 /* Description: Indicates the presence or not of a valid field */
<> 144:ef7eb2e8f9f7 6781
<> 144:ef7eb2e8f9f7 6782 /* Bit 1 : Indicates if the low level has locked to the field */
<> 144:ef7eb2e8f9f7 6783 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
<> 144:ef7eb2e8f9f7 6784 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
<> 144:ef7eb2e8f9f7 6785 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
<> 144:ef7eb2e8f9f7 6786 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
<> 144:ef7eb2e8f9f7 6787
<> 144:ef7eb2e8f9f7 6788 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
<> 144:ef7eb2e8f9f7 6789 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
<> 144:ef7eb2e8f9f7 6790 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
<> 144:ef7eb2e8f9f7 6791 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
<> 144:ef7eb2e8f9f7 6792 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
<> 144:ef7eb2e8f9f7 6793
<> 144:ef7eb2e8f9f7 6794 /* Register: NFCT_FRAMEDELAYMIN */
<> 144:ef7eb2e8f9f7 6795 /* Description: Minimum frame delay */
<> 144:ef7eb2e8f9f7 6796
<> 144:ef7eb2e8f9f7 6797 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
<> 144:ef7eb2e8f9f7 6798 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
<> 144:ef7eb2e8f9f7 6799 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
<> 144:ef7eb2e8f9f7 6800
<> 144:ef7eb2e8f9f7 6801 /* Register: NFCT_FRAMEDELAYMAX */
<> 144:ef7eb2e8f9f7 6802 /* Description: Maximum frame delay */
<> 144:ef7eb2e8f9f7 6803
<> 144:ef7eb2e8f9f7 6804 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
<> 144:ef7eb2e8f9f7 6805 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
<> 144:ef7eb2e8f9f7 6806 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
<> 144:ef7eb2e8f9f7 6807
<> 144:ef7eb2e8f9f7 6808 /* Register: NFCT_FRAMEDELAYMODE */
<> 144:ef7eb2e8f9f7 6809 /* Description: Configuration register for the Frame Delay Timer */
<> 144:ef7eb2e8f9f7 6810
<> 144:ef7eb2e8f9f7 6811 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
<> 144:ef7eb2e8f9f7 6812 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
<> 144:ef7eb2e8f9f7 6813 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
<> 144:ef7eb2e8f9f7 6814 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
<> 144:ef7eb2e8f9f7 6815 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
<> 144:ef7eb2e8f9f7 6816 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
<> 144:ef7eb2e8f9f7 6817 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
<> 144:ef7eb2e8f9f7 6818
<> 144:ef7eb2e8f9f7 6819 /* Register: NFCT_PACKETPTR */
<> 144:ef7eb2e8f9f7 6820 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
<> 144:ef7eb2e8f9f7 6821
<> 144:ef7eb2e8f9f7 6822 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
<> 144:ef7eb2e8f9f7 6823 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 6824 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 6825
<> 144:ef7eb2e8f9f7 6826 /* Register: NFCT_MAXLEN */
<> 144:ef7eb2e8f9f7 6827 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
<> 144:ef7eb2e8f9f7 6828
<> 144:ef7eb2e8f9f7 6829 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
<> 144:ef7eb2e8f9f7 6830 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
<> 144:ef7eb2e8f9f7 6831 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
<> 144:ef7eb2e8f9f7 6832
<> 144:ef7eb2e8f9f7 6833 /* Register: NFCT_TXD_FRAMECONFIG */
<> 144:ef7eb2e8f9f7 6834 /* Description: Configuration of outgoing frames */
<> 144:ef7eb2e8f9f7 6835
<> 144:ef7eb2e8f9f7 6836 /* Bit 4 : CRC mode for outgoing frames */
<> 144:ef7eb2e8f9f7 6837 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
<> 144:ef7eb2e8f9f7 6838 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
<> 144:ef7eb2e8f9f7 6839 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
<> 144:ef7eb2e8f9f7 6840 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
<> 144:ef7eb2e8f9f7 6841
<> 144:ef7eb2e8f9f7 6842 /* Bit 2 : Adding SoF or not in TX frames */
<> 144:ef7eb2e8f9f7 6843 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
<> 144:ef7eb2e8f9f7 6844 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
<> 144:ef7eb2e8f9f7 6845 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
<> 144:ef7eb2e8f9f7 6846 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
<> 144:ef7eb2e8f9f7 6847
<> 144:ef7eb2e8f9f7 6848 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
<> 144:ef7eb2e8f9f7 6849 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
<> 144:ef7eb2e8f9f7 6850 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
<> 144:ef7eb2e8f9f7 6851 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
<> 144:ef7eb2e8f9f7 6852 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
<> 144:ef7eb2e8f9f7 6853
<> 144:ef7eb2e8f9f7 6854 /* Bit 0 : Adding parity or not in the frame */
<> 144:ef7eb2e8f9f7 6855 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
<> 144:ef7eb2e8f9f7 6856 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
<> 144:ef7eb2e8f9f7 6857 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
<> 144:ef7eb2e8f9f7 6858 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
<> 144:ef7eb2e8f9f7 6859
<> 144:ef7eb2e8f9f7 6860 /* Register: NFCT_TXD_AMOUNT */
<> 144:ef7eb2e8f9f7 6861 /* Description: Size of outgoing frame */
<> 144:ef7eb2e8f9f7 6862
<> 144:ef7eb2e8f9f7 6863 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
<> 144:ef7eb2e8f9f7 6864 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
<> 144:ef7eb2e8f9f7 6865 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
<> 144:ef7eb2e8f9f7 6866
<> 144:ef7eb2e8f9f7 6867 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
<> 144:ef7eb2e8f9f7 6868 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
<> 144:ef7eb2e8f9f7 6869 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
<> 144:ef7eb2e8f9f7 6870
<> 144:ef7eb2e8f9f7 6871 /* Register: NFCT_RXD_FRAMECONFIG */
<> 144:ef7eb2e8f9f7 6872 /* Description: Configuration of incoming frames */
<> 144:ef7eb2e8f9f7 6873
<> 144:ef7eb2e8f9f7 6874 /* Bit 4 : CRC mode for incoming frames */
<> 144:ef7eb2e8f9f7 6875 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
<> 144:ef7eb2e8f9f7 6876 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
<> 144:ef7eb2e8f9f7 6877 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
<> 144:ef7eb2e8f9f7 6878 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
<> 144:ef7eb2e8f9f7 6879
<> 144:ef7eb2e8f9f7 6880 /* Bit 2 : SoF expected or not in RX frames */
<> 144:ef7eb2e8f9f7 6881 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
<> 144:ef7eb2e8f9f7 6882 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
<> 144:ef7eb2e8f9f7 6883 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
<> 144:ef7eb2e8f9f7 6884 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
<> 144:ef7eb2e8f9f7 6885
<> 144:ef7eb2e8f9f7 6886 /* Bit 0 : Parity expected or not in RX frame */
<> 144:ef7eb2e8f9f7 6887 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
<> 144:ef7eb2e8f9f7 6888 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
<> 144:ef7eb2e8f9f7 6889 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
<> 144:ef7eb2e8f9f7 6890 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
<> 144:ef7eb2e8f9f7 6891
<> 144:ef7eb2e8f9f7 6892 /* Register: NFCT_RXD_AMOUNT */
<> 144:ef7eb2e8f9f7 6893 /* Description: Size of last incoming frame */
<> 144:ef7eb2e8f9f7 6894
<> 144:ef7eb2e8f9f7 6895 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
<> 144:ef7eb2e8f9f7 6896 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
<> 144:ef7eb2e8f9f7 6897 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
<> 144:ef7eb2e8f9f7 6898
<> 144:ef7eb2e8f9f7 6899 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
<> 144:ef7eb2e8f9f7 6900 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
<> 144:ef7eb2e8f9f7 6901 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
<> 144:ef7eb2e8f9f7 6902
<> 144:ef7eb2e8f9f7 6903 /* Register: NFCT_NFCID1_LAST */
<> 144:ef7eb2e8f9f7 6904 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
<> 144:ef7eb2e8f9f7 6905
<> 144:ef7eb2e8f9f7 6906 /* Bits 31..24 : NFCID1 byte W */
<> 144:ef7eb2e8f9f7 6907 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
<> 144:ef7eb2e8f9f7 6908 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
<> 144:ef7eb2e8f9f7 6909
<> 144:ef7eb2e8f9f7 6910 /* Bits 23..16 : NFCID1 byte X */
<> 144:ef7eb2e8f9f7 6911 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
<> 144:ef7eb2e8f9f7 6912 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
<> 144:ef7eb2e8f9f7 6913
<> 144:ef7eb2e8f9f7 6914 /* Bits 15..8 : NFCID1 byte Y */
<> 144:ef7eb2e8f9f7 6915 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
<> 144:ef7eb2e8f9f7 6916 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
<> 144:ef7eb2e8f9f7 6917
<> 144:ef7eb2e8f9f7 6918 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
<> 144:ef7eb2e8f9f7 6919 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
<> 144:ef7eb2e8f9f7 6920 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
<> 144:ef7eb2e8f9f7 6921
<> 144:ef7eb2e8f9f7 6922 /* Register: NFCT_NFCID1_2ND_LAST */
<> 144:ef7eb2e8f9f7 6923 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
<> 144:ef7eb2e8f9f7 6924
<> 144:ef7eb2e8f9f7 6925 /* Bits 23..16 : NFCID1 byte T */
<> 144:ef7eb2e8f9f7 6926 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
<> 144:ef7eb2e8f9f7 6927 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
<> 144:ef7eb2e8f9f7 6928
<> 144:ef7eb2e8f9f7 6929 /* Bits 15..8 : NFCID1 byte U */
<> 144:ef7eb2e8f9f7 6930 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
<> 144:ef7eb2e8f9f7 6931 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
<> 144:ef7eb2e8f9f7 6932
<> 144:ef7eb2e8f9f7 6933 /* Bits 7..0 : NFCID1 byte V */
<> 144:ef7eb2e8f9f7 6934 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
<> 144:ef7eb2e8f9f7 6935 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
<> 144:ef7eb2e8f9f7 6936
<> 144:ef7eb2e8f9f7 6937 /* Register: NFCT_NFCID1_3RD_LAST */
<> 144:ef7eb2e8f9f7 6938 /* Description: Third last NFCID1 part (10 bytes ID) */
<> 144:ef7eb2e8f9f7 6939
<> 144:ef7eb2e8f9f7 6940 /* Bits 23..16 : NFCID1 byte Q */
<> 144:ef7eb2e8f9f7 6941 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
<> 144:ef7eb2e8f9f7 6942 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
<> 144:ef7eb2e8f9f7 6943
<> 144:ef7eb2e8f9f7 6944 /* Bits 15..8 : NFCID1 byte R */
<> 144:ef7eb2e8f9f7 6945 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
<> 144:ef7eb2e8f9f7 6946 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
<> 144:ef7eb2e8f9f7 6947
<> 144:ef7eb2e8f9f7 6948 /* Bits 7..0 : NFCID1 byte S */
<> 144:ef7eb2e8f9f7 6949 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
<> 144:ef7eb2e8f9f7 6950 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
<> 144:ef7eb2e8f9f7 6951
<> 144:ef7eb2e8f9f7 6952 /* Register: NFCT_SENSRES */
<> 144:ef7eb2e8f9f7 6953 /* Description: NFC-A SENS_RES auto-response settings */
<> 144:ef7eb2e8f9f7 6954
<> 144:ef7eb2e8f9f7 6955 /* Bits 15..12 : Reserved for future use. Shall be 0. */
<> 144:ef7eb2e8f9f7 6956 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
<> 144:ef7eb2e8f9f7 6957 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
<> 144:ef7eb2e8f9f7 6958
<> 144:ef7eb2e8f9f7 6959 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
<> 144:ef7eb2e8f9f7 6960 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
<> 144:ef7eb2e8f9f7 6961 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
<> 144:ef7eb2e8f9f7 6962
<> 144:ef7eb2e8f9f7 6963 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
<> 144:ef7eb2e8f9f7 6964 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
<> 144:ef7eb2e8f9f7 6965 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
<> 144:ef7eb2e8f9f7 6966 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
<> 144:ef7eb2e8f9f7 6967 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
<> 144:ef7eb2e8f9f7 6968 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
<> 144:ef7eb2e8f9f7 6969
<> 144:ef7eb2e8f9f7 6970 /* Bit 5 : Reserved for future use. Shall be 0. */
<> 144:ef7eb2e8f9f7 6971 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
<> 144:ef7eb2e8f9f7 6972 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
<> 144:ef7eb2e8f9f7 6973
<> 144:ef7eb2e8f9f7 6974 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
<> 144:ef7eb2e8f9f7 6975 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
<> 144:ef7eb2e8f9f7 6976 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
<> 144:ef7eb2e8f9f7 6977 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
<> 144:ef7eb2e8f9f7 6978 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
<> 144:ef7eb2e8f9f7 6979 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
<> 144:ef7eb2e8f9f7 6980 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
<> 144:ef7eb2e8f9f7 6981 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
<> 144:ef7eb2e8f9f7 6982 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
<> 144:ef7eb2e8f9f7 6983
<> 144:ef7eb2e8f9f7 6984 /* Register: NFCT_SELRES */
<> 144:ef7eb2e8f9f7 6985 /* Description: NFC-A SEL_RES auto-response settings */
<> 144:ef7eb2e8f9f7 6986
<> 144:ef7eb2e8f9f7 6987 /* Bit 7 : Reserved for future use. Shall be 0. */
<> 144:ef7eb2e8f9f7 6988 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
<> 144:ef7eb2e8f9f7 6989 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
<> 144:ef7eb2e8f9f7 6990
<> 144:ef7eb2e8f9f7 6991 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
<> 144:ef7eb2e8f9f7 6992 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
<> 144:ef7eb2e8f9f7 6993 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
<> 144:ef7eb2e8f9f7 6994
<> 144:ef7eb2e8f9f7 6995 /* Bits 4..3 : Reserved for future use. Shall be 0. */
<> 144:ef7eb2e8f9f7 6996 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
<> 144:ef7eb2e8f9f7 6997 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
<> 144:ef7eb2e8f9f7 6998
<> 144:ef7eb2e8f9f7 6999 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
<> 144:ef7eb2e8f9f7 7000 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
<> 144:ef7eb2e8f9f7 7001 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
<> 144:ef7eb2e8f9f7 7002 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
<> 144:ef7eb2e8f9f7 7003 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
<> 144:ef7eb2e8f9f7 7004
<> 144:ef7eb2e8f9f7 7005 /* Bits 1..0 : Reserved for future use. Shall be 0. */
<> 144:ef7eb2e8f9f7 7006 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
<> 144:ef7eb2e8f9f7 7007 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
<> 144:ef7eb2e8f9f7 7008
<> 144:ef7eb2e8f9f7 7009
<> 144:ef7eb2e8f9f7 7010 /* Peripheral: NVMC */
<> 144:ef7eb2e8f9f7 7011 /* Description: Non Volatile Memory Controller */
<> 144:ef7eb2e8f9f7 7012
<> 144:ef7eb2e8f9f7 7013 /* Register: NVMC_READY */
<> 144:ef7eb2e8f9f7 7014 /* Description: Ready flag */
<> 144:ef7eb2e8f9f7 7015
<> 144:ef7eb2e8f9f7 7016 /* Bit 0 : NVMC is ready or busy */
<> 144:ef7eb2e8f9f7 7017 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 7018 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 7019 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
<> 144:ef7eb2e8f9f7 7020 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
<> 144:ef7eb2e8f9f7 7021
<> 144:ef7eb2e8f9f7 7022 /* Register: NVMC_CONFIG */
<> 144:ef7eb2e8f9f7 7023 /* Description: Configuration register */
<> 144:ef7eb2e8f9f7 7024
<> 144:ef7eb2e8f9f7 7025 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
<> 144:ef7eb2e8f9f7 7026 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
<> 144:ef7eb2e8f9f7 7027 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
<> 144:ef7eb2e8f9f7 7028 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
<> 144:ef7eb2e8f9f7 7029 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
<> 144:ef7eb2e8f9f7 7030 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
<> 144:ef7eb2e8f9f7 7031
<> 144:ef7eb2e8f9f7 7032 /* Register: NVMC_ERASEPAGE */
<> 144:ef7eb2e8f9f7 7033 /* Description: Register for erasing a page in Code area */
<> 144:ef7eb2e8f9f7 7034
<> 144:ef7eb2e8f9f7 7035 /* Bits 31..0 : Register for starting erase of a page in Code area */
<> 144:ef7eb2e8f9f7 7036 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
<> 144:ef7eb2e8f9f7 7037 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
<> 144:ef7eb2e8f9f7 7038
<> 144:ef7eb2e8f9f7 7039 /* Register: NVMC_ERASEPCR1 */
<> 144:ef7eb2e8f9f7 7040 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
<> 144:ef7eb2e8f9f7 7041
<> 144:ef7eb2e8f9f7 7042 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
<> 144:ef7eb2e8f9f7 7043 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
<> 144:ef7eb2e8f9f7 7044 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
<> 144:ef7eb2e8f9f7 7045
<> 144:ef7eb2e8f9f7 7046 /* Register: NVMC_ERASEALL */
<> 144:ef7eb2e8f9f7 7047 /* Description: Register for erasing all non-volatile user memory */
<> 144:ef7eb2e8f9f7 7048
<> 144:ef7eb2e8f9f7 7049 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
<> 144:ef7eb2e8f9f7 7050 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
<> 144:ef7eb2e8f9f7 7051 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
<> 144:ef7eb2e8f9f7 7052 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
<> 144:ef7eb2e8f9f7 7053 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
<> 144:ef7eb2e8f9f7 7054
<> 144:ef7eb2e8f9f7 7055 /* Register: NVMC_ERASEPCR0 */
<> 144:ef7eb2e8f9f7 7056 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
<> 144:ef7eb2e8f9f7 7057
<> 144:ef7eb2e8f9f7 7058 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
<> 144:ef7eb2e8f9f7 7059 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
<> 144:ef7eb2e8f9f7 7060 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
<> 144:ef7eb2e8f9f7 7061
<> 144:ef7eb2e8f9f7 7062 /* Register: NVMC_ERASEUICR */
<> 144:ef7eb2e8f9f7 7063 /* Description: Register for erasing User Information Configuration Registers */
<> 144:ef7eb2e8f9f7 7064
<> 144:ef7eb2e8f9f7 7065 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
<> 144:ef7eb2e8f9f7 7066 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
<> 144:ef7eb2e8f9f7 7067 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
<> 144:ef7eb2e8f9f7 7068 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
<> 144:ef7eb2e8f9f7 7069 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
<> 144:ef7eb2e8f9f7 7070
<> 144:ef7eb2e8f9f7 7071 /* Register: NVMC_ICACHECNF */
<> 144:ef7eb2e8f9f7 7072 /* Description: I-Code cache configuration register. */
<> 144:ef7eb2e8f9f7 7073
<> 144:ef7eb2e8f9f7 7074 /* Bit 8 : Cache profiling enable */
<> 144:ef7eb2e8f9f7 7075 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
<> 144:ef7eb2e8f9f7 7076 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
<> 144:ef7eb2e8f9f7 7077 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
<> 144:ef7eb2e8f9f7 7078 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
<> 144:ef7eb2e8f9f7 7079
<> 144:ef7eb2e8f9f7 7080 /* Bit 0 : Cache enable */
<> 144:ef7eb2e8f9f7 7081 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
<> 144:ef7eb2e8f9f7 7082 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
<> 144:ef7eb2e8f9f7 7083 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
<> 144:ef7eb2e8f9f7 7084 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
<> 144:ef7eb2e8f9f7 7085
<> 144:ef7eb2e8f9f7 7086 /* Register: NVMC_IHIT */
<> 144:ef7eb2e8f9f7 7087 /* Description: I-Code cache hit counter. */
<> 144:ef7eb2e8f9f7 7088
<> 144:ef7eb2e8f9f7 7089 /* Bits 31..0 : Number of cache hits */
<> 144:ef7eb2e8f9f7 7090 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
<> 144:ef7eb2e8f9f7 7091 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
<> 144:ef7eb2e8f9f7 7092
<> 144:ef7eb2e8f9f7 7093 /* Register: NVMC_IMISS */
<> 144:ef7eb2e8f9f7 7094 /* Description: I-Code cache miss counter. */
<> 144:ef7eb2e8f9f7 7095
<> 144:ef7eb2e8f9f7 7096 /* Bits 31..0 : Number of cache misses */
<> 144:ef7eb2e8f9f7 7097 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
<> 144:ef7eb2e8f9f7 7098 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
<> 144:ef7eb2e8f9f7 7099
<> 144:ef7eb2e8f9f7 7100
<> 144:ef7eb2e8f9f7 7101 /* Peripheral: GPIO */
<> 144:ef7eb2e8f9f7 7102 /* Description: GPIO Port 1 */
<> 144:ef7eb2e8f9f7 7103
<> 144:ef7eb2e8f9f7 7104 /* Register: GPIO_OUT */
<> 144:ef7eb2e8f9f7 7105 /* Description: Write GPIO port */
<> 144:ef7eb2e8f9f7 7106
<> 144:ef7eb2e8f9f7 7107 /* Bit 31 : P0.31 pin */
<> 144:ef7eb2e8f9f7 7108 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 7109 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 7110 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7111 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7112
<> 144:ef7eb2e8f9f7 7113 /* Bit 30 : P0.30 pin */
<> 144:ef7eb2e8f9f7 7114 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 7115 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 7116 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7117 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7118
<> 144:ef7eb2e8f9f7 7119 /* Bit 29 : P0.29 pin */
<> 144:ef7eb2e8f9f7 7120 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 7121 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 7122 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7123 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7124
<> 144:ef7eb2e8f9f7 7125 /* Bit 28 : P0.28 pin */
<> 144:ef7eb2e8f9f7 7126 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 7127 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 7128 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7129 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7130
<> 144:ef7eb2e8f9f7 7131 /* Bit 27 : P0.27 pin */
<> 144:ef7eb2e8f9f7 7132 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 7133 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 7134 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7135 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7136
<> 144:ef7eb2e8f9f7 7137 /* Bit 26 : P0.26 pin */
<> 144:ef7eb2e8f9f7 7138 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 7139 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 7140 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7141 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7142
<> 144:ef7eb2e8f9f7 7143 /* Bit 25 : P0.25 pin */
<> 144:ef7eb2e8f9f7 7144 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 7145 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 7146 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7147 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7148
<> 144:ef7eb2e8f9f7 7149 /* Bit 24 : P0.24 pin */
<> 144:ef7eb2e8f9f7 7150 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 7151 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 7152 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7153 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7154
<> 144:ef7eb2e8f9f7 7155 /* Bit 23 : P0.23 pin */
<> 144:ef7eb2e8f9f7 7156 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 7157 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 7158 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7159 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7160
<> 144:ef7eb2e8f9f7 7161 /* Bit 22 : P0.22 pin */
<> 144:ef7eb2e8f9f7 7162 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 7163 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 7164 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7165 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7166
<> 144:ef7eb2e8f9f7 7167 /* Bit 21 : P0.21 pin */
<> 144:ef7eb2e8f9f7 7168 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 7169 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 7170 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7171 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7172
<> 144:ef7eb2e8f9f7 7173 /* Bit 20 : P0.20 pin */
<> 144:ef7eb2e8f9f7 7174 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 7175 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 7176 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7177 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7178
<> 144:ef7eb2e8f9f7 7179 /* Bit 19 : P0.19 pin */
<> 144:ef7eb2e8f9f7 7180 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 7181 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 7182 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7183 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7184
<> 144:ef7eb2e8f9f7 7185 /* Bit 18 : P0.18 pin */
<> 144:ef7eb2e8f9f7 7186 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 7187 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 7188 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7189 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7190
<> 144:ef7eb2e8f9f7 7191 /* Bit 17 : P0.17 pin */
<> 144:ef7eb2e8f9f7 7192 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 7193 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 7194 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7195 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7196
<> 144:ef7eb2e8f9f7 7197 /* Bit 16 : P0.16 pin */
<> 144:ef7eb2e8f9f7 7198 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 7199 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 7200 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7201 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7202
<> 144:ef7eb2e8f9f7 7203 /* Bit 15 : P0.15 pin */
<> 144:ef7eb2e8f9f7 7204 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 7205 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 7206 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7207 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7208
<> 144:ef7eb2e8f9f7 7209 /* Bit 14 : P0.14 pin */
<> 144:ef7eb2e8f9f7 7210 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 7211 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 7212 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7213 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7214
<> 144:ef7eb2e8f9f7 7215 /* Bit 13 : P0.13 pin */
<> 144:ef7eb2e8f9f7 7216 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 7217 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 7218 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7219 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7220
<> 144:ef7eb2e8f9f7 7221 /* Bit 12 : P0.12 pin */
<> 144:ef7eb2e8f9f7 7222 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 7223 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 7224 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7225 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7226
<> 144:ef7eb2e8f9f7 7227 /* Bit 11 : P0.11 pin */
<> 144:ef7eb2e8f9f7 7228 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 7229 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 7230 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7231 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7232
<> 144:ef7eb2e8f9f7 7233 /* Bit 10 : P0.10 pin */
<> 144:ef7eb2e8f9f7 7234 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 7235 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 7236 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7237 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7238
<> 144:ef7eb2e8f9f7 7239 /* Bit 9 : P0.9 pin */
<> 144:ef7eb2e8f9f7 7240 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 7241 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 7242 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7243 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7244
<> 144:ef7eb2e8f9f7 7245 /* Bit 8 : P0.8 pin */
<> 144:ef7eb2e8f9f7 7246 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 7247 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 7248 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7249 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7250
<> 144:ef7eb2e8f9f7 7251 /* Bit 7 : P0.7 pin */
<> 144:ef7eb2e8f9f7 7252 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 7253 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 7254 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7255 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7256
<> 144:ef7eb2e8f9f7 7257 /* Bit 6 : P0.6 pin */
<> 144:ef7eb2e8f9f7 7258 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 7259 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 7260 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7261 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7262
<> 144:ef7eb2e8f9f7 7263 /* Bit 5 : P0.5 pin */
<> 144:ef7eb2e8f9f7 7264 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 7265 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 7266 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7267 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7268
<> 144:ef7eb2e8f9f7 7269 /* Bit 4 : P0.4 pin */
<> 144:ef7eb2e8f9f7 7270 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 7271 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 7272 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7273 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7274
<> 144:ef7eb2e8f9f7 7275 /* Bit 3 : P0.3 pin */
<> 144:ef7eb2e8f9f7 7276 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 7277 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 7278 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7279 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7280
<> 144:ef7eb2e8f9f7 7281 /* Bit 2 : P0.2 pin */
<> 144:ef7eb2e8f9f7 7282 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 7283 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 7284 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7285 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7286
<> 144:ef7eb2e8f9f7 7287 /* Bit 1 : P0.1 pin */
<> 144:ef7eb2e8f9f7 7288 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 7289 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 7290 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7291 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7292
<> 144:ef7eb2e8f9f7 7293 /* Bit 0 : P0.0 pin */
<> 144:ef7eb2e8f9f7 7294 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 7295 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 7296 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
<> 144:ef7eb2e8f9f7 7297 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
<> 144:ef7eb2e8f9f7 7298
<> 144:ef7eb2e8f9f7 7299 /* Register: GPIO_OUTSET */
<> 144:ef7eb2e8f9f7 7300 /* Description: Set individual bits in GPIO port */
<> 144:ef7eb2e8f9f7 7301
<> 144:ef7eb2e8f9f7 7302 /* Bit 31 : P0.31 pin */
<> 144:ef7eb2e8f9f7 7303 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 7304 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 7305 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7306 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7307 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7308
<> 144:ef7eb2e8f9f7 7309 /* Bit 30 : P0.30 pin */
<> 144:ef7eb2e8f9f7 7310 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 7311 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 7312 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7313 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7314 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7315
<> 144:ef7eb2e8f9f7 7316 /* Bit 29 : P0.29 pin */
<> 144:ef7eb2e8f9f7 7317 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 7318 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 7319 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7320 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7321 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7322
<> 144:ef7eb2e8f9f7 7323 /* Bit 28 : P0.28 pin */
<> 144:ef7eb2e8f9f7 7324 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 7325 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 7326 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7327 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7328 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7329
<> 144:ef7eb2e8f9f7 7330 /* Bit 27 : P0.27 pin */
<> 144:ef7eb2e8f9f7 7331 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 7332 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 7333 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7334 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7335 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7336
<> 144:ef7eb2e8f9f7 7337 /* Bit 26 : P0.26 pin */
<> 144:ef7eb2e8f9f7 7338 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 7339 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 7340 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7341 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7342 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7343
<> 144:ef7eb2e8f9f7 7344 /* Bit 25 : P0.25 pin */
<> 144:ef7eb2e8f9f7 7345 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 7346 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 7347 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7348 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7349 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7350
<> 144:ef7eb2e8f9f7 7351 /* Bit 24 : P0.24 pin */
<> 144:ef7eb2e8f9f7 7352 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 7353 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 7354 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7355 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7356 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7357
<> 144:ef7eb2e8f9f7 7358 /* Bit 23 : P0.23 pin */
<> 144:ef7eb2e8f9f7 7359 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 7360 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 7361 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7362 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7363 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7364
<> 144:ef7eb2e8f9f7 7365 /* Bit 22 : P0.22 pin */
<> 144:ef7eb2e8f9f7 7366 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 7367 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 7368 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7369 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7370 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7371
<> 144:ef7eb2e8f9f7 7372 /* Bit 21 : P0.21 pin */
<> 144:ef7eb2e8f9f7 7373 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 7374 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 7375 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7376 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7377 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7378
<> 144:ef7eb2e8f9f7 7379 /* Bit 20 : P0.20 pin */
<> 144:ef7eb2e8f9f7 7380 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 7381 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 7382 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7383 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7384 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7385
<> 144:ef7eb2e8f9f7 7386 /* Bit 19 : P0.19 pin */
<> 144:ef7eb2e8f9f7 7387 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 7388 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 7389 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7390 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7391 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7392
<> 144:ef7eb2e8f9f7 7393 /* Bit 18 : P0.18 pin */
<> 144:ef7eb2e8f9f7 7394 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 7395 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 7396 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7397 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7398 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7399
<> 144:ef7eb2e8f9f7 7400 /* Bit 17 : P0.17 pin */
<> 144:ef7eb2e8f9f7 7401 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 7402 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 7403 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7404 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7405 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7406
<> 144:ef7eb2e8f9f7 7407 /* Bit 16 : P0.16 pin */
<> 144:ef7eb2e8f9f7 7408 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 7409 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 7410 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7411 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7412 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7413
<> 144:ef7eb2e8f9f7 7414 /* Bit 15 : P0.15 pin */
<> 144:ef7eb2e8f9f7 7415 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 7416 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 7417 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7418 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7419 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7420
<> 144:ef7eb2e8f9f7 7421 /* Bit 14 : P0.14 pin */
<> 144:ef7eb2e8f9f7 7422 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 7423 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 7424 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7425 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7426 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7427
<> 144:ef7eb2e8f9f7 7428 /* Bit 13 : P0.13 pin */
<> 144:ef7eb2e8f9f7 7429 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 7430 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 7431 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7432 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7433 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7434
<> 144:ef7eb2e8f9f7 7435 /* Bit 12 : P0.12 pin */
<> 144:ef7eb2e8f9f7 7436 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 7437 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 7438 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7439 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7440 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7441
<> 144:ef7eb2e8f9f7 7442 /* Bit 11 : P0.11 pin */
<> 144:ef7eb2e8f9f7 7443 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 7444 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 7445 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7446 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7447 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7448
<> 144:ef7eb2e8f9f7 7449 /* Bit 10 : P0.10 pin */
<> 144:ef7eb2e8f9f7 7450 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 7451 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 7452 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7453 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7454 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7455
<> 144:ef7eb2e8f9f7 7456 /* Bit 9 : P0.9 pin */
<> 144:ef7eb2e8f9f7 7457 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 7458 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 7459 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7460 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7461 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7462
<> 144:ef7eb2e8f9f7 7463 /* Bit 8 : P0.8 pin */
<> 144:ef7eb2e8f9f7 7464 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 7465 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 7466 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7467 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7468 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7469
<> 144:ef7eb2e8f9f7 7470 /* Bit 7 : P0.7 pin */
<> 144:ef7eb2e8f9f7 7471 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 7472 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 7473 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7474 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7475 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7476
<> 144:ef7eb2e8f9f7 7477 /* Bit 6 : P0.6 pin */
<> 144:ef7eb2e8f9f7 7478 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 7479 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 7480 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7481 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7482 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7483
<> 144:ef7eb2e8f9f7 7484 /* Bit 5 : P0.5 pin */
<> 144:ef7eb2e8f9f7 7485 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 7486 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 7487 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7488 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7489 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7490
<> 144:ef7eb2e8f9f7 7491 /* Bit 4 : P0.4 pin */
<> 144:ef7eb2e8f9f7 7492 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 7493 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 7494 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7495 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7496 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7497
<> 144:ef7eb2e8f9f7 7498 /* Bit 3 : P0.3 pin */
<> 144:ef7eb2e8f9f7 7499 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 7500 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 7501 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7502 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7503 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7504
<> 144:ef7eb2e8f9f7 7505 /* Bit 2 : P0.2 pin */
<> 144:ef7eb2e8f9f7 7506 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 7507 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 7508 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7509 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7510 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7511
<> 144:ef7eb2e8f9f7 7512 /* Bit 1 : P0.1 pin */
<> 144:ef7eb2e8f9f7 7513 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 7514 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 7515 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7516 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7517 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7518
<> 144:ef7eb2e8f9f7 7519 /* Bit 0 : P0.0 pin */
<> 144:ef7eb2e8f9f7 7520 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 7521 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 7522 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7523 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7524 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7525
<> 144:ef7eb2e8f9f7 7526 /* Register: GPIO_OUTCLR */
<> 144:ef7eb2e8f9f7 7527 /* Description: Clear individual bits in GPIO port */
<> 144:ef7eb2e8f9f7 7528
<> 144:ef7eb2e8f9f7 7529 /* Bit 31 : P0.31 pin */
<> 144:ef7eb2e8f9f7 7530 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 7531 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 7532 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7533 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7534 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7535
<> 144:ef7eb2e8f9f7 7536 /* Bit 30 : P0.30 pin */
<> 144:ef7eb2e8f9f7 7537 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 7538 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 7539 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7540 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7541 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7542
<> 144:ef7eb2e8f9f7 7543 /* Bit 29 : P0.29 pin */
<> 144:ef7eb2e8f9f7 7544 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 7545 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 7546 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7547 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7548 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7549
<> 144:ef7eb2e8f9f7 7550 /* Bit 28 : P0.28 pin */
<> 144:ef7eb2e8f9f7 7551 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 7552 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 7553 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7554 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7555 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7556
<> 144:ef7eb2e8f9f7 7557 /* Bit 27 : P0.27 pin */
<> 144:ef7eb2e8f9f7 7558 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 7559 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 7560 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7561 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7562 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7563
<> 144:ef7eb2e8f9f7 7564 /* Bit 26 : P0.26 pin */
<> 144:ef7eb2e8f9f7 7565 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 7566 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 7567 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7568 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7569 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7570
<> 144:ef7eb2e8f9f7 7571 /* Bit 25 : P0.25 pin */
<> 144:ef7eb2e8f9f7 7572 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 7573 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 7574 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7575 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7576 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7577
<> 144:ef7eb2e8f9f7 7578 /* Bit 24 : P0.24 pin */
<> 144:ef7eb2e8f9f7 7579 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 7580 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 7581 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7582 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7583 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7584
<> 144:ef7eb2e8f9f7 7585 /* Bit 23 : P0.23 pin */
<> 144:ef7eb2e8f9f7 7586 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 7587 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 7588 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7589 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7590 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7591
<> 144:ef7eb2e8f9f7 7592 /* Bit 22 : P0.22 pin */
<> 144:ef7eb2e8f9f7 7593 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 7594 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 7595 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7596 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7597 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7598
<> 144:ef7eb2e8f9f7 7599 /* Bit 21 : P0.21 pin */
<> 144:ef7eb2e8f9f7 7600 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 7601 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 7602 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7603 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7604 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7605
<> 144:ef7eb2e8f9f7 7606 /* Bit 20 : P0.20 pin */
<> 144:ef7eb2e8f9f7 7607 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 7608 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 7609 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7610 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7611 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7612
<> 144:ef7eb2e8f9f7 7613 /* Bit 19 : P0.19 pin */
<> 144:ef7eb2e8f9f7 7614 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 7615 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 7616 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7617 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7618 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7619
<> 144:ef7eb2e8f9f7 7620 /* Bit 18 : P0.18 pin */
<> 144:ef7eb2e8f9f7 7621 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 7622 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 7623 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7624 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7625 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7626
<> 144:ef7eb2e8f9f7 7627 /* Bit 17 : P0.17 pin */
<> 144:ef7eb2e8f9f7 7628 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 7629 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 7630 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7631 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7632 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7633
<> 144:ef7eb2e8f9f7 7634 /* Bit 16 : P0.16 pin */
<> 144:ef7eb2e8f9f7 7635 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 7636 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 7637 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7638 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7639 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7640
<> 144:ef7eb2e8f9f7 7641 /* Bit 15 : P0.15 pin */
<> 144:ef7eb2e8f9f7 7642 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 7643 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 7644 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7645 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7646 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7647
<> 144:ef7eb2e8f9f7 7648 /* Bit 14 : P0.14 pin */
<> 144:ef7eb2e8f9f7 7649 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 7650 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 7651 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7652 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7653 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7654
<> 144:ef7eb2e8f9f7 7655 /* Bit 13 : P0.13 pin */
<> 144:ef7eb2e8f9f7 7656 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 7657 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 7658 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7659 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7660 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7661
<> 144:ef7eb2e8f9f7 7662 /* Bit 12 : P0.12 pin */
<> 144:ef7eb2e8f9f7 7663 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 7664 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 7665 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7666 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7667 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7668
<> 144:ef7eb2e8f9f7 7669 /* Bit 11 : P0.11 pin */
<> 144:ef7eb2e8f9f7 7670 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 7671 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 7672 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7673 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7674 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7675
<> 144:ef7eb2e8f9f7 7676 /* Bit 10 : P0.10 pin */
<> 144:ef7eb2e8f9f7 7677 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 7678 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 7679 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7680 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7681 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7682
<> 144:ef7eb2e8f9f7 7683 /* Bit 9 : P0.9 pin */
<> 144:ef7eb2e8f9f7 7684 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 7685 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 7686 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7687 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7688 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7689
<> 144:ef7eb2e8f9f7 7690 /* Bit 8 : P0.8 pin */
<> 144:ef7eb2e8f9f7 7691 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 7692 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 7693 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7694 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7695 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7696
<> 144:ef7eb2e8f9f7 7697 /* Bit 7 : P0.7 pin */
<> 144:ef7eb2e8f9f7 7698 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 7699 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 7700 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7701 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7702 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7703
<> 144:ef7eb2e8f9f7 7704 /* Bit 6 : P0.6 pin */
<> 144:ef7eb2e8f9f7 7705 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 7706 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 7707 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7708 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7709 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7710
<> 144:ef7eb2e8f9f7 7711 /* Bit 5 : P0.5 pin */
<> 144:ef7eb2e8f9f7 7712 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 7713 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 7714 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7715 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7716 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7717
<> 144:ef7eb2e8f9f7 7718 /* Bit 4 : P0.4 pin */
<> 144:ef7eb2e8f9f7 7719 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 7720 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 7721 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7722 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7723 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7724
<> 144:ef7eb2e8f9f7 7725 /* Bit 3 : P0.3 pin */
<> 144:ef7eb2e8f9f7 7726 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 7727 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 7728 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7729 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7730 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7731
<> 144:ef7eb2e8f9f7 7732 /* Bit 2 : P0.2 pin */
<> 144:ef7eb2e8f9f7 7733 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 7734 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 7735 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7736 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7737 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7738
<> 144:ef7eb2e8f9f7 7739 /* Bit 1 : P0.1 pin */
<> 144:ef7eb2e8f9f7 7740 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 7741 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 7742 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7743 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7744 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7745
<> 144:ef7eb2e8f9f7 7746 /* Bit 0 : P0.0 pin */
<> 144:ef7eb2e8f9f7 7747 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 7748 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 7749 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
<> 144:ef7eb2e8f9f7 7750 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
<> 144:ef7eb2e8f9f7 7751 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 7752
<> 144:ef7eb2e8f9f7 7753 /* Register: GPIO_IN */
<> 144:ef7eb2e8f9f7 7754 /* Description: Read GPIO port */
<> 144:ef7eb2e8f9f7 7755
<> 144:ef7eb2e8f9f7 7756 /* Bit 31 : P0.31 pin */
<> 144:ef7eb2e8f9f7 7757 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 7758 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 7759 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7760 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7761
<> 144:ef7eb2e8f9f7 7762 /* Bit 30 : P0.30 pin */
<> 144:ef7eb2e8f9f7 7763 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 7764 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 7765 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7766 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7767
<> 144:ef7eb2e8f9f7 7768 /* Bit 29 : P0.29 pin */
<> 144:ef7eb2e8f9f7 7769 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 7770 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 7771 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7772 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7773
<> 144:ef7eb2e8f9f7 7774 /* Bit 28 : P0.28 pin */
<> 144:ef7eb2e8f9f7 7775 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 7776 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 7777 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7778 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7779
<> 144:ef7eb2e8f9f7 7780 /* Bit 27 : P0.27 pin */
<> 144:ef7eb2e8f9f7 7781 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 7782 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 7783 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7784 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7785
<> 144:ef7eb2e8f9f7 7786 /* Bit 26 : P0.26 pin */
<> 144:ef7eb2e8f9f7 7787 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 7788 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 7789 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7790 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7791
<> 144:ef7eb2e8f9f7 7792 /* Bit 25 : P0.25 pin */
<> 144:ef7eb2e8f9f7 7793 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 7794 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 7795 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7796 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7797
<> 144:ef7eb2e8f9f7 7798 /* Bit 24 : P0.24 pin */
<> 144:ef7eb2e8f9f7 7799 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 7800 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 7801 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7802 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7803
<> 144:ef7eb2e8f9f7 7804 /* Bit 23 : P0.23 pin */
<> 144:ef7eb2e8f9f7 7805 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 7806 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 7807 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7808 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7809
<> 144:ef7eb2e8f9f7 7810 /* Bit 22 : P0.22 pin */
<> 144:ef7eb2e8f9f7 7811 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 7812 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 7813 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7814 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7815
<> 144:ef7eb2e8f9f7 7816 /* Bit 21 : P0.21 pin */
<> 144:ef7eb2e8f9f7 7817 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 7818 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 7819 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7820 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7821
<> 144:ef7eb2e8f9f7 7822 /* Bit 20 : P0.20 pin */
<> 144:ef7eb2e8f9f7 7823 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 7824 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 7825 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7826 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7827
<> 144:ef7eb2e8f9f7 7828 /* Bit 19 : P0.19 pin */
<> 144:ef7eb2e8f9f7 7829 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 7830 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 7831 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7832 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7833
<> 144:ef7eb2e8f9f7 7834 /* Bit 18 : P0.18 pin */
<> 144:ef7eb2e8f9f7 7835 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 7836 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 7837 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7838 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7839
<> 144:ef7eb2e8f9f7 7840 /* Bit 17 : P0.17 pin */
<> 144:ef7eb2e8f9f7 7841 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 7842 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 7843 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7844 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7845
<> 144:ef7eb2e8f9f7 7846 /* Bit 16 : P0.16 pin */
<> 144:ef7eb2e8f9f7 7847 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 7848 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 7849 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7850 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7851
<> 144:ef7eb2e8f9f7 7852 /* Bit 15 : P0.15 pin */
<> 144:ef7eb2e8f9f7 7853 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 7854 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 7855 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7856 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7857
<> 144:ef7eb2e8f9f7 7858 /* Bit 14 : P0.14 pin */
<> 144:ef7eb2e8f9f7 7859 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 7860 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 7861 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7862 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7863
<> 144:ef7eb2e8f9f7 7864 /* Bit 13 : P0.13 pin */
<> 144:ef7eb2e8f9f7 7865 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 7866 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 7867 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7868 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7869
<> 144:ef7eb2e8f9f7 7870 /* Bit 12 : P0.12 pin */
<> 144:ef7eb2e8f9f7 7871 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 7872 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 7873 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7874 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7875
<> 144:ef7eb2e8f9f7 7876 /* Bit 11 : P0.11 pin */
<> 144:ef7eb2e8f9f7 7877 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 7878 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 7879 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7880 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7881
<> 144:ef7eb2e8f9f7 7882 /* Bit 10 : P0.10 pin */
<> 144:ef7eb2e8f9f7 7883 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 7884 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 7885 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7886 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7887
<> 144:ef7eb2e8f9f7 7888 /* Bit 9 : P0.9 pin */
<> 144:ef7eb2e8f9f7 7889 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 7890 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 7891 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7892 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7893
<> 144:ef7eb2e8f9f7 7894 /* Bit 8 : P0.8 pin */
<> 144:ef7eb2e8f9f7 7895 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 7896 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 7897 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7898 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7899
<> 144:ef7eb2e8f9f7 7900 /* Bit 7 : P0.7 pin */
<> 144:ef7eb2e8f9f7 7901 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 7902 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 7903 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7904 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7905
<> 144:ef7eb2e8f9f7 7906 /* Bit 6 : P0.6 pin */
<> 144:ef7eb2e8f9f7 7907 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 7908 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 7909 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7910 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7911
<> 144:ef7eb2e8f9f7 7912 /* Bit 5 : P0.5 pin */
<> 144:ef7eb2e8f9f7 7913 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 7914 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 7915 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7916 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7917
<> 144:ef7eb2e8f9f7 7918 /* Bit 4 : P0.4 pin */
<> 144:ef7eb2e8f9f7 7919 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 7920 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 7921 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7922 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7923
<> 144:ef7eb2e8f9f7 7924 /* Bit 3 : P0.3 pin */
<> 144:ef7eb2e8f9f7 7925 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 7926 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 7927 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7928 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7929
<> 144:ef7eb2e8f9f7 7930 /* Bit 2 : P0.2 pin */
<> 144:ef7eb2e8f9f7 7931 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 7932 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 7933 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7934 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7935
<> 144:ef7eb2e8f9f7 7936 /* Bit 1 : P0.1 pin */
<> 144:ef7eb2e8f9f7 7937 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 7938 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 7939 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7940 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7941
<> 144:ef7eb2e8f9f7 7942 /* Bit 0 : P0.0 pin */
<> 144:ef7eb2e8f9f7 7943 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 7944 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 7945 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
<> 144:ef7eb2e8f9f7 7946 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
<> 144:ef7eb2e8f9f7 7947
<> 144:ef7eb2e8f9f7 7948 /* Register: GPIO_DIR */
<> 144:ef7eb2e8f9f7 7949 /* Description: Direction of GPIO pins */
<> 144:ef7eb2e8f9f7 7950
<> 144:ef7eb2e8f9f7 7951 /* Bit 31 : P0.31 pin */
<> 144:ef7eb2e8f9f7 7952 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 7953 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 7954 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7955 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7956
<> 144:ef7eb2e8f9f7 7957 /* Bit 30 : P0.30 pin */
<> 144:ef7eb2e8f9f7 7958 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 7959 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 7960 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7961 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7962
<> 144:ef7eb2e8f9f7 7963 /* Bit 29 : P0.29 pin */
<> 144:ef7eb2e8f9f7 7964 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 7965 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 7966 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7967 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7968
<> 144:ef7eb2e8f9f7 7969 /* Bit 28 : P0.28 pin */
<> 144:ef7eb2e8f9f7 7970 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 7971 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 7972 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7973 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7974
<> 144:ef7eb2e8f9f7 7975 /* Bit 27 : P0.27 pin */
<> 144:ef7eb2e8f9f7 7976 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 7977 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 7978 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7979 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7980
<> 144:ef7eb2e8f9f7 7981 /* Bit 26 : P0.26 pin */
<> 144:ef7eb2e8f9f7 7982 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 7983 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 7984 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7985 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7986
<> 144:ef7eb2e8f9f7 7987 /* Bit 25 : P0.25 pin */
<> 144:ef7eb2e8f9f7 7988 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 7989 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 7990 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7991 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7992
<> 144:ef7eb2e8f9f7 7993 /* Bit 24 : P0.24 pin */
<> 144:ef7eb2e8f9f7 7994 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 7995 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 7996 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 7997 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 7998
<> 144:ef7eb2e8f9f7 7999 /* Bit 23 : P0.23 pin */
<> 144:ef7eb2e8f9f7 8000 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 8001 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 8002 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8003 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8004
<> 144:ef7eb2e8f9f7 8005 /* Bit 22 : P0.22 pin */
<> 144:ef7eb2e8f9f7 8006 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 8007 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 8008 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8009 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8010
<> 144:ef7eb2e8f9f7 8011 /* Bit 21 : P0.21 pin */
<> 144:ef7eb2e8f9f7 8012 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 8013 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 8014 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8015 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8016
<> 144:ef7eb2e8f9f7 8017 /* Bit 20 : P0.20 pin */
<> 144:ef7eb2e8f9f7 8018 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 8019 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 8020 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8021 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8022
<> 144:ef7eb2e8f9f7 8023 /* Bit 19 : P0.19 pin */
<> 144:ef7eb2e8f9f7 8024 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 8025 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 8026 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8027 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8028
<> 144:ef7eb2e8f9f7 8029 /* Bit 18 : P0.18 pin */
<> 144:ef7eb2e8f9f7 8030 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 8031 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 8032 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8033 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8034
<> 144:ef7eb2e8f9f7 8035 /* Bit 17 : P0.17 pin */
<> 144:ef7eb2e8f9f7 8036 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 8037 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 8038 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8039 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8040
<> 144:ef7eb2e8f9f7 8041 /* Bit 16 : P0.16 pin */
<> 144:ef7eb2e8f9f7 8042 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 8043 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 8044 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8045 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8046
<> 144:ef7eb2e8f9f7 8047 /* Bit 15 : P0.15 pin */
<> 144:ef7eb2e8f9f7 8048 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 8049 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 8050 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8051 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8052
<> 144:ef7eb2e8f9f7 8053 /* Bit 14 : P0.14 pin */
<> 144:ef7eb2e8f9f7 8054 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 8055 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 8056 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8057 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8058
<> 144:ef7eb2e8f9f7 8059 /* Bit 13 : P0.13 pin */
<> 144:ef7eb2e8f9f7 8060 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 8061 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 8062 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8063 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8064
<> 144:ef7eb2e8f9f7 8065 /* Bit 12 : P0.12 pin */
<> 144:ef7eb2e8f9f7 8066 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 8067 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 8068 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8069 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8070
<> 144:ef7eb2e8f9f7 8071 /* Bit 11 : P0.11 pin */
<> 144:ef7eb2e8f9f7 8072 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 8073 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 8074 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8075 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8076
<> 144:ef7eb2e8f9f7 8077 /* Bit 10 : P0.10 pin */
<> 144:ef7eb2e8f9f7 8078 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 8079 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 8080 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8081 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8082
<> 144:ef7eb2e8f9f7 8083 /* Bit 9 : P0.9 pin */
<> 144:ef7eb2e8f9f7 8084 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 8085 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 8086 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8087 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8088
<> 144:ef7eb2e8f9f7 8089 /* Bit 8 : P0.8 pin */
<> 144:ef7eb2e8f9f7 8090 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 8091 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 8092 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8093 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8094
<> 144:ef7eb2e8f9f7 8095 /* Bit 7 : P0.7 pin */
<> 144:ef7eb2e8f9f7 8096 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 8097 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 8098 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8099 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8100
<> 144:ef7eb2e8f9f7 8101 /* Bit 6 : P0.6 pin */
<> 144:ef7eb2e8f9f7 8102 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 8103 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 8104 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8105 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8106
<> 144:ef7eb2e8f9f7 8107 /* Bit 5 : P0.5 pin */
<> 144:ef7eb2e8f9f7 8108 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 8109 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 8110 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8111 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8112
<> 144:ef7eb2e8f9f7 8113 /* Bit 4 : P0.4 pin */
<> 144:ef7eb2e8f9f7 8114 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 8115 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 8116 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8117 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8118
<> 144:ef7eb2e8f9f7 8119 /* Bit 3 : P0.3 pin */
<> 144:ef7eb2e8f9f7 8120 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 8121 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 8122 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8123 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8124
<> 144:ef7eb2e8f9f7 8125 /* Bit 2 : P0.2 pin */
<> 144:ef7eb2e8f9f7 8126 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 8127 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 8128 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8129 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8130
<> 144:ef7eb2e8f9f7 8131 /* Bit 1 : P0.1 pin */
<> 144:ef7eb2e8f9f7 8132 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 8133 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 8134 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8135 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8136
<> 144:ef7eb2e8f9f7 8137 /* Bit 0 : P0.0 pin */
<> 144:ef7eb2e8f9f7 8138 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 8139 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 8140 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
<> 144:ef7eb2e8f9f7 8141 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
<> 144:ef7eb2e8f9f7 8142
<> 144:ef7eb2e8f9f7 8143 /* Register: GPIO_DIRSET */
<> 144:ef7eb2e8f9f7 8144 /* Description: DIR set register */
<> 144:ef7eb2e8f9f7 8145
<> 144:ef7eb2e8f9f7 8146 /* Bit 31 : Set as output pin 31 */
<> 144:ef7eb2e8f9f7 8147 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 8148 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 8149 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8150 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8151 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8152
<> 144:ef7eb2e8f9f7 8153 /* Bit 30 : Set as output pin 30 */
<> 144:ef7eb2e8f9f7 8154 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 8155 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 8156 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8157 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8158 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8159
<> 144:ef7eb2e8f9f7 8160 /* Bit 29 : Set as output pin 29 */
<> 144:ef7eb2e8f9f7 8161 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 8162 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 8163 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8164 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8165 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8166
<> 144:ef7eb2e8f9f7 8167 /* Bit 28 : Set as output pin 28 */
<> 144:ef7eb2e8f9f7 8168 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 8169 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 8170 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8171 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8172 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8173
<> 144:ef7eb2e8f9f7 8174 /* Bit 27 : Set as output pin 27 */
<> 144:ef7eb2e8f9f7 8175 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 8176 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 8177 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8178 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8179 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8180
<> 144:ef7eb2e8f9f7 8181 /* Bit 26 : Set as output pin 26 */
<> 144:ef7eb2e8f9f7 8182 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 8183 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 8184 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8185 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8186 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8187
<> 144:ef7eb2e8f9f7 8188 /* Bit 25 : Set as output pin 25 */
<> 144:ef7eb2e8f9f7 8189 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 8190 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 8191 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8192 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8193 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8194
<> 144:ef7eb2e8f9f7 8195 /* Bit 24 : Set as output pin 24 */
<> 144:ef7eb2e8f9f7 8196 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 8197 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 8198 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8199 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8200 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8201
<> 144:ef7eb2e8f9f7 8202 /* Bit 23 : Set as output pin 23 */
<> 144:ef7eb2e8f9f7 8203 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 8204 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 8205 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8206 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8207 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8208
<> 144:ef7eb2e8f9f7 8209 /* Bit 22 : Set as output pin 22 */
<> 144:ef7eb2e8f9f7 8210 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 8211 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 8212 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8213 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8214 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8215
<> 144:ef7eb2e8f9f7 8216 /* Bit 21 : Set as output pin 21 */
<> 144:ef7eb2e8f9f7 8217 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 8218 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 8219 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8220 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8221 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8222
<> 144:ef7eb2e8f9f7 8223 /* Bit 20 : Set as output pin 20 */
<> 144:ef7eb2e8f9f7 8224 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 8225 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 8226 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8227 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8228 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8229
<> 144:ef7eb2e8f9f7 8230 /* Bit 19 : Set as output pin 19 */
<> 144:ef7eb2e8f9f7 8231 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 8232 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 8233 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8234 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8235 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8236
<> 144:ef7eb2e8f9f7 8237 /* Bit 18 : Set as output pin 18 */
<> 144:ef7eb2e8f9f7 8238 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 8239 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 8240 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8241 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8242 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8243
<> 144:ef7eb2e8f9f7 8244 /* Bit 17 : Set as output pin 17 */
<> 144:ef7eb2e8f9f7 8245 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 8246 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 8247 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8248 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8249 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8250
<> 144:ef7eb2e8f9f7 8251 /* Bit 16 : Set as output pin 16 */
<> 144:ef7eb2e8f9f7 8252 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 8253 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 8254 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8255 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8256 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8257
<> 144:ef7eb2e8f9f7 8258 /* Bit 15 : Set as output pin 15 */
<> 144:ef7eb2e8f9f7 8259 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 8260 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 8261 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8262 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8263 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8264
<> 144:ef7eb2e8f9f7 8265 /* Bit 14 : Set as output pin 14 */
<> 144:ef7eb2e8f9f7 8266 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 8267 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 8268 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8269 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8270 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8271
<> 144:ef7eb2e8f9f7 8272 /* Bit 13 : Set as output pin 13 */
<> 144:ef7eb2e8f9f7 8273 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 8274 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 8275 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8276 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8277 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8278
<> 144:ef7eb2e8f9f7 8279 /* Bit 12 : Set as output pin 12 */
<> 144:ef7eb2e8f9f7 8280 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 8281 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 8282 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8283 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8284 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8285
<> 144:ef7eb2e8f9f7 8286 /* Bit 11 : Set as output pin 11 */
<> 144:ef7eb2e8f9f7 8287 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 8288 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 8289 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8290 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8291 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8292
<> 144:ef7eb2e8f9f7 8293 /* Bit 10 : Set as output pin 10 */
<> 144:ef7eb2e8f9f7 8294 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 8295 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 8296 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8297 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8298 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8299
<> 144:ef7eb2e8f9f7 8300 /* Bit 9 : Set as output pin 9 */
<> 144:ef7eb2e8f9f7 8301 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 8302 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 8303 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8304 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8305 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8306
<> 144:ef7eb2e8f9f7 8307 /* Bit 8 : Set as output pin 8 */
<> 144:ef7eb2e8f9f7 8308 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 8309 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 8310 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8311 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8312 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8313
<> 144:ef7eb2e8f9f7 8314 /* Bit 7 : Set as output pin 7 */
<> 144:ef7eb2e8f9f7 8315 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 8316 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 8317 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8318 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8319 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8320
<> 144:ef7eb2e8f9f7 8321 /* Bit 6 : Set as output pin 6 */
<> 144:ef7eb2e8f9f7 8322 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 8323 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 8324 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8325 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8326 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8327
<> 144:ef7eb2e8f9f7 8328 /* Bit 5 : Set as output pin 5 */
<> 144:ef7eb2e8f9f7 8329 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 8330 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 8331 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8332 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8333 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8334
<> 144:ef7eb2e8f9f7 8335 /* Bit 4 : Set as output pin 4 */
<> 144:ef7eb2e8f9f7 8336 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 8337 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 8338 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8339 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8340 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8341
<> 144:ef7eb2e8f9f7 8342 /* Bit 3 : Set as output pin 3 */
<> 144:ef7eb2e8f9f7 8343 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 8344 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 8345 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8346 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8347 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8348
<> 144:ef7eb2e8f9f7 8349 /* Bit 2 : Set as output pin 2 */
<> 144:ef7eb2e8f9f7 8350 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 8351 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 8352 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8353 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8354 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8355
<> 144:ef7eb2e8f9f7 8356 /* Bit 1 : Set as output pin 1 */
<> 144:ef7eb2e8f9f7 8357 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 8358 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 8359 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8360 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8361 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8362
<> 144:ef7eb2e8f9f7 8363 /* Bit 0 : Set as output pin 0 */
<> 144:ef7eb2e8f9f7 8364 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 8365 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 8366 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8367 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8368 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8369
<> 144:ef7eb2e8f9f7 8370 /* Register: GPIO_DIRCLR */
<> 144:ef7eb2e8f9f7 8371 /* Description: DIR clear register */
<> 144:ef7eb2e8f9f7 8372
<> 144:ef7eb2e8f9f7 8373 /* Bit 31 : Set as input pin 31 */
<> 144:ef7eb2e8f9f7 8374 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 8375 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 8376 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8377 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8378 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8379
<> 144:ef7eb2e8f9f7 8380 /* Bit 30 : Set as input pin 30 */
<> 144:ef7eb2e8f9f7 8381 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 8382 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 8383 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8384 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8385 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8386
<> 144:ef7eb2e8f9f7 8387 /* Bit 29 : Set as input pin 29 */
<> 144:ef7eb2e8f9f7 8388 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 8389 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 8390 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8391 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8392 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8393
<> 144:ef7eb2e8f9f7 8394 /* Bit 28 : Set as input pin 28 */
<> 144:ef7eb2e8f9f7 8395 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 8396 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 8397 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8398 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8399 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8400
<> 144:ef7eb2e8f9f7 8401 /* Bit 27 : Set as input pin 27 */
<> 144:ef7eb2e8f9f7 8402 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 8403 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 8404 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8405 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8406 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8407
<> 144:ef7eb2e8f9f7 8408 /* Bit 26 : Set as input pin 26 */
<> 144:ef7eb2e8f9f7 8409 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 8410 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 8411 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8412 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8413 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8414
<> 144:ef7eb2e8f9f7 8415 /* Bit 25 : Set as input pin 25 */
<> 144:ef7eb2e8f9f7 8416 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 8417 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 8418 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8419 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8420 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8421
<> 144:ef7eb2e8f9f7 8422 /* Bit 24 : Set as input pin 24 */
<> 144:ef7eb2e8f9f7 8423 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 8424 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 8425 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8426 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8427 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8428
<> 144:ef7eb2e8f9f7 8429 /* Bit 23 : Set as input pin 23 */
<> 144:ef7eb2e8f9f7 8430 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 8431 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 8432 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8433 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8434 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8435
<> 144:ef7eb2e8f9f7 8436 /* Bit 22 : Set as input pin 22 */
<> 144:ef7eb2e8f9f7 8437 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 8438 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 8439 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8440 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8441 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8442
<> 144:ef7eb2e8f9f7 8443 /* Bit 21 : Set as input pin 21 */
<> 144:ef7eb2e8f9f7 8444 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 8445 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 8446 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8447 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8448 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8449
<> 144:ef7eb2e8f9f7 8450 /* Bit 20 : Set as input pin 20 */
<> 144:ef7eb2e8f9f7 8451 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 8452 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 8453 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8454 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8455 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8456
<> 144:ef7eb2e8f9f7 8457 /* Bit 19 : Set as input pin 19 */
<> 144:ef7eb2e8f9f7 8458 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 8459 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 8460 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8461 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8462 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8463
<> 144:ef7eb2e8f9f7 8464 /* Bit 18 : Set as input pin 18 */
<> 144:ef7eb2e8f9f7 8465 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 8466 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 8467 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8468 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8469 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8470
<> 144:ef7eb2e8f9f7 8471 /* Bit 17 : Set as input pin 17 */
<> 144:ef7eb2e8f9f7 8472 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 8473 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 8474 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8475 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8476 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8477
<> 144:ef7eb2e8f9f7 8478 /* Bit 16 : Set as input pin 16 */
<> 144:ef7eb2e8f9f7 8479 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 8480 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 8481 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8482 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8483 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8484
<> 144:ef7eb2e8f9f7 8485 /* Bit 15 : Set as input pin 15 */
<> 144:ef7eb2e8f9f7 8486 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 8487 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 8488 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8489 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8490 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8491
<> 144:ef7eb2e8f9f7 8492 /* Bit 14 : Set as input pin 14 */
<> 144:ef7eb2e8f9f7 8493 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 8494 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 8495 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8496 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8497 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8498
<> 144:ef7eb2e8f9f7 8499 /* Bit 13 : Set as input pin 13 */
<> 144:ef7eb2e8f9f7 8500 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 8501 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 8502 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8503 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8504 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8505
<> 144:ef7eb2e8f9f7 8506 /* Bit 12 : Set as input pin 12 */
<> 144:ef7eb2e8f9f7 8507 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 8508 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 8509 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8510 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8511 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8512
<> 144:ef7eb2e8f9f7 8513 /* Bit 11 : Set as input pin 11 */
<> 144:ef7eb2e8f9f7 8514 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 8515 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 8516 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8517 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8518 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8519
<> 144:ef7eb2e8f9f7 8520 /* Bit 10 : Set as input pin 10 */
<> 144:ef7eb2e8f9f7 8521 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 8522 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 8523 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8524 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8525 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8526
<> 144:ef7eb2e8f9f7 8527 /* Bit 9 : Set as input pin 9 */
<> 144:ef7eb2e8f9f7 8528 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 8529 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 8530 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8531 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8532 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8533
<> 144:ef7eb2e8f9f7 8534 /* Bit 8 : Set as input pin 8 */
<> 144:ef7eb2e8f9f7 8535 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 8536 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 8537 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8538 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8539 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8540
<> 144:ef7eb2e8f9f7 8541 /* Bit 7 : Set as input pin 7 */
<> 144:ef7eb2e8f9f7 8542 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 8543 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 8544 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8545 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8546 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8547
<> 144:ef7eb2e8f9f7 8548 /* Bit 6 : Set as input pin 6 */
<> 144:ef7eb2e8f9f7 8549 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 8550 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 8551 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8552 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8553 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8554
<> 144:ef7eb2e8f9f7 8555 /* Bit 5 : Set as input pin 5 */
<> 144:ef7eb2e8f9f7 8556 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 8557 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 8558 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8559 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8560 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8561
<> 144:ef7eb2e8f9f7 8562 /* Bit 4 : Set as input pin 4 */
<> 144:ef7eb2e8f9f7 8563 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 8564 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 8565 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8566 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8567 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8568
<> 144:ef7eb2e8f9f7 8569 /* Bit 3 : Set as input pin 3 */
<> 144:ef7eb2e8f9f7 8570 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 8571 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 8572 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8573 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8574 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8575
<> 144:ef7eb2e8f9f7 8576 /* Bit 2 : Set as input pin 2 */
<> 144:ef7eb2e8f9f7 8577 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 8578 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 8579 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8580 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8581 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8582
<> 144:ef7eb2e8f9f7 8583 /* Bit 1 : Set as input pin 1 */
<> 144:ef7eb2e8f9f7 8584 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 8585 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 8586 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8587 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8588 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8589
<> 144:ef7eb2e8f9f7 8590 /* Bit 0 : Set as input pin 0 */
<> 144:ef7eb2e8f9f7 8591 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 8592 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 8593 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
<> 144:ef7eb2e8f9f7 8594 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
<> 144:ef7eb2e8f9f7 8595 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
<> 144:ef7eb2e8f9f7 8596
<> 144:ef7eb2e8f9f7 8597 /* Register: GPIO_LATCH */
<> 144:ef7eb2e8f9f7 8598 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
<> 144:ef7eb2e8f9f7 8599
<> 144:ef7eb2e8f9f7 8600 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8601 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
<> 144:ef7eb2e8f9f7 8602 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
<> 144:ef7eb2e8f9f7 8603 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8604 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8605
<> 144:ef7eb2e8f9f7 8606 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8607 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
<> 144:ef7eb2e8f9f7 8608 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
<> 144:ef7eb2e8f9f7 8609 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8610 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8611
<> 144:ef7eb2e8f9f7 8612 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8613 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
<> 144:ef7eb2e8f9f7 8614 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
<> 144:ef7eb2e8f9f7 8615 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8616 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8617
<> 144:ef7eb2e8f9f7 8618 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8619 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
<> 144:ef7eb2e8f9f7 8620 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
<> 144:ef7eb2e8f9f7 8621 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8622 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8623
<> 144:ef7eb2e8f9f7 8624 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8625 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
<> 144:ef7eb2e8f9f7 8626 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
<> 144:ef7eb2e8f9f7 8627 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8628 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8629
<> 144:ef7eb2e8f9f7 8630 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8631 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
<> 144:ef7eb2e8f9f7 8632 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
<> 144:ef7eb2e8f9f7 8633 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8634 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8635
<> 144:ef7eb2e8f9f7 8636 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8637 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
<> 144:ef7eb2e8f9f7 8638 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
<> 144:ef7eb2e8f9f7 8639 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8640 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8641
<> 144:ef7eb2e8f9f7 8642 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8643 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
<> 144:ef7eb2e8f9f7 8644 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
<> 144:ef7eb2e8f9f7 8645 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8646 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8647
<> 144:ef7eb2e8f9f7 8648 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8649 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
<> 144:ef7eb2e8f9f7 8650 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
<> 144:ef7eb2e8f9f7 8651 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8652 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8653
<> 144:ef7eb2e8f9f7 8654 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8655 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
<> 144:ef7eb2e8f9f7 8656 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
<> 144:ef7eb2e8f9f7 8657 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8658 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8659
<> 144:ef7eb2e8f9f7 8660 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8661 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
<> 144:ef7eb2e8f9f7 8662 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
<> 144:ef7eb2e8f9f7 8663 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8664 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8665
<> 144:ef7eb2e8f9f7 8666 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8667 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
<> 144:ef7eb2e8f9f7 8668 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
<> 144:ef7eb2e8f9f7 8669 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8670 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8671
<> 144:ef7eb2e8f9f7 8672 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8673 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
<> 144:ef7eb2e8f9f7 8674 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
<> 144:ef7eb2e8f9f7 8675 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8676 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8677
<> 144:ef7eb2e8f9f7 8678 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8679 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
<> 144:ef7eb2e8f9f7 8680 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
<> 144:ef7eb2e8f9f7 8681 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8682 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8683
<> 144:ef7eb2e8f9f7 8684 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8685 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
<> 144:ef7eb2e8f9f7 8686 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
<> 144:ef7eb2e8f9f7 8687 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8688 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8689
<> 144:ef7eb2e8f9f7 8690 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8691 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
<> 144:ef7eb2e8f9f7 8692 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
<> 144:ef7eb2e8f9f7 8693 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8694 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8695
<> 144:ef7eb2e8f9f7 8696 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8697 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
<> 144:ef7eb2e8f9f7 8698 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
<> 144:ef7eb2e8f9f7 8699 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8700 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8701
<> 144:ef7eb2e8f9f7 8702 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8703 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
<> 144:ef7eb2e8f9f7 8704 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
<> 144:ef7eb2e8f9f7 8705 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8706 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8707
<> 144:ef7eb2e8f9f7 8708 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8709 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
<> 144:ef7eb2e8f9f7 8710 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
<> 144:ef7eb2e8f9f7 8711 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8712 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8713
<> 144:ef7eb2e8f9f7 8714 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8715 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
<> 144:ef7eb2e8f9f7 8716 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
<> 144:ef7eb2e8f9f7 8717 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8718 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8719
<> 144:ef7eb2e8f9f7 8720 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8721 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
<> 144:ef7eb2e8f9f7 8722 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
<> 144:ef7eb2e8f9f7 8723 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8724 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8725
<> 144:ef7eb2e8f9f7 8726 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8727 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
<> 144:ef7eb2e8f9f7 8728 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
<> 144:ef7eb2e8f9f7 8729 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8730 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8731
<> 144:ef7eb2e8f9f7 8732 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8733 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
<> 144:ef7eb2e8f9f7 8734 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
<> 144:ef7eb2e8f9f7 8735 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8736 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8737
<> 144:ef7eb2e8f9f7 8738 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8739 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
<> 144:ef7eb2e8f9f7 8740 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
<> 144:ef7eb2e8f9f7 8741 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8742 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8743
<> 144:ef7eb2e8f9f7 8744 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8745 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
<> 144:ef7eb2e8f9f7 8746 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
<> 144:ef7eb2e8f9f7 8747 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8748 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8749
<> 144:ef7eb2e8f9f7 8750 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8751 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
<> 144:ef7eb2e8f9f7 8752 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
<> 144:ef7eb2e8f9f7 8753 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8754 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8755
<> 144:ef7eb2e8f9f7 8756 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8757 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
<> 144:ef7eb2e8f9f7 8758 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
<> 144:ef7eb2e8f9f7 8759 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8760 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8761
<> 144:ef7eb2e8f9f7 8762 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8763 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
<> 144:ef7eb2e8f9f7 8764 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
<> 144:ef7eb2e8f9f7 8765 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8766 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8767
<> 144:ef7eb2e8f9f7 8768 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8769 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
<> 144:ef7eb2e8f9f7 8770 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
<> 144:ef7eb2e8f9f7 8771 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8772 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8773
<> 144:ef7eb2e8f9f7 8774 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8775 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
<> 144:ef7eb2e8f9f7 8776 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
<> 144:ef7eb2e8f9f7 8777 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8778 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8779
<> 144:ef7eb2e8f9f7 8780 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8781 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
<> 144:ef7eb2e8f9f7 8782 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
<> 144:ef7eb2e8f9f7 8783 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8784 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8785
<> 144:ef7eb2e8f9f7 8786 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
<> 144:ef7eb2e8f9f7 8787 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
<> 144:ef7eb2e8f9f7 8788 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
<> 144:ef7eb2e8f9f7 8789 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
<> 144:ef7eb2e8f9f7 8790 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
<> 144:ef7eb2e8f9f7 8791
<> 144:ef7eb2e8f9f7 8792 /* Register: GPIO_DETECTMODE */
<> 144:ef7eb2e8f9f7 8793 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
<> 144:ef7eb2e8f9f7 8794
<> 144:ef7eb2e8f9f7 8795 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
<> 144:ef7eb2e8f9f7 8796 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
<> 144:ef7eb2e8f9f7 8797 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
<> 144:ef7eb2e8f9f7 8798 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
<> 144:ef7eb2e8f9f7 8799 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
<> 144:ef7eb2e8f9f7 8800
<> 144:ef7eb2e8f9f7 8801 /* Register: GPIO_PIN_CNF */
<> 144:ef7eb2e8f9f7 8802 /* Description: Description collection[0]: Configuration of GPIO pins */
<> 144:ef7eb2e8f9f7 8803
<> 144:ef7eb2e8f9f7 8804 /* Bits 17..16 : Pin sensing mechanism */
<> 144:ef7eb2e8f9f7 8805 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
<> 144:ef7eb2e8f9f7 8806 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
<> 144:ef7eb2e8f9f7 8807 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 8808 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
<> 144:ef7eb2e8f9f7 8809 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
<> 144:ef7eb2e8f9f7 8810
<> 144:ef7eb2e8f9f7 8811 /* Bits 10..8 : Drive configuration */
<> 144:ef7eb2e8f9f7 8812 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
<> 144:ef7eb2e8f9f7 8813 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
<> 144:ef7eb2e8f9f7 8814 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
<> 144:ef7eb2e8f9f7 8815 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
<> 144:ef7eb2e8f9f7 8816 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
<> 144:ef7eb2e8f9f7 8817 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
<> 144:ef7eb2e8f9f7 8818 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
<> 144:ef7eb2e8f9f7 8819 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
<> 144:ef7eb2e8f9f7 8820 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
<> 144:ef7eb2e8f9f7 8821 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
<> 144:ef7eb2e8f9f7 8822
<> 144:ef7eb2e8f9f7 8823 /* Bits 3..2 : Pull configuration */
<> 144:ef7eb2e8f9f7 8824 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
<> 144:ef7eb2e8f9f7 8825 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
<> 144:ef7eb2e8f9f7 8826 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
<> 144:ef7eb2e8f9f7 8827 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
<> 144:ef7eb2e8f9f7 8828 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
<> 144:ef7eb2e8f9f7 8829
<> 144:ef7eb2e8f9f7 8830 /* Bit 1 : Connect or disconnect input buffer */
<> 144:ef7eb2e8f9f7 8831 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
<> 144:ef7eb2e8f9f7 8832 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
<> 144:ef7eb2e8f9f7 8833 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
<> 144:ef7eb2e8f9f7 8834 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
<> 144:ef7eb2e8f9f7 8835
<> 144:ef7eb2e8f9f7 8836 /* Bit 0 : Pin direction. Same physical register as DIR register */
<> 144:ef7eb2e8f9f7 8837 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
<> 144:ef7eb2e8f9f7 8838 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
<> 144:ef7eb2e8f9f7 8839 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
<> 144:ef7eb2e8f9f7 8840 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
<> 144:ef7eb2e8f9f7 8841
<> 144:ef7eb2e8f9f7 8842
<> 144:ef7eb2e8f9f7 8843 /* Peripheral: PDM */
<> 144:ef7eb2e8f9f7 8844 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
<> 144:ef7eb2e8f9f7 8845
<> 144:ef7eb2e8f9f7 8846 /* Register: PDM_INTEN */
<> 144:ef7eb2e8f9f7 8847 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 8848
<> 144:ef7eb2e8f9f7 8849 /* Bit 2 : Enable or disable interrupt for END event */
<> 144:ef7eb2e8f9f7 8850 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 8851 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 8852 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8853 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8854
<> 144:ef7eb2e8f9f7 8855 /* Bit 1 : Enable or disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 8856 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 8857 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 8858 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8859 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8860
<> 144:ef7eb2e8f9f7 8861 /* Bit 0 : Enable or disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 8862 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 8863 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 8864 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8865 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8866
<> 144:ef7eb2e8f9f7 8867 /* Register: PDM_INTENSET */
<> 144:ef7eb2e8f9f7 8868 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 8869
<> 144:ef7eb2e8f9f7 8870 /* Bit 2 : Write '1' to Enable interrupt for END event */
<> 144:ef7eb2e8f9f7 8871 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 8872 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 8873 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 8874 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 8875 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8876
<> 144:ef7eb2e8f9f7 8877 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 8878 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 8879 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 8880 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 8881 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 8882 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8883
<> 144:ef7eb2e8f9f7 8884 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 8885 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 8886 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 8887 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 8888 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 8889 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8890
<> 144:ef7eb2e8f9f7 8891 /* Register: PDM_INTENCLR */
<> 144:ef7eb2e8f9f7 8892 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 8893
<> 144:ef7eb2e8f9f7 8894 /* Bit 2 : Write '1' to Disable interrupt for END event */
<> 144:ef7eb2e8f9f7 8895 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 8896 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 8897 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 8898 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 8899 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8900
<> 144:ef7eb2e8f9f7 8901 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 8902 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 8903 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 8904 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 8905 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 8906 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8907
<> 144:ef7eb2e8f9f7 8908 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 8909 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 8910 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 8911 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 8912 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 8913 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8914
<> 144:ef7eb2e8f9f7 8915 /* Register: PDM_ENABLE */
<> 144:ef7eb2e8f9f7 8916 /* Description: PDM module enable register */
<> 144:ef7eb2e8f9f7 8917
<> 144:ef7eb2e8f9f7 8918 /* Bit 0 : Enable or disable PDM module */
<> 144:ef7eb2e8f9f7 8919 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 8920 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 8921 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 8922 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 8923
<> 144:ef7eb2e8f9f7 8924 /* Register: PDM_PDMCLKCTRL */
<> 144:ef7eb2e8f9f7 8925 /* Description: PDM clock generator control */
<> 144:ef7eb2e8f9f7 8926
<> 144:ef7eb2e8f9f7 8927 /* Bits 31..0 : PDM_CLK frequency */
<> 144:ef7eb2e8f9f7 8928 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
<> 144:ef7eb2e8f9f7 8929 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
<> 144:ef7eb2e8f9f7 8930 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
<> 144:ef7eb2e8f9f7 8931 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
<> 144:ef7eb2e8f9f7 8932 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
<> 144:ef7eb2e8f9f7 8933
<> 144:ef7eb2e8f9f7 8934 /* Register: PDM_MODE */
<> 144:ef7eb2e8f9f7 8935 /* Description: Defines the routing of the connected PDM microphones' signals */
<> 144:ef7eb2e8f9f7 8936
<> 144:ef7eb2e8f9f7 8937 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
<> 144:ef7eb2e8f9f7 8938 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
<> 144:ef7eb2e8f9f7 8939 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
<> 144:ef7eb2e8f9f7 8940 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
<> 144:ef7eb2e8f9f7 8941 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
<> 144:ef7eb2e8f9f7 8942
<> 144:ef7eb2e8f9f7 8943 /* Bit 0 : Mono or stereo operation */
<> 144:ef7eb2e8f9f7 8944 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
<> 144:ef7eb2e8f9f7 8945 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
<> 144:ef7eb2e8f9f7 8946 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
<> 144:ef7eb2e8f9f7 8947 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
<> 144:ef7eb2e8f9f7 8948
<> 144:ef7eb2e8f9f7 8949 /* Register: PDM_GAINL */
<> 144:ef7eb2e8f9f7 8950 /* Description: Left output gain adjustment */
<> 144:ef7eb2e8f9f7 8951
<> 144:ef7eb2e8f9f7 8952 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
<> 144:ef7eb2e8f9f7 8953 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
<> 144:ef7eb2e8f9f7 8954 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
<> 144:ef7eb2e8f9f7 8955 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
<> 144:ef7eb2e8f9f7 8956 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
<> 144:ef7eb2e8f9f7 8957 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
<> 144:ef7eb2e8f9f7 8958
<> 144:ef7eb2e8f9f7 8959 /* Register: PDM_GAINR */
<> 144:ef7eb2e8f9f7 8960 /* Description: Right output gain adjustment */
<> 144:ef7eb2e8f9f7 8961
<> 144:ef7eb2e8f9f7 8962 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
<> 144:ef7eb2e8f9f7 8963 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
<> 144:ef7eb2e8f9f7 8964 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
<> 144:ef7eb2e8f9f7 8965 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
<> 144:ef7eb2e8f9f7 8966 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
<> 144:ef7eb2e8f9f7 8967 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
<> 144:ef7eb2e8f9f7 8968
<> 144:ef7eb2e8f9f7 8969 /* Register: PDM_PSEL_CLK */
<> 144:ef7eb2e8f9f7 8970 /* Description: Pin number configuration for PDM CLK signal */
<> 144:ef7eb2e8f9f7 8971
<> 144:ef7eb2e8f9f7 8972 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 8973 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 8974 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 8975 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 8976 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 8977
<> 144:ef7eb2e8f9f7 8978 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 8979 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 8980 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 8981
<> 144:ef7eb2e8f9f7 8982 /* Register: PDM_PSEL_DIN */
<> 144:ef7eb2e8f9f7 8983 /* Description: Pin number configuration for PDM DIN signal */
<> 144:ef7eb2e8f9f7 8984
<> 144:ef7eb2e8f9f7 8985 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 8986 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 8987 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 8988 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 8989 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 8990
<> 144:ef7eb2e8f9f7 8991 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 8992 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 8993 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 8994
<> 144:ef7eb2e8f9f7 8995 /* Register: PDM_SAMPLE_PTR */
<> 144:ef7eb2e8f9f7 8996 /* Description: RAM address pointer to write samples to with EasyDMA */
<> 144:ef7eb2e8f9f7 8997
<> 144:ef7eb2e8f9f7 8998 /* Bits 31..0 : Address to write PDM samples to over DMA */
<> 144:ef7eb2e8f9f7 8999 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
<> 144:ef7eb2e8f9f7 9000 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
<> 144:ef7eb2e8f9f7 9001
<> 144:ef7eb2e8f9f7 9002 /* Register: PDM_SAMPLE_MAXCNT */
<> 144:ef7eb2e8f9f7 9003 /* Description: Number of samples to allocate memory for in EasyDMA mode */
<> 144:ef7eb2e8f9f7 9004
<> 144:ef7eb2e8f9f7 9005 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
<> 144:ef7eb2e8f9f7 9006 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
<> 144:ef7eb2e8f9f7 9007 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
<> 144:ef7eb2e8f9f7 9008
<> 144:ef7eb2e8f9f7 9009
<> 144:ef7eb2e8f9f7 9010 /* Peripheral: POWER */
<> 144:ef7eb2e8f9f7 9011 /* Description: Power control */
<> 144:ef7eb2e8f9f7 9012
<> 144:ef7eb2e8f9f7 9013 /* Register: POWER_INTENSET */
<> 144:ef7eb2e8f9f7 9014 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 9015
<> 144:ef7eb2e8f9f7 9016 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
<> 144:ef7eb2e8f9f7 9017 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
<> 144:ef7eb2e8f9f7 9018 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
<> 144:ef7eb2e8f9f7 9019 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 9020 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 9021 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 9022
<> 144:ef7eb2e8f9f7 9023 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
<> 144:ef7eb2e8f9f7 9024 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
<> 144:ef7eb2e8f9f7 9025 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
<> 144:ef7eb2e8f9f7 9026 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 9027 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 9028 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 9029
<> 144:ef7eb2e8f9f7 9030 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
<> 144:ef7eb2e8f9f7 9031 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
<> 144:ef7eb2e8f9f7 9032 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
<> 144:ef7eb2e8f9f7 9033 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 9034 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 9035 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 9036
<> 144:ef7eb2e8f9f7 9037 /* Register: POWER_INTENCLR */
<> 144:ef7eb2e8f9f7 9038 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 9039
<> 144:ef7eb2e8f9f7 9040 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
<> 144:ef7eb2e8f9f7 9041 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
<> 144:ef7eb2e8f9f7 9042 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
<> 144:ef7eb2e8f9f7 9043 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 9044 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 9045 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 9046
<> 144:ef7eb2e8f9f7 9047 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
<> 144:ef7eb2e8f9f7 9048 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
<> 144:ef7eb2e8f9f7 9049 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
<> 144:ef7eb2e8f9f7 9050 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 9051 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 9052 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 9053
<> 144:ef7eb2e8f9f7 9054 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
<> 144:ef7eb2e8f9f7 9055 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
<> 144:ef7eb2e8f9f7 9056 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
<> 144:ef7eb2e8f9f7 9057 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 9058 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 9059 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 9060
<> 144:ef7eb2e8f9f7 9061 /* Register: POWER_RESETREAS */
<> 144:ef7eb2e8f9f7 9062 /* Description: Reset reason */
<> 144:ef7eb2e8f9f7 9063
<> 144:ef7eb2e8f9f7 9064 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
<> 144:ef7eb2e8f9f7 9065 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
<> 144:ef7eb2e8f9f7 9066 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
<> 144:ef7eb2e8f9f7 9067 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9068 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9069
<> 144:ef7eb2e8f9f7 9070 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
<> 144:ef7eb2e8f9f7 9071 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
<> 144:ef7eb2e8f9f7 9072 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
<> 144:ef7eb2e8f9f7 9073 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9074 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9075
<> 144:ef7eb2e8f9f7 9076 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
<> 144:ef7eb2e8f9f7 9077 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
<> 144:ef7eb2e8f9f7 9078 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
<> 144:ef7eb2e8f9f7 9079 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9080 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9081
<> 144:ef7eb2e8f9f7 9082 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
<> 144:ef7eb2e8f9f7 9083 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
<> 144:ef7eb2e8f9f7 9084 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
<> 144:ef7eb2e8f9f7 9085 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9086 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9087
<> 144:ef7eb2e8f9f7 9088 /* Bit 3 : Reset from CPU lock-up detected */
<> 144:ef7eb2e8f9f7 9089 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
<> 144:ef7eb2e8f9f7 9090 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
<> 144:ef7eb2e8f9f7 9091 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9092 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9093
<> 144:ef7eb2e8f9f7 9094 /* Bit 2 : Reset from soft reset detected */
<> 144:ef7eb2e8f9f7 9095 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
<> 144:ef7eb2e8f9f7 9096 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
<> 144:ef7eb2e8f9f7 9097 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9098 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9099
<> 144:ef7eb2e8f9f7 9100 /* Bit 1 : Reset from watchdog detected */
<> 144:ef7eb2e8f9f7 9101 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
<> 144:ef7eb2e8f9f7 9102 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
<> 144:ef7eb2e8f9f7 9103 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9104 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9105
<> 144:ef7eb2e8f9f7 9106 /* Bit 0 : Reset from pin-reset detected */
<> 144:ef7eb2e8f9f7 9107 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
<> 144:ef7eb2e8f9f7 9108 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
<> 144:ef7eb2e8f9f7 9109 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
<> 144:ef7eb2e8f9f7 9110 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
<> 144:ef7eb2e8f9f7 9111
<> 144:ef7eb2e8f9f7 9112 /* Register: POWER_RAMSTATUS */
<> 144:ef7eb2e8f9f7 9113 /* Description: Deprecated register - RAM status register */
<> 144:ef7eb2e8f9f7 9114
<> 144:ef7eb2e8f9f7 9115 /* Bit 3 : RAM block 3 is on or off/powering up */
<> 144:ef7eb2e8f9f7 9116 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
<> 144:ef7eb2e8f9f7 9117 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
<> 144:ef7eb2e8f9f7 9118 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9119 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9120
<> 144:ef7eb2e8f9f7 9121 /* Bit 2 : RAM block 2 is on or off/powering up */
<> 144:ef7eb2e8f9f7 9122 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
<> 144:ef7eb2e8f9f7 9123 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
<> 144:ef7eb2e8f9f7 9124 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9125 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9126
<> 144:ef7eb2e8f9f7 9127 /* Bit 1 : RAM block 1 is on or off/powering up */
<> 144:ef7eb2e8f9f7 9128 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
<> 144:ef7eb2e8f9f7 9129 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
<> 144:ef7eb2e8f9f7 9130 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9131 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9132
<> 144:ef7eb2e8f9f7 9133 /* Bit 0 : RAM block 0 is on or off/powering up */
<> 144:ef7eb2e8f9f7 9134 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
<> 144:ef7eb2e8f9f7 9135 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
<> 144:ef7eb2e8f9f7 9136 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9137 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9138
<> 144:ef7eb2e8f9f7 9139 /* Register: POWER_SYSTEMOFF */
<> 144:ef7eb2e8f9f7 9140 /* Description: System OFF register */
<> 144:ef7eb2e8f9f7 9141
<> 144:ef7eb2e8f9f7 9142 /* Bit 0 : Enable System OFF mode */
<> 144:ef7eb2e8f9f7 9143 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
<> 144:ef7eb2e8f9f7 9144 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
<> 144:ef7eb2e8f9f7 9145 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
<> 144:ef7eb2e8f9f7 9146
<> 144:ef7eb2e8f9f7 9147 /* Register: POWER_POFCON */
<> 144:ef7eb2e8f9f7 9148 /* Description: Power failure comparator configuration */
<> 144:ef7eb2e8f9f7 9149
<> 144:ef7eb2e8f9f7 9150 /* Bits 4..1 : Power failure comparator threshold setting */
<> 144:ef7eb2e8f9f7 9151 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
<> 144:ef7eb2e8f9f7 9152 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
<> 144:ef7eb2e8f9f7 9153 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
<> 144:ef7eb2e8f9f7 9154 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
<> 144:ef7eb2e8f9f7 9155 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
<> 144:ef7eb2e8f9f7 9156 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
<> 144:ef7eb2e8f9f7 9157 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
<> 144:ef7eb2e8f9f7 9158 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
<> 144:ef7eb2e8f9f7 9159 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
<> 144:ef7eb2e8f9f7 9160 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
<> 144:ef7eb2e8f9f7 9161 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
<> 144:ef7eb2e8f9f7 9162 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
<> 144:ef7eb2e8f9f7 9163 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
<> 144:ef7eb2e8f9f7 9164 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
<> 144:ef7eb2e8f9f7 9165
<> 144:ef7eb2e8f9f7 9166 /* Bit 0 : Enable or disable power failure comparator */
<> 144:ef7eb2e8f9f7 9167 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
<> 144:ef7eb2e8f9f7 9168 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
<> 144:ef7eb2e8f9f7 9169 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 9170 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 9171
<> 144:ef7eb2e8f9f7 9172 /* Register: POWER_GPREGRET */
<> 144:ef7eb2e8f9f7 9173 /* Description: General purpose retention register */
<> 144:ef7eb2e8f9f7 9174
<> 144:ef7eb2e8f9f7 9175 /* Bits 7..0 : General purpose retention register */
<> 144:ef7eb2e8f9f7 9176 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
<> 144:ef7eb2e8f9f7 9177 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
<> 144:ef7eb2e8f9f7 9178
<> 144:ef7eb2e8f9f7 9179 /* Register: POWER_GPREGRET2 */
<> 144:ef7eb2e8f9f7 9180 /* Description: General purpose retention register */
<> 144:ef7eb2e8f9f7 9181
<> 144:ef7eb2e8f9f7 9182 /* Bits 7..0 : General purpose retention register */
<> 144:ef7eb2e8f9f7 9183 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
<> 144:ef7eb2e8f9f7 9184 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
<> 144:ef7eb2e8f9f7 9185
<> 144:ef7eb2e8f9f7 9186 /* Register: POWER_RAMON */
<> 144:ef7eb2e8f9f7 9187 /* Description: Deprecated register - RAM on/off register (this register is retained) */
<> 144:ef7eb2e8f9f7 9188
<> 144:ef7eb2e8f9f7 9189 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
<> 144:ef7eb2e8f9f7 9190 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
<> 144:ef7eb2e8f9f7 9191 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
<> 144:ef7eb2e8f9f7 9192 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9193 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9194
<> 144:ef7eb2e8f9f7 9195 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
<> 144:ef7eb2e8f9f7 9196 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
<> 144:ef7eb2e8f9f7 9197 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
<> 144:ef7eb2e8f9f7 9198 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9199 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9200
<> 144:ef7eb2e8f9f7 9201 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
<> 144:ef7eb2e8f9f7 9202 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
<> 144:ef7eb2e8f9f7 9203 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
<> 144:ef7eb2e8f9f7 9204 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9205 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9206
<> 144:ef7eb2e8f9f7 9207 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
<> 144:ef7eb2e8f9f7 9208 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
<> 144:ef7eb2e8f9f7 9209 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
<> 144:ef7eb2e8f9f7 9210 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9211 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9212
<> 144:ef7eb2e8f9f7 9213 /* Register: POWER_RAMONB */
<> 144:ef7eb2e8f9f7 9214 /* Description: Deprecated register - RAM on/off register (this register is retained) */
<> 144:ef7eb2e8f9f7 9215
<> 144:ef7eb2e8f9f7 9216 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
<> 144:ef7eb2e8f9f7 9217 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
<> 144:ef7eb2e8f9f7 9218 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
<> 144:ef7eb2e8f9f7 9219 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9220 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9221
<> 144:ef7eb2e8f9f7 9222 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
<> 144:ef7eb2e8f9f7 9223 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
<> 144:ef7eb2e8f9f7 9224 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
<> 144:ef7eb2e8f9f7 9225 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9226 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9227
<> 144:ef7eb2e8f9f7 9228 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
<> 144:ef7eb2e8f9f7 9229 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
<> 144:ef7eb2e8f9f7 9230 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
<> 144:ef7eb2e8f9f7 9231 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9232 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9233
<> 144:ef7eb2e8f9f7 9234 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
<> 144:ef7eb2e8f9f7 9235 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
<> 144:ef7eb2e8f9f7 9236 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
<> 144:ef7eb2e8f9f7 9237 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9238 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9239
<> 144:ef7eb2e8f9f7 9240 /* Register: POWER_DCDCEN */
<> 144:ef7eb2e8f9f7 9241 /* Description: DC/DC enable register */
<> 144:ef7eb2e8f9f7 9242
<> 144:ef7eb2e8f9f7 9243 /* Bit 0 : Enable or disable DC/DC converter */
<> 144:ef7eb2e8f9f7 9244 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
<> 144:ef7eb2e8f9f7 9245 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
<> 144:ef7eb2e8f9f7 9246 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 9247 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 9248
<> 144:ef7eb2e8f9f7 9249 /* Register: POWER_RAM_POWER */
<> 144:ef7eb2e8f9f7 9250 /* Description: Description cluster[0]: RAM0 power control register */
<> 144:ef7eb2e8f9f7 9251
<> 144:ef7eb2e8f9f7 9252 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
<> 144:ef7eb2e8f9f7 9253 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
<> 144:ef7eb2e8f9f7 9254 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
<> 144:ef7eb2e8f9f7 9255 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9256 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9257
<> 144:ef7eb2e8f9f7 9258 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
<> 144:ef7eb2e8f9f7 9259 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
<> 144:ef7eb2e8f9f7 9260 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
<> 144:ef7eb2e8f9f7 9261 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9262 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9263
<> 144:ef7eb2e8f9f7 9264 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
<> 144:ef7eb2e8f9f7 9265 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
<> 144:ef7eb2e8f9f7 9266 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
<> 144:ef7eb2e8f9f7 9267 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9268 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9269
<> 144:ef7eb2e8f9f7 9270 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
<> 144:ef7eb2e8f9f7 9271 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
<> 144:ef7eb2e8f9f7 9272 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
<> 144:ef7eb2e8f9f7 9273 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9274 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9275
<> 144:ef7eb2e8f9f7 9276 /* Register: POWER_RAM_POWERSET */
<> 144:ef7eb2e8f9f7 9277 /* Description: Description cluster[0]: RAM0 power control set register */
<> 144:ef7eb2e8f9f7 9278
<> 144:ef7eb2e8f9f7 9279 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
<> 144:ef7eb2e8f9f7 9280 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
<> 144:ef7eb2e8f9f7 9281 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
<> 144:ef7eb2e8f9f7 9282 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9283
<> 144:ef7eb2e8f9f7 9284 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
<> 144:ef7eb2e8f9f7 9285 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
<> 144:ef7eb2e8f9f7 9286 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
<> 144:ef7eb2e8f9f7 9287 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9288
<> 144:ef7eb2e8f9f7 9289 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
<> 144:ef7eb2e8f9f7 9290 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
<> 144:ef7eb2e8f9f7 9291 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
<> 144:ef7eb2e8f9f7 9292 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9293
<> 144:ef7eb2e8f9f7 9294 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
<> 144:ef7eb2e8f9f7 9295 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
<> 144:ef7eb2e8f9f7 9296 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
<> 144:ef7eb2e8f9f7 9297 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
<> 144:ef7eb2e8f9f7 9298
<> 144:ef7eb2e8f9f7 9299 /* Register: POWER_RAM_POWERCLR */
<> 144:ef7eb2e8f9f7 9300 /* Description: Description cluster[0]: RAM0 power control clear register */
<> 144:ef7eb2e8f9f7 9301
<> 144:ef7eb2e8f9f7 9302 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
<> 144:ef7eb2e8f9f7 9303 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
<> 144:ef7eb2e8f9f7 9304 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
<> 144:ef7eb2e8f9f7 9305 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9306
<> 144:ef7eb2e8f9f7 9307 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
<> 144:ef7eb2e8f9f7 9308 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
<> 144:ef7eb2e8f9f7 9309 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
<> 144:ef7eb2e8f9f7 9310 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9311
<> 144:ef7eb2e8f9f7 9312 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
<> 144:ef7eb2e8f9f7 9313 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
<> 144:ef7eb2e8f9f7 9314 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
<> 144:ef7eb2e8f9f7 9315 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9316
<> 144:ef7eb2e8f9f7 9317 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
<> 144:ef7eb2e8f9f7 9318 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
<> 144:ef7eb2e8f9f7 9319 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
<> 144:ef7eb2e8f9f7 9320 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
<> 144:ef7eb2e8f9f7 9321
<> 144:ef7eb2e8f9f7 9322
<> 144:ef7eb2e8f9f7 9323 /* Peripheral: PPI */
<> 144:ef7eb2e8f9f7 9324 /* Description: Programmable Peripheral Interconnect */
<> 144:ef7eb2e8f9f7 9325
<> 144:ef7eb2e8f9f7 9326 /* Register: PPI_CHEN */
<> 144:ef7eb2e8f9f7 9327 /* Description: Channel enable register */
<> 144:ef7eb2e8f9f7 9328
<> 144:ef7eb2e8f9f7 9329 /* Bit 31 : Enable or disable channel 31 */
<> 144:ef7eb2e8f9f7 9330 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
<> 144:ef7eb2e8f9f7 9331 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
<> 144:ef7eb2e8f9f7 9332 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9333 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9334
<> 144:ef7eb2e8f9f7 9335 /* Bit 30 : Enable or disable channel 30 */
<> 144:ef7eb2e8f9f7 9336 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
<> 144:ef7eb2e8f9f7 9337 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
<> 144:ef7eb2e8f9f7 9338 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9339 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9340
<> 144:ef7eb2e8f9f7 9341 /* Bit 29 : Enable or disable channel 29 */
<> 144:ef7eb2e8f9f7 9342 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
<> 144:ef7eb2e8f9f7 9343 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
<> 144:ef7eb2e8f9f7 9344 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9345 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9346
<> 144:ef7eb2e8f9f7 9347 /* Bit 28 : Enable or disable channel 28 */
<> 144:ef7eb2e8f9f7 9348 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
<> 144:ef7eb2e8f9f7 9349 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
<> 144:ef7eb2e8f9f7 9350 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9351 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9352
<> 144:ef7eb2e8f9f7 9353 /* Bit 27 : Enable or disable channel 27 */
<> 144:ef7eb2e8f9f7 9354 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
<> 144:ef7eb2e8f9f7 9355 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
<> 144:ef7eb2e8f9f7 9356 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9357 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9358
<> 144:ef7eb2e8f9f7 9359 /* Bit 26 : Enable or disable channel 26 */
<> 144:ef7eb2e8f9f7 9360 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
<> 144:ef7eb2e8f9f7 9361 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
<> 144:ef7eb2e8f9f7 9362 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9363 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9364
<> 144:ef7eb2e8f9f7 9365 /* Bit 25 : Enable or disable channel 25 */
<> 144:ef7eb2e8f9f7 9366 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
<> 144:ef7eb2e8f9f7 9367 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
<> 144:ef7eb2e8f9f7 9368 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9369 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9370
<> 144:ef7eb2e8f9f7 9371 /* Bit 24 : Enable or disable channel 24 */
<> 144:ef7eb2e8f9f7 9372 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
<> 144:ef7eb2e8f9f7 9373 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
<> 144:ef7eb2e8f9f7 9374 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9375 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9376
<> 144:ef7eb2e8f9f7 9377 /* Bit 23 : Enable or disable channel 23 */
<> 144:ef7eb2e8f9f7 9378 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
<> 144:ef7eb2e8f9f7 9379 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
<> 144:ef7eb2e8f9f7 9380 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9381 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9382
<> 144:ef7eb2e8f9f7 9383 /* Bit 22 : Enable or disable channel 22 */
<> 144:ef7eb2e8f9f7 9384 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
<> 144:ef7eb2e8f9f7 9385 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
<> 144:ef7eb2e8f9f7 9386 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9387 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9388
<> 144:ef7eb2e8f9f7 9389 /* Bit 21 : Enable or disable channel 21 */
<> 144:ef7eb2e8f9f7 9390 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
<> 144:ef7eb2e8f9f7 9391 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
<> 144:ef7eb2e8f9f7 9392 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9393 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9394
<> 144:ef7eb2e8f9f7 9395 /* Bit 20 : Enable or disable channel 20 */
<> 144:ef7eb2e8f9f7 9396 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
<> 144:ef7eb2e8f9f7 9397 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
<> 144:ef7eb2e8f9f7 9398 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9399 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9400
<> 144:ef7eb2e8f9f7 9401 /* Bit 19 : Enable or disable channel 19 */
<> 144:ef7eb2e8f9f7 9402 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
<> 144:ef7eb2e8f9f7 9403 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
<> 144:ef7eb2e8f9f7 9404 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9405 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9406
<> 144:ef7eb2e8f9f7 9407 /* Bit 18 : Enable or disable channel 18 */
<> 144:ef7eb2e8f9f7 9408 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
<> 144:ef7eb2e8f9f7 9409 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
<> 144:ef7eb2e8f9f7 9410 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9411 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9412
<> 144:ef7eb2e8f9f7 9413 /* Bit 17 : Enable or disable channel 17 */
<> 144:ef7eb2e8f9f7 9414 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
<> 144:ef7eb2e8f9f7 9415 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
<> 144:ef7eb2e8f9f7 9416 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9417 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9418
<> 144:ef7eb2e8f9f7 9419 /* Bit 16 : Enable or disable channel 16 */
<> 144:ef7eb2e8f9f7 9420 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
<> 144:ef7eb2e8f9f7 9421 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
<> 144:ef7eb2e8f9f7 9422 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9423 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9424
<> 144:ef7eb2e8f9f7 9425 /* Bit 15 : Enable or disable channel 15 */
<> 144:ef7eb2e8f9f7 9426 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
<> 144:ef7eb2e8f9f7 9427 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
<> 144:ef7eb2e8f9f7 9428 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9429 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9430
<> 144:ef7eb2e8f9f7 9431 /* Bit 14 : Enable or disable channel 14 */
<> 144:ef7eb2e8f9f7 9432 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
<> 144:ef7eb2e8f9f7 9433 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
<> 144:ef7eb2e8f9f7 9434 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9435 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9436
<> 144:ef7eb2e8f9f7 9437 /* Bit 13 : Enable or disable channel 13 */
<> 144:ef7eb2e8f9f7 9438 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
<> 144:ef7eb2e8f9f7 9439 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
<> 144:ef7eb2e8f9f7 9440 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9441 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9442
<> 144:ef7eb2e8f9f7 9443 /* Bit 12 : Enable or disable channel 12 */
<> 144:ef7eb2e8f9f7 9444 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
<> 144:ef7eb2e8f9f7 9445 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
<> 144:ef7eb2e8f9f7 9446 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9447 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9448
<> 144:ef7eb2e8f9f7 9449 /* Bit 11 : Enable or disable channel 11 */
<> 144:ef7eb2e8f9f7 9450 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
<> 144:ef7eb2e8f9f7 9451 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
<> 144:ef7eb2e8f9f7 9452 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9453 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9454
<> 144:ef7eb2e8f9f7 9455 /* Bit 10 : Enable or disable channel 10 */
<> 144:ef7eb2e8f9f7 9456 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
<> 144:ef7eb2e8f9f7 9457 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
<> 144:ef7eb2e8f9f7 9458 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9459 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9460
<> 144:ef7eb2e8f9f7 9461 /* Bit 9 : Enable or disable channel 9 */
<> 144:ef7eb2e8f9f7 9462 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
<> 144:ef7eb2e8f9f7 9463 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
<> 144:ef7eb2e8f9f7 9464 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9465 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9466
<> 144:ef7eb2e8f9f7 9467 /* Bit 8 : Enable or disable channel 8 */
<> 144:ef7eb2e8f9f7 9468 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
<> 144:ef7eb2e8f9f7 9469 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
<> 144:ef7eb2e8f9f7 9470 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9471 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9472
<> 144:ef7eb2e8f9f7 9473 /* Bit 7 : Enable or disable channel 7 */
<> 144:ef7eb2e8f9f7 9474 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
<> 144:ef7eb2e8f9f7 9475 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
<> 144:ef7eb2e8f9f7 9476 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9477 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9478
<> 144:ef7eb2e8f9f7 9479 /* Bit 6 : Enable or disable channel 6 */
<> 144:ef7eb2e8f9f7 9480 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
<> 144:ef7eb2e8f9f7 9481 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
<> 144:ef7eb2e8f9f7 9482 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9483 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9484
<> 144:ef7eb2e8f9f7 9485 /* Bit 5 : Enable or disable channel 5 */
<> 144:ef7eb2e8f9f7 9486 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
<> 144:ef7eb2e8f9f7 9487 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
<> 144:ef7eb2e8f9f7 9488 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9489 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9490
<> 144:ef7eb2e8f9f7 9491 /* Bit 4 : Enable or disable channel 4 */
<> 144:ef7eb2e8f9f7 9492 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
<> 144:ef7eb2e8f9f7 9493 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
<> 144:ef7eb2e8f9f7 9494 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9495 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9496
<> 144:ef7eb2e8f9f7 9497 /* Bit 3 : Enable or disable channel 3 */
<> 144:ef7eb2e8f9f7 9498 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
<> 144:ef7eb2e8f9f7 9499 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
<> 144:ef7eb2e8f9f7 9500 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9501 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9502
<> 144:ef7eb2e8f9f7 9503 /* Bit 2 : Enable or disable channel 2 */
<> 144:ef7eb2e8f9f7 9504 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
<> 144:ef7eb2e8f9f7 9505 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
<> 144:ef7eb2e8f9f7 9506 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9507 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9508
<> 144:ef7eb2e8f9f7 9509 /* Bit 1 : Enable or disable channel 1 */
<> 144:ef7eb2e8f9f7 9510 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
<> 144:ef7eb2e8f9f7 9511 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
<> 144:ef7eb2e8f9f7 9512 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9513 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9514
<> 144:ef7eb2e8f9f7 9515 /* Bit 0 : Enable or disable channel 0 */
<> 144:ef7eb2e8f9f7 9516 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
<> 144:ef7eb2e8f9f7 9517 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
<> 144:ef7eb2e8f9f7 9518 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
<> 144:ef7eb2e8f9f7 9519 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
<> 144:ef7eb2e8f9f7 9520
<> 144:ef7eb2e8f9f7 9521 /* Register: PPI_CHENSET */
<> 144:ef7eb2e8f9f7 9522 /* Description: Channel enable set register */
<> 144:ef7eb2e8f9f7 9523
<> 144:ef7eb2e8f9f7 9524 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9525 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
<> 144:ef7eb2e8f9f7 9526 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
<> 144:ef7eb2e8f9f7 9527 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9528 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9529 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9530
<> 144:ef7eb2e8f9f7 9531 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9532 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
<> 144:ef7eb2e8f9f7 9533 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
<> 144:ef7eb2e8f9f7 9534 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9535 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9536 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9537
<> 144:ef7eb2e8f9f7 9538 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9539 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
<> 144:ef7eb2e8f9f7 9540 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
<> 144:ef7eb2e8f9f7 9541 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9542 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9543 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9544
<> 144:ef7eb2e8f9f7 9545 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9546 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
<> 144:ef7eb2e8f9f7 9547 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
<> 144:ef7eb2e8f9f7 9548 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9549 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9550 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9551
<> 144:ef7eb2e8f9f7 9552 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9553 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
<> 144:ef7eb2e8f9f7 9554 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
<> 144:ef7eb2e8f9f7 9555 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9556 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9557 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9558
<> 144:ef7eb2e8f9f7 9559 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9560 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
<> 144:ef7eb2e8f9f7 9561 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
<> 144:ef7eb2e8f9f7 9562 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9563 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9564 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9565
<> 144:ef7eb2e8f9f7 9566 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9567 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
<> 144:ef7eb2e8f9f7 9568 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
<> 144:ef7eb2e8f9f7 9569 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9570 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9571 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9572
<> 144:ef7eb2e8f9f7 9573 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9574 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
<> 144:ef7eb2e8f9f7 9575 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
<> 144:ef7eb2e8f9f7 9576 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9577 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9578 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9579
<> 144:ef7eb2e8f9f7 9580 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9581 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
<> 144:ef7eb2e8f9f7 9582 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
<> 144:ef7eb2e8f9f7 9583 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9584 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9585 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9586
<> 144:ef7eb2e8f9f7 9587 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9588 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
<> 144:ef7eb2e8f9f7 9589 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
<> 144:ef7eb2e8f9f7 9590 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9591 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9592 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9593
<> 144:ef7eb2e8f9f7 9594 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9595 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
<> 144:ef7eb2e8f9f7 9596 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
<> 144:ef7eb2e8f9f7 9597 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9598 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9599 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9600
<> 144:ef7eb2e8f9f7 9601 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9602 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
<> 144:ef7eb2e8f9f7 9603 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
<> 144:ef7eb2e8f9f7 9604 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9605 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9606 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9607
<> 144:ef7eb2e8f9f7 9608 /* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9609 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
<> 144:ef7eb2e8f9f7 9610 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
<> 144:ef7eb2e8f9f7 9611 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9612 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9613 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9614
<> 144:ef7eb2e8f9f7 9615 /* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9616 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
<> 144:ef7eb2e8f9f7 9617 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
<> 144:ef7eb2e8f9f7 9618 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9619 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9620 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9621
<> 144:ef7eb2e8f9f7 9622 /* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9623 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
<> 144:ef7eb2e8f9f7 9624 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
<> 144:ef7eb2e8f9f7 9625 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9626 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9627 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9628
<> 144:ef7eb2e8f9f7 9629 /* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9630 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
<> 144:ef7eb2e8f9f7 9631 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
<> 144:ef7eb2e8f9f7 9632 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9633 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9634 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9635
<> 144:ef7eb2e8f9f7 9636 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9637 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
<> 144:ef7eb2e8f9f7 9638 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
<> 144:ef7eb2e8f9f7 9639 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9640 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9641 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9642
<> 144:ef7eb2e8f9f7 9643 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9644 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
<> 144:ef7eb2e8f9f7 9645 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
<> 144:ef7eb2e8f9f7 9646 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9647 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9648 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9649
<> 144:ef7eb2e8f9f7 9650 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9651 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
<> 144:ef7eb2e8f9f7 9652 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
<> 144:ef7eb2e8f9f7 9653 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9654 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9655 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9656
<> 144:ef7eb2e8f9f7 9657 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9658 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
<> 144:ef7eb2e8f9f7 9659 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
<> 144:ef7eb2e8f9f7 9660 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9661 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9662 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9663
<> 144:ef7eb2e8f9f7 9664 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9665 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
<> 144:ef7eb2e8f9f7 9666 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
<> 144:ef7eb2e8f9f7 9667 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9668 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9669 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9670
<> 144:ef7eb2e8f9f7 9671 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9672 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
<> 144:ef7eb2e8f9f7 9673 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
<> 144:ef7eb2e8f9f7 9674 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9675 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9676 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9677
<> 144:ef7eb2e8f9f7 9678 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9679 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
<> 144:ef7eb2e8f9f7 9680 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
<> 144:ef7eb2e8f9f7 9681 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9682 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9683 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9684
<> 144:ef7eb2e8f9f7 9685 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9686 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
<> 144:ef7eb2e8f9f7 9687 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
<> 144:ef7eb2e8f9f7 9688 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9689 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9690 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9691
<> 144:ef7eb2e8f9f7 9692 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9693 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
<> 144:ef7eb2e8f9f7 9694 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
<> 144:ef7eb2e8f9f7 9695 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9696 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9697 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9698
<> 144:ef7eb2e8f9f7 9699 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9700 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
<> 144:ef7eb2e8f9f7 9701 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
<> 144:ef7eb2e8f9f7 9702 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9703 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9704 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9705
<> 144:ef7eb2e8f9f7 9706 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9707 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
<> 144:ef7eb2e8f9f7 9708 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
<> 144:ef7eb2e8f9f7 9709 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9710 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9711 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9712
<> 144:ef7eb2e8f9f7 9713 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9714 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
<> 144:ef7eb2e8f9f7 9715 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
<> 144:ef7eb2e8f9f7 9716 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9717 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9718 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9719
<> 144:ef7eb2e8f9f7 9720 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9721 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
<> 144:ef7eb2e8f9f7 9722 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
<> 144:ef7eb2e8f9f7 9723 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9724 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9725 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9726
<> 144:ef7eb2e8f9f7 9727 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9728 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
<> 144:ef7eb2e8f9f7 9729 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
<> 144:ef7eb2e8f9f7 9730 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9731 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9732 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9733
<> 144:ef7eb2e8f9f7 9734 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9735 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
<> 144:ef7eb2e8f9f7 9736 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
<> 144:ef7eb2e8f9f7 9737 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9738 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9739 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9740
<> 144:ef7eb2e8f9f7 9741 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9742 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
<> 144:ef7eb2e8f9f7 9743 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
<> 144:ef7eb2e8f9f7 9744 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9745 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9746 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
<> 144:ef7eb2e8f9f7 9747
<> 144:ef7eb2e8f9f7 9748 /* Register: PPI_CHENCLR */
<> 144:ef7eb2e8f9f7 9749 /* Description: Channel enable clear register */
<> 144:ef7eb2e8f9f7 9750
<> 144:ef7eb2e8f9f7 9751 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9752 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
<> 144:ef7eb2e8f9f7 9753 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
<> 144:ef7eb2e8f9f7 9754 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9755 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9756 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9757
<> 144:ef7eb2e8f9f7 9758 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9759 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
<> 144:ef7eb2e8f9f7 9760 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
<> 144:ef7eb2e8f9f7 9761 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9762 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9763 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9764
<> 144:ef7eb2e8f9f7 9765 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9766 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
<> 144:ef7eb2e8f9f7 9767 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
<> 144:ef7eb2e8f9f7 9768 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9769 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9770 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9771
<> 144:ef7eb2e8f9f7 9772 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9773 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
<> 144:ef7eb2e8f9f7 9774 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
<> 144:ef7eb2e8f9f7 9775 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9776 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9777 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9778
<> 144:ef7eb2e8f9f7 9779 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9780 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
<> 144:ef7eb2e8f9f7 9781 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
<> 144:ef7eb2e8f9f7 9782 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9783 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9784 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9785
<> 144:ef7eb2e8f9f7 9786 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9787 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
<> 144:ef7eb2e8f9f7 9788 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
<> 144:ef7eb2e8f9f7 9789 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9790 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9791 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9792
<> 144:ef7eb2e8f9f7 9793 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9794 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
<> 144:ef7eb2e8f9f7 9795 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
<> 144:ef7eb2e8f9f7 9796 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9797 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9798 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9799
<> 144:ef7eb2e8f9f7 9800 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9801 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
<> 144:ef7eb2e8f9f7 9802 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
<> 144:ef7eb2e8f9f7 9803 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9804 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9805 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9806
<> 144:ef7eb2e8f9f7 9807 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9808 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
<> 144:ef7eb2e8f9f7 9809 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
<> 144:ef7eb2e8f9f7 9810 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9811 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9812 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9813
<> 144:ef7eb2e8f9f7 9814 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9815 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
<> 144:ef7eb2e8f9f7 9816 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
<> 144:ef7eb2e8f9f7 9817 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9818 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9819 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9820
<> 144:ef7eb2e8f9f7 9821 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9822 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
<> 144:ef7eb2e8f9f7 9823 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
<> 144:ef7eb2e8f9f7 9824 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9825 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9826 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9827
<> 144:ef7eb2e8f9f7 9828 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9829 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
<> 144:ef7eb2e8f9f7 9830 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
<> 144:ef7eb2e8f9f7 9831 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9832 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9833 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9834
<> 144:ef7eb2e8f9f7 9835 /* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9836 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
<> 144:ef7eb2e8f9f7 9837 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
<> 144:ef7eb2e8f9f7 9838 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9839 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9840 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9841
<> 144:ef7eb2e8f9f7 9842 /* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9843 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
<> 144:ef7eb2e8f9f7 9844 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
<> 144:ef7eb2e8f9f7 9845 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9846 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9847 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9848
<> 144:ef7eb2e8f9f7 9849 /* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9850 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
<> 144:ef7eb2e8f9f7 9851 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
<> 144:ef7eb2e8f9f7 9852 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9853 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9854 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9855
<> 144:ef7eb2e8f9f7 9856 /* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9857 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
<> 144:ef7eb2e8f9f7 9858 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
<> 144:ef7eb2e8f9f7 9859 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9860 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9861 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9862
<> 144:ef7eb2e8f9f7 9863 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9864 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
<> 144:ef7eb2e8f9f7 9865 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
<> 144:ef7eb2e8f9f7 9866 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9867 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9868 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9869
<> 144:ef7eb2e8f9f7 9870 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9871 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
<> 144:ef7eb2e8f9f7 9872 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
<> 144:ef7eb2e8f9f7 9873 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9874 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9875 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9876
<> 144:ef7eb2e8f9f7 9877 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9878 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
<> 144:ef7eb2e8f9f7 9879 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
<> 144:ef7eb2e8f9f7 9880 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9881 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9882 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9883
<> 144:ef7eb2e8f9f7 9884 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9885 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
<> 144:ef7eb2e8f9f7 9886 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
<> 144:ef7eb2e8f9f7 9887 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9888 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9889 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9890
<> 144:ef7eb2e8f9f7 9891 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9892 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
<> 144:ef7eb2e8f9f7 9893 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
<> 144:ef7eb2e8f9f7 9894 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9895 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9896 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9897
<> 144:ef7eb2e8f9f7 9898 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9899 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
<> 144:ef7eb2e8f9f7 9900 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
<> 144:ef7eb2e8f9f7 9901 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9902 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9903 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9904
<> 144:ef7eb2e8f9f7 9905 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9906 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
<> 144:ef7eb2e8f9f7 9907 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
<> 144:ef7eb2e8f9f7 9908 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9909 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9910 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9911
<> 144:ef7eb2e8f9f7 9912 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9913 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
<> 144:ef7eb2e8f9f7 9914 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
<> 144:ef7eb2e8f9f7 9915 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9916 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9917 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9918
<> 144:ef7eb2e8f9f7 9919 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9920 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
<> 144:ef7eb2e8f9f7 9921 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
<> 144:ef7eb2e8f9f7 9922 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9923 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9924 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9925
<> 144:ef7eb2e8f9f7 9926 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9927 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
<> 144:ef7eb2e8f9f7 9928 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
<> 144:ef7eb2e8f9f7 9929 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9930 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9931 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9932
<> 144:ef7eb2e8f9f7 9933 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9934 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
<> 144:ef7eb2e8f9f7 9935 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
<> 144:ef7eb2e8f9f7 9936 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9937 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9938 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9939
<> 144:ef7eb2e8f9f7 9940 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9941 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
<> 144:ef7eb2e8f9f7 9942 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
<> 144:ef7eb2e8f9f7 9943 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9944 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9945 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9946
<> 144:ef7eb2e8f9f7 9947 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9948 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
<> 144:ef7eb2e8f9f7 9949 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
<> 144:ef7eb2e8f9f7 9950 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9951 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9952 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9953
<> 144:ef7eb2e8f9f7 9954 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9955 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
<> 144:ef7eb2e8f9f7 9956 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
<> 144:ef7eb2e8f9f7 9957 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9958 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9959 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9960
<> 144:ef7eb2e8f9f7 9961 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9962 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
<> 144:ef7eb2e8f9f7 9963 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
<> 144:ef7eb2e8f9f7 9964 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9965 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9966 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9967
<> 144:ef7eb2e8f9f7 9968 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
<> 144:ef7eb2e8f9f7 9969 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
<> 144:ef7eb2e8f9f7 9970 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
<> 144:ef7eb2e8f9f7 9971 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
<> 144:ef7eb2e8f9f7 9972 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
<> 144:ef7eb2e8f9f7 9973 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
<> 144:ef7eb2e8f9f7 9974
<> 144:ef7eb2e8f9f7 9975 /* Register: PPI_CH_EEP */
<> 144:ef7eb2e8f9f7 9976 /* Description: Description cluster[0]: Channel 0 event end-point */
<> 144:ef7eb2e8f9f7 9977
<> 144:ef7eb2e8f9f7 9978 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
<> 144:ef7eb2e8f9f7 9979 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
<> 144:ef7eb2e8f9f7 9980 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
<> 144:ef7eb2e8f9f7 9981
<> 144:ef7eb2e8f9f7 9982 /* Register: PPI_CH_TEP */
<> 144:ef7eb2e8f9f7 9983 /* Description: Description cluster[0]: Channel 0 task end-point */
<> 144:ef7eb2e8f9f7 9984
<> 144:ef7eb2e8f9f7 9985 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
<> 144:ef7eb2e8f9f7 9986 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
<> 144:ef7eb2e8f9f7 9987 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
<> 144:ef7eb2e8f9f7 9988
<> 144:ef7eb2e8f9f7 9989 /* Register: PPI_CHG */
<> 144:ef7eb2e8f9f7 9990 /* Description: Description collection[0]: Channel group 0 */
<> 144:ef7eb2e8f9f7 9991
<> 144:ef7eb2e8f9f7 9992 /* Bit 31 : Include or exclude channel 31 */
<> 144:ef7eb2e8f9f7 9993 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
<> 144:ef7eb2e8f9f7 9994 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
<> 144:ef7eb2e8f9f7 9995 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 9996 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 9997
<> 144:ef7eb2e8f9f7 9998 /* Bit 30 : Include or exclude channel 30 */
<> 144:ef7eb2e8f9f7 9999 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
<> 144:ef7eb2e8f9f7 10000 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
<> 144:ef7eb2e8f9f7 10001 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10002 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10003
<> 144:ef7eb2e8f9f7 10004 /* Bit 29 : Include or exclude channel 29 */
<> 144:ef7eb2e8f9f7 10005 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
<> 144:ef7eb2e8f9f7 10006 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
<> 144:ef7eb2e8f9f7 10007 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10008 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10009
<> 144:ef7eb2e8f9f7 10010 /* Bit 28 : Include or exclude channel 28 */
<> 144:ef7eb2e8f9f7 10011 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
<> 144:ef7eb2e8f9f7 10012 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
<> 144:ef7eb2e8f9f7 10013 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10014 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10015
<> 144:ef7eb2e8f9f7 10016 /* Bit 27 : Include or exclude channel 27 */
<> 144:ef7eb2e8f9f7 10017 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
<> 144:ef7eb2e8f9f7 10018 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
<> 144:ef7eb2e8f9f7 10019 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10020 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10021
<> 144:ef7eb2e8f9f7 10022 /* Bit 26 : Include or exclude channel 26 */
<> 144:ef7eb2e8f9f7 10023 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
<> 144:ef7eb2e8f9f7 10024 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
<> 144:ef7eb2e8f9f7 10025 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10026 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10027
<> 144:ef7eb2e8f9f7 10028 /* Bit 25 : Include or exclude channel 25 */
<> 144:ef7eb2e8f9f7 10029 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
<> 144:ef7eb2e8f9f7 10030 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
<> 144:ef7eb2e8f9f7 10031 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10032 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10033
<> 144:ef7eb2e8f9f7 10034 /* Bit 24 : Include or exclude channel 24 */
<> 144:ef7eb2e8f9f7 10035 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
<> 144:ef7eb2e8f9f7 10036 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
<> 144:ef7eb2e8f9f7 10037 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10038 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10039
<> 144:ef7eb2e8f9f7 10040 /* Bit 23 : Include or exclude channel 23 */
<> 144:ef7eb2e8f9f7 10041 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
<> 144:ef7eb2e8f9f7 10042 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
<> 144:ef7eb2e8f9f7 10043 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10044 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10045
<> 144:ef7eb2e8f9f7 10046 /* Bit 22 : Include or exclude channel 22 */
<> 144:ef7eb2e8f9f7 10047 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
<> 144:ef7eb2e8f9f7 10048 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
<> 144:ef7eb2e8f9f7 10049 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10050 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10051
<> 144:ef7eb2e8f9f7 10052 /* Bit 21 : Include or exclude channel 21 */
<> 144:ef7eb2e8f9f7 10053 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
<> 144:ef7eb2e8f9f7 10054 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
<> 144:ef7eb2e8f9f7 10055 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10056 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10057
<> 144:ef7eb2e8f9f7 10058 /* Bit 20 : Include or exclude channel 20 */
<> 144:ef7eb2e8f9f7 10059 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
<> 144:ef7eb2e8f9f7 10060 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
<> 144:ef7eb2e8f9f7 10061 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10062 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10063
<> 144:ef7eb2e8f9f7 10064 /* Bit 19 : Include or exclude channel 19 */
<> 144:ef7eb2e8f9f7 10065 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
<> 144:ef7eb2e8f9f7 10066 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
<> 144:ef7eb2e8f9f7 10067 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10068 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10069
<> 144:ef7eb2e8f9f7 10070 /* Bit 18 : Include or exclude channel 18 */
<> 144:ef7eb2e8f9f7 10071 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
<> 144:ef7eb2e8f9f7 10072 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
<> 144:ef7eb2e8f9f7 10073 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10074 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10075
<> 144:ef7eb2e8f9f7 10076 /* Bit 17 : Include or exclude channel 17 */
<> 144:ef7eb2e8f9f7 10077 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
<> 144:ef7eb2e8f9f7 10078 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
<> 144:ef7eb2e8f9f7 10079 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10080 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10081
<> 144:ef7eb2e8f9f7 10082 /* Bit 16 : Include or exclude channel 16 */
<> 144:ef7eb2e8f9f7 10083 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
<> 144:ef7eb2e8f9f7 10084 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
<> 144:ef7eb2e8f9f7 10085 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10086 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10087
<> 144:ef7eb2e8f9f7 10088 /* Bit 15 : Include or exclude channel 15 */
<> 144:ef7eb2e8f9f7 10089 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
<> 144:ef7eb2e8f9f7 10090 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
<> 144:ef7eb2e8f9f7 10091 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10092 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10093
<> 144:ef7eb2e8f9f7 10094 /* Bit 14 : Include or exclude channel 14 */
<> 144:ef7eb2e8f9f7 10095 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
<> 144:ef7eb2e8f9f7 10096 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
<> 144:ef7eb2e8f9f7 10097 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10098 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10099
<> 144:ef7eb2e8f9f7 10100 /* Bit 13 : Include or exclude channel 13 */
<> 144:ef7eb2e8f9f7 10101 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
<> 144:ef7eb2e8f9f7 10102 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
<> 144:ef7eb2e8f9f7 10103 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10104 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10105
<> 144:ef7eb2e8f9f7 10106 /* Bit 12 : Include or exclude channel 12 */
<> 144:ef7eb2e8f9f7 10107 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
<> 144:ef7eb2e8f9f7 10108 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
<> 144:ef7eb2e8f9f7 10109 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10110 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10111
<> 144:ef7eb2e8f9f7 10112 /* Bit 11 : Include or exclude channel 11 */
<> 144:ef7eb2e8f9f7 10113 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
<> 144:ef7eb2e8f9f7 10114 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
<> 144:ef7eb2e8f9f7 10115 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10116 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10117
<> 144:ef7eb2e8f9f7 10118 /* Bit 10 : Include or exclude channel 10 */
<> 144:ef7eb2e8f9f7 10119 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
<> 144:ef7eb2e8f9f7 10120 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
<> 144:ef7eb2e8f9f7 10121 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10122 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10123
<> 144:ef7eb2e8f9f7 10124 /* Bit 9 : Include or exclude channel 9 */
<> 144:ef7eb2e8f9f7 10125 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
<> 144:ef7eb2e8f9f7 10126 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
<> 144:ef7eb2e8f9f7 10127 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10128 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10129
<> 144:ef7eb2e8f9f7 10130 /* Bit 8 : Include or exclude channel 8 */
<> 144:ef7eb2e8f9f7 10131 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
<> 144:ef7eb2e8f9f7 10132 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
<> 144:ef7eb2e8f9f7 10133 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10134 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10135
<> 144:ef7eb2e8f9f7 10136 /* Bit 7 : Include or exclude channel 7 */
<> 144:ef7eb2e8f9f7 10137 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
<> 144:ef7eb2e8f9f7 10138 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
<> 144:ef7eb2e8f9f7 10139 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10140 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10141
<> 144:ef7eb2e8f9f7 10142 /* Bit 6 : Include or exclude channel 6 */
<> 144:ef7eb2e8f9f7 10143 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
<> 144:ef7eb2e8f9f7 10144 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
<> 144:ef7eb2e8f9f7 10145 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10146 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10147
<> 144:ef7eb2e8f9f7 10148 /* Bit 5 : Include or exclude channel 5 */
<> 144:ef7eb2e8f9f7 10149 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
<> 144:ef7eb2e8f9f7 10150 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
<> 144:ef7eb2e8f9f7 10151 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10152 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10153
<> 144:ef7eb2e8f9f7 10154 /* Bit 4 : Include or exclude channel 4 */
<> 144:ef7eb2e8f9f7 10155 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
<> 144:ef7eb2e8f9f7 10156 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
<> 144:ef7eb2e8f9f7 10157 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10158 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10159
<> 144:ef7eb2e8f9f7 10160 /* Bit 3 : Include or exclude channel 3 */
<> 144:ef7eb2e8f9f7 10161 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
<> 144:ef7eb2e8f9f7 10162 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
<> 144:ef7eb2e8f9f7 10163 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10164 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10165
<> 144:ef7eb2e8f9f7 10166 /* Bit 2 : Include or exclude channel 2 */
<> 144:ef7eb2e8f9f7 10167 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
<> 144:ef7eb2e8f9f7 10168 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
<> 144:ef7eb2e8f9f7 10169 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10170 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10171
<> 144:ef7eb2e8f9f7 10172 /* Bit 1 : Include or exclude channel 1 */
<> 144:ef7eb2e8f9f7 10173 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
<> 144:ef7eb2e8f9f7 10174 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
<> 144:ef7eb2e8f9f7 10175 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10176 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10177
<> 144:ef7eb2e8f9f7 10178 /* Bit 0 : Include or exclude channel 0 */
<> 144:ef7eb2e8f9f7 10179 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
<> 144:ef7eb2e8f9f7 10180 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
<> 144:ef7eb2e8f9f7 10181 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
<> 144:ef7eb2e8f9f7 10182 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
<> 144:ef7eb2e8f9f7 10183
<> 144:ef7eb2e8f9f7 10184 /* Register: PPI_FORK_TEP */
<> 144:ef7eb2e8f9f7 10185 /* Description: Description cluster[0]: Channel 0 task end-point */
<> 144:ef7eb2e8f9f7 10186
<> 144:ef7eb2e8f9f7 10187 /* Bits 31..0 : Pointer to task register */
<> 144:ef7eb2e8f9f7 10188 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
<> 144:ef7eb2e8f9f7 10189 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
<> 144:ef7eb2e8f9f7 10190
<> 144:ef7eb2e8f9f7 10191
<> 144:ef7eb2e8f9f7 10192 /* Peripheral: PWM */
<> 144:ef7eb2e8f9f7 10193 /* Description: Pulse Width Modulation Unit 0 */
<> 144:ef7eb2e8f9f7 10194
<> 144:ef7eb2e8f9f7 10195 /* Register: PWM_SHORTS */
<> 144:ef7eb2e8f9f7 10196 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 10197
<> 144:ef7eb2e8f9f7 10198 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
<> 144:ef7eb2e8f9f7 10199 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
<> 144:ef7eb2e8f9f7 10200 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
<> 144:ef7eb2e8f9f7 10201 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10202 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10203
<> 144:ef7eb2e8f9f7 10204 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
<> 144:ef7eb2e8f9f7 10205 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
<> 144:ef7eb2e8f9f7 10206 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
<> 144:ef7eb2e8f9f7 10207 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10208 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10209
<> 144:ef7eb2e8f9f7 10210 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
<> 144:ef7eb2e8f9f7 10211 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
<> 144:ef7eb2e8f9f7 10212 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
<> 144:ef7eb2e8f9f7 10213 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10214 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10215
<> 144:ef7eb2e8f9f7 10216 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
<> 144:ef7eb2e8f9f7 10217 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
<> 144:ef7eb2e8f9f7 10218 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
<> 144:ef7eb2e8f9f7 10219 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10220 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10221
<> 144:ef7eb2e8f9f7 10222 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
<> 144:ef7eb2e8f9f7 10223 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
<> 144:ef7eb2e8f9f7 10224 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
<> 144:ef7eb2e8f9f7 10225 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10226 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10227
<> 144:ef7eb2e8f9f7 10228 /* Register: PWM_INTEN */
<> 144:ef7eb2e8f9f7 10229 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 10230
<> 144:ef7eb2e8f9f7 10231 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
<> 144:ef7eb2e8f9f7 10232 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
<> 144:ef7eb2e8f9f7 10233 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
<> 144:ef7eb2e8f9f7 10234 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10235 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10236
<> 144:ef7eb2e8f9f7 10237 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
<> 144:ef7eb2e8f9f7 10238 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
<> 144:ef7eb2e8f9f7 10239 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
<> 144:ef7eb2e8f9f7 10240 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10241 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10242
<> 144:ef7eb2e8f9f7 10243 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
<> 144:ef7eb2e8f9f7 10244 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
<> 144:ef7eb2e8f9f7 10245 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
<> 144:ef7eb2e8f9f7 10246 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10247 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10248
<> 144:ef7eb2e8f9f7 10249 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
<> 144:ef7eb2e8f9f7 10250 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
<> 144:ef7eb2e8f9f7 10251 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
<> 144:ef7eb2e8f9f7 10252 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10253 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10254
<> 144:ef7eb2e8f9f7 10255 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
<> 144:ef7eb2e8f9f7 10256 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
<> 144:ef7eb2e8f9f7 10257 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
<> 144:ef7eb2e8f9f7 10258 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10259 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10260
<> 144:ef7eb2e8f9f7 10261 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
<> 144:ef7eb2e8f9f7 10262 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
<> 144:ef7eb2e8f9f7 10263 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
<> 144:ef7eb2e8f9f7 10264 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10265 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10266
<> 144:ef7eb2e8f9f7 10267 /* Bit 1 : Enable or disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 10268 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 10269 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 10270 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10271 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10272
<> 144:ef7eb2e8f9f7 10273 /* Register: PWM_INTENSET */
<> 144:ef7eb2e8f9f7 10274 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 10275
<> 144:ef7eb2e8f9f7 10276 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
<> 144:ef7eb2e8f9f7 10277 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
<> 144:ef7eb2e8f9f7 10278 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
<> 144:ef7eb2e8f9f7 10279 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10280 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10281 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10282
<> 144:ef7eb2e8f9f7 10283 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
<> 144:ef7eb2e8f9f7 10284 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
<> 144:ef7eb2e8f9f7 10285 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
<> 144:ef7eb2e8f9f7 10286 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10287 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10288 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10289
<> 144:ef7eb2e8f9f7 10290 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
<> 144:ef7eb2e8f9f7 10291 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
<> 144:ef7eb2e8f9f7 10292 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
<> 144:ef7eb2e8f9f7 10293 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10294 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10295 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10296
<> 144:ef7eb2e8f9f7 10297 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
<> 144:ef7eb2e8f9f7 10298 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
<> 144:ef7eb2e8f9f7 10299 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
<> 144:ef7eb2e8f9f7 10300 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10301 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10302 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10303
<> 144:ef7eb2e8f9f7 10304 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
<> 144:ef7eb2e8f9f7 10305 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
<> 144:ef7eb2e8f9f7 10306 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
<> 144:ef7eb2e8f9f7 10307 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10308 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10309 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10310
<> 144:ef7eb2e8f9f7 10311 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
<> 144:ef7eb2e8f9f7 10312 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
<> 144:ef7eb2e8f9f7 10313 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
<> 144:ef7eb2e8f9f7 10314 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10315 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10316 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10317
<> 144:ef7eb2e8f9f7 10318 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 10319 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 10320 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 10321 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10322 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10323 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10324
<> 144:ef7eb2e8f9f7 10325 /* Register: PWM_INTENCLR */
<> 144:ef7eb2e8f9f7 10326 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 10327
<> 144:ef7eb2e8f9f7 10328 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
<> 144:ef7eb2e8f9f7 10329 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
<> 144:ef7eb2e8f9f7 10330 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
<> 144:ef7eb2e8f9f7 10331 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10332 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10333 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10334
<> 144:ef7eb2e8f9f7 10335 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
<> 144:ef7eb2e8f9f7 10336 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
<> 144:ef7eb2e8f9f7 10337 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
<> 144:ef7eb2e8f9f7 10338 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10339 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10340 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10341
<> 144:ef7eb2e8f9f7 10342 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
<> 144:ef7eb2e8f9f7 10343 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
<> 144:ef7eb2e8f9f7 10344 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
<> 144:ef7eb2e8f9f7 10345 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10346 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10347 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10348
<> 144:ef7eb2e8f9f7 10349 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
<> 144:ef7eb2e8f9f7 10350 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
<> 144:ef7eb2e8f9f7 10351 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
<> 144:ef7eb2e8f9f7 10352 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10353 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10354 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10355
<> 144:ef7eb2e8f9f7 10356 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
<> 144:ef7eb2e8f9f7 10357 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
<> 144:ef7eb2e8f9f7 10358 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
<> 144:ef7eb2e8f9f7 10359 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10360 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10361 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10362
<> 144:ef7eb2e8f9f7 10363 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
<> 144:ef7eb2e8f9f7 10364 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
<> 144:ef7eb2e8f9f7 10365 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
<> 144:ef7eb2e8f9f7 10366 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10367 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10368 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10369
<> 144:ef7eb2e8f9f7 10370 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 10371 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 10372 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 10373 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10374 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10375 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10376
<> 144:ef7eb2e8f9f7 10377 /* Register: PWM_ENABLE */
<> 144:ef7eb2e8f9f7 10378 /* Description: PWM module enable register */
<> 144:ef7eb2e8f9f7 10379
<> 144:ef7eb2e8f9f7 10380 /* Bit 0 : Enable or disable PWM module */
<> 144:ef7eb2e8f9f7 10381 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 10382 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 10383 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 10384 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10385
<> 144:ef7eb2e8f9f7 10386 /* Register: PWM_MODE */
<> 144:ef7eb2e8f9f7 10387 /* Description: Selects operating mode of the wave counter */
<> 144:ef7eb2e8f9f7 10388
<> 144:ef7eb2e8f9f7 10389 /* Bit 0 : Selects up or up and down as wave counter mode */
<> 144:ef7eb2e8f9f7 10390 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
<> 144:ef7eb2e8f9f7 10391 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
<> 144:ef7eb2e8f9f7 10392 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
<> 144:ef7eb2e8f9f7 10393 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
<> 144:ef7eb2e8f9f7 10394
<> 144:ef7eb2e8f9f7 10395 /* Register: PWM_COUNTERTOP */
<> 144:ef7eb2e8f9f7 10396 /* Description: Value up to which the pulse generator counter counts */
<> 144:ef7eb2e8f9f7 10397
<> 144:ef7eb2e8f9f7 10398 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
<> 144:ef7eb2e8f9f7 10399 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
<> 144:ef7eb2e8f9f7 10400 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
<> 144:ef7eb2e8f9f7 10401
<> 144:ef7eb2e8f9f7 10402 /* Register: PWM_PRESCALER */
<> 144:ef7eb2e8f9f7 10403 /* Description: Configuration for PWM_CLK */
<> 144:ef7eb2e8f9f7 10404
<> 144:ef7eb2e8f9f7 10405 /* Bits 2..0 : Pre-scaler of PWM_CLK */
<> 144:ef7eb2e8f9f7 10406 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
<> 144:ef7eb2e8f9f7 10407 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
<> 144:ef7eb2e8f9f7 10408 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */
<> 144:ef7eb2e8f9f7 10409 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */
<> 144:ef7eb2e8f9f7 10410 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */
<> 144:ef7eb2e8f9f7 10411 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */
<> 144:ef7eb2e8f9f7 10412 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */
<> 144:ef7eb2e8f9f7 10413 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */
<> 144:ef7eb2e8f9f7 10414 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */
<> 144:ef7eb2e8f9f7 10415 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
<> 144:ef7eb2e8f9f7 10416
<> 144:ef7eb2e8f9f7 10417 /* Register: PWM_DECODER */
<> 144:ef7eb2e8f9f7 10418 /* Description: Configuration of the decoder */
<> 144:ef7eb2e8f9f7 10419
<> 144:ef7eb2e8f9f7 10420 /* Bit 8 : Selects source for advancing the active sequence */
<> 144:ef7eb2e8f9f7 10421 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 10422 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 10423 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
<> 144:ef7eb2e8f9f7 10424 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
<> 144:ef7eb2e8f9f7 10425
<> 144:ef7eb2e8f9f7 10426 /* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
<> 144:ef7eb2e8f9f7 10427 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
<> 144:ef7eb2e8f9f7 10428 #define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
<> 144:ef7eb2e8f9f7 10429 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
<> 144:ef7eb2e8f9f7 10430 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
<> 144:ef7eb2e8f9f7 10431 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
<> 144:ef7eb2e8f9f7 10432 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
<> 144:ef7eb2e8f9f7 10433
<> 144:ef7eb2e8f9f7 10434 /* Register: PWM_LOOP */
<> 144:ef7eb2e8f9f7 10435 /* Description: Amount of playback of a loop */
<> 144:ef7eb2e8f9f7 10436
<> 144:ef7eb2e8f9f7 10437 /* Bits 15..0 : Amount of playback of pattern cycles */
<> 144:ef7eb2e8f9f7 10438 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
<> 144:ef7eb2e8f9f7 10439 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
<> 144:ef7eb2e8f9f7 10440 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
<> 144:ef7eb2e8f9f7 10441
<> 144:ef7eb2e8f9f7 10442 /* Register: PWM_SEQ_PTR */
<> 144:ef7eb2e8f9f7 10443 /* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */
<> 144:ef7eb2e8f9f7 10444
<> 144:ef7eb2e8f9f7 10445 /* Bits 31..0 : Beginning address in Data RAM of sequence A */
<> 144:ef7eb2e8f9f7 10446 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 10447 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 10448
<> 144:ef7eb2e8f9f7 10449 /* Register: PWM_SEQ_CNT */
<> 144:ef7eb2e8f9f7 10450 /* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */
<> 144:ef7eb2e8f9f7 10451
<> 144:ef7eb2e8f9f7 10452 /* Bits 14..0 : Amount of values (duty cycles) in sequence A */
<> 144:ef7eb2e8f9f7 10453 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
<> 144:ef7eb2e8f9f7 10454 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
<> 144:ef7eb2e8f9f7 10455 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
<> 144:ef7eb2e8f9f7 10456
<> 144:ef7eb2e8f9f7 10457 /* Register: PWM_SEQ_REFRESH */
<> 144:ef7eb2e8f9f7 10458 /* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
<> 144:ef7eb2e8f9f7 10459
<> 144:ef7eb2e8f9f7 10460 /* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
<> 144:ef7eb2e8f9f7 10461 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
<> 144:ef7eb2e8f9f7 10462 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
<> 144:ef7eb2e8f9f7 10463 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
<> 144:ef7eb2e8f9f7 10464
<> 144:ef7eb2e8f9f7 10465 /* Register: PWM_SEQ_ENDDELAY */
<> 144:ef7eb2e8f9f7 10466 /* Description: Description cluster[0]: Time added after the sequence */
<> 144:ef7eb2e8f9f7 10467
<> 144:ef7eb2e8f9f7 10468 /* Bits 23..0 : Time added after the sequence in PWM periods */
<> 144:ef7eb2e8f9f7 10469 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
<> 144:ef7eb2e8f9f7 10470 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
<> 144:ef7eb2e8f9f7 10471
<> 144:ef7eb2e8f9f7 10472 /* Register: PWM_PSEL_OUT */
<> 144:ef7eb2e8f9f7 10473 /* Description: Description collection[0]: Output pin select for PWM channel 0 */
<> 144:ef7eb2e8f9f7 10474
<> 144:ef7eb2e8f9f7 10475 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 10476 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 10477 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 10478 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 10479 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 10480
<> 144:ef7eb2e8f9f7 10481 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 10482 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 10483 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 10484
<> 144:ef7eb2e8f9f7 10485
<> 144:ef7eb2e8f9f7 10486 /* Peripheral: QDEC */
<> 144:ef7eb2e8f9f7 10487 /* Description: Quadrature Decoder */
<> 144:ef7eb2e8f9f7 10488
<> 144:ef7eb2e8f9f7 10489 /* Register: QDEC_SHORTS */
<> 144:ef7eb2e8f9f7 10490 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 10491
<> 144:ef7eb2e8f9f7 10492 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
<> 144:ef7eb2e8f9f7 10493 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
<> 144:ef7eb2e8f9f7 10494 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
<> 144:ef7eb2e8f9f7 10495 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10496 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10497
<> 144:ef7eb2e8f9f7 10498 /* Bit 5 : Shortcut between DBLRDY event and STOP task */
<> 144:ef7eb2e8f9f7 10499 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
<> 144:ef7eb2e8f9f7 10500 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
<> 144:ef7eb2e8f9f7 10501 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10502 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10503
<> 144:ef7eb2e8f9f7 10504 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
<> 144:ef7eb2e8f9f7 10505 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
<> 144:ef7eb2e8f9f7 10506 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
<> 144:ef7eb2e8f9f7 10507 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10508 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10509
<> 144:ef7eb2e8f9f7 10510 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */
<> 144:ef7eb2e8f9f7 10511 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
<> 144:ef7eb2e8f9f7 10512 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
<> 144:ef7eb2e8f9f7 10513 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10514 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10515
<> 144:ef7eb2e8f9f7 10516 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
<> 144:ef7eb2e8f9f7 10517 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
<> 144:ef7eb2e8f9f7 10518 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
<> 144:ef7eb2e8f9f7 10519 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10520 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10521
<> 144:ef7eb2e8f9f7 10522 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
<> 144:ef7eb2e8f9f7 10523 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
<> 144:ef7eb2e8f9f7 10524 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
<> 144:ef7eb2e8f9f7 10525 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10526 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10527
<> 144:ef7eb2e8f9f7 10528 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
<> 144:ef7eb2e8f9f7 10529 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
<> 144:ef7eb2e8f9f7 10530 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
<> 144:ef7eb2e8f9f7 10531 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10532 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10533
<> 144:ef7eb2e8f9f7 10534 /* Register: QDEC_INTENSET */
<> 144:ef7eb2e8f9f7 10535 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 10536
<> 144:ef7eb2e8f9f7 10537 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 10538 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 10539 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 10540 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10541 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10542 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10543
<> 144:ef7eb2e8f9f7 10544 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
<> 144:ef7eb2e8f9f7 10545 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
<> 144:ef7eb2e8f9f7 10546 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
<> 144:ef7eb2e8f9f7 10547 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10548 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10549 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10550
<> 144:ef7eb2e8f9f7 10551 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
<> 144:ef7eb2e8f9f7 10552 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
<> 144:ef7eb2e8f9f7 10553 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
<> 144:ef7eb2e8f9f7 10554 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10555 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10556 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10557
<> 144:ef7eb2e8f9f7 10558 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
<> 144:ef7eb2e8f9f7 10559 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
<> 144:ef7eb2e8f9f7 10560 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
<> 144:ef7eb2e8f9f7 10561 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10562 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10563 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10564
<> 144:ef7eb2e8f9f7 10565 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
<> 144:ef7eb2e8f9f7 10566 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
<> 144:ef7eb2e8f9f7 10567 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
<> 144:ef7eb2e8f9f7 10568 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10569 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10570 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10571
<> 144:ef7eb2e8f9f7 10572 /* Register: QDEC_INTENCLR */
<> 144:ef7eb2e8f9f7 10573 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 10574
<> 144:ef7eb2e8f9f7 10575 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 10576 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 10577 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 10578 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10579 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10580 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10581
<> 144:ef7eb2e8f9f7 10582 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
<> 144:ef7eb2e8f9f7 10583 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
<> 144:ef7eb2e8f9f7 10584 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
<> 144:ef7eb2e8f9f7 10585 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10586 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10587 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10588
<> 144:ef7eb2e8f9f7 10589 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
<> 144:ef7eb2e8f9f7 10590 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
<> 144:ef7eb2e8f9f7 10591 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
<> 144:ef7eb2e8f9f7 10592 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10593 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10594 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10595
<> 144:ef7eb2e8f9f7 10596 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
<> 144:ef7eb2e8f9f7 10597 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
<> 144:ef7eb2e8f9f7 10598 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
<> 144:ef7eb2e8f9f7 10599 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10600 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10601 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10602
<> 144:ef7eb2e8f9f7 10603 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
<> 144:ef7eb2e8f9f7 10604 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
<> 144:ef7eb2e8f9f7 10605 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
<> 144:ef7eb2e8f9f7 10606 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10607 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10608 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10609
<> 144:ef7eb2e8f9f7 10610 /* Register: QDEC_ENABLE */
<> 144:ef7eb2e8f9f7 10611 /* Description: Enable the quadrature decoder */
<> 144:ef7eb2e8f9f7 10612
<> 144:ef7eb2e8f9f7 10613 /* Bit 0 : Enable or disable the quadrature decoder */
<> 144:ef7eb2e8f9f7 10614 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 10615 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 10616 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10617 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10618
<> 144:ef7eb2e8f9f7 10619 /* Register: QDEC_LEDPOL */
<> 144:ef7eb2e8f9f7 10620 /* Description: LED output pin polarity */
<> 144:ef7eb2e8f9f7 10621
<> 144:ef7eb2e8f9f7 10622 /* Bit 0 : LED output pin polarity */
<> 144:ef7eb2e8f9f7 10623 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
<> 144:ef7eb2e8f9f7 10624 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
<> 144:ef7eb2e8f9f7 10625 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
<> 144:ef7eb2e8f9f7 10626 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
<> 144:ef7eb2e8f9f7 10627
<> 144:ef7eb2e8f9f7 10628 /* Register: QDEC_SAMPLEPER */
<> 144:ef7eb2e8f9f7 10629 /* Description: Sample period */
<> 144:ef7eb2e8f9f7 10630
<> 144:ef7eb2e8f9f7 10631 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
<> 144:ef7eb2e8f9f7 10632 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
<> 144:ef7eb2e8f9f7 10633 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
<> 144:ef7eb2e8f9f7 10634 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
<> 144:ef7eb2e8f9f7 10635 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
<> 144:ef7eb2e8f9f7 10636 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
<> 144:ef7eb2e8f9f7 10637 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
<> 144:ef7eb2e8f9f7 10638 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
<> 144:ef7eb2e8f9f7 10639 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
<> 144:ef7eb2e8f9f7 10640 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
<> 144:ef7eb2e8f9f7 10641 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
<> 144:ef7eb2e8f9f7 10642 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
<> 144:ef7eb2e8f9f7 10643 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
<> 144:ef7eb2e8f9f7 10644 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
<> 144:ef7eb2e8f9f7 10645
<> 144:ef7eb2e8f9f7 10646 /* Register: QDEC_SAMPLE */
<> 144:ef7eb2e8f9f7 10647 /* Description: Motion sample value */
<> 144:ef7eb2e8f9f7 10648
<> 144:ef7eb2e8f9f7 10649 /* Bits 31..0 : Last motion sample */
<> 144:ef7eb2e8f9f7 10650 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
<> 144:ef7eb2e8f9f7 10651 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
<> 144:ef7eb2e8f9f7 10652
<> 144:ef7eb2e8f9f7 10653 /* Register: QDEC_REPORTPER */
<> 144:ef7eb2e8f9f7 10654 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
<> 144:ef7eb2e8f9f7 10655
<> 144:ef7eb2e8f9f7 10656 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
<> 144:ef7eb2e8f9f7 10657 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
<> 144:ef7eb2e8f9f7 10658 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
<> 144:ef7eb2e8f9f7 10659 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
<> 144:ef7eb2e8f9f7 10660 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
<> 144:ef7eb2e8f9f7 10661 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
<> 144:ef7eb2e8f9f7 10662 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
<> 144:ef7eb2e8f9f7 10663 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
<> 144:ef7eb2e8f9f7 10664 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
<> 144:ef7eb2e8f9f7 10665 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
<> 144:ef7eb2e8f9f7 10666 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
<> 144:ef7eb2e8f9f7 10667 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
<> 144:ef7eb2e8f9f7 10668
<> 144:ef7eb2e8f9f7 10669 /* Register: QDEC_ACC */
<> 144:ef7eb2e8f9f7 10670 /* Description: Register accumulating the valid transitions */
<> 144:ef7eb2e8f9f7 10671
<> 144:ef7eb2e8f9f7 10672 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
<> 144:ef7eb2e8f9f7 10673 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
<> 144:ef7eb2e8f9f7 10674 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
<> 144:ef7eb2e8f9f7 10675
<> 144:ef7eb2e8f9f7 10676 /* Register: QDEC_ACCREAD */
<> 144:ef7eb2e8f9f7 10677 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
<> 144:ef7eb2e8f9f7 10678
<> 144:ef7eb2e8f9f7 10679 /* Bits 31..0 : Snapshot of the ACC register. */
<> 144:ef7eb2e8f9f7 10680 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
<> 144:ef7eb2e8f9f7 10681 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
<> 144:ef7eb2e8f9f7 10682
<> 144:ef7eb2e8f9f7 10683 /* Register: QDEC_PSEL_LED */
<> 144:ef7eb2e8f9f7 10684 /* Description: Pin select for LED signal */
<> 144:ef7eb2e8f9f7 10685
<> 144:ef7eb2e8f9f7 10686 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 10687 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 10688 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 10689 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 10690 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 10691
<> 144:ef7eb2e8f9f7 10692 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 10693 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 10694 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 10695
<> 144:ef7eb2e8f9f7 10696 /* Register: QDEC_PSEL_A */
<> 144:ef7eb2e8f9f7 10697 /* Description: Pin select for A signal */
<> 144:ef7eb2e8f9f7 10698
<> 144:ef7eb2e8f9f7 10699 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 10700 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 10701 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 10702 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 10703 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 10704
<> 144:ef7eb2e8f9f7 10705 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 10706 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 10707 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 10708
<> 144:ef7eb2e8f9f7 10709 /* Register: QDEC_PSEL_B */
<> 144:ef7eb2e8f9f7 10710 /* Description: Pin select for B signal */
<> 144:ef7eb2e8f9f7 10711
<> 144:ef7eb2e8f9f7 10712 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 10713 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 10714 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 10715 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 10716 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 10717
<> 144:ef7eb2e8f9f7 10718 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 10719 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 10720 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 10721
<> 144:ef7eb2e8f9f7 10722 /* Register: QDEC_DBFEN */
<> 144:ef7eb2e8f9f7 10723 /* Description: Enable input debounce filters */
<> 144:ef7eb2e8f9f7 10724
<> 144:ef7eb2e8f9f7 10725 /* Bit 0 : Enable input debounce filters */
<> 144:ef7eb2e8f9f7 10726 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
<> 144:ef7eb2e8f9f7 10727 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
<> 144:ef7eb2e8f9f7 10728 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
<> 144:ef7eb2e8f9f7 10729 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
<> 144:ef7eb2e8f9f7 10730
<> 144:ef7eb2e8f9f7 10731 /* Register: QDEC_LEDPRE */
<> 144:ef7eb2e8f9f7 10732 /* Description: Time period the LED is switched ON prior to sampling */
<> 144:ef7eb2e8f9f7 10733
<> 144:ef7eb2e8f9f7 10734 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
<> 144:ef7eb2e8f9f7 10735 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
<> 144:ef7eb2e8f9f7 10736 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
<> 144:ef7eb2e8f9f7 10737
<> 144:ef7eb2e8f9f7 10738 /* Register: QDEC_ACCDBL */
<> 144:ef7eb2e8f9f7 10739 /* Description: Register accumulating the number of detected double transitions */
<> 144:ef7eb2e8f9f7 10740
<> 144:ef7eb2e8f9f7 10741 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
<> 144:ef7eb2e8f9f7 10742 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
<> 144:ef7eb2e8f9f7 10743 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
<> 144:ef7eb2e8f9f7 10744
<> 144:ef7eb2e8f9f7 10745 /* Register: QDEC_ACCDBLREAD */
<> 144:ef7eb2e8f9f7 10746 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
<> 144:ef7eb2e8f9f7 10747
<> 144:ef7eb2e8f9f7 10748 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
<> 144:ef7eb2e8f9f7 10749 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
<> 144:ef7eb2e8f9f7 10750 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
<> 144:ef7eb2e8f9f7 10751
<> 144:ef7eb2e8f9f7 10752
<> 144:ef7eb2e8f9f7 10753 /* Peripheral: RADIO */
<> 144:ef7eb2e8f9f7 10754 /* Description: 2.4 GHz Radio */
<> 144:ef7eb2e8f9f7 10755
<> 144:ef7eb2e8f9f7 10756 /* Register: RADIO_SHORTS */
<> 144:ef7eb2e8f9f7 10757 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 10758
<> 144:ef7eb2e8f9f7 10759 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
<> 144:ef7eb2e8f9f7 10760 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
<> 144:ef7eb2e8f9f7 10761 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
<> 144:ef7eb2e8f9f7 10762 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10763 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10764
<> 144:ef7eb2e8f9f7 10765 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
<> 144:ef7eb2e8f9f7 10766 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
<> 144:ef7eb2e8f9f7 10767 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
<> 144:ef7eb2e8f9f7 10768 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10769 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10770
<> 144:ef7eb2e8f9f7 10771 /* Bit 5 : Shortcut between END event and START task */
<> 144:ef7eb2e8f9f7 10772 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
<> 144:ef7eb2e8f9f7 10773 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
<> 144:ef7eb2e8f9f7 10774 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10775 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10776
<> 144:ef7eb2e8f9f7 10777 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
<> 144:ef7eb2e8f9f7 10778 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
<> 144:ef7eb2e8f9f7 10779 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
<> 144:ef7eb2e8f9f7 10780 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10781 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10782
<> 144:ef7eb2e8f9f7 10783 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
<> 144:ef7eb2e8f9f7 10784 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
<> 144:ef7eb2e8f9f7 10785 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
<> 144:ef7eb2e8f9f7 10786 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10787 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10788
<> 144:ef7eb2e8f9f7 10789 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
<> 144:ef7eb2e8f9f7 10790 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
<> 144:ef7eb2e8f9f7 10791 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
<> 144:ef7eb2e8f9f7 10792 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10793 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10794
<> 144:ef7eb2e8f9f7 10795 /* Bit 1 : Shortcut between END event and DISABLE task */
<> 144:ef7eb2e8f9f7 10796 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
<> 144:ef7eb2e8f9f7 10797 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
<> 144:ef7eb2e8f9f7 10798 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10799 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10800
<> 144:ef7eb2e8f9f7 10801 /* Bit 0 : Shortcut between READY event and START task */
<> 144:ef7eb2e8f9f7 10802 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
<> 144:ef7eb2e8f9f7 10803 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
<> 144:ef7eb2e8f9f7 10804 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 10805 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 10806
<> 144:ef7eb2e8f9f7 10807 /* Register: RADIO_INTENSET */
<> 144:ef7eb2e8f9f7 10808 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 10809
<> 144:ef7eb2e8f9f7 10810 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
<> 144:ef7eb2e8f9f7 10811 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
<> 144:ef7eb2e8f9f7 10812 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
<> 144:ef7eb2e8f9f7 10813 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10814 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10815 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10816
<> 144:ef7eb2e8f9f7 10817 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
<> 144:ef7eb2e8f9f7 10818 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
<> 144:ef7eb2e8f9f7 10819 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
<> 144:ef7eb2e8f9f7 10820 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10821 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10822 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10823
<> 144:ef7eb2e8f9f7 10824 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
<> 144:ef7eb2e8f9f7 10825 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
<> 144:ef7eb2e8f9f7 10826 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
<> 144:ef7eb2e8f9f7 10827 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10828 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10829 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10830
<> 144:ef7eb2e8f9f7 10831 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
<> 144:ef7eb2e8f9f7 10832 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
<> 144:ef7eb2e8f9f7 10833 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
<> 144:ef7eb2e8f9f7 10834 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10835 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10836 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10837
<> 144:ef7eb2e8f9f7 10838 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
<> 144:ef7eb2e8f9f7 10839 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
<> 144:ef7eb2e8f9f7 10840 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
<> 144:ef7eb2e8f9f7 10841 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10842 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10843 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10844
<> 144:ef7eb2e8f9f7 10845 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
<> 144:ef7eb2e8f9f7 10846 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
<> 144:ef7eb2e8f9f7 10847 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
<> 144:ef7eb2e8f9f7 10848 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10849 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10850 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10851
<> 144:ef7eb2e8f9f7 10852 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
<> 144:ef7eb2e8f9f7 10853 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
<> 144:ef7eb2e8f9f7 10854 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
<> 144:ef7eb2e8f9f7 10855 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10856 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10857 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10858
<> 144:ef7eb2e8f9f7 10859 /* Bit 3 : Write '1' to Enable interrupt for END event */
<> 144:ef7eb2e8f9f7 10860 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 10861 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 10862 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10863 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10864 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10865
<> 144:ef7eb2e8f9f7 10866 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
<> 144:ef7eb2e8f9f7 10867 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
<> 144:ef7eb2e8f9f7 10868 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
<> 144:ef7eb2e8f9f7 10869 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10870 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10871 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10872
<> 144:ef7eb2e8f9f7 10873 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
<> 144:ef7eb2e8f9f7 10874 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
<> 144:ef7eb2e8f9f7 10875 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
<> 144:ef7eb2e8f9f7 10876 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10877 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10878 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10879
<> 144:ef7eb2e8f9f7 10880 /* Bit 0 : Write '1' to Enable interrupt for READY event */
<> 144:ef7eb2e8f9f7 10881 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 10882 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 10883 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10884 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10885 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 10886
<> 144:ef7eb2e8f9f7 10887 /* Register: RADIO_INTENCLR */
<> 144:ef7eb2e8f9f7 10888 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 10889
<> 144:ef7eb2e8f9f7 10890 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
<> 144:ef7eb2e8f9f7 10891 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
<> 144:ef7eb2e8f9f7 10892 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
<> 144:ef7eb2e8f9f7 10893 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10894 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10895 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10896
<> 144:ef7eb2e8f9f7 10897 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
<> 144:ef7eb2e8f9f7 10898 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
<> 144:ef7eb2e8f9f7 10899 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
<> 144:ef7eb2e8f9f7 10900 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10901 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10902 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10903
<> 144:ef7eb2e8f9f7 10904 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
<> 144:ef7eb2e8f9f7 10905 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
<> 144:ef7eb2e8f9f7 10906 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
<> 144:ef7eb2e8f9f7 10907 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10908 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10909 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10910
<> 144:ef7eb2e8f9f7 10911 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
<> 144:ef7eb2e8f9f7 10912 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
<> 144:ef7eb2e8f9f7 10913 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
<> 144:ef7eb2e8f9f7 10914 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10915 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10916 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10917
<> 144:ef7eb2e8f9f7 10918 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
<> 144:ef7eb2e8f9f7 10919 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
<> 144:ef7eb2e8f9f7 10920 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
<> 144:ef7eb2e8f9f7 10921 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10922 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10923 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10924
<> 144:ef7eb2e8f9f7 10925 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
<> 144:ef7eb2e8f9f7 10926 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
<> 144:ef7eb2e8f9f7 10927 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
<> 144:ef7eb2e8f9f7 10928 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10929 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10930 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10931
<> 144:ef7eb2e8f9f7 10932 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
<> 144:ef7eb2e8f9f7 10933 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
<> 144:ef7eb2e8f9f7 10934 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
<> 144:ef7eb2e8f9f7 10935 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10936 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10937 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10938
<> 144:ef7eb2e8f9f7 10939 /* Bit 3 : Write '1' to Disable interrupt for END event */
<> 144:ef7eb2e8f9f7 10940 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 10941 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 10942 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10943 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10944 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10945
<> 144:ef7eb2e8f9f7 10946 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
<> 144:ef7eb2e8f9f7 10947 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
<> 144:ef7eb2e8f9f7 10948 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
<> 144:ef7eb2e8f9f7 10949 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10950 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10951 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10952
<> 144:ef7eb2e8f9f7 10953 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
<> 144:ef7eb2e8f9f7 10954 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
<> 144:ef7eb2e8f9f7 10955 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
<> 144:ef7eb2e8f9f7 10956 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10957 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10958 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10959
<> 144:ef7eb2e8f9f7 10960 /* Bit 0 : Write '1' to Disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 10961 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 10962 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 10963 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 10964 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 10965 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 10966
<> 144:ef7eb2e8f9f7 10967 /* Register: RADIO_CRCSTATUS */
<> 144:ef7eb2e8f9f7 10968 /* Description: CRC status */
<> 144:ef7eb2e8f9f7 10969
<> 144:ef7eb2e8f9f7 10970 /* Bit 0 : CRC status of packet received */
<> 144:ef7eb2e8f9f7 10971 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
<> 144:ef7eb2e8f9f7 10972 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
<> 144:ef7eb2e8f9f7 10973 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
<> 144:ef7eb2e8f9f7 10974 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
<> 144:ef7eb2e8f9f7 10975
<> 144:ef7eb2e8f9f7 10976 /* Register: RADIO_RXMATCH */
<> 144:ef7eb2e8f9f7 10977 /* Description: Received address */
<> 144:ef7eb2e8f9f7 10978
<> 144:ef7eb2e8f9f7 10979 /* Bits 2..0 : Received address */
<> 144:ef7eb2e8f9f7 10980 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
<> 144:ef7eb2e8f9f7 10981 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
<> 144:ef7eb2e8f9f7 10982
<> 144:ef7eb2e8f9f7 10983 /* Register: RADIO_RXCRC */
<> 144:ef7eb2e8f9f7 10984 /* Description: CRC field of previously received packet */
<> 144:ef7eb2e8f9f7 10985
<> 144:ef7eb2e8f9f7 10986 /* Bits 23..0 : CRC field of previously received packet */
<> 144:ef7eb2e8f9f7 10987 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
<> 144:ef7eb2e8f9f7 10988 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
<> 144:ef7eb2e8f9f7 10989
<> 144:ef7eb2e8f9f7 10990 /* Register: RADIO_DAI */
<> 144:ef7eb2e8f9f7 10991 /* Description: Device address match index */
<> 144:ef7eb2e8f9f7 10992
<> 144:ef7eb2e8f9f7 10993 /* Bits 2..0 : Device address match index */
<> 144:ef7eb2e8f9f7 10994 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
<> 144:ef7eb2e8f9f7 10995 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
<> 144:ef7eb2e8f9f7 10996
<> 144:ef7eb2e8f9f7 10997 /* Register: RADIO_PACKETPTR */
<> 144:ef7eb2e8f9f7 10998 /* Description: Packet pointer */
<> 144:ef7eb2e8f9f7 10999
<> 144:ef7eb2e8f9f7 11000 /* Bits 31..0 : Packet pointer */
<> 144:ef7eb2e8f9f7 11001 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
<> 144:ef7eb2e8f9f7 11002 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
<> 144:ef7eb2e8f9f7 11003
<> 144:ef7eb2e8f9f7 11004 /* Register: RADIO_FREQUENCY */
<> 144:ef7eb2e8f9f7 11005 /* Description: Frequency */
<> 144:ef7eb2e8f9f7 11006
<> 144:ef7eb2e8f9f7 11007 /* Bit 8 : Channel map selection. */
<> 144:ef7eb2e8f9f7 11008 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
<> 144:ef7eb2e8f9f7 11009 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
<> 144:ef7eb2e8f9f7 11010 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
<> 144:ef7eb2e8f9f7 11011 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
<> 144:ef7eb2e8f9f7 11012
<> 144:ef7eb2e8f9f7 11013 /* Bits 6..0 : Radio channel frequency */
<> 144:ef7eb2e8f9f7 11014 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 11015 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 11016
<> 144:ef7eb2e8f9f7 11017 /* Register: RADIO_TXPOWER */
<> 144:ef7eb2e8f9f7 11018 /* Description: Output power */
<> 144:ef7eb2e8f9f7 11019
<> 144:ef7eb2e8f9f7 11020 /* Bits 7..0 : RADIO output power. */
<> 144:ef7eb2e8f9f7 11021 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
<> 144:ef7eb2e8f9f7 11022 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
<> 144:ef7eb2e8f9f7 11023 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
<> 144:ef7eb2e8f9f7 11024 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
<> 144:ef7eb2e8f9f7 11025 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
<> 144:ef7eb2e8f9f7 11026 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */
<> 144:ef7eb2e8f9f7 11027 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
<> 144:ef7eb2e8f9f7 11028 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
<> 144:ef7eb2e8f9f7 11029 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
<> 144:ef7eb2e8f9f7 11030 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
<> 144:ef7eb2e8f9f7 11031 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
<> 144:ef7eb2e8f9f7 11032 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
<> 144:ef7eb2e8f9f7 11033
<> 144:ef7eb2e8f9f7 11034 /* Register: RADIO_MODE */
<> 144:ef7eb2e8f9f7 11035 /* Description: Data rate and modulation */
<> 144:ef7eb2e8f9f7 11036
<> 144:ef7eb2e8f9f7 11037 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
<> 144:ef7eb2e8f9f7 11038 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 11039 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 11040 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
<> 144:ef7eb2e8f9f7 11041 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
<> 144:ef7eb2e8f9f7 11042 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
<> 144:ef7eb2e8f9f7 11043 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
<> 144:ef7eb2e8f9f7 11044
<> 144:ef7eb2e8f9f7 11045 /* Register: RADIO_PCNF0 */
<> 144:ef7eb2e8f9f7 11046 /* Description: Packet configuration register 0 */
<> 144:ef7eb2e8f9f7 11047
<> 144:ef7eb2e8f9f7 11048 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
<> 144:ef7eb2e8f9f7 11049 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
<> 144:ef7eb2e8f9f7 11050 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
<> 144:ef7eb2e8f9f7 11051 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
<> 144:ef7eb2e8f9f7 11052 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
<> 144:ef7eb2e8f9f7 11053
<> 144:ef7eb2e8f9f7 11054 /* Bit 20 : Include or exclude S1 field in RAM */
<> 144:ef7eb2e8f9f7 11055 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
<> 144:ef7eb2e8f9f7 11056 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
<> 144:ef7eb2e8f9f7 11057 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
<> 144:ef7eb2e8f9f7 11058 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
<> 144:ef7eb2e8f9f7 11059
<> 144:ef7eb2e8f9f7 11060 /* Bits 19..16 : Length on air of S1 field in number of bits. */
<> 144:ef7eb2e8f9f7 11061 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
<> 144:ef7eb2e8f9f7 11062 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
<> 144:ef7eb2e8f9f7 11063
<> 144:ef7eb2e8f9f7 11064 /* Bit 8 : Length on air of S0 field in number of bytes. */
<> 144:ef7eb2e8f9f7 11065 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
<> 144:ef7eb2e8f9f7 11066 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
<> 144:ef7eb2e8f9f7 11067
<> 144:ef7eb2e8f9f7 11068 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
<> 144:ef7eb2e8f9f7 11069 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
<> 144:ef7eb2e8f9f7 11070 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
<> 144:ef7eb2e8f9f7 11071
<> 144:ef7eb2e8f9f7 11072 /* Register: RADIO_PCNF1 */
<> 144:ef7eb2e8f9f7 11073 /* Description: Packet configuration register 1 */
<> 144:ef7eb2e8f9f7 11074
<> 144:ef7eb2e8f9f7 11075 /* Bit 25 : Enable or disable packet whitening */
<> 144:ef7eb2e8f9f7 11076 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
<> 144:ef7eb2e8f9f7 11077 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
<> 144:ef7eb2e8f9f7 11078 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11079 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11080
<> 144:ef7eb2e8f9f7 11081 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
<> 144:ef7eb2e8f9f7 11082 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
<> 144:ef7eb2e8f9f7 11083 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
<> 144:ef7eb2e8f9f7 11084 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
<> 144:ef7eb2e8f9f7 11085 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
<> 144:ef7eb2e8f9f7 11086
<> 144:ef7eb2e8f9f7 11087 /* Bits 18..16 : Base address length in number of bytes */
<> 144:ef7eb2e8f9f7 11088 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
<> 144:ef7eb2e8f9f7 11089 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
<> 144:ef7eb2e8f9f7 11090
<> 144:ef7eb2e8f9f7 11091 /* Bits 15..8 : Static length in number of bytes */
<> 144:ef7eb2e8f9f7 11092 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
<> 144:ef7eb2e8f9f7 11093 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
<> 144:ef7eb2e8f9f7 11094
<> 144:ef7eb2e8f9f7 11095 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
<> 144:ef7eb2e8f9f7 11096 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
<> 144:ef7eb2e8f9f7 11097 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
<> 144:ef7eb2e8f9f7 11098
<> 144:ef7eb2e8f9f7 11099 /* Register: RADIO_BASE0 */
<> 144:ef7eb2e8f9f7 11100 /* Description: Base address 0 */
<> 144:ef7eb2e8f9f7 11101
<> 144:ef7eb2e8f9f7 11102 /* Bits 31..0 : Base address 0 */
<> 144:ef7eb2e8f9f7 11103 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
<> 144:ef7eb2e8f9f7 11104 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
<> 144:ef7eb2e8f9f7 11105
<> 144:ef7eb2e8f9f7 11106 /* Register: RADIO_BASE1 */
<> 144:ef7eb2e8f9f7 11107 /* Description: Base address 1 */
<> 144:ef7eb2e8f9f7 11108
<> 144:ef7eb2e8f9f7 11109 /* Bits 31..0 : Base address 1 */
<> 144:ef7eb2e8f9f7 11110 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
<> 144:ef7eb2e8f9f7 11111 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
<> 144:ef7eb2e8f9f7 11112
<> 144:ef7eb2e8f9f7 11113 /* Register: RADIO_PREFIX0 */
<> 144:ef7eb2e8f9f7 11114 /* Description: Prefixes bytes for logical addresses 0-3 */
<> 144:ef7eb2e8f9f7 11115
<> 144:ef7eb2e8f9f7 11116 /* Bits 31..24 : Address prefix 3. */
<> 144:ef7eb2e8f9f7 11117 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
<> 144:ef7eb2e8f9f7 11118 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
<> 144:ef7eb2e8f9f7 11119
<> 144:ef7eb2e8f9f7 11120 /* Bits 23..16 : Address prefix 2. */
<> 144:ef7eb2e8f9f7 11121 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
<> 144:ef7eb2e8f9f7 11122 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
<> 144:ef7eb2e8f9f7 11123
<> 144:ef7eb2e8f9f7 11124 /* Bits 15..8 : Address prefix 1. */
<> 144:ef7eb2e8f9f7 11125 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
<> 144:ef7eb2e8f9f7 11126 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
<> 144:ef7eb2e8f9f7 11127
<> 144:ef7eb2e8f9f7 11128 /* Bits 7..0 : Address prefix 0. */
<> 144:ef7eb2e8f9f7 11129 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
<> 144:ef7eb2e8f9f7 11130 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
<> 144:ef7eb2e8f9f7 11131
<> 144:ef7eb2e8f9f7 11132 /* Register: RADIO_PREFIX1 */
<> 144:ef7eb2e8f9f7 11133 /* Description: Prefixes bytes for logical addresses 4-7 */
<> 144:ef7eb2e8f9f7 11134
<> 144:ef7eb2e8f9f7 11135 /* Bits 31..24 : Address prefix 7. */
<> 144:ef7eb2e8f9f7 11136 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
<> 144:ef7eb2e8f9f7 11137 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
<> 144:ef7eb2e8f9f7 11138
<> 144:ef7eb2e8f9f7 11139 /* Bits 23..16 : Address prefix 6. */
<> 144:ef7eb2e8f9f7 11140 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
<> 144:ef7eb2e8f9f7 11141 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
<> 144:ef7eb2e8f9f7 11142
<> 144:ef7eb2e8f9f7 11143 /* Bits 15..8 : Address prefix 5. */
<> 144:ef7eb2e8f9f7 11144 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
<> 144:ef7eb2e8f9f7 11145 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
<> 144:ef7eb2e8f9f7 11146
<> 144:ef7eb2e8f9f7 11147 /* Bits 7..0 : Address prefix 4. */
<> 144:ef7eb2e8f9f7 11148 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
<> 144:ef7eb2e8f9f7 11149 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
<> 144:ef7eb2e8f9f7 11150
<> 144:ef7eb2e8f9f7 11151 /* Register: RADIO_TXADDRESS */
<> 144:ef7eb2e8f9f7 11152 /* Description: Transmit address select */
<> 144:ef7eb2e8f9f7 11153
<> 144:ef7eb2e8f9f7 11154 /* Bits 2..0 : Transmit address select */
<> 144:ef7eb2e8f9f7 11155 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
<> 144:ef7eb2e8f9f7 11156 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
<> 144:ef7eb2e8f9f7 11157
<> 144:ef7eb2e8f9f7 11158 /* Register: RADIO_RXADDRESSES */
<> 144:ef7eb2e8f9f7 11159 /* Description: Receive address select */
<> 144:ef7eb2e8f9f7 11160
<> 144:ef7eb2e8f9f7 11161 /* Bit 7 : Enable or disable reception on logical address 7. */
<> 144:ef7eb2e8f9f7 11162 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
<> 144:ef7eb2e8f9f7 11163 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
<> 144:ef7eb2e8f9f7 11164 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11165 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11166
<> 144:ef7eb2e8f9f7 11167 /* Bit 6 : Enable or disable reception on logical address 6. */
<> 144:ef7eb2e8f9f7 11168 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
<> 144:ef7eb2e8f9f7 11169 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
<> 144:ef7eb2e8f9f7 11170 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11171 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11172
<> 144:ef7eb2e8f9f7 11173 /* Bit 5 : Enable or disable reception on logical address 5. */
<> 144:ef7eb2e8f9f7 11174 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
<> 144:ef7eb2e8f9f7 11175 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
<> 144:ef7eb2e8f9f7 11176 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11177 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11178
<> 144:ef7eb2e8f9f7 11179 /* Bit 4 : Enable or disable reception on logical address 4. */
<> 144:ef7eb2e8f9f7 11180 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
<> 144:ef7eb2e8f9f7 11181 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
<> 144:ef7eb2e8f9f7 11182 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11183 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11184
<> 144:ef7eb2e8f9f7 11185 /* Bit 3 : Enable or disable reception on logical address 3. */
<> 144:ef7eb2e8f9f7 11186 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
<> 144:ef7eb2e8f9f7 11187 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
<> 144:ef7eb2e8f9f7 11188 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11189 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11190
<> 144:ef7eb2e8f9f7 11191 /* Bit 2 : Enable or disable reception on logical address 2. */
<> 144:ef7eb2e8f9f7 11192 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
<> 144:ef7eb2e8f9f7 11193 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
<> 144:ef7eb2e8f9f7 11194 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11195 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11196
<> 144:ef7eb2e8f9f7 11197 /* Bit 1 : Enable or disable reception on logical address 1. */
<> 144:ef7eb2e8f9f7 11198 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
<> 144:ef7eb2e8f9f7 11199 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
<> 144:ef7eb2e8f9f7 11200 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11201 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11202
<> 144:ef7eb2e8f9f7 11203 /* Bit 0 : Enable or disable reception on logical address 0. */
<> 144:ef7eb2e8f9f7 11204 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
<> 144:ef7eb2e8f9f7 11205 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
<> 144:ef7eb2e8f9f7 11206 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11207 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11208
<> 144:ef7eb2e8f9f7 11209 /* Register: RADIO_CRCCNF */
<> 144:ef7eb2e8f9f7 11210 /* Description: CRC configuration */
<> 144:ef7eb2e8f9f7 11211
<> 144:ef7eb2e8f9f7 11212 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
<> 144:ef7eb2e8f9f7 11213 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
<> 144:ef7eb2e8f9f7 11214 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
<> 144:ef7eb2e8f9f7 11215 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
<> 144:ef7eb2e8f9f7 11216 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
<> 144:ef7eb2e8f9f7 11217
<> 144:ef7eb2e8f9f7 11218 /* Bits 1..0 : CRC length in number of bytes. */
<> 144:ef7eb2e8f9f7 11219 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
<> 144:ef7eb2e8f9f7 11220 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
<> 144:ef7eb2e8f9f7 11221 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
<> 144:ef7eb2e8f9f7 11222 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
<> 144:ef7eb2e8f9f7 11223 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
<> 144:ef7eb2e8f9f7 11224 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
<> 144:ef7eb2e8f9f7 11225
<> 144:ef7eb2e8f9f7 11226 /* Register: RADIO_CRCPOLY */
<> 144:ef7eb2e8f9f7 11227 /* Description: CRC polynomial */
<> 144:ef7eb2e8f9f7 11228
<> 144:ef7eb2e8f9f7 11229 /* Bits 23..0 : CRC polynomial */
<> 144:ef7eb2e8f9f7 11230 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
<> 144:ef7eb2e8f9f7 11231 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
<> 144:ef7eb2e8f9f7 11232
<> 144:ef7eb2e8f9f7 11233 /* Register: RADIO_CRCINIT */
<> 144:ef7eb2e8f9f7 11234 /* Description: CRC initial value */
<> 144:ef7eb2e8f9f7 11235
<> 144:ef7eb2e8f9f7 11236 /* Bits 23..0 : CRC initial value */
<> 144:ef7eb2e8f9f7 11237 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
<> 144:ef7eb2e8f9f7 11238 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
<> 144:ef7eb2e8f9f7 11239
<> 144:ef7eb2e8f9f7 11240 /* Register: RADIO_TIFS */
<> 144:ef7eb2e8f9f7 11241 /* Description: Inter Frame Spacing in us */
<> 144:ef7eb2e8f9f7 11242
<> 144:ef7eb2e8f9f7 11243 /* Bits 7..0 : Inter Frame Spacing in us */
<> 144:ef7eb2e8f9f7 11244 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
<> 144:ef7eb2e8f9f7 11245 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
<> 144:ef7eb2e8f9f7 11246
<> 144:ef7eb2e8f9f7 11247 /* Register: RADIO_RSSISAMPLE */
<> 144:ef7eb2e8f9f7 11248 /* Description: RSSI sample */
<> 144:ef7eb2e8f9f7 11249
<> 144:ef7eb2e8f9f7 11250 /* Bits 6..0 : RSSI sample */
<> 144:ef7eb2e8f9f7 11251 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
<> 144:ef7eb2e8f9f7 11252 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
<> 144:ef7eb2e8f9f7 11253
<> 144:ef7eb2e8f9f7 11254 /* Register: RADIO_STATE */
<> 144:ef7eb2e8f9f7 11255 /* Description: Current radio state */
<> 144:ef7eb2e8f9f7 11256
<> 144:ef7eb2e8f9f7 11257 /* Bits 3..0 : Current radio state */
<> 144:ef7eb2e8f9f7 11258 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
<> 144:ef7eb2e8f9f7 11259 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
<> 144:ef7eb2e8f9f7 11260 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
<> 144:ef7eb2e8f9f7 11261 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
<> 144:ef7eb2e8f9f7 11262 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
<> 144:ef7eb2e8f9f7 11263 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
<> 144:ef7eb2e8f9f7 11264 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
<> 144:ef7eb2e8f9f7 11265 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
<> 144:ef7eb2e8f9f7 11266 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
<> 144:ef7eb2e8f9f7 11267 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
<> 144:ef7eb2e8f9f7 11268 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
<> 144:ef7eb2e8f9f7 11269
<> 144:ef7eb2e8f9f7 11270 /* Register: RADIO_DATAWHITEIV */
<> 144:ef7eb2e8f9f7 11271 /* Description: Data whitening initial value */
<> 144:ef7eb2e8f9f7 11272
<> 144:ef7eb2e8f9f7 11273 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
<> 144:ef7eb2e8f9f7 11274 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
<> 144:ef7eb2e8f9f7 11275 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
<> 144:ef7eb2e8f9f7 11276
<> 144:ef7eb2e8f9f7 11277 /* Register: RADIO_BCC */
<> 144:ef7eb2e8f9f7 11278 /* Description: Bit counter compare */
<> 144:ef7eb2e8f9f7 11279
<> 144:ef7eb2e8f9f7 11280 /* Bits 31..0 : Bit counter compare */
<> 144:ef7eb2e8f9f7 11281 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
<> 144:ef7eb2e8f9f7 11282 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
<> 144:ef7eb2e8f9f7 11283
<> 144:ef7eb2e8f9f7 11284 /* Register: RADIO_DAB */
<> 144:ef7eb2e8f9f7 11285 /* Description: Description collection[0]: Device address base segment 0 */
<> 144:ef7eb2e8f9f7 11286
<> 144:ef7eb2e8f9f7 11287 /* Bits 31..0 : Device address base segment 0 */
<> 144:ef7eb2e8f9f7 11288 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
<> 144:ef7eb2e8f9f7 11289 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
<> 144:ef7eb2e8f9f7 11290
<> 144:ef7eb2e8f9f7 11291 /* Register: RADIO_DAP */
<> 144:ef7eb2e8f9f7 11292 /* Description: Description collection[0]: Device address prefix 0 */
<> 144:ef7eb2e8f9f7 11293
<> 144:ef7eb2e8f9f7 11294 /* Bits 15..0 : Device address prefix 0 */
<> 144:ef7eb2e8f9f7 11295 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
<> 144:ef7eb2e8f9f7 11296 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
<> 144:ef7eb2e8f9f7 11297
<> 144:ef7eb2e8f9f7 11298 /* Register: RADIO_DACNF */
<> 144:ef7eb2e8f9f7 11299 /* Description: Device address match configuration */
<> 144:ef7eb2e8f9f7 11300
<> 144:ef7eb2e8f9f7 11301 /* Bit 15 : TxAdd for device address 7 */
<> 144:ef7eb2e8f9f7 11302 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
<> 144:ef7eb2e8f9f7 11303 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
<> 144:ef7eb2e8f9f7 11304
<> 144:ef7eb2e8f9f7 11305 /* Bit 14 : TxAdd for device address 6 */
<> 144:ef7eb2e8f9f7 11306 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
<> 144:ef7eb2e8f9f7 11307 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
<> 144:ef7eb2e8f9f7 11308
<> 144:ef7eb2e8f9f7 11309 /* Bit 13 : TxAdd for device address 5 */
<> 144:ef7eb2e8f9f7 11310 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
<> 144:ef7eb2e8f9f7 11311 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
<> 144:ef7eb2e8f9f7 11312
<> 144:ef7eb2e8f9f7 11313 /* Bit 12 : TxAdd for device address 4 */
<> 144:ef7eb2e8f9f7 11314 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
<> 144:ef7eb2e8f9f7 11315 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
<> 144:ef7eb2e8f9f7 11316
<> 144:ef7eb2e8f9f7 11317 /* Bit 11 : TxAdd for device address 3 */
<> 144:ef7eb2e8f9f7 11318 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
<> 144:ef7eb2e8f9f7 11319 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
<> 144:ef7eb2e8f9f7 11320
<> 144:ef7eb2e8f9f7 11321 /* Bit 10 : TxAdd for device address 2 */
<> 144:ef7eb2e8f9f7 11322 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
<> 144:ef7eb2e8f9f7 11323 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
<> 144:ef7eb2e8f9f7 11324
<> 144:ef7eb2e8f9f7 11325 /* Bit 9 : TxAdd for device address 1 */
<> 144:ef7eb2e8f9f7 11326 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
<> 144:ef7eb2e8f9f7 11327 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
<> 144:ef7eb2e8f9f7 11328
<> 144:ef7eb2e8f9f7 11329 /* Bit 8 : TxAdd for device address 0 */
<> 144:ef7eb2e8f9f7 11330 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
<> 144:ef7eb2e8f9f7 11331 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
<> 144:ef7eb2e8f9f7 11332
<> 144:ef7eb2e8f9f7 11333 /* Bit 7 : Enable or disable device address matching using device address 7 */
<> 144:ef7eb2e8f9f7 11334 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
<> 144:ef7eb2e8f9f7 11335 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
<> 144:ef7eb2e8f9f7 11336 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11337 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11338
<> 144:ef7eb2e8f9f7 11339 /* Bit 6 : Enable or disable device address matching using device address 6 */
<> 144:ef7eb2e8f9f7 11340 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
<> 144:ef7eb2e8f9f7 11341 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
<> 144:ef7eb2e8f9f7 11342 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11343 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11344
<> 144:ef7eb2e8f9f7 11345 /* Bit 5 : Enable or disable device address matching using device address 5 */
<> 144:ef7eb2e8f9f7 11346 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
<> 144:ef7eb2e8f9f7 11347 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
<> 144:ef7eb2e8f9f7 11348 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11349 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11350
<> 144:ef7eb2e8f9f7 11351 /* Bit 4 : Enable or disable device address matching using device address 4 */
<> 144:ef7eb2e8f9f7 11352 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
<> 144:ef7eb2e8f9f7 11353 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
<> 144:ef7eb2e8f9f7 11354 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11355 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11356
<> 144:ef7eb2e8f9f7 11357 /* Bit 3 : Enable or disable device address matching using device address 3 */
<> 144:ef7eb2e8f9f7 11358 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
<> 144:ef7eb2e8f9f7 11359 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
<> 144:ef7eb2e8f9f7 11360 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11361 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11362
<> 144:ef7eb2e8f9f7 11363 /* Bit 2 : Enable or disable device address matching using device address 2 */
<> 144:ef7eb2e8f9f7 11364 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
<> 144:ef7eb2e8f9f7 11365 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
<> 144:ef7eb2e8f9f7 11366 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11367 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11368
<> 144:ef7eb2e8f9f7 11369 /* Bit 1 : Enable or disable device address matching using device address 1 */
<> 144:ef7eb2e8f9f7 11370 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
<> 144:ef7eb2e8f9f7 11371 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
<> 144:ef7eb2e8f9f7 11372 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11373 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11374
<> 144:ef7eb2e8f9f7 11375 /* Bit 0 : Enable or disable device address matching using device address 0 */
<> 144:ef7eb2e8f9f7 11376 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
<> 144:ef7eb2e8f9f7 11377 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
<> 144:ef7eb2e8f9f7 11378 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11379 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11380
<> 144:ef7eb2e8f9f7 11381 /* Register: RADIO_MODECNF0 */
<> 144:ef7eb2e8f9f7 11382 /* Description: Radio mode configuration register 0 */
<> 144:ef7eb2e8f9f7 11383
<> 144:ef7eb2e8f9f7 11384 /* Bits 9..8 : Default TX value */
<> 144:ef7eb2e8f9f7 11385 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
<> 144:ef7eb2e8f9f7 11386 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
<> 144:ef7eb2e8f9f7 11387 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
<> 144:ef7eb2e8f9f7 11388 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
<> 144:ef7eb2e8f9f7 11389 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
<> 144:ef7eb2e8f9f7 11390
<> 144:ef7eb2e8f9f7 11391 /* Bit 0 : Radio ramp-up time */
<> 144:ef7eb2e8f9f7 11392 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
<> 144:ef7eb2e8f9f7 11393 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
<> 144:ef7eb2e8f9f7 11394 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
<> 144:ef7eb2e8f9f7 11395 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
<> 144:ef7eb2e8f9f7 11396
<> 144:ef7eb2e8f9f7 11397 /* Register: RADIO_POWER */
<> 144:ef7eb2e8f9f7 11398 /* Description: Peripheral power control */
<> 144:ef7eb2e8f9f7 11399
<> 144:ef7eb2e8f9f7 11400 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
<> 144:ef7eb2e8f9f7 11401 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
<> 144:ef7eb2e8f9f7 11402 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
<> 144:ef7eb2e8f9f7 11403 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
<> 144:ef7eb2e8f9f7 11404 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
<> 144:ef7eb2e8f9f7 11405
<> 144:ef7eb2e8f9f7 11406
<> 144:ef7eb2e8f9f7 11407 /* Peripheral: RNG */
<> 144:ef7eb2e8f9f7 11408 /* Description: Random Number Generator */
<> 144:ef7eb2e8f9f7 11409
<> 144:ef7eb2e8f9f7 11410 /* Register: RNG_SHORTS */
<> 144:ef7eb2e8f9f7 11411 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 11412
<> 144:ef7eb2e8f9f7 11413 /* Bit 0 : Shortcut between VALRDY event and STOP task */
<> 144:ef7eb2e8f9f7 11414 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
<> 144:ef7eb2e8f9f7 11415 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
<> 144:ef7eb2e8f9f7 11416 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 11417 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 11418
<> 144:ef7eb2e8f9f7 11419 /* Register: RNG_INTENSET */
<> 144:ef7eb2e8f9f7 11420 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 11421
<> 144:ef7eb2e8f9f7 11422 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
<> 144:ef7eb2e8f9f7 11423 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
<> 144:ef7eb2e8f9f7 11424 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
<> 144:ef7eb2e8f9f7 11425 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11426 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11427 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11428
<> 144:ef7eb2e8f9f7 11429 /* Register: RNG_INTENCLR */
<> 144:ef7eb2e8f9f7 11430 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 11431
<> 144:ef7eb2e8f9f7 11432 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
<> 144:ef7eb2e8f9f7 11433 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
<> 144:ef7eb2e8f9f7 11434 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
<> 144:ef7eb2e8f9f7 11435 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11436 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11437 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11438
<> 144:ef7eb2e8f9f7 11439 /* Register: RNG_CONFIG */
<> 144:ef7eb2e8f9f7 11440 /* Description: Configuration register */
<> 144:ef7eb2e8f9f7 11441
<> 144:ef7eb2e8f9f7 11442 /* Bit 0 : Bias correction */
<> 144:ef7eb2e8f9f7 11443 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
<> 144:ef7eb2e8f9f7 11444 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
<> 144:ef7eb2e8f9f7 11445 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 11446 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 11447
<> 144:ef7eb2e8f9f7 11448 /* Register: RNG_VALUE */
<> 144:ef7eb2e8f9f7 11449 /* Description: Output random number */
<> 144:ef7eb2e8f9f7 11450
<> 144:ef7eb2e8f9f7 11451 /* Bits 7..0 : Generated random number */
<> 144:ef7eb2e8f9f7 11452 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
<> 144:ef7eb2e8f9f7 11453 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
<> 144:ef7eb2e8f9f7 11454
<> 144:ef7eb2e8f9f7 11455
<> 144:ef7eb2e8f9f7 11456 /* Peripheral: RTC */
<> 144:ef7eb2e8f9f7 11457 /* Description: Real time counter 0 */
<> 144:ef7eb2e8f9f7 11458
<> 144:ef7eb2e8f9f7 11459 /* Register: RTC_INTENSET */
<> 144:ef7eb2e8f9f7 11460 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 11461
<> 144:ef7eb2e8f9f7 11462 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 11463 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11464 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11465 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11466 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11467 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11468
<> 144:ef7eb2e8f9f7 11469 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 11470 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11471 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11472 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11473 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11474 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11475
<> 144:ef7eb2e8f9f7 11476 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 11477 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11478 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11479 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11480 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11481 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11482
<> 144:ef7eb2e8f9f7 11483 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 11484 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11485 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11486 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11487 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11488 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11489
<> 144:ef7eb2e8f9f7 11490 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
<> 144:ef7eb2e8f9f7 11491 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11492 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11493 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11494 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11495 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11496
<> 144:ef7eb2e8f9f7 11497 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
<> 144:ef7eb2e8f9f7 11498 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
<> 144:ef7eb2e8f9f7 11499 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
<> 144:ef7eb2e8f9f7 11500 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11501 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11502 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11503
<> 144:ef7eb2e8f9f7 11504 /* Register: RTC_INTENCLR */
<> 144:ef7eb2e8f9f7 11505 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 11506
<> 144:ef7eb2e8f9f7 11507 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 11508 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11509 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11510 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11511 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11512 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11513
<> 144:ef7eb2e8f9f7 11514 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 11515 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11516 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11517 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11518 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11519 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11520
<> 144:ef7eb2e8f9f7 11521 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 11522 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11523 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11524 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11525 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11526 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11527
<> 144:ef7eb2e8f9f7 11528 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 11529 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11530 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11531 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11532 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11533 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11534
<> 144:ef7eb2e8f9f7 11535 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
<> 144:ef7eb2e8f9f7 11536 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11537 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11538 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11539 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11540 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11541
<> 144:ef7eb2e8f9f7 11542 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
<> 144:ef7eb2e8f9f7 11543 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
<> 144:ef7eb2e8f9f7 11544 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
<> 144:ef7eb2e8f9f7 11545 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11546 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11547 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11548
<> 144:ef7eb2e8f9f7 11549 /* Register: RTC_EVTEN */
<> 144:ef7eb2e8f9f7 11550 /* Description: Enable or disable event routing */
<> 144:ef7eb2e8f9f7 11551
<> 144:ef7eb2e8f9f7 11552 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 11553 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11554 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11555 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11556 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11557
<> 144:ef7eb2e8f9f7 11558 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 11559 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11560 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11561 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11562 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11563
<> 144:ef7eb2e8f9f7 11564 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 11565 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11566 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11567 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11568 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11569
<> 144:ef7eb2e8f9f7 11570 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 11571 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11572 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11573 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11574 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11575
<> 144:ef7eb2e8f9f7 11576 /* Bit 1 : Enable or disable event routing for OVRFLW event */
<> 144:ef7eb2e8f9f7 11577 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11578 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11579 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11580 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11581
<> 144:ef7eb2e8f9f7 11582 /* Bit 0 : Enable or disable event routing for TICK event */
<> 144:ef7eb2e8f9f7 11583 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
<> 144:ef7eb2e8f9f7 11584 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
<> 144:ef7eb2e8f9f7 11585 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11586 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11587
<> 144:ef7eb2e8f9f7 11588 /* Register: RTC_EVTENSET */
<> 144:ef7eb2e8f9f7 11589 /* Description: Enable event routing */
<> 144:ef7eb2e8f9f7 11590
<> 144:ef7eb2e8f9f7 11591 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 11592 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11593 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11594 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11595 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11596 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11597
<> 144:ef7eb2e8f9f7 11598 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 11599 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11600 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11601 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11602 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11603 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11604
<> 144:ef7eb2e8f9f7 11605 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 11606 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11607 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11608 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11609 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11610 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11611
<> 144:ef7eb2e8f9f7 11612 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 11613 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11614 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11615 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11616 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11617 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11618
<> 144:ef7eb2e8f9f7 11619 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
<> 144:ef7eb2e8f9f7 11620 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11621 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11622 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11623 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11624 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11625
<> 144:ef7eb2e8f9f7 11626 /* Bit 0 : Write '1' to Enable event routing for TICK event */
<> 144:ef7eb2e8f9f7 11627 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
<> 144:ef7eb2e8f9f7 11628 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
<> 144:ef7eb2e8f9f7 11629 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11630 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11631 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11632
<> 144:ef7eb2e8f9f7 11633 /* Register: RTC_EVTENCLR */
<> 144:ef7eb2e8f9f7 11634 /* Description: Disable event routing */
<> 144:ef7eb2e8f9f7 11635
<> 144:ef7eb2e8f9f7 11636 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 11637 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11638 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 11639 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11640 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11641 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11642
<> 144:ef7eb2e8f9f7 11643 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 11644 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11645 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 11646 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11647 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11648 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11649
<> 144:ef7eb2e8f9f7 11650 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 11651 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11652 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 11653 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11654 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11655 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11656
<> 144:ef7eb2e8f9f7 11657 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 11658 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11659 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 11660 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11661 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11662 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11663
<> 144:ef7eb2e8f9f7 11664 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
<> 144:ef7eb2e8f9f7 11665 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11666 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
<> 144:ef7eb2e8f9f7 11667 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11668 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11669 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11670
<> 144:ef7eb2e8f9f7 11671 /* Bit 0 : Write '1' to Disable event routing for TICK event */
<> 144:ef7eb2e8f9f7 11672 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
<> 144:ef7eb2e8f9f7 11673 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
<> 144:ef7eb2e8f9f7 11674 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11675 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11676 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11677
<> 144:ef7eb2e8f9f7 11678 /* Register: RTC_COUNTER */
<> 144:ef7eb2e8f9f7 11679 /* Description: Current COUNTER value */
<> 144:ef7eb2e8f9f7 11680
<> 144:ef7eb2e8f9f7 11681 /* Bits 23..0 : Counter value */
<> 144:ef7eb2e8f9f7 11682 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
<> 144:ef7eb2e8f9f7 11683 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
<> 144:ef7eb2e8f9f7 11684
<> 144:ef7eb2e8f9f7 11685 /* Register: RTC_PRESCALER */
<> 144:ef7eb2e8f9f7 11686 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
<> 144:ef7eb2e8f9f7 11687
<> 144:ef7eb2e8f9f7 11688 /* Bits 11..0 : Prescaler value */
<> 144:ef7eb2e8f9f7 11689 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
<> 144:ef7eb2e8f9f7 11690 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
<> 144:ef7eb2e8f9f7 11691
<> 144:ef7eb2e8f9f7 11692 /* Register: RTC_CC */
<> 144:ef7eb2e8f9f7 11693 /* Description: Description collection[0]: Compare register 0 */
<> 144:ef7eb2e8f9f7 11694
<> 144:ef7eb2e8f9f7 11695 /* Bits 23..0 : Compare value */
<> 144:ef7eb2e8f9f7 11696 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
<> 144:ef7eb2e8f9f7 11697 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
<> 144:ef7eb2e8f9f7 11698
<> 144:ef7eb2e8f9f7 11699
<> 144:ef7eb2e8f9f7 11700 /* Peripheral: SAADC */
<> 144:ef7eb2e8f9f7 11701 /* Description: Analog to Digital Converter */
<> 144:ef7eb2e8f9f7 11702
<> 144:ef7eb2e8f9f7 11703 /* Register: SAADC_INTEN */
<> 144:ef7eb2e8f9f7 11704 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 11705
<> 144:ef7eb2e8f9f7 11706 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
<> 144:ef7eb2e8f9f7 11707 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
<> 144:ef7eb2e8f9f7 11708 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
<> 144:ef7eb2e8f9f7 11709 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11710 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11711
<> 144:ef7eb2e8f9f7 11712 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
<> 144:ef7eb2e8f9f7 11713 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
<> 144:ef7eb2e8f9f7 11714 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
<> 144:ef7eb2e8f9f7 11715 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11716 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11717
<> 144:ef7eb2e8f9f7 11718 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
<> 144:ef7eb2e8f9f7 11719 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
<> 144:ef7eb2e8f9f7 11720 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
<> 144:ef7eb2e8f9f7 11721 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11722 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11723
<> 144:ef7eb2e8f9f7 11724 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
<> 144:ef7eb2e8f9f7 11725 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
<> 144:ef7eb2e8f9f7 11726 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
<> 144:ef7eb2e8f9f7 11727 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11728 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11729
<> 144:ef7eb2e8f9f7 11730 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
<> 144:ef7eb2e8f9f7 11731 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
<> 144:ef7eb2e8f9f7 11732 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
<> 144:ef7eb2e8f9f7 11733 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11734 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11735
<> 144:ef7eb2e8f9f7 11736 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
<> 144:ef7eb2e8f9f7 11737 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
<> 144:ef7eb2e8f9f7 11738 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
<> 144:ef7eb2e8f9f7 11739 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11740 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11741
<> 144:ef7eb2e8f9f7 11742 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
<> 144:ef7eb2e8f9f7 11743 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
<> 144:ef7eb2e8f9f7 11744 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
<> 144:ef7eb2e8f9f7 11745 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11746 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11747
<> 144:ef7eb2e8f9f7 11748 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
<> 144:ef7eb2e8f9f7 11749 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
<> 144:ef7eb2e8f9f7 11750 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
<> 144:ef7eb2e8f9f7 11751 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11752 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11753
<> 144:ef7eb2e8f9f7 11754 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
<> 144:ef7eb2e8f9f7 11755 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
<> 144:ef7eb2e8f9f7 11756 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
<> 144:ef7eb2e8f9f7 11757 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11758 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11759
<> 144:ef7eb2e8f9f7 11760 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
<> 144:ef7eb2e8f9f7 11761 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
<> 144:ef7eb2e8f9f7 11762 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
<> 144:ef7eb2e8f9f7 11763 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11764 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11765
<> 144:ef7eb2e8f9f7 11766 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
<> 144:ef7eb2e8f9f7 11767 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
<> 144:ef7eb2e8f9f7 11768 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
<> 144:ef7eb2e8f9f7 11769 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11770 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11771
<> 144:ef7eb2e8f9f7 11772 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
<> 144:ef7eb2e8f9f7 11773 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
<> 144:ef7eb2e8f9f7 11774 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
<> 144:ef7eb2e8f9f7 11775 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11776 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11777
<> 144:ef7eb2e8f9f7 11778 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
<> 144:ef7eb2e8f9f7 11779 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
<> 144:ef7eb2e8f9f7 11780 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
<> 144:ef7eb2e8f9f7 11781 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11782 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11783
<> 144:ef7eb2e8f9f7 11784 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
<> 144:ef7eb2e8f9f7 11785 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
<> 144:ef7eb2e8f9f7 11786 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
<> 144:ef7eb2e8f9f7 11787 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11788 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11789
<> 144:ef7eb2e8f9f7 11790 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
<> 144:ef7eb2e8f9f7 11791 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
<> 144:ef7eb2e8f9f7 11792 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
<> 144:ef7eb2e8f9f7 11793 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11794 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11795
<> 144:ef7eb2e8f9f7 11796 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
<> 144:ef7eb2e8f9f7 11797 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
<> 144:ef7eb2e8f9f7 11798 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
<> 144:ef7eb2e8f9f7 11799 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11800 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11801
<> 144:ef7eb2e8f9f7 11802 /* Bit 5 : Enable or disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 11803 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 11804 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 11805 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11806 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11807
<> 144:ef7eb2e8f9f7 11808 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
<> 144:ef7eb2e8f9f7 11809 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
<> 144:ef7eb2e8f9f7 11810 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
<> 144:ef7eb2e8f9f7 11811 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11812 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11813
<> 144:ef7eb2e8f9f7 11814 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
<> 144:ef7eb2e8f9f7 11815 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
<> 144:ef7eb2e8f9f7 11816 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
<> 144:ef7eb2e8f9f7 11817 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11818 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11819
<> 144:ef7eb2e8f9f7 11820 /* Bit 2 : Enable or disable interrupt for DONE event */
<> 144:ef7eb2e8f9f7 11821 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
<> 144:ef7eb2e8f9f7 11822 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
<> 144:ef7eb2e8f9f7 11823 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11824 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11825
<> 144:ef7eb2e8f9f7 11826 /* Bit 1 : Enable or disable interrupt for END event */
<> 144:ef7eb2e8f9f7 11827 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 11828 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 11829 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11830 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11831
<> 144:ef7eb2e8f9f7 11832 /* Bit 0 : Enable or disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 11833 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 11834 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 11835 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 11836 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11837
<> 144:ef7eb2e8f9f7 11838 /* Register: SAADC_INTENSET */
<> 144:ef7eb2e8f9f7 11839 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 11840
<> 144:ef7eb2e8f9f7 11841 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
<> 144:ef7eb2e8f9f7 11842 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
<> 144:ef7eb2e8f9f7 11843 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
<> 144:ef7eb2e8f9f7 11844 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11845 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11846 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11847
<> 144:ef7eb2e8f9f7 11848 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
<> 144:ef7eb2e8f9f7 11849 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
<> 144:ef7eb2e8f9f7 11850 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
<> 144:ef7eb2e8f9f7 11851 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11852 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11853 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11854
<> 144:ef7eb2e8f9f7 11855 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
<> 144:ef7eb2e8f9f7 11856 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
<> 144:ef7eb2e8f9f7 11857 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
<> 144:ef7eb2e8f9f7 11858 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11859 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11860 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11861
<> 144:ef7eb2e8f9f7 11862 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
<> 144:ef7eb2e8f9f7 11863 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
<> 144:ef7eb2e8f9f7 11864 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
<> 144:ef7eb2e8f9f7 11865 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11866 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11867 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11868
<> 144:ef7eb2e8f9f7 11869 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
<> 144:ef7eb2e8f9f7 11870 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
<> 144:ef7eb2e8f9f7 11871 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
<> 144:ef7eb2e8f9f7 11872 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11873 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11874 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11875
<> 144:ef7eb2e8f9f7 11876 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
<> 144:ef7eb2e8f9f7 11877 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
<> 144:ef7eb2e8f9f7 11878 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
<> 144:ef7eb2e8f9f7 11879 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11880 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11881 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11882
<> 144:ef7eb2e8f9f7 11883 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
<> 144:ef7eb2e8f9f7 11884 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
<> 144:ef7eb2e8f9f7 11885 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
<> 144:ef7eb2e8f9f7 11886 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11887 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11888 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11889
<> 144:ef7eb2e8f9f7 11890 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
<> 144:ef7eb2e8f9f7 11891 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
<> 144:ef7eb2e8f9f7 11892 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
<> 144:ef7eb2e8f9f7 11893 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11894 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11895 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11896
<> 144:ef7eb2e8f9f7 11897 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
<> 144:ef7eb2e8f9f7 11898 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
<> 144:ef7eb2e8f9f7 11899 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
<> 144:ef7eb2e8f9f7 11900 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11901 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11902 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11903
<> 144:ef7eb2e8f9f7 11904 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
<> 144:ef7eb2e8f9f7 11905 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
<> 144:ef7eb2e8f9f7 11906 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
<> 144:ef7eb2e8f9f7 11907 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11908 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11909 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11910
<> 144:ef7eb2e8f9f7 11911 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
<> 144:ef7eb2e8f9f7 11912 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
<> 144:ef7eb2e8f9f7 11913 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
<> 144:ef7eb2e8f9f7 11914 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11915 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11916 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11917
<> 144:ef7eb2e8f9f7 11918 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
<> 144:ef7eb2e8f9f7 11919 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
<> 144:ef7eb2e8f9f7 11920 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
<> 144:ef7eb2e8f9f7 11921 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11922 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11923 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11924
<> 144:ef7eb2e8f9f7 11925 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
<> 144:ef7eb2e8f9f7 11926 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
<> 144:ef7eb2e8f9f7 11927 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
<> 144:ef7eb2e8f9f7 11928 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11929 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11930 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11931
<> 144:ef7eb2e8f9f7 11932 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
<> 144:ef7eb2e8f9f7 11933 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
<> 144:ef7eb2e8f9f7 11934 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
<> 144:ef7eb2e8f9f7 11935 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11936 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11937 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11938
<> 144:ef7eb2e8f9f7 11939 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
<> 144:ef7eb2e8f9f7 11940 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
<> 144:ef7eb2e8f9f7 11941 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
<> 144:ef7eb2e8f9f7 11942 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11943 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11944 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11945
<> 144:ef7eb2e8f9f7 11946 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
<> 144:ef7eb2e8f9f7 11947 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
<> 144:ef7eb2e8f9f7 11948 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
<> 144:ef7eb2e8f9f7 11949 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11950 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11951 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11952
<> 144:ef7eb2e8f9f7 11953 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 11954 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 11955 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 11956 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11957 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11958 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11959
<> 144:ef7eb2e8f9f7 11960 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
<> 144:ef7eb2e8f9f7 11961 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
<> 144:ef7eb2e8f9f7 11962 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
<> 144:ef7eb2e8f9f7 11963 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11964 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11965 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11966
<> 144:ef7eb2e8f9f7 11967 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
<> 144:ef7eb2e8f9f7 11968 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
<> 144:ef7eb2e8f9f7 11969 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
<> 144:ef7eb2e8f9f7 11970 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11971 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11972 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11973
<> 144:ef7eb2e8f9f7 11974 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
<> 144:ef7eb2e8f9f7 11975 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
<> 144:ef7eb2e8f9f7 11976 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
<> 144:ef7eb2e8f9f7 11977 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11978 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11979 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11980
<> 144:ef7eb2e8f9f7 11981 /* Bit 1 : Write '1' to Enable interrupt for END event */
<> 144:ef7eb2e8f9f7 11982 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 11983 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 11984 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11985 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11986 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11987
<> 144:ef7eb2e8f9f7 11988 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 11989 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 11990 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 11991 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 11992 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 11993 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 11994
<> 144:ef7eb2e8f9f7 11995 /* Register: SAADC_INTENCLR */
<> 144:ef7eb2e8f9f7 11996 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 11997
<> 144:ef7eb2e8f9f7 11998 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
<> 144:ef7eb2e8f9f7 11999 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
<> 144:ef7eb2e8f9f7 12000 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
<> 144:ef7eb2e8f9f7 12001 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12002 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12003 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12004
<> 144:ef7eb2e8f9f7 12005 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
<> 144:ef7eb2e8f9f7 12006 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
<> 144:ef7eb2e8f9f7 12007 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
<> 144:ef7eb2e8f9f7 12008 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12009 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12010 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12011
<> 144:ef7eb2e8f9f7 12012 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
<> 144:ef7eb2e8f9f7 12013 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
<> 144:ef7eb2e8f9f7 12014 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
<> 144:ef7eb2e8f9f7 12015 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12016 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12017 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12018
<> 144:ef7eb2e8f9f7 12019 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
<> 144:ef7eb2e8f9f7 12020 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
<> 144:ef7eb2e8f9f7 12021 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
<> 144:ef7eb2e8f9f7 12022 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12023 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12024 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12025
<> 144:ef7eb2e8f9f7 12026 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
<> 144:ef7eb2e8f9f7 12027 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
<> 144:ef7eb2e8f9f7 12028 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
<> 144:ef7eb2e8f9f7 12029 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12030 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12031 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12032
<> 144:ef7eb2e8f9f7 12033 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
<> 144:ef7eb2e8f9f7 12034 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
<> 144:ef7eb2e8f9f7 12035 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
<> 144:ef7eb2e8f9f7 12036 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12037 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12038 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12039
<> 144:ef7eb2e8f9f7 12040 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
<> 144:ef7eb2e8f9f7 12041 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
<> 144:ef7eb2e8f9f7 12042 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
<> 144:ef7eb2e8f9f7 12043 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12044 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12045 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12046
<> 144:ef7eb2e8f9f7 12047 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
<> 144:ef7eb2e8f9f7 12048 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
<> 144:ef7eb2e8f9f7 12049 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
<> 144:ef7eb2e8f9f7 12050 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12051 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12052 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12053
<> 144:ef7eb2e8f9f7 12054 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
<> 144:ef7eb2e8f9f7 12055 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
<> 144:ef7eb2e8f9f7 12056 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
<> 144:ef7eb2e8f9f7 12057 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12058 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12059 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12060
<> 144:ef7eb2e8f9f7 12061 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
<> 144:ef7eb2e8f9f7 12062 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
<> 144:ef7eb2e8f9f7 12063 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
<> 144:ef7eb2e8f9f7 12064 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12065 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12066 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12067
<> 144:ef7eb2e8f9f7 12068 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
<> 144:ef7eb2e8f9f7 12069 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
<> 144:ef7eb2e8f9f7 12070 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
<> 144:ef7eb2e8f9f7 12071 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12072 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12073 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12074
<> 144:ef7eb2e8f9f7 12075 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
<> 144:ef7eb2e8f9f7 12076 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
<> 144:ef7eb2e8f9f7 12077 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
<> 144:ef7eb2e8f9f7 12078 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12079 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12080 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12081
<> 144:ef7eb2e8f9f7 12082 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
<> 144:ef7eb2e8f9f7 12083 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
<> 144:ef7eb2e8f9f7 12084 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
<> 144:ef7eb2e8f9f7 12085 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12086 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12087 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12088
<> 144:ef7eb2e8f9f7 12089 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
<> 144:ef7eb2e8f9f7 12090 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
<> 144:ef7eb2e8f9f7 12091 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
<> 144:ef7eb2e8f9f7 12092 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12093 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12094 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12095
<> 144:ef7eb2e8f9f7 12096 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
<> 144:ef7eb2e8f9f7 12097 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
<> 144:ef7eb2e8f9f7 12098 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
<> 144:ef7eb2e8f9f7 12099 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12100 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12101 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12102
<> 144:ef7eb2e8f9f7 12103 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
<> 144:ef7eb2e8f9f7 12104 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
<> 144:ef7eb2e8f9f7 12105 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
<> 144:ef7eb2e8f9f7 12106 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12107 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12108 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12109
<> 144:ef7eb2e8f9f7 12110 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 12111 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 12112 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 12113 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12114 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12115 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12116
<> 144:ef7eb2e8f9f7 12117 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
<> 144:ef7eb2e8f9f7 12118 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
<> 144:ef7eb2e8f9f7 12119 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
<> 144:ef7eb2e8f9f7 12120 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12121 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12122 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12123
<> 144:ef7eb2e8f9f7 12124 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
<> 144:ef7eb2e8f9f7 12125 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
<> 144:ef7eb2e8f9f7 12126 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
<> 144:ef7eb2e8f9f7 12127 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12128 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12129 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12130
<> 144:ef7eb2e8f9f7 12131 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
<> 144:ef7eb2e8f9f7 12132 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
<> 144:ef7eb2e8f9f7 12133 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
<> 144:ef7eb2e8f9f7 12134 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12135 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12136 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12137
<> 144:ef7eb2e8f9f7 12138 /* Bit 1 : Write '1' to Disable interrupt for END event */
<> 144:ef7eb2e8f9f7 12139 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 12140 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 12141 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12142 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12143 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12144
<> 144:ef7eb2e8f9f7 12145 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 12146 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 12147 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 12148 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12149 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12150 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12151
<> 144:ef7eb2e8f9f7 12152 /* Register: SAADC_STATUS */
<> 144:ef7eb2e8f9f7 12153 /* Description: Status */
<> 144:ef7eb2e8f9f7 12154
<> 144:ef7eb2e8f9f7 12155 /* Bit 0 : Status */
<> 144:ef7eb2e8f9f7 12156 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
<> 144:ef7eb2e8f9f7 12157 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
<> 144:ef7eb2e8f9f7 12158 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
<> 144:ef7eb2e8f9f7 12159 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
<> 144:ef7eb2e8f9f7 12160
<> 144:ef7eb2e8f9f7 12161 /* Register: SAADC_ENABLE */
<> 144:ef7eb2e8f9f7 12162 /* Description: Enable or disable ADC */
<> 144:ef7eb2e8f9f7 12163
<> 144:ef7eb2e8f9f7 12164 /* Bit 0 : Enable or disable ADC */
<> 144:ef7eb2e8f9f7 12165 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 12166 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 12167 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
<> 144:ef7eb2e8f9f7 12168 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
<> 144:ef7eb2e8f9f7 12169
<> 144:ef7eb2e8f9f7 12170 /* Register: SAADC_CH_PSELP */
<> 144:ef7eb2e8f9f7 12171 /* Description: Description cluster[0]: Input positive pin selection for CH[0] */
<> 144:ef7eb2e8f9f7 12172
<> 144:ef7eb2e8f9f7 12173 /* Bits 4..0 : Analog positive input channel */
<> 144:ef7eb2e8f9f7 12174 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
<> 144:ef7eb2e8f9f7 12175 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
<> 144:ef7eb2e8f9f7 12176 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
<> 144:ef7eb2e8f9f7 12177 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
<> 144:ef7eb2e8f9f7 12178 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
<> 144:ef7eb2e8f9f7 12179 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
<> 144:ef7eb2e8f9f7 12180 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
<> 144:ef7eb2e8f9f7 12181 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
<> 144:ef7eb2e8f9f7 12182 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
<> 144:ef7eb2e8f9f7 12183 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
<> 144:ef7eb2e8f9f7 12184 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
<> 144:ef7eb2e8f9f7 12185 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
<> 144:ef7eb2e8f9f7 12186
<> 144:ef7eb2e8f9f7 12187 /* Register: SAADC_CH_PSELN */
<> 144:ef7eb2e8f9f7 12188 /* Description: Description cluster[0]: Input negative pin selection for CH[0] */
<> 144:ef7eb2e8f9f7 12189
<> 144:ef7eb2e8f9f7 12190 /* Bits 4..0 : Analog negative input, enables differential channel */
<> 144:ef7eb2e8f9f7 12191 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
<> 144:ef7eb2e8f9f7 12192 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
<> 144:ef7eb2e8f9f7 12193 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
<> 144:ef7eb2e8f9f7 12194 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
<> 144:ef7eb2e8f9f7 12195 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
<> 144:ef7eb2e8f9f7 12196 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
<> 144:ef7eb2e8f9f7 12197 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
<> 144:ef7eb2e8f9f7 12198 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
<> 144:ef7eb2e8f9f7 12199 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
<> 144:ef7eb2e8f9f7 12200 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
<> 144:ef7eb2e8f9f7 12201 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
<> 144:ef7eb2e8f9f7 12202 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
<> 144:ef7eb2e8f9f7 12203
<> 144:ef7eb2e8f9f7 12204 /* Register: SAADC_CH_CONFIG */
<> 144:ef7eb2e8f9f7 12205 /* Description: Description cluster[0]: Input configuration for CH[0] */
<> 144:ef7eb2e8f9f7 12206
<> 144:ef7eb2e8f9f7 12207 /* Bit 24 : Enable burst mode */
<> 144:ef7eb2e8f9f7 12208 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
<> 144:ef7eb2e8f9f7 12209 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
<> 144:ef7eb2e8f9f7 12210 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
<> 144:ef7eb2e8f9f7 12211 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
<> 144:ef7eb2e8f9f7 12212
<> 144:ef7eb2e8f9f7 12213 /* Bit 20 : Enable differential mode */
<> 144:ef7eb2e8f9f7 12214 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 12215 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 12216 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
<> 144:ef7eb2e8f9f7 12217 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
<> 144:ef7eb2e8f9f7 12218
<> 144:ef7eb2e8f9f7 12219 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
<> 144:ef7eb2e8f9f7 12220 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
<> 144:ef7eb2e8f9f7 12221 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
<> 144:ef7eb2e8f9f7 12222 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
<> 144:ef7eb2e8f9f7 12223 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
<> 144:ef7eb2e8f9f7 12224 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
<> 144:ef7eb2e8f9f7 12225 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
<> 144:ef7eb2e8f9f7 12226 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
<> 144:ef7eb2e8f9f7 12227 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
<> 144:ef7eb2e8f9f7 12228
<> 144:ef7eb2e8f9f7 12229 /* Bit 12 : Reference control */
<> 144:ef7eb2e8f9f7 12230 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
<> 144:ef7eb2e8f9f7 12231 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
<> 144:ef7eb2e8f9f7 12232 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
<> 144:ef7eb2e8f9f7 12233 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
<> 144:ef7eb2e8f9f7 12234
<> 144:ef7eb2e8f9f7 12235 /* Bits 10..8 : Gain control */
<> 144:ef7eb2e8f9f7 12236 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
<> 144:ef7eb2e8f9f7 12237 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
<> 144:ef7eb2e8f9f7 12238 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
<> 144:ef7eb2e8f9f7 12239 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
<> 144:ef7eb2e8f9f7 12240 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
<> 144:ef7eb2e8f9f7 12241 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
<> 144:ef7eb2e8f9f7 12242 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
<> 144:ef7eb2e8f9f7 12243 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
<> 144:ef7eb2e8f9f7 12244 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
<> 144:ef7eb2e8f9f7 12245 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
<> 144:ef7eb2e8f9f7 12246
<> 144:ef7eb2e8f9f7 12247 /* Bits 5..4 : Negative channel resistor control */
<> 144:ef7eb2e8f9f7 12248 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
<> 144:ef7eb2e8f9f7 12249 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
<> 144:ef7eb2e8f9f7 12250 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
<> 144:ef7eb2e8f9f7 12251 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
<> 144:ef7eb2e8f9f7 12252 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
<> 144:ef7eb2e8f9f7 12253 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
<> 144:ef7eb2e8f9f7 12254
<> 144:ef7eb2e8f9f7 12255 /* Bits 1..0 : Positive channel resistor control */
<> 144:ef7eb2e8f9f7 12256 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
<> 144:ef7eb2e8f9f7 12257 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
<> 144:ef7eb2e8f9f7 12258 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
<> 144:ef7eb2e8f9f7 12259 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
<> 144:ef7eb2e8f9f7 12260 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
<> 144:ef7eb2e8f9f7 12261 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
<> 144:ef7eb2e8f9f7 12262
<> 144:ef7eb2e8f9f7 12263 /* Register: SAADC_CH_LIMIT */
<> 144:ef7eb2e8f9f7 12264 /* Description: Description cluster[0]: High/low limits for event monitoring a channel */
<> 144:ef7eb2e8f9f7 12265
<> 144:ef7eb2e8f9f7 12266 /* Bits 31..16 : High level limit */
<> 144:ef7eb2e8f9f7 12267 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
<> 144:ef7eb2e8f9f7 12268 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
<> 144:ef7eb2e8f9f7 12269
<> 144:ef7eb2e8f9f7 12270 /* Bits 15..0 : Low level limit */
<> 144:ef7eb2e8f9f7 12271 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
<> 144:ef7eb2e8f9f7 12272 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
<> 144:ef7eb2e8f9f7 12273
<> 144:ef7eb2e8f9f7 12274 /* Register: SAADC_RESOLUTION */
<> 144:ef7eb2e8f9f7 12275 /* Description: Resolution configuration */
<> 144:ef7eb2e8f9f7 12276
<> 144:ef7eb2e8f9f7 12277 /* Bits 2..0 : Set the resolution */
<> 144:ef7eb2e8f9f7 12278 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
<> 144:ef7eb2e8f9f7 12279 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
<> 144:ef7eb2e8f9f7 12280 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
<> 144:ef7eb2e8f9f7 12281 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
<> 144:ef7eb2e8f9f7 12282 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
<> 144:ef7eb2e8f9f7 12283 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
<> 144:ef7eb2e8f9f7 12284
<> 144:ef7eb2e8f9f7 12285 /* Register: SAADC_OVERSAMPLE */
<> 144:ef7eb2e8f9f7 12286 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
<> 144:ef7eb2e8f9f7 12287
<> 144:ef7eb2e8f9f7 12288 /* Bits 3..0 : Oversample control */
<> 144:ef7eb2e8f9f7 12289 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
<> 144:ef7eb2e8f9f7 12290 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
<> 144:ef7eb2e8f9f7 12291 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
<> 144:ef7eb2e8f9f7 12292 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
<> 144:ef7eb2e8f9f7 12293 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
<> 144:ef7eb2e8f9f7 12294 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
<> 144:ef7eb2e8f9f7 12295 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
<> 144:ef7eb2e8f9f7 12296 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
<> 144:ef7eb2e8f9f7 12297 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
<> 144:ef7eb2e8f9f7 12298 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
<> 144:ef7eb2e8f9f7 12299 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
<> 144:ef7eb2e8f9f7 12300
<> 144:ef7eb2e8f9f7 12301 /* Register: SAADC_SAMPLERATE */
<> 144:ef7eb2e8f9f7 12302 /* Description: Controls normal or continuous sample rate */
<> 144:ef7eb2e8f9f7 12303
<> 144:ef7eb2e8f9f7 12304 /* Bit 12 : Select mode for sample rate control */
<> 144:ef7eb2e8f9f7 12305 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 12306 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 12307 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
<> 144:ef7eb2e8f9f7 12308 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
<> 144:ef7eb2e8f9f7 12309
<> 144:ef7eb2e8f9f7 12310 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
<> 144:ef7eb2e8f9f7 12311 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
<> 144:ef7eb2e8f9f7 12312 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
<> 144:ef7eb2e8f9f7 12313
<> 144:ef7eb2e8f9f7 12314 /* Register: SAADC_RESULT_PTR */
<> 144:ef7eb2e8f9f7 12315 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 12316
<> 144:ef7eb2e8f9f7 12317 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 12318 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 12319 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 12320
<> 144:ef7eb2e8f9f7 12321 /* Register: SAADC_RESULT_MAXCNT */
<> 144:ef7eb2e8f9f7 12322 /* Description: Maximum number of buffer words to transfer */
<> 144:ef7eb2e8f9f7 12323
<> 144:ef7eb2e8f9f7 12324 /* Bits 14..0 : Maximum number of buffer words to transfer */
<> 144:ef7eb2e8f9f7 12325 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12326 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12327
<> 144:ef7eb2e8f9f7 12328 /* Register: SAADC_RESULT_AMOUNT */
<> 144:ef7eb2e8f9f7 12329 /* Description: Number of buffer words transferred since last START */
<> 144:ef7eb2e8f9f7 12330
<> 144:ef7eb2e8f9f7 12331 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
<> 144:ef7eb2e8f9f7 12332 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12333 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12334
<> 144:ef7eb2e8f9f7 12335
<> 144:ef7eb2e8f9f7 12336 /* Peripheral: SPI */
<> 144:ef7eb2e8f9f7 12337 /* Description: Serial Peripheral Interface 0 */
<> 144:ef7eb2e8f9f7 12338
<> 144:ef7eb2e8f9f7 12339 /* Register: SPI_INTENSET */
<> 144:ef7eb2e8f9f7 12340 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 12341
<> 144:ef7eb2e8f9f7 12342 /* Bit 2 : Write '1' to Enable interrupt for READY event */
<> 144:ef7eb2e8f9f7 12343 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 12344 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 12345 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12346 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12347 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12348
<> 144:ef7eb2e8f9f7 12349 /* Register: SPI_INTENCLR */
<> 144:ef7eb2e8f9f7 12350 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 12351
<> 144:ef7eb2e8f9f7 12352 /* Bit 2 : Write '1' to Disable interrupt for READY event */
<> 144:ef7eb2e8f9f7 12353 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
<> 144:ef7eb2e8f9f7 12354 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
<> 144:ef7eb2e8f9f7 12355 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12356 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12357 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12358
<> 144:ef7eb2e8f9f7 12359 /* Register: SPI_ENABLE */
<> 144:ef7eb2e8f9f7 12360 /* Description: Enable SPI */
<> 144:ef7eb2e8f9f7 12361
<> 144:ef7eb2e8f9f7 12362 /* Bits 3..0 : Enable or disable SPI */
<> 144:ef7eb2e8f9f7 12363 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 12364 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 12365 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
<> 144:ef7eb2e8f9f7 12366 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
<> 144:ef7eb2e8f9f7 12367
<> 144:ef7eb2e8f9f7 12368 /* Register: SPI_PSEL_SCK */
<> 144:ef7eb2e8f9f7 12369 /* Description: Pin select for SCK */
<> 144:ef7eb2e8f9f7 12370
<> 144:ef7eb2e8f9f7 12371 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
<> 144:ef7eb2e8f9f7 12372 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
<> 144:ef7eb2e8f9f7 12373 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
<> 144:ef7eb2e8f9f7 12374 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12375
<> 144:ef7eb2e8f9f7 12376 /* Register: SPI_PSEL_MOSI */
<> 144:ef7eb2e8f9f7 12377 /* Description: Pin select for MOSI */
<> 144:ef7eb2e8f9f7 12378
<> 144:ef7eb2e8f9f7 12379 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
<> 144:ef7eb2e8f9f7 12380 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
<> 144:ef7eb2e8f9f7 12381 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
<> 144:ef7eb2e8f9f7 12382 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12383
<> 144:ef7eb2e8f9f7 12384 /* Register: SPI_PSEL_MISO */
<> 144:ef7eb2e8f9f7 12385 /* Description: Pin select for MISO */
<> 144:ef7eb2e8f9f7 12386
<> 144:ef7eb2e8f9f7 12387 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
<> 144:ef7eb2e8f9f7 12388 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
<> 144:ef7eb2e8f9f7 12389 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
<> 144:ef7eb2e8f9f7 12390 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12391
<> 144:ef7eb2e8f9f7 12392 /* Register: SPI_RXD */
<> 144:ef7eb2e8f9f7 12393 /* Description: RXD register */
<> 144:ef7eb2e8f9f7 12394
<> 144:ef7eb2e8f9f7 12395 /* Bits 7..0 : RX data received. Double buffered */
<> 144:ef7eb2e8f9f7 12396 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
<> 144:ef7eb2e8f9f7 12397 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
<> 144:ef7eb2e8f9f7 12398
<> 144:ef7eb2e8f9f7 12399 /* Register: SPI_TXD */
<> 144:ef7eb2e8f9f7 12400 /* Description: TXD register */
<> 144:ef7eb2e8f9f7 12401
<> 144:ef7eb2e8f9f7 12402 /* Bits 7..0 : TX data to send. Double buffered */
<> 144:ef7eb2e8f9f7 12403 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
<> 144:ef7eb2e8f9f7 12404 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
<> 144:ef7eb2e8f9f7 12405
<> 144:ef7eb2e8f9f7 12406 /* Register: SPI_FREQUENCY */
<> 144:ef7eb2e8f9f7 12407 /* Description: SPI frequency */
<> 144:ef7eb2e8f9f7 12408
<> 144:ef7eb2e8f9f7 12409 /* Bits 31..0 : SPI master data rate */
<> 144:ef7eb2e8f9f7 12410 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 12411 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 12412 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
<> 144:ef7eb2e8f9f7 12413 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
<> 144:ef7eb2e8f9f7 12414 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
<> 144:ef7eb2e8f9f7 12415 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
<> 144:ef7eb2e8f9f7 12416 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
<> 144:ef7eb2e8f9f7 12417 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
<> 144:ef7eb2e8f9f7 12418 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
<> 144:ef7eb2e8f9f7 12419
<> 144:ef7eb2e8f9f7 12420 /* Register: SPI_CONFIG */
<> 144:ef7eb2e8f9f7 12421 /* Description: Configuration register */
<> 144:ef7eb2e8f9f7 12422
<> 144:ef7eb2e8f9f7 12423 /* Bit 2 : Serial clock (SCK) polarity */
<> 144:ef7eb2e8f9f7 12424 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
<> 144:ef7eb2e8f9f7 12425 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
<> 144:ef7eb2e8f9f7 12426 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
<> 144:ef7eb2e8f9f7 12427 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
<> 144:ef7eb2e8f9f7 12428
<> 144:ef7eb2e8f9f7 12429 /* Bit 1 : Serial clock (SCK) phase */
<> 144:ef7eb2e8f9f7 12430 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
<> 144:ef7eb2e8f9f7 12431 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
<> 144:ef7eb2e8f9f7 12432 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
<> 144:ef7eb2e8f9f7 12433 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
<> 144:ef7eb2e8f9f7 12434
<> 144:ef7eb2e8f9f7 12435 /* Bit 0 : Bit order */
<> 144:ef7eb2e8f9f7 12436 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
<> 144:ef7eb2e8f9f7 12437 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
<> 144:ef7eb2e8f9f7 12438 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
<> 144:ef7eb2e8f9f7 12439 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
<> 144:ef7eb2e8f9f7 12440
<> 144:ef7eb2e8f9f7 12441
<> 144:ef7eb2e8f9f7 12442 /* Peripheral: SPIM */
<> 144:ef7eb2e8f9f7 12443 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
<> 144:ef7eb2e8f9f7 12444
<> 144:ef7eb2e8f9f7 12445 /* Register: SPIM_SHORTS */
<> 144:ef7eb2e8f9f7 12446 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 12447
<> 144:ef7eb2e8f9f7 12448 /* Bit 17 : Shortcut between END event and START task */
<> 144:ef7eb2e8f9f7 12449 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
<> 144:ef7eb2e8f9f7 12450 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
<> 144:ef7eb2e8f9f7 12451 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 12452 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 12453
<> 144:ef7eb2e8f9f7 12454 /* Register: SPIM_INTENSET */
<> 144:ef7eb2e8f9f7 12455 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 12456
<> 144:ef7eb2e8f9f7 12457 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 12458 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 12459 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 12460 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12461 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12462 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12463
<> 144:ef7eb2e8f9f7 12464 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 12465 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 12466 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 12467 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12468 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12469 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12470
<> 144:ef7eb2e8f9f7 12471 /* Bit 6 : Write '1' to Enable interrupt for END event */
<> 144:ef7eb2e8f9f7 12472 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 12473 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 12474 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12475 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12476 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12477
<> 144:ef7eb2e8f9f7 12478 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 12479 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 12480 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 12481 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12482 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12483 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12484
<> 144:ef7eb2e8f9f7 12485 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 12486 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 12487 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 12488 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12489 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12490 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12491
<> 144:ef7eb2e8f9f7 12492 /* Register: SPIM_INTENCLR */
<> 144:ef7eb2e8f9f7 12493 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 12494
<> 144:ef7eb2e8f9f7 12495 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
<> 144:ef7eb2e8f9f7 12496 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
<> 144:ef7eb2e8f9f7 12497 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
<> 144:ef7eb2e8f9f7 12498 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12499 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12500 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12501
<> 144:ef7eb2e8f9f7 12502 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 12503 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 12504 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 12505 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12506 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12507 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12508
<> 144:ef7eb2e8f9f7 12509 /* Bit 6 : Write '1' to Disable interrupt for END event */
<> 144:ef7eb2e8f9f7 12510 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 12511 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 12512 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12513 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12514 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12515
<> 144:ef7eb2e8f9f7 12516 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 12517 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 12518 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 12519 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12520 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12521 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12522
<> 144:ef7eb2e8f9f7 12523 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 12524 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 12525 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 12526 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12527 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12528 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12529
<> 144:ef7eb2e8f9f7 12530 /* Register: SPIM_ENABLE */
<> 144:ef7eb2e8f9f7 12531 /* Description: Enable SPIM */
<> 144:ef7eb2e8f9f7 12532
<> 144:ef7eb2e8f9f7 12533 /* Bits 3..0 : Enable or disable SPIM */
<> 144:ef7eb2e8f9f7 12534 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 12535 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 12536 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
<> 144:ef7eb2e8f9f7 12537 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
<> 144:ef7eb2e8f9f7 12538
<> 144:ef7eb2e8f9f7 12539 /* Register: SPIM_PSEL_SCK */
<> 144:ef7eb2e8f9f7 12540 /* Description: Pin select for SCK */
<> 144:ef7eb2e8f9f7 12541
<> 144:ef7eb2e8f9f7 12542 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12543 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12544 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12545 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12546 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12547
<> 144:ef7eb2e8f9f7 12548 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12549 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12550 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12551
<> 144:ef7eb2e8f9f7 12552 /* Register: SPIM_PSEL_MOSI */
<> 144:ef7eb2e8f9f7 12553 /* Description: Pin select for MOSI signal */
<> 144:ef7eb2e8f9f7 12554
<> 144:ef7eb2e8f9f7 12555 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12556 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12557 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12558 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12559 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12560
<> 144:ef7eb2e8f9f7 12561 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12562 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12563 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12564
<> 144:ef7eb2e8f9f7 12565 /* Register: SPIM_PSEL_MISO */
<> 144:ef7eb2e8f9f7 12566 /* Description: Pin select for MISO signal */
<> 144:ef7eb2e8f9f7 12567
<> 144:ef7eb2e8f9f7 12568 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12569 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12570 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12571 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12572 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12573
<> 144:ef7eb2e8f9f7 12574 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12575 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12576 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12577
<> 144:ef7eb2e8f9f7 12578 /* Register: SPIM_FREQUENCY */
<> 144:ef7eb2e8f9f7 12579 /* Description: SPI frequency */
<> 144:ef7eb2e8f9f7 12580
<> 144:ef7eb2e8f9f7 12581 /* Bits 31..0 : SPI master data rate */
<> 144:ef7eb2e8f9f7 12582 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 12583 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 12584 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
<> 144:ef7eb2e8f9f7 12585 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
<> 144:ef7eb2e8f9f7 12586 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
<> 144:ef7eb2e8f9f7 12587 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
<> 144:ef7eb2e8f9f7 12588 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
<> 144:ef7eb2e8f9f7 12589 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
<> 144:ef7eb2e8f9f7 12590 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
<> 144:ef7eb2e8f9f7 12591
<> 144:ef7eb2e8f9f7 12592 /* Register: SPIM_RXD_PTR */
<> 144:ef7eb2e8f9f7 12593 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 12594
<> 144:ef7eb2e8f9f7 12595 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 12596 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 12597 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 12598
<> 144:ef7eb2e8f9f7 12599 /* Register: SPIM_RXD_MAXCNT */
<> 144:ef7eb2e8f9f7 12600 /* Description: Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 12601
<> 144:ef7eb2e8f9f7 12602 /* Bits 7..0 : Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 12603 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12604 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12605
<> 144:ef7eb2e8f9f7 12606 /* Register: SPIM_RXD_AMOUNT */
<> 144:ef7eb2e8f9f7 12607 /* Description: Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 12608
<> 144:ef7eb2e8f9f7 12609 /* Bits 7..0 : Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 12610 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12611 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12612
<> 144:ef7eb2e8f9f7 12613 /* Register: SPIM_RXD_LIST */
<> 144:ef7eb2e8f9f7 12614 /* Description: EasyDMA list type */
<> 144:ef7eb2e8f9f7 12615
<> 144:ef7eb2e8f9f7 12616 /* Bits 2..0 : List type */
<> 144:ef7eb2e8f9f7 12617 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
<> 144:ef7eb2e8f9f7 12618 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
<> 144:ef7eb2e8f9f7 12619 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
<> 144:ef7eb2e8f9f7 12620 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
<> 144:ef7eb2e8f9f7 12621
<> 144:ef7eb2e8f9f7 12622 /* Register: SPIM_TXD_PTR */
<> 144:ef7eb2e8f9f7 12623 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 12624
<> 144:ef7eb2e8f9f7 12625 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 12626 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 12627 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 12628
<> 144:ef7eb2e8f9f7 12629 /* Register: SPIM_TXD_MAXCNT */
<> 144:ef7eb2e8f9f7 12630 /* Description: Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 12631
<> 144:ef7eb2e8f9f7 12632 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 12633 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12634 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12635
<> 144:ef7eb2e8f9f7 12636 /* Register: SPIM_TXD_AMOUNT */
<> 144:ef7eb2e8f9f7 12637 /* Description: Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 12638
<> 144:ef7eb2e8f9f7 12639 /* Bits 7..0 : Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 12640 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12641 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12642
<> 144:ef7eb2e8f9f7 12643 /* Register: SPIM_TXD_LIST */
<> 144:ef7eb2e8f9f7 12644 /* Description: EasyDMA list type */
<> 144:ef7eb2e8f9f7 12645
<> 144:ef7eb2e8f9f7 12646 /* Bits 2..0 : List type */
<> 144:ef7eb2e8f9f7 12647 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
<> 144:ef7eb2e8f9f7 12648 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
<> 144:ef7eb2e8f9f7 12649 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
<> 144:ef7eb2e8f9f7 12650 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
<> 144:ef7eb2e8f9f7 12651
<> 144:ef7eb2e8f9f7 12652 /* Register: SPIM_CONFIG */
<> 144:ef7eb2e8f9f7 12653 /* Description: Configuration register */
<> 144:ef7eb2e8f9f7 12654
<> 144:ef7eb2e8f9f7 12655 /* Bit 2 : Serial clock (SCK) polarity */
<> 144:ef7eb2e8f9f7 12656 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
<> 144:ef7eb2e8f9f7 12657 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
<> 144:ef7eb2e8f9f7 12658 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
<> 144:ef7eb2e8f9f7 12659 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
<> 144:ef7eb2e8f9f7 12660
<> 144:ef7eb2e8f9f7 12661 /* Bit 1 : Serial clock (SCK) phase */
<> 144:ef7eb2e8f9f7 12662 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
<> 144:ef7eb2e8f9f7 12663 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
<> 144:ef7eb2e8f9f7 12664 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
<> 144:ef7eb2e8f9f7 12665 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
<> 144:ef7eb2e8f9f7 12666
<> 144:ef7eb2e8f9f7 12667 /* Bit 0 : Bit order */
<> 144:ef7eb2e8f9f7 12668 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
<> 144:ef7eb2e8f9f7 12669 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
<> 144:ef7eb2e8f9f7 12670 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
<> 144:ef7eb2e8f9f7 12671 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
<> 144:ef7eb2e8f9f7 12672
<> 144:ef7eb2e8f9f7 12673 /* Register: SPIM_ORC */
<> 144:ef7eb2e8f9f7 12674 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
<> 144:ef7eb2e8f9f7 12675
<> 144:ef7eb2e8f9f7 12676 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
<> 144:ef7eb2e8f9f7 12677 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
<> 144:ef7eb2e8f9f7 12678 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
<> 144:ef7eb2e8f9f7 12679
<> 144:ef7eb2e8f9f7 12680
<> 144:ef7eb2e8f9f7 12681 /* Peripheral: SPIS */
<> 144:ef7eb2e8f9f7 12682 /* Description: SPI Slave 0 */
<> 144:ef7eb2e8f9f7 12683
<> 144:ef7eb2e8f9f7 12684 /* Register: SPIS_SHORTS */
<> 144:ef7eb2e8f9f7 12685 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 12686
<> 144:ef7eb2e8f9f7 12687 /* Bit 2 : Shortcut between END event and ACQUIRE task */
<> 144:ef7eb2e8f9f7 12688 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
<> 144:ef7eb2e8f9f7 12689 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
<> 144:ef7eb2e8f9f7 12690 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 12691 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 12692
<> 144:ef7eb2e8f9f7 12693 /* Register: SPIS_INTENSET */
<> 144:ef7eb2e8f9f7 12694 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 12695
<> 144:ef7eb2e8f9f7 12696 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
<> 144:ef7eb2e8f9f7 12697 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
<> 144:ef7eb2e8f9f7 12698 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
<> 144:ef7eb2e8f9f7 12699 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12700 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12701 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12702
<> 144:ef7eb2e8f9f7 12703 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 12704 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 12705 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 12706 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12707 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12708 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12709
<> 144:ef7eb2e8f9f7 12710 /* Bit 1 : Write '1' to Enable interrupt for END event */
<> 144:ef7eb2e8f9f7 12711 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 12712 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 12713 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12714 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12715 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12716
<> 144:ef7eb2e8f9f7 12717 /* Register: SPIS_INTENCLR */
<> 144:ef7eb2e8f9f7 12718 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 12719
<> 144:ef7eb2e8f9f7 12720 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
<> 144:ef7eb2e8f9f7 12721 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
<> 144:ef7eb2e8f9f7 12722 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
<> 144:ef7eb2e8f9f7 12723 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12724 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12725 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12726
<> 144:ef7eb2e8f9f7 12727 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 12728 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 12729 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 12730 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12731 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12732 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12733
<> 144:ef7eb2e8f9f7 12734 /* Bit 1 : Write '1' to Disable interrupt for END event */
<> 144:ef7eb2e8f9f7 12735 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
<> 144:ef7eb2e8f9f7 12736 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
<> 144:ef7eb2e8f9f7 12737 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12738 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12739 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12740
<> 144:ef7eb2e8f9f7 12741 /* Register: SPIS_SEMSTAT */
<> 144:ef7eb2e8f9f7 12742 /* Description: Semaphore status register */
<> 144:ef7eb2e8f9f7 12743
<> 144:ef7eb2e8f9f7 12744 /* Bits 1..0 : Semaphore status */
<> 144:ef7eb2e8f9f7 12745 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
<> 144:ef7eb2e8f9f7 12746 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
<> 144:ef7eb2e8f9f7 12747 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
<> 144:ef7eb2e8f9f7 12748 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
<> 144:ef7eb2e8f9f7 12749 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
<> 144:ef7eb2e8f9f7 12750 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
<> 144:ef7eb2e8f9f7 12751
<> 144:ef7eb2e8f9f7 12752 /* Register: SPIS_STATUS */
<> 144:ef7eb2e8f9f7 12753 /* Description: Status from last transaction */
<> 144:ef7eb2e8f9f7 12754
<> 144:ef7eb2e8f9f7 12755 /* Bit 1 : RX buffer overflow detected, and prevented */
<> 144:ef7eb2e8f9f7 12756 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
<> 144:ef7eb2e8f9f7 12757 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
<> 144:ef7eb2e8f9f7 12758 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 12759 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 12760 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
<> 144:ef7eb2e8f9f7 12761
<> 144:ef7eb2e8f9f7 12762 /* Bit 0 : TX buffer over-read detected, and prevented */
<> 144:ef7eb2e8f9f7 12763 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
<> 144:ef7eb2e8f9f7 12764 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
<> 144:ef7eb2e8f9f7 12765 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 12766 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 12767 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
<> 144:ef7eb2e8f9f7 12768
<> 144:ef7eb2e8f9f7 12769 /* Register: SPIS_ENABLE */
<> 144:ef7eb2e8f9f7 12770 /* Description: Enable SPI slave */
<> 144:ef7eb2e8f9f7 12771
<> 144:ef7eb2e8f9f7 12772 /* Bits 3..0 : Enable or disable SPI slave */
<> 144:ef7eb2e8f9f7 12773 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 12774 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 12775 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
<> 144:ef7eb2e8f9f7 12776 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
<> 144:ef7eb2e8f9f7 12777
<> 144:ef7eb2e8f9f7 12778 /* Register: SPIS_PSEL_SCK */
<> 144:ef7eb2e8f9f7 12779 /* Description: Pin select for SCK */
<> 144:ef7eb2e8f9f7 12780
<> 144:ef7eb2e8f9f7 12781 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12782 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12783 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12784 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12785 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12786
<> 144:ef7eb2e8f9f7 12787 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12788 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12789 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12790
<> 144:ef7eb2e8f9f7 12791 /* Register: SPIS_PSEL_MISO */
<> 144:ef7eb2e8f9f7 12792 /* Description: Pin select for MISO signal */
<> 144:ef7eb2e8f9f7 12793
<> 144:ef7eb2e8f9f7 12794 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12795 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12796 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12797 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12798 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12799
<> 144:ef7eb2e8f9f7 12800 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12801 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12802 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12803
<> 144:ef7eb2e8f9f7 12804 /* Register: SPIS_PSEL_MOSI */
<> 144:ef7eb2e8f9f7 12805 /* Description: Pin select for MOSI signal */
<> 144:ef7eb2e8f9f7 12806
<> 144:ef7eb2e8f9f7 12807 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12808 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12809 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12810 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12811 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12812
<> 144:ef7eb2e8f9f7 12813 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12814 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12815 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12816
<> 144:ef7eb2e8f9f7 12817 /* Register: SPIS_PSEL_CSN */
<> 144:ef7eb2e8f9f7 12818 /* Description: Pin select for CSN signal */
<> 144:ef7eb2e8f9f7 12819
<> 144:ef7eb2e8f9f7 12820 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 12821 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 12822 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 12823 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 12824 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 12825
<> 144:ef7eb2e8f9f7 12826 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 12827 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 12828 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 12829
<> 144:ef7eb2e8f9f7 12830 /* Register: SPIS_RXD_PTR */
<> 144:ef7eb2e8f9f7 12831 /* Description: RXD data pointer */
<> 144:ef7eb2e8f9f7 12832
<> 144:ef7eb2e8f9f7 12833 /* Bits 31..0 : RXD data pointer */
<> 144:ef7eb2e8f9f7 12834 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 12835 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 12836
<> 144:ef7eb2e8f9f7 12837 /* Register: SPIS_RXD_MAXCNT */
<> 144:ef7eb2e8f9f7 12838 /* Description: Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 12839
<> 144:ef7eb2e8f9f7 12840 /* Bits 7..0 : Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 12841 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12842 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12843
<> 144:ef7eb2e8f9f7 12844 /* Register: SPIS_RXD_AMOUNT */
<> 144:ef7eb2e8f9f7 12845 /* Description: Number of bytes received in last granted transaction */
<> 144:ef7eb2e8f9f7 12846
<> 144:ef7eb2e8f9f7 12847 /* Bits 7..0 : Number of bytes received in the last granted transaction */
<> 144:ef7eb2e8f9f7 12848 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12849 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12850
<> 144:ef7eb2e8f9f7 12851 /* Register: SPIS_TXD_PTR */
<> 144:ef7eb2e8f9f7 12852 /* Description: TXD data pointer */
<> 144:ef7eb2e8f9f7 12853
<> 144:ef7eb2e8f9f7 12854 /* Bits 31..0 : TXD data pointer */
<> 144:ef7eb2e8f9f7 12855 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 12856 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 12857
<> 144:ef7eb2e8f9f7 12858 /* Register: SPIS_TXD_MAXCNT */
<> 144:ef7eb2e8f9f7 12859 /* Description: Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 12860
<> 144:ef7eb2e8f9f7 12861 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 12862 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12863 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 12864
<> 144:ef7eb2e8f9f7 12865 /* Register: SPIS_TXD_AMOUNT */
<> 144:ef7eb2e8f9f7 12866 /* Description: Number of bytes transmitted in last granted transaction */
<> 144:ef7eb2e8f9f7 12867
<> 144:ef7eb2e8f9f7 12868 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
<> 144:ef7eb2e8f9f7 12869 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12870 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 12871
<> 144:ef7eb2e8f9f7 12872 /* Register: SPIS_CONFIG */
<> 144:ef7eb2e8f9f7 12873 /* Description: Configuration register */
<> 144:ef7eb2e8f9f7 12874
<> 144:ef7eb2e8f9f7 12875 /* Bit 2 : Serial clock (SCK) polarity */
<> 144:ef7eb2e8f9f7 12876 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
<> 144:ef7eb2e8f9f7 12877 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
<> 144:ef7eb2e8f9f7 12878 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
<> 144:ef7eb2e8f9f7 12879 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
<> 144:ef7eb2e8f9f7 12880
<> 144:ef7eb2e8f9f7 12881 /* Bit 1 : Serial clock (SCK) phase */
<> 144:ef7eb2e8f9f7 12882 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
<> 144:ef7eb2e8f9f7 12883 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
<> 144:ef7eb2e8f9f7 12884 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
<> 144:ef7eb2e8f9f7 12885 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
<> 144:ef7eb2e8f9f7 12886
<> 144:ef7eb2e8f9f7 12887 /* Bit 0 : Bit order */
<> 144:ef7eb2e8f9f7 12888 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
<> 144:ef7eb2e8f9f7 12889 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
<> 144:ef7eb2e8f9f7 12890 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
<> 144:ef7eb2e8f9f7 12891 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
<> 144:ef7eb2e8f9f7 12892
<> 144:ef7eb2e8f9f7 12893 /* Register: SPIS_DEF */
<> 144:ef7eb2e8f9f7 12894 /* Description: Default character. Character clocked out in case of an ignored transaction. */
<> 144:ef7eb2e8f9f7 12895
<> 144:ef7eb2e8f9f7 12896 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
<> 144:ef7eb2e8f9f7 12897 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
<> 144:ef7eb2e8f9f7 12898 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
<> 144:ef7eb2e8f9f7 12899
<> 144:ef7eb2e8f9f7 12900 /* Register: SPIS_ORC */
<> 144:ef7eb2e8f9f7 12901 /* Description: Over-read character */
<> 144:ef7eb2e8f9f7 12902
<> 144:ef7eb2e8f9f7 12903 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
<> 144:ef7eb2e8f9f7 12904 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
<> 144:ef7eb2e8f9f7 12905 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
<> 144:ef7eb2e8f9f7 12906
<> 144:ef7eb2e8f9f7 12907
<> 144:ef7eb2e8f9f7 12908 /* Peripheral: TEMP */
<> 144:ef7eb2e8f9f7 12909 /* Description: Temperature Sensor */
<> 144:ef7eb2e8f9f7 12910
<> 144:ef7eb2e8f9f7 12911 /* Register: TEMP_INTENSET */
<> 144:ef7eb2e8f9f7 12912 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 12913
<> 144:ef7eb2e8f9f7 12914 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
<> 144:ef7eb2e8f9f7 12915 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
<> 144:ef7eb2e8f9f7 12916 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
<> 144:ef7eb2e8f9f7 12917 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12918 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12919 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 12920
<> 144:ef7eb2e8f9f7 12921 /* Register: TEMP_INTENCLR */
<> 144:ef7eb2e8f9f7 12922 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 12923
<> 144:ef7eb2e8f9f7 12924 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
<> 144:ef7eb2e8f9f7 12925 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
<> 144:ef7eb2e8f9f7 12926 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
<> 144:ef7eb2e8f9f7 12927 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 12928 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 12929 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 12930
<> 144:ef7eb2e8f9f7 12931 /* Register: TEMP_TEMP */
<> 144:ef7eb2e8f9f7 12932 /* Description: Temperature in degC (0.25deg steps) */
<> 144:ef7eb2e8f9f7 12933
<> 144:ef7eb2e8f9f7 12934 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
<> 144:ef7eb2e8f9f7 12935 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
<> 144:ef7eb2e8f9f7 12936 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
<> 144:ef7eb2e8f9f7 12937
<> 144:ef7eb2e8f9f7 12938 /* Register: TEMP_A0 */
<> 144:ef7eb2e8f9f7 12939 /* Description: Slope of 1st piece wise linear function */
<> 144:ef7eb2e8f9f7 12940
<> 144:ef7eb2e8f9f7 12941 /* Bits 11..0 : Slope of 1st piece wise linear function */
<> 144:ef7eb2e8f9f7 12942 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
<> 144:ef7eb2e8f9f7 12943 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
<> 144:ef7eb2e8f9f7 12944
<> 144:ef7eb2e8f9f7 12945 /* Register: TEMP_A1 */
<> 144:ef7eb2e8f9f7 12946 /* Description: Slope of 2nd piece wise linear function */
<> 144:ef7eb2e8f9f7 12947
<> 144:ef7eb2e8f9f7 12948 /* Bits 11..0 : Slope of 2nd piece wise linear function */
<> 144:ef7eb2e8f9f7 12949 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
<> 144:ef7eb2e8f9f7 12950 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
<> 144:ef7eb2e8f9f7 12951
<> 144:ef7eb2e8f9f7 12952 /* Register: TEMP_A2 */
<> 144:ef7eb2e8f9f7 12953 /* Description: Slope of 3rd piece wise linear function */
<> 144:ef7eb2e8f9f7 12954
<> 144:ef7eb2e8f9f7 12955 /* Bits 11..0 : Slope of 3rd piece wise linear function */
<> 144:ef7eb2e8f9f7 12956 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
<> 144:ef7eb2e8f9f7 12957 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
<> 144:ef7eb2e8f9f7 12958
<> 144:ef7eb2e8f9f7 12959 /* Register: TEMP_A3 */
<> 144:ef7eb2e8f9f7 12960 /* Description: Slope of 4th piece wise linear function */
<> 144:ef7eb2e8f9f7 12961
<> 144:ef7eb2e8f9f7 12962 /* Bits 11..0 : Slope of 4th piece wise linear function */
<> 144:ef7eb2e8f9f7 12963 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
<> 144:ef7eb2e8f9f7 12964 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
<> 144:ef7eb2e8f9f7 12965
<> 144:ef7eb2e8f9f7 12966 /* Register: TEMP_A4 */
<> 144:ef7eb2e8f9f7 12967 /* Description: Slope of 5th piece wise linear function */
<> 144:ef7eb2e8f9f7 12968
<> 144:ef7eb2e8f9f7 12969 /* Bits 11..0 : Slope of 5th piece wise linear function */
<> 144:ef7eb2e8f9f7 12970 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
<> 144:ef7eb2e8f9f7 12971 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
<> 144:ef7eb2e8f9f7 12972
<> 144:ef7eb2e8f9f7 12973 /* Register: TEMP_A5 */
<> 144:ef7eb2e8f9f7 12974 /* Description: Slope of 6th piece wise linear function */
<> 144:ef7eb2e8f9f7 12975
<> 144:ef7eb2e8f9f7 12976 /* Bits 11..0 : Slope of 6th piece wise linear function */
<> 144:ef7eb2e8f9f7 12977 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
<> 144:ef7eb2e8f9f7 12978 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
<> 144:ef7eb2e8f9f7 12979
<> 144:ef7eb2e8f9f7 12980 /* Register: TEMP_B0 */
<> 144:ef7eb2e8f9f7 12981 /* Description: y-intercept of 1st piece wise linear function */
<> 144:ef7eb2e8f9f7 12982
<> 144:ef7eb2e8f9f7 12983 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
<> 144:ef7eb2e8f9f7 12984 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
<> 144:ef7eb2e8f9f7 12985 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
<> 144:ef7eb2e8f9f7 12986
<> 144:ef7eb2e8f9f7 12987 /* Register: TEMP_B1 */
<> 144:ef7eb2e8f9f7 12988 /* Description: y-intercept of 2nd piece wise linear function */
<> 144:ef7eb2e8f9f7 12989
<> 144:ef7eb2e8f9f7 12990 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
<> 144:ef7eb2e8f9f7 12991 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
<> 144:ef7eb2e8f9f7 12992 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
<> 144:ef7eb2e8f9f7 12993
<> 144:ef7eb2e8f9f7 12994 /* Register: TEMP_B2 */
<> 144:ef7eb2e8f9f7 12995 /* Description: y-intercept of 3rd piece wise linear function */
<> 144:ef7eb2e8f9f7 12996
<> 144:ef7eb2e8f9f7 12997 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
<> 144:ef7eb2e8f9f7 12998 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
<> 144:ef7eb2e8f9f7 12999 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
<> 144:ef7eb2e8f9f7 13000
<> 144:ef7eb2e8f9f7 13001 /* Register: TEMP_B3 */
<> 144:ef7eb2e8f9f7 13002 /* Description: y-intercept of 4th piece wise linear function */
<> 144:ef7eb2e8f9f7 13003
<> 144:ef7eb2e8f9f7 13004 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
<> 144:ef7eb2e8f9f7 13005 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
<> 144:ef7eb2e8f9f7 13006 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
<> 144:ef7eb2e8f9f7 13007
<> 144:ef7eb2e8f9f7 13008 /* Register: TEMP_B4 */
<> 144:ef7eb2e8f9f7 13009 /* Description: y-intercept of 5th piece wise linear function */
<> 144:ef7eb2e8f9f7 13010
<> 144:ef7eb2e8f9f7 13011 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
<> 144:ef7eb2e8f9f7 13012 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
<> 144:ef7eb2e8f9f7 13013 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
<> 144:ef7eb2e8f9f7 13014
<> 144:ef7eb2e8f9f7 13015 /* Register: TEMP_B5 */
<> 144:ef7eb2e8f9f7 13016 /* Description: y-intercept of 6th piece wise linear function */
<> 144:ef7eb2e8f9f7 13017
<> 144:ef7eb2e8f9f7 13018 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
<> 144:ef7eb2e8f9f7 13019 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
<> 144:ef7eb2e8f9f7 13020 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
<> 144:ef7eb2e8f9f7 13021
<> 144:ef7eb2e8f9f7 13022 /* Register: TEMP_T0 */
<> 144:ef7eb2e8f9f7 13023 /* Description: End point of 1st piece wise linear function */
<> 144:ef7eb2e8f9f7 13024
<> 144:ef7eb2e8f9f7 13025 /* Bits 7..0 : End point of 1st piece wise linear function */
<> 144:ef7eb2e8f9f7 13026 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
<> 144:ef7eb2e8f9f7 13027 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
<> 144:ef7eb2e8f9f7 13028
<> 144:ef7eb2e8f9f7 13029 /* Register: TEMP_T1 */
<> 144:ef7eb2e8f9f7 13030 /* Description: End point of 2nd piece wise linear function */
<> 144:ef7eb2e8f9f7 13031
<> 144:ef7eb2e8f9f7 13032 /* Bits 7..0 : End point of 2nd piece wise linear function */
<> 144:ef7eb2e8f9f7 13033 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
<> 144:ef7eb2e8f9f7 13034 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
<> 144:ef7eb2e8f9f7 13035
<> 144:ef7eb2e8f9f7 13036 /* Register: TEMP_T2 */
<> 144:ef7eb2e8f9f7 13037 /* Description: End point of 3rd piece wise linear function */
<> 144:ef7eb2e8f9f7 13038
<> 144:ef7eb2e8f9f7 13039 /* Bits 7..0 : End point of 3rd piece wise linear function */
<> 144:ef7eb2e8f9f7 13040 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
<> 144:ef7eb2e8f9f7 13041 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
<> 144:ef7eb2e8f9f7 13042
<> 144:ef7eb2e8f9f7 13043 /* Register: TEMP_T3 */
<> 144:ef7eb2e8f9f7 13044 /* Description: End point of 4th piece wise linear function */
<> 144:ef7eb2e8f9f7 13045
<> 144:ef7eb2e8f9f7 13046 /* Bits 7..0 : End point of 4th piece wise linear function */
<> 144:ef7eb2e8f9f7 13047 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
<> 144:ef7eb2e8f9f7 13048 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
<> 144:ef7eb2e8f9f7 13049
<> 144:ef7eb2e8f9f7 13050 /* Register: TEMP_T4 */
<> 144:ef7eb2e8f9f7 13051 /* Description: End point of 5th piece wise linear function */
<> 144:ef7eb2e8f9f7 13052
<> 144:ef7eb2e8f9f7 13053 /* Bits 7..0 : End point of 5th piece wise linear function */
<> 144:ef7eb2e8f9f7 13054 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
<> 144:ef7eb2e8f9f7 13055 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
<> 144:ef7eb2e8f9f7 13056
<> 144:ef7eb2e8f9f7 13057
<> 144:ef7eb2e8f9f7 13058 /* Peripheral: TIMER */
<> 144:ef7eb2e8f9f7 13059 /* Description: Timer/Counter 0 */
<> 144:ef7eb2e8f9f7 13060
<> 144:ef7eb2e8f9f7 13061 /* Register: TIMER_SHORTS */
<> 144:ef7eb2e8f9f7 13062 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 13063
<> 144:ef7eb2e8f9f7 13064 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
<> 144:ef7eb2e8f9f7 13065 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
<> 144:ef7eb2e8f9f7 13066 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
<> 144:ef7eb2e8f9f7 13067 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13068 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13069
<> 144:ef7eb2e8f9f7 13070 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
<> 144:ef7eb2e8f9f7 13071 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
<> 144:ef7eb2e8f9f7 13072 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
<> 144:ef7eb2e8f9f7 13073 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13074 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13075
<> 144:ef7eb2e8f9f7 13076 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
<> 144:ef7eb2e8f9f7 13077 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
<> 144:ef7eb2e8f9f7 13078 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
<> 144:ef7eb2e8f9f7 13079 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13080 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13081
<> 144:ef7eb2e8f9f7 13082 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
<> 144:ef7eb2e8f9f7 13083 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
<> 144:ef7eb2e8f9f7 13084 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
<> 144:ef7eb2e8f9f7 13085 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13086 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13087
<> 144:ef7eb2e8f9f7 13088 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
<> 144:ef7eb2e8f9f7 13089 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
<> 144:ef7eb2e8f9f7 13090 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
<> 144:ef7eb2e8f9f7 13091 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13092 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13093
<> 144:ef7eb2e8f9f7 13094 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
<> 144:ef7eb2e8f9f7 13095 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
<> 144:ef7eb2e8f9f7 13096 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
<> 144:ef7eb2e8f9f7 13097 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13098 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13099
<> 144:ef7eb2e8f9f7 13100 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
<> 144:ef7eb2e8f9f7 13101 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
<> 144:ef7eb2e8f9f7 13102 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
<> 144:ef7eb2e8f9f7 13103 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13104 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13105
<> 144:ef7eb2e8f9f7 13106 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
<> 144:ef7eb2e8f9f7 13107 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
<> 144:ef7eb2e8f9f7 13108 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
<> 144:ef7eb2e8f9f7 13109 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13110 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13111
<> 144:ef7eb2e8f9f7 13112 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
<> 144:ef7eb2e8f9f7 13113 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
<> 144:ef7eb2e8f9f7 13114 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
<> 144:ef7eb2e8f9f7 13115 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13116 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13117
<> 144:ef7eb2e8f9f7 13118 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
<> 144:ef7eb2e8f9f7 13119 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
<> 144:ef7eb2e8f9f7 13120 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
<> 144:ef7eb2e8f9f7 13121 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13122 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13123
<> 144:ef7eb2e8f9f7 13124 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
<> 144:ef7eb2e8f9f7 13125 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
<> 144:ef7eb2e8f9f7 13126 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
<> 144:ef7eb2e8f9f7 13127 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13128 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13129
<> 144:ef7eb2e8f9f7 13130 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
<> 144:ef7eb2e8f9f7 13131 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
<> 144:ef7eb2e8f9f7 13132 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
<> 144:ef7eb2e8f9f7 13133 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13134 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13135
<> 144:ef7eb2e8f9f7 13136 /* Register: TIMER_INTENSET */
<> 144:ef7eb2e8f9f7 13137 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 13138
<> 144:ef7eb2e8f9f7 13139 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
<> 144:ef7eb2e8f9f7 13140 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
<> 144:ef7eb2e8f9f7 13141 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
<> 144:ef7eb2e8f9f7 13142 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13143 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13144 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13145
<> 144:ef7eb2e8f9f7 13146 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
<> 144:ef7eb2e8f9f7 13147 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
<> 144:ef7eb2e8f9f7 13148 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
<> 144:ef7eb2e8f9f7 13149 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13150 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13151 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13152
<> 144:ef7eb2e8f9f7 13153 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 13154 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 13155 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 13156 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13157 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13158 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13159
<> 144:ef7eb2e8f9f7 13160 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 13161 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 13162 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 13163 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13164 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13165 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13166
<> 144:ef7eb2e8f9f7 13167 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 13168 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 13169 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 13170 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13171 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13172 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13173
<> 144:ef7eb2e8f9f7 13174 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 13175 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 13176 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 13177 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13178 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13179 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13180
<> 144:ef7eb2e8f9f7 13181 /* Register: TIMER_INTENCLR */
<> 144:ef7eb2e8f9f7 13182 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 13183
<> 144:ef7eb2e8f9f7 13184 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
<> 144:ef7eb2e8f9f7 13185 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
<> 144:ef7eb2e8f9f7 13186 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
<> 144:ef7eb2e8f9f7 13187 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13188 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13189 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13190
<> 144:ef7eb2e8f9f7 13191 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
<> 144:ef7eb2e8f9f7 13192 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
<> 144:ef7eb2e8f9f7 13193 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
<> 144:ef7eb2e8f9f7 13194 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13195 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13196 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13197
<> 144:ef7eb2e8f9f7 13198 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
<> 144:ef7eb2e8f9f7 13199 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 13200 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
<> 144:ef7eb2e8f9f7 13201 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13202 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13203 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13204
<> 144:ef7eb2e8f9f7 13205 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
<> 144:ef7eb2e8f9f7 13206 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 13207 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
<> 144:ef7eb2e8f9f7 13208 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13209 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13210 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13211
<> 144:ef7eb2e8f9f7 13212 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
<> 144:ef7eb2e8f9f7 13213 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 13214 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
<> 144:ef7eb2e8f9f7 13215 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13216 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13217 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13218
<> 144:ef7eb2e8f9f7 13219 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
<> 144:ef7eb2e8f9f7 13220 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 13221 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
<> 144:ef7eb2e8f9f7 13222 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13223 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13224 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13225
<> 144:ef7eb2e8f9f7 13226 /* Register: TIMER_MODE */
<> 144:ef7eb2e8f9f7 13227 /* Description: Timer mode selection */
<> 144:ef7eb2e8f9f7 13228
<> 144:ef7eb2e8f9f7 13229 /* Bits 1..0 : Timer mode */
<> 144:ef7eb2e8f9f7 13230 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
<> 144:ef7eb2e8f9f7 13231 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
<> 144:ef7eb2e8f9f7 13232 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
<> 144:ef7eb2e8f9f7 13233 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
<> 144:ef7eb2e8f9f7 13234 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
<> 144:ef7eb2e8f9f7 13235
<> 144:ef7eb2e8f9f7 13236 /* Register: TIMER_BITMODE */
<> 144:ef7eb2e8f9f7 13237 /* Description: Configure the number of bits used by the TIMER */
<> 144:ef7eb2e8f9f7 13238
<> 144:ef7eb2e8f9f7 13239 /* Bits 1..0 : Timer bit width */
<> 144:ef7eb2e8f9f7 13240 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
<> 144:ef7eb2e8f9f7 13241 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
<> 144:ef7eb2e8f9f7 13242 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
<> 144:ef7eb2e8f9f7 13243 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
<> 144:ef7eb2e8f9f7 13244 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
<> 144:ef7eb2e8f9f7 13245 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
<> 144:ef7eb2e8f9f7 13246
<> 144:ef7eb2e8f9f7 13247 /* Register: TIMER_PRESCALER */
<> 144:ef7eb2e8f9f7 13248 /* Description: Timer prescaler register */
<> 144:ef7eb2e8f9f7 13249
<> 144:ef7eb2e8f9f7 13250 /* Bits 3..0 : Prescaler value */
<> 144:ef7eb2e8f9f7 13251 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
<> 144:ef7eb2e8f9f7 13252 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
<> 144:ef7eb2e8f9f7 13253
<> 144:ef7eb2e8f9f7 13254 /* Register: TIMER_CC */
<> 144:ef7eb2e8f9f7 13255 /* Description: Description collection[0]: Capture/Compare register 0 */
<> 144:ef7eb2e8f9f7 13256
<> 144:ef7eb2e8f9f7 13257 /* Bits 31..0 : Capture/Compare value */
<> 144:ef7eb2e8f9f7 13258 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
<> 144:ef7eb2e8f9f7 13259 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
<> 144:ef7eb2e8f9f7 13260
<> 144:ef7eb2e8f9f7 13261
<> 144:ef7eb2e8f9f7 13262 /* Peripheral: TWI */
<> 144:ef7eb2e8f9f7 13263 /* Description: I2C compatible Two-Wire Interface 0 */
<> 144:ef7eb2e8f9f7 13264
<> 144:ef7eb2e8f9f7 13265 /* Register: TWI_SHORTS */
<> 144:ef7eb2e8f9f7 13266 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 13267
<> 144:ef7eb2e8f9f7 13268 /* Bit 1 : Shortcut between BB event and STOP task */
<> 144:ef7eb2e8f9f7 13269 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
<> 144:ef7eb2e8f9f7 13270 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
<> 144:ef7eb2e8f9f7 13271 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13272 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13273
<> 144:ef7eb2e8f9f7 13274 /* Bit 0 : Shortcut between BB event and SUSPEND task */
<> 144:ef7eb2e8f9f7 13275 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13276 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13277 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13278 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13279
<> 144:ef7eb2e8f9f7 13280 /* Register: TWI_INTENSET */
<> 144:ef7eb2e8f9f7 13281 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 13282
<> 144:ef7eb2e8f9f7 13283 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
<> 144:ef7eb2e8f9f7 13284 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13285 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13286 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13287 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13288 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13289
<> 144:ef7eb2e8f9f7 13290 /* Bit 14 : Write '1' to Enable interrupt for BB event */
<> 144:ef7eb2e8f9f7 13291 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
<> 144:ef7eb2e8f9f7 13292 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
<> 144:ef7eb2e8f9f7 13293 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13294 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13295 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13296
<> 144:ef7eb2e8f9f7 13297 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13298 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13299 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13300 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13301 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13302 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13303
<> 144:ef7eb2e8f9f7 13304 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
<> 144:ef7eb2e8f9f7 13305 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
<> 144:ef7eb2e8f9f7 13306 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
<> 144:ef7eb2e8f9f7 13307 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13308 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13309 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13310
<> 144:ef7eb2e8f9f7 13311 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
<> 144:ef7eb2e8f9f7 13312 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
<> 144:ef7eb2e8f9f7 13313 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
<> 144:ef7eb2e8f9f7 13314 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13315 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13316 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13317
<> 144:ef7eb2e8f9f7 13318 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13319 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13320 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13321 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13322 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13323 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13324
<> 144:ef7eb2e8f9f7 13325 /* Register: TWI_INTENCLR */
<> 144:ef7eb2e8f9f7 13326 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 13327
<> 144:ef7eb2e8f9f7 13328 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
<> 144:ef7eb2e8f9f7 13329 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13330 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13331 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13332 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13333 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13334
<> 144:ef7eb2e8f9f7 13335 /* Bit 14 : Write '1' to Disable interrupt for BB event */
<> 144:ef7eb2e8f9f7 13336 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
<> 144:ef7eb2e8f9f7 13337 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
<> 144:ef7eb2e8f9f7 13338 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13339 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13340 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13341
<> 144:ef7eb2e8f9f7 13342 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13343 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13344 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13345 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13346 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13347 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13348
<> 144:ef7eb2e8f9f7 13349 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
<> 144:ef7eb2e8f9f7 13350 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
<> 144:ef7eb2e8f9f7 13351 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
<> 144:ef7eb2e8f9f7 13352 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13353 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13354 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13355
<> 144:ef7eb2e8f9f7 13356 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
<> 144:ef7eb2e8f9f7 13357 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
<> 144:ef7eb2e8f9f7 13358 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
<> 144:ef7eb2e8f9f7 13359 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13360 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13361 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13362
<> 144:ef7eb2e8f9f7 13363 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13364 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13365 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13366 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13367 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13368 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13369
<> 144:ef7eb2e8f9f7 13370 /* Register: TWI_ERRORSRC */
<> 144:ef7eb2e8f9f7 13371 /* Description: Error source */
<> 144:ef7eb2e8f9f7 13372
<> 144:ef7eb2e8f9f7 13373 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
<> 144:ef7eb2e8f9f7 13374 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
<> 144:ef7eb2e8f9f7 13375 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
<> 144:ef7eb2e8f9f7 13376 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 13377 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 13378
<> 144:ef7eb2e8f9f7 13379 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
<> 144:ef7eb2e8f9f7 13380 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
<> 144:ef7eb2e8f9f7 13381 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
<> 144:ef7eb2e8f9f7 13382 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 13383 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 13384
<> 144:ef7eb2e8f9f7 13385 /* Bit 0 : Overrun error */
<> 144:ef7eb2e8f9f7 13386 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
<> 144:ef7eb2e8f9f7 13387 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
<> 144:ef7eb2e8f9f7 13388 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
<> 144:ef7eb2e8f9f7 13389 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
<> 144:ef7eb2e8f9f7 13390
<> 144:ef7eb2e8f9f7 13391 /* Register: TWI_ENABLE */
<> 144:ef7eb2e8f9f7 13392 /* Description: Enable TWI */
<> 144:ef7eb2e8f9f7 13393
<> 144:ef7eb2e8f9f7 13394 /* Bits 3..0 : Enable or disable TWI */
<> 144:ef7eb2e8f9f7 13395 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 13396 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 13397 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
<> 144:ef7eb2e8f9f7 13398 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
<> 144:ef7eb2e8f9f7 13399
<> 144:ef7eb2e8f9f7 13400 /* Register: TWI_PSELSCL */
<> 144:ef7eb2e8f9f7 13401 /* Description: Pin select for SCL */
<> 144:ef7eb2e8f9f7 13402
<> 144:ef7eb2e8f9f7 13403 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
<> 144:ef7eb2e8f9f7 13404 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
<> 144:ef7eb2e8f9f7 13405 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
<> 144:ef7eb2e8f9f7 13406 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 13407
<> 144:ef7eb2e8f9f7 13408 /* Register: TWI_PSELSDA */
<> 144:ef7eb2e8f9f7 13409 /* Description: Pin select for SDA */
<> 144:ef7eb2e8f9f7 13410
<> 144:ef7eb2e8f9f7 13411 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
<> 144:ef7eb2e8f9f7 13412 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
<> 144:ef7eb2e8f9f7 13413 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
<> 144:ef7eb2e8f9f7 13414 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 13415
<> 144:ef7eb2e8f9f7 13416 /* Register: TWI_RXD */
<> 144:ef7eb2e8f9f7 13417 /* Description: RXD register */
<> 144:ef7eb2e8f9f7 13418
<> 144:ef7eb2e8f9f7 13419 /* Bits 7..0 : RXD register */
<> 144:ef7eb2e8f9f7 13420 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
<> 144:ef7eb2e8f9f7 13421 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
<> 144:ef7eb2e8f9f7 13422
<> 144:ef7eb2e8f9f7 13423 /* Register: TWI_TXD */
<> 144:ef7eb2e8f9f7 13424 /* Description: TXD register */
<> 144:ef7eb2e8f9f7 13425
<> 144:ef7eb2e8f9f7 13426 /* Bits 7..0 : TXD register */
<> 144:ef7eb2e8f9f7 13427 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
<> 144:ef7eb2e8f9f7 13428 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
<> 144:ef7eb2e8f9f7 13429
<> 144:ef7eb2e8f9f7 13430 /* Register: TWI_FREQUENCY */
<> 144:ef7eb2e8f9f7 13431 /* Description: TWI frequency */
<> 144:ef7eb2e8f9f7 13432
<> 144:ef7eb2e8f9f7 13433 /* Bits 31..0 : TWI master clock frequency */
<> 144:ef7eb2e8f9f7 13434 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 13435 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 13436 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
<> 144:ef7eb2e8f9f7 13437 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
<> 144:ef7eb2e8f9f7 13438 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
<> 144:ef7eb2e8f9f7 13439
<> 144:ef7eb2e8f9f7 13440 /* Register: TWI_ADDRESS */
<> 144:ef7eb2e8f9f7 13441 /* Description: Address used in the TWI transfer */
<> 144:ef7eb2e8f9f7 13442
<> 144:ef7eb2e8f9f7 13443 /* Bits 6..0 : Address used in the TWI transfer */
<> 144:ef7eb2e8f9f7 13444 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
<> 144:ef7eb2e8f9f7 13445 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
<> 144:ef7eb2e8f9f7 13446
<> 144:ef7eb2e8f9f7 13447
<> 144:ef7eb2e8f9f7 13448 /* Peripheral: TWIM */
<> 144:ef7eb2e8f9f7 13449 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
<> 144:ef7eb2e8f9f7 13450
<> 144:ef7eb2e8f9f7 13451 /* Register: TWIM_SHORTS */
<> 144:ef7eb2e8f9f7 13452 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 13453
<> 144:ef7eb2e8f9f7 13454 /* Bit 12 : Shortcut between LASTRX event and STOP task */
<> 144:ef7eb2e8f9f7 13455 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
<> 144:ef7eb2e8f9f7 13456 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
<> 144:ef7eb2e8f9f7 13457 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13458 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13459
<> 144:ef7eb2e8f9f7 13460 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */
<> 144:ef7eb2e8f9f7 13461 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
<> 144:ef7eb2e8f9f7 13462 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
<> 144:ef7eb2e8f9f7 13463 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13464 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13465
<> 144:ef7eb2e8f9f7 13466 /* Bit 9 : Shortcut between LASTTX event and STOP task */
<> 144:ef7eb2e8f9f7 13467 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
<> 144:ef7eb2e8f9f7 13468 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
<> 144:ef7eb2e8f9f7 13469 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13470 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13471
<> 144:ef7eb2e8f9f7 13472 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
<> 144:ef7eb2e8f9f7 13473 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13474 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13475 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13476 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13477
<> 144:ef7eb2e8f9f7 13478 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */
<> 144:ef7eb2e8f9f7 13479 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
<> 144:ef7eb2e8f9f7 13480 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
<> 144:ef7eb2e8f9f7 13481 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13482 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13483
<> 144:ef7eb2e8f9f7 13484 /* Register: TWIM_INTEN */
<> 144:ef7eb2e8f9f7 13485 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 13486
<> 144:ef7eb2e8f9f7 13487 /* Bit 24 : Enable or disable interrupt for LASTTX event */
<> 144:ef7eb2e8f9f7 13488 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
<> 144:ef7eb2e8f9f7 13489 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
<> 144:ef7eb2e8f9f7 13490 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13491 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13492
<> 144:ef7eb2e8f9f7 13493 /* Bit 23 : Enable or disable interrupt for LASTRX event */
<> 144:ef7eb2e8f9f7 13494 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
<> 144:ef7eb2e8f9f7 13495 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
<> 144:ef7eb2e8f9f7 13496 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13497 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13498
<> 144:ef7eb2e8f9f7 13499 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 13500 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13501 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13502 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13503 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13504
<> 144:ef7eb2e8f9f7 13505 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 13506 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13507 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13508 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13509 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13510
<> 144:ef7eb2e8f9f7 13511 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
<> 144:ef7eb2e8f9f7 13512 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13513 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13514 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13515 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13516
<> 144:ef7eb2e8f9f7 13517 /* Bit 9 : Enable or disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13518 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13519 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13520 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13521 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13522
<> 144:ef7eb2e8f9f7 13523 /* Bit 1 : Enable or disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13524 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13525 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13526 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13527 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13528
<> 144:ef7eb2e8f9f7 13529 /* Register: TWIM_INTENSET */
<> 144:ef7eb2e8f9f7 13530 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 13531
<> 144:ef7eb2e8f9f7 13532 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
<> 144:ef7eb2e8f9f7 13533 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
<> 144:ef7eb2e8f9f7 13534 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
<> 144:ef7eb2e8f9f7 13535 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13536 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13537 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13538
<> 144:ef7eb2e8f9f7 13539 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
<> 144:ef7eb2e8f9f7 13540 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
<> 144:ef7eb2e8f9f7 13541 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
<> 144:ef7eb2e8f9f7 13542 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13543 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13544 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13545
<> 144:ef7eb2e8f9f7 13546 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 13547 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13548 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13549 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13550 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13551 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13552
<> 144:ef7eb2e8f9f7 13553 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 13554 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13555 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13556 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13557 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13558 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13559
<> 144:ef7eb2e8f9f7 13560 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
<> 144:ef7eb2e8f9f7 13561 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13562 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13563 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13564 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13565 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13566
<> 144:ef7eb2e8f9f7 13567 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13568 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13569 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13570 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13571 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13572 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13573
<> 144:ef7eb2e8f9f7 13574 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13575 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13576 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13577 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13578 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13579 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13580
<> 144:ef7eb2e8f9f7 13581 /* Register: TWIM_INTENCLR */
<> 144:ef7eb2e8f9f7 13582 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 13583
<> 144:ef7eb2e8f9f7 13584 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
<> 144:ef7eb2e8f9f7 13585 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
<> 144:ef7eb2e8f9f7 13586 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
<> 144:ef7eb2e8f9f7 13587 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13588 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13589 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13590
<> 144:ef7eb2e8f9f7 13591 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
<> 144:ef7eb2e8f9f7 13592 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
<> 144:ef7eb2e8f9f7 13593 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
<> 144:ef7eb2e8f9f7 13594 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13595 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13596 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13597
<> 144:ef7eb2e8f9f7 13598 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 13599 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13600 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13601 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13602 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13603 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13604
<> 144:ef7eb2e8f9f7 13605 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 13606 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13607 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13608 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13609 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13610 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13611
<> 144:ef7eb2e8f9f7 13612 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
<> 144:ef7eb2e8f9f7 13613 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13614 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
<> 144:ef7eb2e8f9f7 13615 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13616 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13617 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13618
<> 144:ef7eb2e8f9f7 13619 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13620 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13621 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13622 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13623 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13624 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13625
<> 144:ef7eb2e8f9f7 13626 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13627 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13628 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13629 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13630 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13631 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13632
<> 144:ef7eb2e8f9f7 13633 /* Register: TWIM_ERRORSRC */
<> 144:ef7eb2e8f9f7 13634 /* Description: Error source */
<> 144:ef7eb2e8f9f7 13635
<> 144:ef7eb2e8f9f7 13636 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
<> 144:ef7eb2e8f9f7 13637 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
<> 144:ef7eb2e8f9f7 13638 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
<> 144:ef7eb2e8f9f7 13639 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
<> 144:ef7eb2e8f9f7 13640 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
<> 144:ef7eb2e8f9f7 13641
<> 144:ef7eb2e8f9f7 13642 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
<> 144:ef7eb2e8f9f7 13643 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
<> 144:ef7eb2e8f9f7 13644 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
<> 144:ef7eb2e8f9f7 13645 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
<> 144:ef7eb2e8f9f7 13646 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
<> 144:ef7eb2e8f9f7 13647
<> 144:ef7eb2e8f9f7 13648 /* Register: TWIM_ENABLE */
<> 144:ef7eb2e8f9f7 13649 /* Description: Enable TWIM */
<> 144:ef7eb2e8f9f7 13650
<> 144:ef7eb2e8f9f7 13651 /* Bits 3..0 : Enable or disable TWIM */
<> 144:ef7eb2e8f9f7 13652 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 13653 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 13654 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
<> 144:ef7eb2e8f9f7 13655 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
<> 144:ef7eb2e8f9f7 13656
<> 144:ef7eb2e8f9f7 13657 /* Register: TWIM_PSEL_SCL */
<> 144:ef7eb2e8f9f7 13658 /* Description: Pin select for SCL signal */
<> 144:ef7eb2e8f9f7 13659
<> 144:ef7eb2e8f9f7 13660 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 13661 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 13662 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 13663 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 13664 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 13665
<> 144:ef7eb2e8f9f7 13666 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 13667 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 13668 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 13669
<> 144:ef7eb2e8f9f7 13670 /* Register: TWIM_PSEL_SDA */
<> 144:ef7eb2e8f9f7 13671 /* Description: Pin select for SDA signal */
<> 144:ef7eb2e8f9f7 13672
<> 144:ef7eb2e8f9f7 13673 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 13674 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 13675 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 13676 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 13677 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 13678
<> 144:ef7eb2e8f9f7 13679 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 13680 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 13681 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 13682
<> 144:ef7eb2e8f9f7 13683 /* Register: TWIM_FREQUENCY */
<> 144:ef7eb2e8f9f7 13684 /* Description: TWI frequency */
<> 144:ef7eb2e8f9f7 13685
<> 144:ef7eb2e8f9f7 13686 /* Bits 31..0 : TWI master clock frequency */
<> 144:ef7eb2e8f9f7 13687 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 13688 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
<> 144:ef7eb2e8f9f7 13689 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
<> 144:ef7eb2e8f9f7 13690 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
<> 144:ef7eb2e8f9f7 13691 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
<> 144:ef7eb2e8f9f7 13692
<> 144:ef7eb2e8f9f7 13693 /* Register: TWIM_RXD_PTR */
<> 144:ef7eb2e8f9f7 13694 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 13695
<> 144:ef7eb2e8f9f7 13696 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 13697 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 13698 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 13699
<> 144:ef7eb2e8f9f7 13700 /* Register: TWIM_RXD_MAXCNT */
<> 144:ef7eb2e8f9f7 13701 /* Description: Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 13702
<> 144:ef7eb2e8f9f7 13703 /* Bits 7..0 : Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 13704 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 13705 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 13706
<> 144:ef7eb2e8f9f7 13707 /* Register: TWIM_RXD_AMOUNT */
<> 144:ef7eb2e8f9f7 13708 /* Description: Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 13709
<> 144:ef7eb2e8f9f7 13710 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
<> 144:ef7eb2e8f9f7 13711 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 13712 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 13713
<> 144:ef7eb2e8f9f7 13714 /* Register: TWIM_RXD_LIST */
<> 144:ef7eb2e8f9f7 13715 /* Description: EasyDMA list type */
<> 144:ef7eb2e8f9f7 13716
<> 144:ef7eb2e8f9f7 13717 /* Bits 2..0 : List type */
<> 144:ef7eb2e8f9f7 13718 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
<> 144:ef7eb2e8f9f7 13719 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
<> 144:ef7eb2e8f9f7 13720 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
<> 144:ef7eb2e8f9f7 13721 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
<> 144:ef7eb2e8f9f7 13722
<> 144:ef7eb2e8f9f7 13723 /* Register: TWIM_TXD_PTR */
<> 144:ef7eb2e8f9f7 13724 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 13725
<> 144:ef7eb2e8f9f7 13726 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 13727 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 13728 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 13729
<> 144:ef7eb2e8f9f7 13730 /* Register: TWIM_TXD_MAXCNT */
<> 144:ef7eb2e8f9f7 13731 /* Description: Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 13732
<> 144:ef7eb2e8f9f7 13733 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 13734 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 13735 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 13736
<> 144:ef7eb2e8f9f7 13737 /* Register: TWIM_TXD_AMOUNT */
<> 144:ef7eb2e8f9f7 13738 /* Description: Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 13739
<> 144:ef7eb2e8f9f7 13740 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
<> 144:ef7eb2e8f9f7 13741 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 13742 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 13743
<> 144:ef7eb2e8f9f7 13744 /* Register: TWIM_TXD_LIST */
<> 144:ef7eb2e8f9f7 13745 /* Description: EasyDMA list type */
<> 144:ef7eb2e8f9f7 13746
<> 144:ef7eb2e8f9f7 13747 /* Bits 2..0 : List type */
<> 144:ef7eb2e8f9f7 13748 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
<> 144:ef7eb2e8f9f7 13749 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
<> 144:ef7eb2e8f9f7 13750 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
<> 144:ef7eb2e8f9f7 13751 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
<> 144:ef7eb2e8f9f7 13752
<> 144:ef7eb2e8f9f7 13753 /* Register: TWIM_ADDRESS */
<> 144:ef7eb2e8f9f7 13754 /* Description: Address used in the TWI transfer */
<> 144:ef7eb2e8f9f7 13755
<> 144:ef7eb2e8f9f7 13756 /* Bits 6..0 : Address used in the TWI transfer */
<> 144:ef7eb2e8f9f7 13757 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
<> 144:ef7eb2e8f9f7 13758 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
<> 144:ef7eb2e8f9f7 13759
<> 144:ef7eb2e8f9f7 13760
<> 144:ef7eb2e8f9f7 13761 /* Peripheral: TWIS */
<> 144:ef7eb2e8f9f7 13762 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
<> 144:ef7eb2e8f9f7 13763
<> 144:ef7eb2e8f9f7 13764 /* Register: TWIS_SHORTS */
<> 144:ef7eb2e8f9f7 13765 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 13766
<> 144:ef7eb2e8f9f7 13767 /* Bit 14 : Shortcut between READ event and SUSPEND task */
<> 144:ef7eb2e8f9f7 13768 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13769 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13770 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13771 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13772
<> 144:ef7eb2e8f9f7 13773 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
<> 144:ef7eb2e8f9f7 13774 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13775 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
<> 144:ef7eb2e8f9f7 13776 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 13777 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 13778
<> 144:ef7eb2e8f9f7 13779 /* Register: TWIS_INTEN */
<> 144:ef7eb2e8f9f7 13780 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 13781
<> 144:ef7eb2e8f9f7 13782 /* Bit 26 : Enable or disable interrupt for READ event */
<> 144:ef7eb2e8f9f7 13783 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
<> 144:ef7eb2e8f9f7 13784 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
<> 144:ef7eb2e8f9f7 13785 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13786 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13787
<> 144:ef7eb2e8f9f7 13788 /* Bit 25 : Enable or disable interrupt for WRITE event */
<> 144:ef7eb2e8f9f7 13789 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
<> 144:ef7eb2e8f9f7 13790 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
<> 144:ef7eb2e8f9f7 13791 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13792 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13793
<> 144:ef7eb2e8f9f7 13794 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 13795 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13796 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13797 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13798 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13799
<> 144:ef7eb2e8f9f7 13800 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 13801 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13802 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13803 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13804 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13805
<> 144:ef7eb2e8f9f7 13806 /* Bit 9 : Enable or disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13807 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13808 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13809 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13810 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13811
<> 144:ef7eb2e8f9f7 13812 /* Bit 1 : Enable or disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13813 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13814 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13815 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13816 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13817
<> 144:ef7eb2e8f9f7 13818 /* Register: TWIS_INTENSET */
<> 144:ef7eb2e8f9f7 13819 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 13820
<> 144:ef7eb2e8f9f7 13821 /* Bit 26 : Write '1' to Enable interrupt for READ event */
<> 144:ef7eb2e8f9f7 13822 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
<> 144:ef7eb2e8f9f7 13823 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
<> 144:ef7eb2e8f9f7 13824 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13825 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13826 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13827
<> 144:ef7eb2e8f9f7 13828 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
<> 144:ef7eb2e8f9f7 13829 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
<> 144:ef7eb2e8f9f7 13830 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
<> 144:ef7eb2e8f9f7 13831 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13832 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13833 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13834
<> 144:ef7eb2e8f9f7 13835 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 13836 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13837 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13838 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13839 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13840 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13841
<> 144:ef7eb2e8f9f7 13842 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 13843 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13844 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13845 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13846 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13847 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13848
<> 144:ef7eb2e8f9f7 13849 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13850 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13851 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13852 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13853 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13854 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13855
<> 144:ef7eb2e8f9f7 13856 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13857 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13858 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13859 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13860 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13861 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 13862
<> 144:ef7eb2e8f9f7 13863 /* Register: TWIS_INTENCLR */
<> 144:ef7eb2e8f9f7 13864 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 13865
<> 144:ef7eb2e8f9f7 13866 /* Bit 26 : Write '1' to Disable interrupt for READ event */
<> 144:ef7eb2e8f9f7 13867 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
<> 144:ef7eb2e8f9f7 13868 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
<> 144:ef7eb2e8f9f7 13869 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13870 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13871 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13872
<> 144:ef7eb2e8f9f7 13873 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
<> 144:ef7eb2e8f9f7 13874 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
<> 144:ef7eb2e8f9f7 13875 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
<> 144:ef7eb2e8f9f7 13876 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13877 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13878 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13879
<> 144:ef7eb2e8f9f7 13880 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 13881 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13882 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 13883 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13884 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13885 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13886
<> 144:ef7eb2e8f9f7 13887 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 13888 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13889 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 13890 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13891 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13892 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13893
<> 144:ef7eb2e8f9f7 13894 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 13895 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 13896 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 13897 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13898 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13899 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13900
<> 144:ef7eb2e8f9f7 13901 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
<> 144:ef7eb2e8f9f7 13902 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
<> 144:ef7eb2e8f9f7 13903 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
<> 144:ef7eb2e8f9f7 13904 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 13905 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 13906 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 13907
<> 144:ef7eb2e8f9f7 13908 /* Register: TWIS_ERRORSRC */
<> 144:ef7eb2e8f9f7 13909 /* Description: Error source */
<> 144:ef7eb2e8f9f7 13910
<> 144:ef7eb2e8f9f7 13911 /* Bit 3 : TX buffer over-read detected, and prevented */
<> 144:ef7eb2e8f9f7 13912 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
<> 144:ef7eb2e8f9f7 13913 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
<> 144:ef7eb2e8f9f7 13914 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
<> 144:ef7eb2e8f9f7 13915 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
<> 144:ef7eb2e8f9f7 13916
<> 144:ef7eb2e8f9f7 13917 /* Bit 2 : NACK sent after receiving a data byte */
<> 144:ef7eb2e8f9f7 13918 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
<> 144:ef7eb2e8f9f7 13919 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
<> 144:ef7eb2e8f9f7 13920 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
<> 144:ef7eb2e8f9f7 13921 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
<> 144:ef7eb2e8f9f7 13922
<> 144:ef7eb2e8f9f7 13923 /* Bit 0 : RX buffer overflow detected, and prevented */
<> 144:ef7eb2e8f9f7 13924 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
<> 144:ef7eb2e8f9f7 13925 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
<> 144:ef7eb2e8f9f7 13926 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
<> 144:ef7eb2e8f9f7 13927 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
<> 144:ef7eb2e8f9f7 13928
<> 144:ef7eb2e8f9f7 13929 /* Register: TWIS_MATCH */
<> 144:ef7eb2e8f9f7 13930 /* Description: Status register indicating which address had a match */
<> 144:ef7eb2e8f9f7 13931
<> 144:ef7eb2e8f9f7 13932 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
<> 144:ef7eb2e8f9f7 13933 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
<> 144:ef7eb2e8f9f7 13934 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
<> 144:ef7eb2e8f9f7 13935
<> 144:ef7eb2e8f9f7 13936 /* Register: TWIS_ENABLE */
<> 144:ef7eb2e8f9f7 13937 /* Description: Enable TWIS */
<> 144:ef7eb2e8f9f7 13938
<> 144:ef7eb2e8f9f7 13939 /* Bits 3..0 : Enable or disable TWIS */
<> 144:ef7eb2e8f9f7 13940 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 13941 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 13942 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
<> 144:ef7eb2e8f9f7 13943 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
<> 144:ef7eb2e8f9f7 13944
<> 144:ef7eb2e8f9f7 13945 /* Register: TWIS_PSEL_SCL */
<> 144:ef7eb2e8f9f7 13946 /* Description: Pin select for SCL signal */
<> 144:ef7eb2e8f9f7 13947
<> 144:ef7eb2e8f9f7 13948 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 13949 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 13950 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 13951 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 13952 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 13953
<> 144:ef7eb2e8f9f7 13954 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 13955 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 13956 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 13957
<> 144:ef7eb2e8f9f7 13958 /* Register: TWIS_PSEL_SDA */
<> 144:ef7eb2e8f9f7 13959 /* Description: Pin select for SDA signal */
<> 144:ef7eb2e8f9f7 13960
<> 144:ef7eb2e8f9f7 13961 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 13962 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 13963 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 13964 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 13965 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 13966
<> 144:ef7eb2e8f9f7 13967 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 13968 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 13969 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 13970
<> 144:ef7eb2e8f9f7 13971 /* Register: TWIS_RXD_PTR */
<> 144:ef7eb2e8f9f7 13972 /* Description: RXD Data pointer */
<> 144:ef7eb2e8f9f7 13973
<> 144:ef7eb2e8f9f7 13974 /* Bits 31..0 : RXD Data pointer */
<> 144:ef7eb2e8f9f7 13975 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 13976 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 13977
<> 144:ef7eb2e8f9f7 13978 /* Register: TWIS_RXD_MAXCNT */
<> 144:ef7eb2e8f9f7 13979 /* Description: Maximum number of bytes in RXD buffer */
<> 144:ef7eb2e8f9f7 13980
<> 144:ef7eb2e8f9f7 13981 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
<> 144:ef7eb2e8f9f7 13982 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 13983 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 13984
<> 144:ef7eb2e8f9f7 13985 /* Register: TWIS_RXD_AMOUNT */
<> 144:ef7eb2e8f9f7 13986 /* Description: Number of bytes transferred in the last RXD transaction */
<> 144:ef7eb2e8f9f7 13987
<> 144:ef7eb2e8f9f7 13988 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
<> 144:ef7eb2e8f9f7 13989 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 13990 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 13991
<> 144:ef7eb2e8f9f7 13992 /* Register: TWIS_TXD_PTR */
<> 144:ef7eb2e8f9f7 13993 /* Description: TXD Data pointer */
<> 144:ef7eb2e8f9f7 13994
<> 144:ef7eb2e8f9f7 13995 /* Bits 31..0 : TXD Data pointer */
<> 144:ef7eb2e8f9f7 13996 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 13997 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 13998
<> 144:ef7eb2e8f9f7 13999 /* Register: TWIS_TXD_MAXCNT */
<> 144:ef7eb2e8f9f7 14000 /* Description: Maximum number of bytes in TXD buffer */
<> 144:ef7eb2e8f9f7 14001
<> 144:ef7eb2e8f9f7 14002 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
<> 144:ef7eb2e8f9f7 14003 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 14004 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 14005
<> 144:ef7eb2e8f9f7 14006 /* Register: TWIS_TXD_AMOUNT */
<> 144:ef7eb2e8f9f7 14007 /* Description: Number of bytes transferred in the last TXD transaction */
<> 144:ef7eb2e8f9f7 14008
<> 144:ef7eb2e8f9f7 14009 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
<> 144:ef7eb2e8f9f7 14010 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 14011 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 14012
<> 144:ef7eb2e8f9f7 14013 /* Register: TWIS_ADDRESS */
<> 144:ef7eb2e8f9f7 14014 /* Description: Description collection[0]: TWI slave address 0 */
<> 144:ef7eb2e8f9f7 14015
<> 144:ef7eb2e8f9f7 14016 /* Bits 6..0 : TWI slave address */
<> 144:ef7eb2e8f9f7 14017 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
<> 144:ef7eb2e8f9f7 14018 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
<> 144:ef7eb2e8f9f7 14019
<> 144:ef7eb2e8f9f7 14020 /* Register: TWIS_CONFIG */
<> 144:ef7eb2e8f9f7 14021 /* Description: Configuration register for the address match mechanism */
<> 144:ef7eb2e8f9f7 14022
<> 144:ef7eb2e8f9f7 14023 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
<> 144:ef7eb2e8f9f7 14024 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
<> 144:ef7eb2e8f9f7 14025 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
<> 144:ef7eb2e8f9f7 14026 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 14027 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 14028
<> 144:ef7eb2e8f9f7 14029 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
<> 144:ef7eb2e8f9f7 14030 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
<> 144:ef7eb2e8f9f7 14031 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
<> 144:ef7eb2e8f9f7 14032 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 14033 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 14034
<> 144:ef7eb2e8f9f7 14035 /* Register: TWIS_ORC */
<> 144:ef7eb2e8f9f7 14036 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
<> 144:ef7eb2e8f9f7 14037
<> 144:ef7eb2e8f9f7 14038 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
<> 144:ef7eb2e8f9f7 14039 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
<> 144:ef7eb2e8f9f7 14040 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
<> 144:ef7eb2e8f9f7 14041
<> 144:ef7eb2e8f9f7 14042
<> 144:ef7eb2e8f9f7 14043 /* Peripheral: UART */
<> 144:ef7eb2e8f9f7 14044 /* Description: Universal Asynchronous Receiver/Transmitter */
<> 144:ef7eb2e8f9f7 14045
<> 144:ef7eb2e8f9f7 14046 /* Register: UART_SHORTS */
<> 144:ef7eb2e8f9f7 14047 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 14048
<> 144:ef7eb2e8f9f7 14049 /* Bit 4 : Shortcut between NCTS event and STOPRX task */
<> 144:ef7eb2e8f9f7 14050 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
<> 144:ef7eb2e8f9f7 14051 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
<> 144:ef7eb2e8f9f7 14052 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 14053 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 14054
<> 144:ef7eb2e8f9f7 14055 /* Bit 3 : Shortcut between CTS event and STARTRX task */
<> 144:ef7eb2e8f9f7 14056 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
<> 144:ef7eb2e8f9f7 14057 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
<> 144:ef7eb2e8f9f7 14058 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 14059 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 14060
<> 144:ef7eb2e8f9f7 14061 /* Register: UART_INTENSET */
<> 144:ef7eb2e8f9f7 14062 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 14063
<> 144:ef7eb2e8f9f7 14064 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
<> 144:ef7eb2e8f9f7 14065 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
<> 144:ef7eb2e8f9f7 14066 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
<> 144:ef7eb2e8f9f7 14067 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14068 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14069 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14070
<> 144:ef7eb2e8f9f7 14071 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 14072 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 14073 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 14074 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14075 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14076 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14077
<> 144:ef7eb2e8f9f7 14078 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
<> 144:ef7eb2e8f9f7 14079 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
<> 144:ef7eb2e8f9f7 14080 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
<> 144:ef7eb2e8f9f7 14081 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14082 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14083 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14084
<> 144:ef7eb2e8f9f7 14085 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
<> 144:ef7eb2e8f9f7 14086 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
<> 144:ef7eb2e8f9f7 14087 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
<> 144:ef7eb2e8f9f7 14088 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14089 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14090 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14091
<> 144:ef7eb2e8f9f7 14092 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
<> 144:ef7eb2e8f9f7 14093 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
<> 144:ef7eb2e8f9f7 14094 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
<> 144:ef7eb2e8f9f7 14095 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14096 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14097 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14098
<> 144:ef7eb2e8f9f7 14099 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
<> 144:ef7eb2e8f9f7 14100 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
<> 144:ef7eb2e8f9f7 14101 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
<> 144:ef7eb2e8f9f7 14102 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14103 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14104 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14105
<> 144:ef7eb2e8f9f7 14106 /* Register: UART_INTENCLR */
<> 144:ef7eb2e8f9f7 14107 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 14108
<> 144:ef7eb2e8f9f7 14109 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
<> 144:ef7eb2e8f9f7 14110 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
<> 144:ef7eb2e8f9f7 14111 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
<> 144:ef7eb2e8f9f7 14112 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14113 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14114 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14115
<> 144:ef7eb2e8f9f7 14116 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 14117 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 14118 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 14119 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14120 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14121 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14122
<> 144:ef7eb2e8f9f7 14123 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
<> 144:ef7eb2e8f9f7 14124 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
<> 144:ef7eb2e8f9f7 14125 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
<> 144:ef7eb2e8f9f7 14126 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14127 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14128 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14129
<> 144:ef7eb2e8f9f7 14130 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
<> 144:ef7eb2e8f9f7 14131 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
<> 144:ef7eb2e8f9f7 14132 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
<> 144:ef7eb2e8f9f7 14133 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14134 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14135 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14136
<> 144:ef7eb2e8f9f7 14137 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
<> 144:ef7eb2e8f9f7 14138 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
<> 144:ef7eb2e8f9f7 14139 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
<> 144:ef7eb2e8f9f7 14140 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14141 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14142 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14143
<> 144:ef7eb2e8f9f7 14144 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
<> 144:ef7eb2e8f9f7 14145 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
<> 144:ef7eb2e8f9f7 14146 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
<> 144:ef7eb2e8f9f7 14147 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14148 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14149 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14150
<> 144:ef7eb2e8f9f7 14151 /* Register: UART_ERRORSRC */
<> 144:ef7eb2e8f9f7 14152 /* Description: Error source */
<> 144:ef7eb2e8f9f7 14153
<> 144:ef7eb2e8f9f7 14154 /* Bit 3 : Break condition */
<> 144:ef7eb2e8f9f7 14155 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
<> 144:ef7eb2e8f9f7 14156 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
<> 144:ef7eb2e8f9f7 14157 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14158 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14159
<> 144:ef7eb2e8f9f7 14160 /* Bit 2 : Framing error occurred */
<> 144:ef7eb2e8f9f7 14161 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
<> 144:ef7eb2e8f9f7 14162 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
<> 144:ef7eb2e8f9f7 14163 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14164 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14165
<> 144:ef7eb2e8f9f7 14166 /* Bit 1 : Parity error */
<> 144:ef7eb2e8f9f7 14167 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
<> 144:ef7eb2e8f9f7 14168 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
<> 144:ef7eb2e8f9f7 14169 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14170 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14171
<> 144:ef7eb2e8f9f7 14172 /* Bit 0 : Overrun error */
<> 144:ef7eb2e8f9f7 14173 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
<> 144:ef7eb2e8f9f7 14174 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
<> 144:ef7eb2e8f9f7 14175 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14176 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14177
<> 144:ef7eb2e8f9f7 14178 /* Register: UART_ENABLE */
<> 144:ef7eb2e8f9f7 14179 /* Description: Enable UART */
<> 144:ef7eb2e8f9f7 14180
<> 144:ef7eb2e8f9f7 14181 /* Bits 3..0 : Enable or disable UART */
<> 144:ef7eb2e8f9f7 14182 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 14183 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 14184 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
<> 144:ef7eb2e8f9f7 14185 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
<> 144:ef7eb2e8f9f7 14186
<> 144:ef7eb2e8f9f7 14187 /* Register: UART_PSELRTS */
<> 144:ef7eb2e8f9f7 14188 /* Description: Pin select for RTS */
<> 144:ef7eb2e8f9f7 14189
<> 144:ef7eb2e8f9f7 14190 /* Bits 31..0 : Pin number configuration for UART RTS signal */
<> 144:ef7eb2e8f9f7 14191 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
<> 144:ef7eb2e8f9f7 14192 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
<> 144:ef7eb2e8f9f7 14193 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14194
<> 144:ef7eb2e8f9f7 14195 /* Register: UART_PSELTXD */
<> 144:ef7eb2e8f9f7 14196 /* Description: Pin select for TXD */
<> 144:ef7eb2e8f9f7 14197
<> 144:ef7eb2e8f9f7 14198 /* Bits 31..0 : Pin number configuration for UART TXD signal */
<> 144:ef7eb2e8f9f7 14199 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
<> 144:ef7eb2e8f9f7 14200 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
<> 144:ef7eb2e8f9f7 14201 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14202
<> 144:ef7eb2e8f9f7 14203 /* Register: UART_PSELCTS */
<> 144:ef7eb2e8f9f7 14204 /* Description: Pin select for CTS */
<> 144:ef7eb2e8f9f7 14205
<> 144:ef7eb2e8f9f7 14206 /* Bits 31..0 : Pin number configuration for UART CTS signal */
<> 144:ef7eb2e8f9f7 14207 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
<> 144:ef7eb2e8f9f7 14208 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
<> 144:ef7eb2e8f9f7 14209 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14210
<> 144:ef7eb2e8f9f7 14211 /* Register: UART_PSELRXD */
<> 144:ef7eb2e8f9f7 14212 /* Description: Pin select for RXD */
<> 144:ef7eb2e8f9f7 14213
<> 144:ef7eb2e8f9f7 14214 /* Bits 31..0 : Pin number configuration for UART RXD signal */
<> 144:ef7eb2e8f9f7 14215 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
<> 144:ef7eb2e8f9f7 14216 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
<> 144:ef7eb2e8f9f7 14217 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14218
<> 144:ef7eb2e8f9f7 14219 /* Register: UART_RXD */
<> 144:ef7eb2e8f9f7 14220 /* Description: RXD register */
<> 144:ef7eb2e8f9f7 14221
<> 144:ef7eb2e8f9f7 14222 /* Bits 7..0 : RX data received in previous transfers, double buffered */
<> 144:ef7eb2e8f9f7 14223 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
<> 144:ef7eb2e8f9f7 14224 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
<> 144:ef7eb2e8f9f7 14225
<> 144:ef7eb2e8f9f7 14226 /* Register: UART_TXD */
<> 144:ef7eb2e8f9f7 14227 /* Description: TXD register */
<> 144:ef7eb2e8f9f7 14228
<> 144:ef7eb2e8f9f7 14229 /* Bits 7..0 : TX data to be transferred */
<> 144:ef7eb2e8f9f7 14230 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
<> 144:ef7eb2e8f9f7 14231 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
<> 144:ef7eb2e8f9f7 14232
<> 144:ef7eb2e8f9f7 14233 /* Register: UART_BAUDRATE */
<> 144:ef7eb2e8f9f7 14234 /* Description: Baud rate */
<> 144:ef7eb2e8f9f7 14235
<> 144:ef7eb2e8f9f7 14236 /* Bits 31..0 : Baud-rate */
<> 144:ef7eb2e8f9f7 14237 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
<> 144:ef7eb2e8f9f7 14238 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
<> 144:ef7eb2e8f9f7 14239 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
<> 144:ef7eb2e8f9f7 14240 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
<> 144:ef7eb2e8f9f7 14241 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
<> 144:ef7eb2e8f9f7 14242 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
<> 144:ef7eb2e8f9f7 14243 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
<> 144:ef7eb2e8f9f7 14244 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
<> 144:ef7eb2e8f9f7 14245 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
<> 144:ef7eb2e8f9f7 14246 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
<> 144:ef7eb2e8f9f7 14247 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
<> 144:ef7eb2e8f9f7 14248 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
<> 144:ef7eb2e8f9f7 14249 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
<> 144:ef7eb2e8f9f7 14250 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
<> 144:ef7eb2e8f9f7 14251 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
<> 144:ef7eb2e8f9f7 14252 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
<> 144:ef7eb2e8f9f7 14253 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
<> 144:ef7eb2e8f9f7 14254 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
<> 144:ef7eb2e8f9f7 14255
<> 144:ef7eb2e8f9f7 14256 /* Register: UART_CONFIG */
<> 144:ef7eb2e8f9f7 14257 /* Description: Configuration of parity and hardware flow control */
<> 144:ef7eb2e8f9f7 14258
<> 144:ef7eb2e8f9f7 14259 /* Bits 3..1 : Parity */
<> 144:ef7eb2e8f9f7 14260 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
<> 144:ef7eb2e8f9f7 14261 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
<> 144:ef7eb2e8f9f7 14262 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
<> 144:ef7eb2e8f9f7 14263 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
<> 144:ef7eb2e8f9f7 14264
<> 144:ef7eb2e8f9f7 14265 /* Bit 0 : Hardware flow control */
<> 144:ef7eb2e8f9f7 14266 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
<> 144:ef7eb2e8f9f7 14267 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
<> 144:ef7eb2e8f9f7 14268 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 14269 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 14270
<> 144:ef7eb2e8f9f7 14271
<> 144:ef7eb2e8f9f7 14272 /* Peripheral: UARTE */
<> 144:ef7eb2e8f9f7 14273 /* Description: UART with EasyDMA */
<> 144:ef7eb2e8f9f7 14274
<> 144:ef7eb2e8f9f7 14275 /* Register: UARTE_SHORTS */
<> 144:ef7eb2e8f9f7 14276 /* Description: Shortcut register */
<> 144:ef7eb2e8f9f7 14277
<> 144:ef7eb2e8f9f7 14278 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */
<> 144:ef7eb2e8f9f7 14279 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
<> 144:ef7eb2e8f9f7 14280 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
<> 144:ef7eb2e8f9f7 14281 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 14282 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 14283
<> 144:ef7eb2e8f9f7 14284 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */
<> 144:ef7eb2e8f9f7 14285 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
<> 144:ef7eb2e8f9f7 14286 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
<> 144:ef7eb2e8f9f7 14287 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
<> 144:ef7eb2e8f9f7 14288 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
<> 144:ef7eb2e8f9f7 14289
<> 144:ef7eb2e8f9f7 14290 /* Register: UARTE_INTEN */
<> 144:ef7eb2e8f9f7 14291 /* Description: Enable or disable interrupt */
<> 144:ef7eb2e8f9f7 14292
<> 144:ef7eb2e8f9f7 14293 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
<> 144:ef7eb2e8f9f7 14294 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
<> 144:ef7eb2e8f9f7 14295 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
<> 144:ef7eb2e8f9f7 14296 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14297 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14298
<> 144:ef7eb2e8f9f7 14299 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 14300 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 14301 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 14302 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14303 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14304
<> 144:ef7eb2e8f9f7 14305 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 14306 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 14307 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 14308 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14309 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14310
<> 144:ef7eb2e8f9f7 14311 /* Bit 17 : Enable or disable interrupt for RXTO event */
<> 144:ef7eb2e8f9f7 14312 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
<> 144:ef7eb2e8f9f7 14313 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
<> 144:ef7eb2e8f9f7 14314 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14315 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14316
<> 144:ef7eb2e8f9f7 14317 /* Bit 9 : Enable or disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 14318 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 14319 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 14320 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14321 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14322
<> 144:ef7eb2e8f9f7 14323 /* Bit 8 : Enable or disable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 14324 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 14325 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 14326 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14327 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14328
<> 144:ef7eb2e8f9f7 14329 /* Bit 4 : Enable or disable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 14330 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 14331 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 14332 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14333 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14334
<> 144:ef7eb2e8f9f7 14335 /* Bit 1 : Enable or disable interrupt for NCTS event */
<> 144:ef7eb2e8f9f7 14336 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
<> 144:ef7eb2e8f9f7 14337 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
<> 144:ef7eb2e8f9f7 14338 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14339 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14340
<> 144:ef7eb2e8f9f7 14341 /* Bit 0 : Enable or disable interrupt for CTS event */
<> 144:ef7eb2e8f9f7 14342 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
<> 144:ef7eb2e8f9f7 14343 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
<> 144:ef7eb2e8f9f7 14344 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14345 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14346
<> 144:ef7eb2e8f9f7 14347 /* Register: UARTE_INTENSET */
<> 144:ef7eb2e8f9f7 14348 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 14349
<> 144:ef7eb2e8f9f7 14350 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
<> 144:ef7eb2e8f9f7 14351 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
<> 144:ef7eb2e8f9f7 14352 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
<> 144:ef7eb2e8f9f7 14353 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14354 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14355 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14356
<> 144:ef7eb2e8f9f7 14357 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 14358 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 14359 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 14360 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14361 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14362 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14363
<> 144:ef7eb2e8f9f7 14364 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 14365 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 14366 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 14367 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14368 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14369 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14370
<> 144:ef7eb2e8f9f7 14371 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
<> 144:ef7eb2e8f9f7 14372 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
<> 144:ef7eb2e8f9f7 14373 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
<> 144:ef7eb2e8f9f7 14374 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14375 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14376 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14377
<> 144:ef7eb2e8f9f7 14378 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 14379 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 14380 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 14381 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14382 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14383 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14384
<> 144:ef7eb2e8f9f7 14385 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 14386 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 14387 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 14388 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14389 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14390 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14391
<> 144:ef7eb2e8f9f7 14392 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 14393 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 14394 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 14395 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14396 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14397 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14398
<> 144:ef7eb2e8f9f7 14399 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
<> 144:ef7eb2e8f9f7 14400 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
<> 144:ef7eb2e8f9f7 14401 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
<> 144:ef7eb2e8f9f7 14402 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14403 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14404 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14405
<> 144:ef7eb2e8f9f7 14406 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
<> 144:ef7eb2e8f9f7 14407 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
<> 144:ef7eb2e8f9f7 14408 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
<> 144:ef7eb2e8f9f7 14409 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14410 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14411 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14412
<> 144:ef7eb2e8f9f7 14413 /* Register: UARTE_INTENCLR */
<> 144:ef7eb2e8f9f7 14414 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 14415
<> 144:ef7eb2e8f9f7 14416 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
<> 144:ef7eb2e8f9f7 14417 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
<> 144:ef7eb2e8f9f7 14418 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
<> 144:ef7eb2e8f9f7 14419 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14420 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14421 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14422
<> 144:ef7eb2e8f9f7 14423 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
<> 144:ef7eb2e8f9f7 14424 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 14425 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
<> 144:ef7eb2e8f9f7 14426 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14427 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14428 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14429
<> 144:ef7eb2e8f9f7 14430 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
<> 144:ef7eb2e8f9f7 14431 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 14432 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
<> 144:ef7eb2e8f9f7 14433 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14434 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14435 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14436
<> 144:ef7eb2e8f9f7 14437 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
<> 144:ef7eb2e8f9f7 14438 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
<> 144:ef7eb2e8f9f7 14439 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
<> 144:ef7eb2e8f9f7 14440 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14441 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14442 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14443
<> 144:ef7eb2e8f9f7 14444 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
<> 144:ef7eb2e8f9f7 14445 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
<> 144:ef7eb2e8f9f7 14446 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
<> 144:ef7eb2e8f9f7 14447 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14448 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14449 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14450
<> 144:ef7eb2e8f9f7 14451 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
<> 144:ef7eb2e8f9f7 14452 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
<> 144:ef7eb2e8f9f7 14453 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
<> 144:ef7eb2e8f9f7 14454 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14455 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14456 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14457
<> 144:ef7eb2e8f9f7 14458 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
<> 144:ef7eb2e8f9f7 14459 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
<> 144:ef7eb2e8f9f7 14460 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
<> 144:ef7eb2e8f9f7 14461 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14462 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14463 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14464
<> 144:ef7eb2e8f9f7 14465 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
<> 144:ef7eb2e8f9f7 14466 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
<> 144:ef7eb2e8f9f7 14467 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
<> 144:ef7eb2e8f9f7 14468 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14469 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14470 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14471
<> 144:ef7eb2e8f9f7 14472 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
<> 144:ef7eb2e8f9f7 14473 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
<> 144:ef7eb2e8f9f7 14474 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
<> 144:ef7eb2e8f9f7 14475 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14476 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14477 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14478
<> 144:ef7eb2e8f9f7 14479 /* Register: UARTE_ERRORSRC */
<> 144:ef7eb2e8f9f7 14480 /* Description: Error source */
<> 144:ef7eb2e8f9f7 14481
<> 144:ef7eb2e8f9f7 14482 /* Bit 3 : Break condition */
<> 144:ef7eb2e8f9f7 14483 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
<> 144:ef7eb2e8f9f7 14484 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
<> 144:ef7eb2e8f9f7 14485 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14486 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14487
<> 144:ef7eb2e8f9f7 14488 /* Bit 2 : Framing error occurred */
<> 144:ef7eb2e8f9f7 14489 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
<> 144:ef7eb2e8f9f7 14490 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
<> 144:ef7eb2e8f9f7 14491 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14492 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14493
<> 144:ef7eb2e8f9f7 14494 /* Bit 1 : Parity error */
<> 144:ef7eb2e8f9f7 14495 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
<> 144:ef7eb2e8f9f7 14496 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
<> 144:ef7eb2e8f9f7 14497 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14498 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14499
<> 144:ef7eb2e8f9f7 14500 /* Bit 0 : Overrun error */
<> 144:ef7eb2e8f9f7 14501 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
<> 144:ef7eb2e8f9f7 14502 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
<> 144:ef7eb2e8f9f7 14503 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
<> 144:ef7eb2e8f9f7 14504 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
<> 144:ef7eb2e8f9f7 14505
<> 144:ef7eb2e8f9f7 14506 /* Register: UARTE_ENABLE */
<> 144:ef7eb2e8f9f7 14507 /* Description: Enable UART */
<> 144:ef7eb2e8f9f7 14508
<> 144:ef7eb2e8f9f7 14509 /* Bits 3..0 : Enable or disable UARTE */
<> 144:ef7eb2e8f9f7 14510 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
<> 144:ef7eb2e8f9f7 14511 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
<> 144:ef7eb2e8f9f7 14512 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
<> 144:ef7eb2e8f9f7 14513 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
<> 144:ef7eb2e8f9f7 14514
<> 144:ef7eb2e8f9f7 14515 /* Register: UARTE_PSEL_RTS */
<> 144:ef7eb2e8f9f7 14516 /* Description: Pin select for RTS signal */
<> 144:ef7eb2e8f9f7 14517
<> 144:ef7eb2e8f9f7 14518 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 14519 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 14520 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 14521 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 14522 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14523
<> 144:ef7eb2e8f9f7 14524 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 14525 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 14526 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 14527
<> 144:ef7eb2e8f9f7 14528 /* Register: UARTE_PSEL_TXD */
<> 144:ef7eb2e8f9f7 14529 /* Description: Pin select for TXD signal */
<> 144:ef7eb2e8f9f7 14530
<> 144:ef7eb2e8f9f7 14531 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 14532 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 14533 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 14534 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 14535 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14536
<> 144:ef7eb2e8f9f7 14537 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 14538 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 14539 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 14540
<> 144:ef7eb2e8f9f7 14541 /* Register: UARTE_PSEL_CTS */
<> 144:ef7eb2e8f9f7 14542 /* Description: Pin select for CTS signal */
<> 144:ef7eb2e8f9f7 14543
<> 144:ef7eb2e8f9f7 14544 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 14545 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 14546 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 14547 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 14548 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14549
<> 144:ef7eb2e8f9f7 14550 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 14551 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 14552 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 14553
<> 144:ef7eb2e8f9f7 14554 /* Register: UARTE_PSEL_RXD */
<> 144:ef7eb2e8f9f7 14555 /* Description: Pin select for RXD signal */
<> 144:ef7eb2e8f9f7 14556
<> 144:ef7eb2e8f9f7 14557 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 14558 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 14559 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 14560 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 14561 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14562
<> 144:ef7eb2e8f9f7 14563 /* Bits 4..0 : Pin number */
<> 144:ef7eb2e8f9f7 14564 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 14565 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 14566
<> 144:ef7eb2e8f9f7 14567 /* Register: UARTE_BAUDRATE */
<> 144:ef7eb2e8f9f7 14568 /* Description: Baud rate */
<> 144:ef7eb2e8f9f7 14569
<> 144:ef7eb2e8f9f7 14570 /* Bits 31..0 : Baud-rate */
<> 144:ef7eb2e8f9f7 14571 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
<> 144:ef7eb2e8f9f7 14572 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
<> 144:ef7eb2e8f9f7 14573 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
<> 144:ef7eb2e8f9f7 14574 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
<> 144:ef7eb2e8f9f7 14575 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
<> 144:ef7eb2e8f9f7 14576 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
<> 144:ef7eb2e8f9f7 14577 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
<> 144:ef7eb2e8f9f7 14578 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
<> 144:ef7eb2e8f9f7 14579 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
<> 144:ef7eb2e8f9f7 14580 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
<> 144:ef7eb2e8f9f7 14581 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
<> 144:ef7eb2e8f9f7 14582 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
<> 144:ef7eb2e8f9f7 14583 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
<> 144:ef7eb2e8f9f7 14584 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
<> 144:ef7eb2e8f9f7 14585 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
<> 144:ef7eb2e8f9f7 14586 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
<> 144:ef7eb2e8f9f7 14587 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
<> 144:ef7eb2e8f9f7 14588 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
<> 144:ef7eb2e8f9f7 14589
<> 144:ef7eb2e8f9f7 14590 /* Register: UARTE_RXD_PTR */
<> 144:ef7eb2e8f9f7 14591 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 14592
<> 144:ef7eb2e8f9f7 14593 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 14594 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 14595 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 14596
<> 144:ef7eb2e8f9f7 14597 /* Register: UARTE_RXD_MAXCNT */
<> 144:ef7eb2e8f9f7 14598 /* Description: Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 14599
<> 144:ef7eb2e8f9f7 14600 /* Bits 7..0 : Maximum number of bytes in receive buffer */
<> 144:ef7eb2e8f9f7 14601 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 14602 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 14603
<> 144:ef7eb2e8f9f7 14604 /* Register: UARTE_RXD_AMOUNT */
<> 144:ef7eb2e8f9f7 14605 /* Description: Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 14606
<> 144:ef7eb2e8f9f7 14607 /* Bits 7..0 : Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 14608 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 14609 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 14610
<> 144:ef7eb2e8f9f7 14611 /* Register: UARTE_TXD_PTR */
<> 144:ef7eb2e8f9f7 14612 /* Description: Data pointer */
<> 144:ef7eb2e8f9f7 14613
<> 144:ef7eb2e8f9f7 14614 /* Bits 31..0 : Data pointer */
<> 144:ef7eb2e8f9f7 14615 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
<> 144:ef7eb2e8f9f7 14616 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
<> 144:ef7eb2e8f9f7 14617
<> 144:ef7eb2e8f9f7 14618 /* Register: UARTE_TXD_MAXCNT */
<> 144:ef7eb2e8f9f7 14619 /* Description: Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 14620
<> 144:ef7eb2e8f9f7 14621 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
<> 144:ef7eb2e8f9f7 14622 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
<> 144:ef7eb2e8f9f7 14623 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
<> 144:ef7eb2e8f9f7 14624
<> 144:ef7eb2e8f9f7 14625 /* Register: UARTE_TXD_AMOUNT */
<> 144:ef7eb2e8f9f7 14626 /* Description: Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 14627
<> 144:ef7eb2e8f9f7 14628 /* Bits 7..0 : Number of bytes transferred in the last transaction */
<> 144:ef7eb2e8f9f7 14629 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
<> 144:ef7eb2e8f9f7 14630 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
<> 144:ef7eb2e8f9f7 14631
<> 144:ef7eb2e8f9f7 14632 /* Register: UARTE_CONFIG */
<> 144:ef7eb2e8f9f7 14633 /* Description: Configuration of parity and hardware flow control */
<> 144:ef7eb2e8f9f7 14634
<> 144:ef7eb2e8f9f7 14635 /* Bits 3..1 : Parity */
<> 144:ef7eb2e8f9f7 14636 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
<> 144:ef7eb2e8f9f7 14637 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
<> 144:ef7eb2e8f9f7 14638 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
<> 144:ef7eb2e8f9f7 14639 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
<> 144:ef7eb2e8f9f7 14640
<> 144:ef7eb2e8f9f7 14641 /* Bit 0 : Hardware flow control */
<> 144:ef7eb2e8f9f7 14642 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
<> 144:ef7eb2e8f9f7 14643 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
<> 144:ef7eb2e8f9f7 14644 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
<> 144:ef7eb2e8f9f7 14645 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
<> 144:ef7eb2e8f9f7 14646
<> 144:ef7eb2e8f9f7 14647
<> 144:ef7eb2e8f9f7 14648 /* Peripheral: UICR */
<> 144:ef7eb2e8f9f7 14649 /* Description: User Information Configuration Registers */
<> 144:ef7eb2e8f9f7 14650
<> 144:ef7eb2e8f9f7 14651 /* Register: UICR_NRFFW */
<> 144:ef7eb2e8f9f7 14652 /* Description: Description collection[0]: Reserved for Nordic firmware design */
<> 144:ef7eb2e8f9f7 14653
<> 144:ef7eb2e8f9f7 14654 /* Bits 31..0 : Reserved for Nordic firmware design */
<> 144:ef7eb2e8f9f7 14655 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
<> 144:ef7eb2e8f9f7 14656 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
<> 144:ef7eb2e8f9f7 14657
<> 144:ef7eb2e8f9f7 14658 /* Register: UICR_NRFHW */
<> 144:ef7eb2e8f9f7 14659 /* Description: Description collection[0]: Reserved for Nordic hardware design */
<> 144:ef7eb2e8f9f7 14660
<> 144:ef7eb2e8f9f7 14661 /* Bits 31..0 : Reserved for Nordic hardware design */
<> 144:ef7eb2e8f9f7 14662 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
<> 144:ef7eb2e8f9f7 14663 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
<> 144:ef7eb2e8f9f7 14664
<> 144:ef7eb2e8f9f7 14665 /* Register: UICR_CUSTOMER */
<> 144:ef7eb2e8f9f7 14666 /* Description: Description collection[0]: Reserved for customer */
<> 144:ef7eb2e8f9f7 14667
<> 144:ef7eb2e8f9f7 14668 /* Bits 31..0 : Reserved for customer */
<> 144:ef7eb2e8f9f7 14669 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
<> 144:ef7eb2e8f9f7 14670 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
<> 144:ef7eb2e8f9f7 14671
<> 144:ef7eb2e8f9f7 14672 /* Register: UICR_PSELRESET */
<> 144:ef7eb2e8f9f7 14673 /* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
<> 144:ef7eb2e8f9f7 14674
<> 144:ef7eb2e8f9f7 14675 /* Bit 31 : Connection */
<> 144:ef7eb2e8f9f7 14676 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
<> 144:ef7eb2e8f9f7 14677 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
<> 144:ef7eb2e8f9f7 14678 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
<> 144:ef7eb2e8f9f7 14679 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
<> 144:ef7eb2e8f9f7 14680
<> 144:ef7eb2e8f9f7 14681 /* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
<> 144:ef7eb2e8f9f7 14682 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
<> 144:ef7eb2e8f9f7 14683 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
<> 144:ef7eb2e8f9f7 14684
<> 144:ef7eb2e8f9f7 14685 /* Register: UICR_APPROTECT */
<> 144:ef7eb2e8f9f7 14686 /* Description: Access Port protection */
<> 144:ef7eb2e8f9f7 14687
<> 144:ef7eb2e8f9f7 14688 /* Bits 7..0 : Enable or disable Access Port protection. */
<> 144:ef7eb2e8f9f7 14689 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
<> 144:ef7eb2e8f9f7 14690 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
<> 144:ef7eb2e8f9f7 14691 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14692 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14693
<> 144:ef7eb2e8f9f7 14694 /* Register: UICR_NFCPINS */
<> 144:ef7eb2e8f9f7 14695 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
<> 144:ef7eb2e8f9f7 14696
<> 144:ef7eb2e8f9f7 14697 /* Bit 0 : Setting of pins dedicated to NFC functionality */
<> 144:ef7eb2e8f9f7 14698 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
<> 144:ef7eb2e8f9f7 14699 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
<> 144:ef7eb2e8f9f7 14700 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
<> 144:ef7eb2e8f9f7 14701 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
<> 144:ef7eb2e8f9f7 14702
<> 144:ef7eb2e8f9f7 14703
<> 144:ef7eb2e8f9f7 14704 /* Peripheral: WDT */
<> 144:ef7eb2e8f9f7 14705 /* Description: Watchdog Timer */
<> 144:ef7eb2e8f9f7 14706
<> 144:ef7eb2e8f9f7 14707 /* Register: WDT_INTENSET */
<> 144:ef7eb2e8f9f7 14708 /* Description: Enable interrupt */
<> 144:ef7eb2e8f9f7 14709
<> 144:ef7eb2e8f9f7 14710 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
<> 144:ef7eb2e8f9f7 14711 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
<> 144:ef7eb2e8f9f7 14712 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
<> 144:ef7eb2e8f9f7 14713 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14714 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14715 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
<> 144:ef7eb2e8f9f7 14716
<> 144:ef7eb2e8f9f7 14717 /* Register: WDT_INTENCLR */
<> 144:ef7eb2e8f9f7 14718 /* Description: Disable interrupt */
<> 144:ef7eb2e8f9f7 14719
<> 144:ef7eb2e8f9f7 14720 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
<> 144:ef7eb2e8f9f7 14721 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
<> 144:ef7eb2e8f9f7 14722 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
<> 144:ef7eb2e8f9f7 14723 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
<> 144:ef7eb2e8f9f7 14724 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
<> 144:ef7eb2e8f9f7 14725 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
<> 144:ef7eb2e8f9f7 14726
<> 144:ef7eb2e8f9f7 14727 /* Register: WDT_RUNSTATUS */
<> 144:ef7eb2e8f9f7 14728 /* Description: Run status */
<> 144:ef7eb2e8f9f7 14729
<> 144:ef7eb2e8f9f7 14730 /* Bit 0 : Indicates whether or not the watchdog is running */
<> 144:ef7eb2e8f9f7 14731 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
<> 144:ef7eb2e8f9f7 14732 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
<> 144:ef7eb2e8f9f7 14733 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
<> 144:ef7eb2e8f9f7 14734 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
<> 144:ef7eb2e8f9f7 14735
<> 144:ef7eb2e8f9f7 14736 /* Register: WDT_REQSTATUS */
<> 144:ef7eb2e8f9f7 14737 /* Description: Request status */
<> 144:ef7eb2e8f9f7 14738
<> 144:ef7eb2e8f9f7 14739 /* Bit 7 : Request status for RR[7] register */
<> 144:ef7eb2e8f9f7 14740 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
<> 144:ef7eb2e8f9f7 14741 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
<> 144:ef7eb2e8f9f7 14742 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14743 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14744
<> 144:ef7eb2e8f9f7 14745 /* Bit 6 : Request status for RR[6] register */
<> 144:ef7eb2e8f9f7 14746 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
<> 144:ef7eb2e8f9f7 14747 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
<> 144:ef7eb2e8f9f7 14748 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14749 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14750
<> 144:ef7eb2e8f9f7 14751 /* Bit 5 : Request status for RR[5] register */
<> 144:ef7eb2e8f9f7 14752 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
<> 144:ef7eb2e8f9f7 14753 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
<> 144:ef7eb2e8f9f7 14754 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14755 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14756
<> 144:ef7eb2e8f9f7 14757 /* Bit 4 : Request status for RR[4] register */
<> 144:ef7eb2e8f9f7 14758 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
<> 144:ef7eb2e8f9f7 14759 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
<> 144:ef7eb2e8f9f7 14760 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14761 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14762
<> 144:ef7eb2e8f9f7 14763 /* Bit 3 : Request status for RR[3] register */
<> 144:ef7eb2e8f9f7 14764 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
<> 144:ef7eb2e8f9f7 14765 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
<> 144:ef7eb2e8f9f7 14766 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14767 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14768
<> 144:ef7eb2e8f9f7 14769 /* Bit 2 : Request status for RR[2] register */
<> 144:ef7eb2e8f9f7 14770 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
<> 144:ef7eb2e8f9f7 14771 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
<> 144:ef7eb2e8f9f7 14772 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14773 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14774
<> 144:ef7eb2e8f9f7 14775 /* Bit 1 : Request status for RR[1] register */
<> 144:ef7eb2e8f9f7 14776 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
<> 144:ef7eb2e8f9f7 14777 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
<> 144:ef7eb2e8f9f7 14778 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14779 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14780
<> 144:ef7eb2e8f9f7 14781 /* Bit 0 : Request status for RR[0] register */
<> 144:ef7eb2e8f9f7 14782 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
<> 144:ef7eb2e8f9f7 14783 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
<> 144:ef7eb2e8f9f7 14784 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
<> 144:ef7eb2e8f9f7 14785 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
<> 144:ef7eb2e8f9f7 14786
<> 144:ef7eb2e8f9f7 14787 /* Register: WDT_CRV */
<> 144:ef7eb2e8f9f7 14788 /* Description: Counter reload value */
<> 144:ef7eb2e8f9f7 14789
<> 144:ef7eb2e8f9f7 14790 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
<> 144:ef7eb2e8f9f7 14791 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
<> 144:ef7eb2e8f9f7 14792 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
<> 144:ef7eb2e8f9f7 14793
<> 144:ef7eb2e8f9f7 14794 /* Register: WDT_RREN */
<> 144:ef7eb2e8f9f7 14795 /* Description: Enable register for reload request registers */
<> 144:ef7eb2e8f9f7 14796
<> 144:ef7eb2e8f9f7 14797 /* Bit 7 : Enable or disable RR[7] register */
<> 144:ef7eb2e8f9f7 14798 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
<> 144:ef7eb2e8f9f7 14799 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
<> 144:ef7eb2e8f9f7 14800 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
<> 144:ef7eb2e8f9f7 14801 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
<> 144:ef7eb2e8f9f7 14802
<> 144:ef7eb2e8f9f7 14803 /* Bit 6 : Enable or disable RR[6] register */
<> 144:ef7eb2e8f9f7 14804 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
<> 144:ef7eb2e8f9f7 14805 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
<> 144:ef7eb2e8f9f7 14806 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
<> 144:ef7eb2e8f9f7 14807 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
<> 144:ef7eb2e8f9f7 14808
<> 144:ef7eb2e8f9f7 14809 /* Bit 5 : Enable or disable RR[5] register */
<> 144:ef7eb2e8f9f7 14810 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
<> 144:ef7eb2e8f9f7 14811 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
<> 144:ef7eb2e8f9f7 14812 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
<> 144:ef7eb2e8f9f7 14813 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
<> 144:ef7eb2e8f9f7 14814
<> 144:ef7eb2e8f9f7 14815 /* Bit 4 : Enable or disable RR[4] register */
<> 144:ef7eb2e8f9f7 14816 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
<> 144:ef7eb2e8f9f7 14817 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
<> 144:ef7eb2e8f9f7 14818 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
<> 144:ef7eb2e8f9f7 14819 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
<> 144:ef7eb2e8f9f7 14820
<> 144:ef7eb2e8f9f7 14821 /* Bit 3 : Enable or disable RR[3] register */
<> 144:ef7eb2e8f9f7 14822 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
<> 144:ef7eb2e8f9f7 14823 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
<> 144:ef7eb2e8f9f7 14824 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
<> 144:ef7eb2e8f9f7 14825 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
<> 144:ef7eb2e8f9f7 14826
<> 144:ef7eb2e8f9f7 14827 /* Bit 2 : Enable or disable RR[2] register */
<> 144:ef7eb2e8f9f7 14828 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
<> 144:ef7eb2e8f9f7 14829 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
<> 144:ef7eb2e8f9f7 14830 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
<> 144:ef7eb2e8f9f7 14831 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
<> 144:ef7eb2e8f9f7 14832
<> 144:ef7eb2e8f9f7 14833 /* Bit 1 : Enable or disable RR[1] register */
<> 144:ef7eb2e8f9f7 14834 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
<> 144:ef7eb2e8f9f7 14835 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
<> 144:ef7eb2e8f9f7 14836 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
<> 144:ef7eb2e8f9f7 14837 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
<> 144:ef7eb2e8f9f7 14838
<> 144:ef7eb2e8f9f7 14839 /* Bit 0 : Enable or disable RR[0] register */
<> 144:ef7eb2e8f9f7 14840 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
<> 144:ef7eb2e8f9f7 14841 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
<> 144:ef7eb2e8f9f7 14842 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
<> 144:ef7eb2e8f9f7 14843 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
<> 144:ef7eb2e8f9f7 14844
<> 144:ef7eb2e8f9f7 14845 /* Register: WDT_CONFIG */
<> 144:ef7eb2e8f9f7 14846 /* Description: Configuration register */
<> 144:ef7eb2e8f9f7 14847
<> 144:ef7eb2e8f9f7 14848 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
<> 144:ef7eb2e8f9f7 14849 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
<> 144:ef7eb2e8f9f7 14850 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
<> 144:ef7eb2e8f9f7 14851 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
<> 144:ef7eb2e8f9f7 14852 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
<> 144:ef7eb2e8f9f7 14853
<> 144:ef7eb2e8f9f7 14854 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
<> 144:ef7eb2e8f9f7 14855 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
<> 144:ef7eb2e8f9f7 14856 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
<> 144:ef7eb2e8f9f7 14857 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
<> 144:ef7eb2e8f9f7 14858 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
<> 144:ef7eb2e8f9f7 14859
<> 144:ef7eb2e8f9f7 14860 /* Register: WDT_RR */
<> 144:ef7eb2e8f9f7 14861 /* Description: Description collection[0]: Reload request 0 */
<> 144:ef7eb2e8f9f7 14862
<> 144:ef7eb2e8f9f7 14863 /* Bits 31..0 : Reload request register */
<> 144:ef7eb2e8f9f7 14864 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
<> 144:ef7eb2e8f9f7 14865 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
<> 144:ef7eb2e8f9f7 14866 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
<> 144:ef7eb2e8f9f7 14867
<> 144:ef7eb2e8f9f7 14868
<> 144:ef7eb2e8f9f7 14869 /*lint --flb "Leave library region" */
<> 144:ef7eb2e8f9f7 14870 #endif